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| TIL306, TIL307 NUMERIC DISPLAYS WITH LOGIC SLBS001 - D1034, JUNE 1982 - REVISED SEPTEMBER 1992 SOLID-STATE DISPLAYS WITH INTEGRAL TTL MSI CIRCUIT CHIP FOR USE IN ALL SYSTEMS WHERE THE DATA TO BE DISPLAYED IS THE PULSE COUNT * * * * * 6,9-mm (0.270-Inch) Character Height High Luminous Intensity TIL306 Has Left Decimal TIL307 Has Right Decimal Easy System Interface * * * Wide Viewing Angle Internal TTL MSI Chip and Counter, Latch, Decoder, and Driver Constant-Current Drive for Light-Emitting Diodes mechanical data These assemblies consist of display chips and a TTL MSI chip mounted on a header with a red molded plastic body. Multiple displays may be mounted on 11,43-mm (0.450-inch) centers. PIN ASSIGNMENTS Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 QB QC QD QA LS RBI MAX-COUNT GND Pin 9 Pin 10 Pin 11 Pin 12 Pin 13 Pin 14 Pin 15 Pin16 PCEI SCEI RBO CLR DP BI CLK VCC 3,56 (0.140) 2,79 (0.110) Seating Plane (see Note A) 4,32 (0.170) MIN 0,56 (0.022) 0,46 (0.018) DIA All Pins 1,52 (0.060) 1,02 (0.040) C of Pin 1 L 3,81 (0.150) 4,42 (0.174) Decimal Point TIL307 7,87 (0.310) 7,62 (0.300) C of Pin 1 L 1 2,54 (0.100) 6,45 (0.254) 4,45 (0.175) 3,94 (0.155) 4 Places 10 0,66 (0.026) 3,81 (0.150) 0,66 (0.026) 3,81 (0.150) 2,54 (0.100) T.P. 14 Places (see Note C) 26,67 (1.050) 25,65 (1.010) Logic Chip Decimal Point TIL306 TIL306 A F TOP VIEW E D.P. D G B C F E TIL307 A G B C D D.P. 10,67 (0.420) 9,65 (0.380) ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES NOTES: A. Lead dimensions are not controlled above the seating plane. B. Centerlines of character segments and decimal points are shown as dashed lines. Associated dimensions are nominal. C. The true-position pin spacing is 2,54 mm (0.100 inch) between centerlines. Each centerline is located with 0,26 mm (0.010 inch) of its true longitudinal position relative to pins 1 and 16. Copyright (c) 1992, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SLBS001-D1034, JUNE 1982-REVISED SEPTEMBER 1992 TL306, TL307 NUMERIC DISPLAYS WITH LOGIC 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 logic diagram Latch Outputs MAX-COUNT QA QC QB QD To Logic Chip QA T QA VCC Count Enable Inputs SCEI PCEI CLK QB T QB a QC T QC f g b e d c QD T QD CLR BI LS Synchronous BCD counter, 4-bit latch, decoder/driver, seven-segment LED display with decimal point RBI RBO DP dp TL306 has left decimal. TL307 has right decimal. TIL306, TIL307 NUMERIC DISPLAYS WITH LOGIC SLBS001 - D1034, JUNE 1982 - REVISED SEPTEMBER 1992 description These internally-driven seven-segment light-emitting-diode (LED) displays contain a BCD counter, a four-bit latch, and a decoder/LED driver in a single 16-pin package. A description of the functions of the inputs and outputs of these devices are in the terminal function table. The TTL MSI circuits contain the equivalent of 86 gates on a single chip. Logic inputs and outputs are completely TTL/DTL compatible. The buffered inputs are implemented with relatively large resistors in series with the bases of the input transistors to lower drive-current requirements to one-half of that required for a standard Series 54/74 TTL input. The serial-carry input, actually two internal loads, is rated as one standard series 54/74 load. The logic outputs, except RBO, are active pullup, and the latch outputs QA, QB, QC, and QD are each capable of driving three standard Series 54/74 loads at a low logic level or six loads at a high logic level while the maximum-count output is capable of driving five Series 54/74 loads at a low logic level or ten loads at a high logic level. The RBO node with passive pull-up serves as a ripple-blanking output with the capability to drive three Series 54/74 loads. The LED driver outputs are designed specifically to maintain a relatively constant on-level current of approximately 7 mA through each LED segment and decimal point. All inputs are diode clamped to minimize transmission-line effects, thereby simplifying system design. Maximum clock frequency is typically 18 MHz and power dissipation is typically 600 mW with all segments on. The display format is as follows: The displays may be interconnected to produce an n-digit display with the following features: * * * * * * * * * Ripple-blanking input and output for blanking leading or trailing zeroes Floating-decimal-point logic capability Overriding blanking for suppressing entire display or pulse modulation of LED brightness Dual count-enable inputs for parallel lookahead and serial ripple logic to build high-speed fully synchronous, multidigit counter systems with no external logic, minimizing total propagation delay from the clock to the last latch output Provision for ripple-count cascading between packages Positive-edge-triggered synchronous BCD counter Parallel BCD data outputs available to drive logic processors or remote slaved displays simultaneously with data being displayed Latch strobe input allows counter to operate while a previous data point is displayed Reset-to-zero capability with clear input. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 TIL306, TIL307 NUMERIC DISPLAYS WITH LOGIC SLBS001 - D1034, JUNE 1982 - REVISED SEPTEMBER 1992 Terminal Functions PIN NAME BLANKING Input (BI) CLEAR Input (CLR) CLOCK Input (CLK) DECIMAL POINT Input (DP) LATCH Outputs (QA, QB, QC, QD) LATCH STROBE Input (LS) MAX-COUNT Output NO. 14 12 15 13 4, 1, 2, 3 DESCRIPTION When high, will blank (turn off) the entire display and force RBO low. Must be low for normal display. May be pulsed to implement intensity control of the display. When low, resets and holds counter at 0. Must be high for normal counting. Each positive-going transition will increment the counter provided that the circuit is in the normal counting mode (serial and parallel count enable inputs low, clear input high). Must be high to display decimal point. The decimal point is not displayed when this input is low or when the display is blanked. The BCD data that drives the decoder can be stored in the 4-bit latch and is available at these outputs for driving other logic and/or processors. The binary weights of the outputs are: QA = 1, QB = 2, QC = 4, QD = 8. When low, data in latches follow the data in the counter. When high, the data in the latches are held constant, and the counter may be operated independently. Will go low when the counter is at 9 and serial count enable input is low. Will return high when the counter changes to 0 and will remain high during counts 1 through 8. Will remain high (inhibited) as long as serial count enable input is high. Must be low for normal counting mode. When high, counter will be inhibited. Logic level must not be changed when the clock is low. When the data in the latches is BCD 0, a low input will blank the entire display and force the RBO low. This input has no effect if the data in the latches is other than 0. Supplies ripple-blanking information for the ripple-blanking input of the next decade. Provides a low if BI is high, or if RBI is low and the data in the latches is BCD 0; otherwise, this output is high. This pin has a resistive pullup circuit suitable for performing a wire-AND function with any open-collector output. Whenever this pin is low, the entire display will be blanked; therefore, this pin may be used as an active-low blanking input. Must be low for normal counting mode, also must be low to enable maximum count output to go low. When high, counter will be inhibited and maximum count output will be driven high. Logic level must not be changed when the clock is low. 5 7 PARALLEL Count Enable Input (PCEI) RIPPLE-BLANKING Input (RBI) RIPPLE-BLANKING Output (RBO) 9 6 11 SERIAL Count Enable Input (SCEI) 10 absolute maximum ratings over operating case temperature range (unless otherwise noted) Supply voltage, VCC (see Note 1): Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Nonrepetitive peak, tw 100 ms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating case temperature range, TC (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 85C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 25C to 85C NOTES: 1. Voltage values are with respect to network ground terminal. 2. Case temperature is the surface temperature of the plastic measured directly over the integrated circuit. Forced-air cooling may be required to maintain this temperature. 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TIL306, TIL307 NUMERIC DISPLAYS WITH LOGIC SLBS001 - D1034, JUNE 1982 - REVISED SEPTEMBER 1992 recommended operating conditions MIN Supply voltage, VCC Low logic level Normalilzed f N lil d fan-out f t from each output, N htt (to Series 54/74 integrated circuits) High logic level QA, QB, QC, QD, RBO MAX-COUNT Output RBO QA, QB, QC, QD MAX-COUNT Output Clock pulse duration, tw(clock) duration ( l k) Clear pulse duration, tw(clear) Latch strobe pulse duration, tw(latch strobe) Setup time tsu time, Operating case temperature, TC PCEI/SCEI before CLOCK CLEAR before CLOCK High logic level Low logic level 25 55 25 45 30 60 0 70 4.75 NOM 5 MAX 5.25 3 5 3 6 10 ns ns ns ns C UNIT V electrical characteristics at 25C case temperature PARAMETER VIH VIL VIK VOH High-level input voltage Low-level input voltage Input clamp voltage RBO High-level output voltage QA, QB, QC, QD MAX-COUNT Output QA, QB, QC, QD, RBO MAX-COUNT Output SCEI IIH High-level input current RBO node Other inputs SCEI IIL Low-level input current RBO node Other inputs IOS ICC Iv p Short circuit output current Short-circuit Supply current Luminous intensity y (see Note 5) Wavelength at peak emission Figure DP Input QA, QB, QC, QD MAX-COUNT Output VCC = 5.25 V 5 25 VCC = 5.25 V, VCC = 5 V VCC = 5 V, See Note 4 See Note 4 700 40 -9 - 15 120 1200 70 660 VCC = 5.25 V, VI = 0.4 V - 1.5 VCC = 5.25 V, VI = 2.4 V - 0.12 - 0.5 20 - 1.6 - 2.4 - 0.8 - 27.5 - 55 200 mA mA cd cd nm mA VCC = 4.75 V, VCC = 4.75 V, VCC = 4.75 V, VCC = 4.75 V, VCC = 4.75 V, VCC = 4.75 V, VCC = 5.25 V, II = - 12 mA IOH = - 120 A IOH = - 240 A IOH = - 400 A IOL = 4.8 mA IOL = 8 mA VI = 5.5 V 2.4 TEST CONDITIONS MIN 2 0.8 - 1.5 TYP MAX UNIT V V V V VOL II Low-level output voltage g (see Note 3) 0.4 04 1 40 V mA A mA A Input current at maximum input voltage Spectral bandwidth VCC = 5 V, See Note 4 20 nm All typical values are at VCC = 5 V. NOTES: 3. This parameter is measured with the display blanked (BI = 5 V). 4. These parameters are measured with all LED segments and the decimal point on. 5. Luminous intensity is measured with a light sensor and filter combination that approximates the CIE (International Commission on Illumination) eye-response curve. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 TIL306, TIL307 NUMERIC DISPLAYS WITH LOGIC SLBS001 - D1034, JUNE 1982 - REVISED SEPTEMBER 1992 switching characteristics, VCC = 5 V, TC = 25C PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL tPHL FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN 12 SERIAL lookahead CLK Input CLK Input MAX-COUNT MAX COUNT Output CL = 15 pF, , See Figure 1 MAX-COUNT MAX COUNT Output QA, QB, QC, QD RL = 560 , , TYP 18 12 23 26 29 28 CL = 15 pF, F See Figure 1 RL = 1.2 k, 1 2 k 38 57 MAX UNIT MHz ns ns ns ns CLR Input QA, QB, QC, QD fmax Maximum clock frequency tPLH Propagation delay time, low-to-high-level output tPHL Propagation delay time, high-to-low-level output PARAMETER MEASUREMENT INFORMATION Output VCC RL From Output Under Test CL = 15 pF NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N3064. Figure 1. Load Circuit 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TIL306, TIL307 NUMERIC DISPLAYS WITH LOGIC SLBS001 - D1034, JUNE 1982 - REVISED SEPTEMBER 1992 TYPICAL CHARACTERISTICS RELATIVE LUMINOUS INTENSITY vs CASE TEMPERATURE Luminous Intensity Relative to Value at TC = 25 C 4 VCC = 5 V 2 RELATIVE SPECTRAL CHARACTERISTICS 1 0.9 0.8 Relative Luminous Intensity 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 600 620 640 660 680 700 VCC = 5 V TC = 25C 1 0.7 0.4 0.2 0.1 0 10 20 30 40 50 60 70 TC - Case Temperature - C - Wavelength - nm Figure 2 Figure 3 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current and complete. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage ("Critical Applications"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI products in such applications requires the written approval of an appropriate TI officer. Questions concerning potential risk applications should be directed to TI through a local SC sales office. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does TI warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. Copyright (c) 1998, Texas Instruments Incorporated |
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