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2SK2299N 2SC4896 CEB14G04 9200B IS455 LL55C24 PI3USB A1108
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 MSP430x1xx Family
User's Guide
2000
Mixed Signal Products
SLAU049
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated
How to Use This Manual
Preface
Read This First
About This Manual
The MSP430x1xx User's Guide is intended to assist the development of MSP430x1xx family products by assembling together and presenting hardware and software information in a manner that is easy for engineers and programmers to use. This manual discusses modules and peripherals of the MSP430x1xx family of devices. Each discussion presents the module or peripheral in a general sense. Not all features and functions of all modules or peripherals are present on all devices. In addition, modules or peripherals may differ in their exact implementation between device families, or may not be fully implemented on an individual device or device family. Therefore, a user must always consult the data sheet of any device of interest to determine what peripherals and modules are implemented, and exactly how they are implemented on that particular device.
How to Use This Manual
This document contains the following chapters: Chapter 1 - Introduction Chapter 2 - Architectural Overview Chapter 3 - System Resets, Interrupts, and Operating Modes Chapter 4 - Memory Chapter 5 - 16-Bit CPU Chapter 6 - Hardware Multiplier Chapter 7 - Basic Clock Module Chapter 8 - Digital I/O Configuration Chapter 9 - Watchdog Timer Chapter 10 - Timer_A Chapter 11 - Timer_B Chapter 12 - USART Peripheral Interface, UART Mode Chapter 13 - USART Peripheral Interface, SPI Mode
Read This First
iii
Related Documentation From Texas Instruments
Chapter 14 - Comparator_A Chapter 15 - ADC12 Appendix A - Peripheral File Map Appendix B - Instruction Set Description Appendix C - Flash Memory
Notational Conventions
This document uses the following conventions.
-
Program listings, program examples, and interactive displays are shown in a special typeface similar to a typewriter's. Here is a sample program listing:
0011 0012 0013 0014 0005 0005 0005 0006 0001 0003 0006 .field .field .field .even 1, 2 3, 4 6, 3
Related Documentation From Texas Instruments
For related documentation see the web site http://www.ti.com/sc/msp430.
FCC Warning
This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference.
iv
Running Title--Attribute Reference
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Features and Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 11x Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 11x1 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 13x Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 14x Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Central Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Operation Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 Oscillator and Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1-2 1-3 1-3 1-4 1-4 2-1 2-2 2-2 2-3 2-3 2-3 2-4 2-4
2
3
System Resets, Interrupts, and Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 System Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.1.2 Device Initialization After System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.2 Global Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.3 MSP430 Interrupt-Priority Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.3.1 Operation of Global Interrupt--Reset/NMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.3.2 Operation of Global Interrupt--Oscillator Fault Control . . . . . . . . . . . . . . . . . . . 3-9 3.4 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.4.1 Interrupt Control Bits in Special-Function Registers (SFRs) . . . . . . . . . . . . . . 3-11 3.4.2 Interrupt Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 3.5 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 3.5.1 Low-Power Mode 0 and 1 (LPM0 and LPM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 3.5.2 Low-Power Modes 2 and 3 (LPM2 and LPM3) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 3.5.3 Low-Power Mode 4 (LPM4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 3.6 Basic Hints for Low-Power Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Data in the Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Internal ROM Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1 Processing of ROM Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2 Computed Branches and Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4-2 4-3 4-4 4-4 4-5
4
Chapter Title--Attribute Reference
v
Contents
4.4
RAM and Peripheral Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.4.1 Random Access Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.4.2 Peripheral Modules--Address Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.4.3 Peripheral Modules--Special Function Registers (SFRs) . . . . . . . . . . . . . . . . 4-10
5
16-Bit CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.1.1 The Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.1.2 The System Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.1.3 The Status Register (SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.1.4 The Constant Generator Registers CG1 and CG2 . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.2 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 5.2.1 Register Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 5.2.2 Indexed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5.2.3 Symbolic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.2.4 Absolute Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.2.5 Indirect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 5.2.6 Indirect Autoincrement Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.2.7 Immediate Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 5.2.8 Clock Cycles, Length of Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 5.3 Instruction Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 5.3.1 Double-Operand Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 5.3.2 Single-Operand Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 5.3.3 Conditional Jumps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 5.3.4 Short Form of Emulated Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21 5.3.5 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 5.4 Instruction Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 Hardware Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.1 Hardware Multiplier Module Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.2 Hardware Multiplier Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.2.1 Multiply Unsigned, 16 x 16 bit, 16 x 8 bit, 8 x 16 bit, 8 x 8 bit . . . . . . . . . . . . . . . . 6-5 6.2.2 Multiply Signed, 16 x 16 bit, 16 x 8 bit, 8x16 bit, 8x 8 bit . . . . . . . . . . . . . . . . . . . . 6-6 6.2.3 Multiply Unsigned and Accumulate, 16x16bit, 16x8bit, 8x16bit, 8x8bit . . . . . . 6-7 6.2.4 Multiply Signed and Accumulate, 16x16bit, 16x8bit, 8x16bit, 8x8bit . . . . . . . . 6-8 6.3 Hardware Multiplier Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 6.4 Hardware Multiplier Special Function Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 6.5 Hardware Multiplier Software Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 6.5.1 Hardware Multiplier Software Restrictions--Address Mode . . . . . . . . . . . . . . . 6-10 6.5.2 Hardware Multiplier Software Restrictions--Interrupt Routines . . . . . . . . . . . . 6-11 6.5.3 Hardware Multiplier Software Restrictions--MACS . . . . . . . . . . . . . . . . . . . . . . 6-12 Basic Clock Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.1 Basic Clock Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.2 LFXT1 and XT2 Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.2.1 LFXT1 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.2.2 XT2 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.2.3 Oscillator Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.2.4 Select DCO Oscillator for MCLK on XT Oscillator Fault . . . . . . . . . . . . . . . . . . . 7-8 7.3 Digitally-Controlled Oscillator (DCO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 7.3.1 Operation of the DCO Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12
6
7
vi
Contents
7.4
7.5
Basic Clock Module Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.1 Starting From Power Up Clear (PUC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.2 Adjusting the Basic Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.3 Basic Clock Features for Low-Power Applications . . . . . . . . . . . . . . . . . . . . . . 7.4.4 Selecting a Crystal Clock for MCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.5 Synchronization of Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Basic Clock Module Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.1 Digitally-Controlled Oscillator (DCO) Clock-Frequency Control . . . . . . . . . . . 7.5.2 Oscillator and Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.3 Special-Function Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-14 7-14 7-14 7-15 7-15 7-17 7-18 7-18 7-18 7-20
8
Digital I/O Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.2 Ports P1, P2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.2.1 Port P1, Port P2 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.2.2 Port P1, Port P2 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 8.2.3 Port P1, P2 Interrupt Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 8.3 Ports P3, P4, P5, P6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 8.3.1 Port P3-P6 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 8.3.2 Port P3-P6 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 The Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.1 Watchdog Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.2 Watchdog Timer Interrupt Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.3 Watchdog Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9-2 9-3 9-5 9-5
9
10 Timer_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.2 Timer_A Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.2.1 Timer Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.2.2 Clock Source Select and Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 10.2.3 Starting the Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 10.3 Timer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 10.3.1 Timer--Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 10.3.2 Timer--Up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 10.3.3 Timer--Continuous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 10.3.4 Timer--Up/Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 10.4 Capture/Compare Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13 10.4.1 Capture/Compare Block--Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14 10.4.2 Capture/Compare Block--Compare Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18 10.5 The Output Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19 10.5.1 Output Unit--Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20 10.5.2 Output Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21 10.5.3 Output Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22 10.6 Timer_A Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24 10.6.1 Timer_A Control Register TACTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25 10.6.2 Timer_A Register TAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-26 10.6.3 Capture/Compare Control Register CCTLx . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27 10.6.4 Timer_A Interrupt Vector Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-29 10.7 Timer_A UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-33
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11 Timer_B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.1.1 Similarities and Differences From Timer_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.2 Timer_B Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.2.1 Timer Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.2.2 Timer Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.2.3 Clock Source Select and Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 11.2.4 Starting the Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 11.3 Timer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 11.3.1 Timer--Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 11.3.2 Timer--Up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 11.3.3 Timer--Continuous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 11.3.4 Timer--Up/Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12 11.4 Capture/Compare Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15 11.4.1 Capture/Compare Block--Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16 11.4.2 Capture/Compare Block--Compare Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19 11.5 The Output Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23 11.5.2 Output Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-25 11.5.3 Output Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-26 11.6 Timer_B Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29 11.6.1 Timer_B Control Register TBCTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29 11.6.2 Timer_B Register TBR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-32 11.6.3 Capture/Compare Control Register CCTLx . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-32 11.6.4 Timer_B Interrupt Vector Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-35 12 USART Peripheral Interface, UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.1 USART Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12.2 USART Peripheral Interface, UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 12.2.1 UART Serial Asynchronous Communication Features . . . . . . . . . . . . . . . . . . . 12-3 12.3 Asynchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 12.3.1 Asynchronous Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 12.3.2 Baud Rate Generation in Asynchronous Communication Format . . . . . . . . . . 12-5 12.3.3 Asynchronous Communication Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7 12.3.4 Idle-Line Multiprocessor Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7 12.3.5 Address-Bit Multiprocessor Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9 12.4 Interrupt and Enable Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11 12.4.1 USART Receive Enable Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11 12.4.2 USART Transmit Enable Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12 12.4.3 USART Receive Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13 12.4.4 USART Transmit Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14 12.5 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15 12.5.1 USART Control Register UCTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16 12.5.2 Transmit Control Register UTCTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17 12.5.3 Receiver Control Register URCTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18 12.5.4 Baud Rate Select and Modulation Control Registers . . . . . . . . . . . . . . . . . . . 12-20 12.5.5 Receive-Data Buffer URXBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21 12.5.6 Transmit Data Buffer UTXBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21 12.6 Utilizing Features of Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-22 12.6.1 Receive-Start Operation From UART Frame . . . . . . . . . . . . . . . . . . . . . . . . . . 12-22 12.6.2 Maximum Utilization of Clock Frequency vs Baud Rate UART Mode . . . . . 12-24 12.6.3 Support of Multiprocessor Modes for Reduced Use of MSP430 Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-25
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12.7
Baud Rate Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.7.1 Bit Timing in Transmit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.7.2 Typical Baud Rates and Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.7.3 Synchronization Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12-25 12-25 12-27 12-28
13 USART Peripheral Interface, SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.1 USART Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.2 USART Peripheral Interface, SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 13.2.1 SPI Mode Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 13.3 Synchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13.3.1 Master SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7 13.3.2 Slave SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8 13.4 Interrupt and Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9 13.4.1 USART Receive/Transmit Enable Bit, Receive Operation . . . . . . . . . . . . . . . . 13-9 13.4.2 USART Receive/Transmit Enable Bit, Transmit Operation . . . . . . . . . . . . . . . 13-11 13.4.3 USART Receive-Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13 13.4.4 Transmit-Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14 13.5 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15 13.5.1 USART Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16 13.5.2 Transmit Control Register UTCTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16 13.5.3 Receive Control Register URCTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18 13.5.4 Baud-Rate Select and Modulation Control Registers . . . . . . . . . . . . . . . . . . . 13-19 13.5.5 Receive Data Buffer URXBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19 13.5.6 Transmit Data Buffer UTXBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-20 14 Comparator_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.1 Comparator_A Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 14.2 Comparator_A Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 14.2.1 Input Analog Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 14.2.2 Input Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 14.2.3 The Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 14.2.4 The Output Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 14.2.5 The Voltage Reference Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 14.2.6 Comparator_A Interrupt Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5 14.3 Comparator_A Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6 14.3.1 Comparator_A, Control Register CACTL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6 14.3.2 Comparator_A, Control Register CACTL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7 14.3.3 Comparator_A, Port Disable Register CAPD . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7 14.4 Comparator_A in Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9 14.4.1 Analog Signals at Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9 14.4.2 Comparator_A Used to Measure Resistive Elements . . . . . . . . . . . . . . . . . . . 14-11 14.4.3 Measuring Two Independent Resistive Element Systems . . . . . . . . . . . . . . . 14-13 14.4.4 Comparator_A Used to Detect a Current or Voltage Level . . . . . . . . . . . . . . . 14-16 14.4.5 Comparator_A Used to Measure a Current or Voltage Level . . . . . . . . . . . . . 14-17 14.4.6 Measuring the Offset Voltage of Comparator_A . . . . . . . . . . . . . . . . . . . . . . . . 14-20 14.4.7 Compensating for the Offset Voltage of Comparator_A . . . . . . . . . . . . . . . . . 14-22 14.4.8 Adding Hysteresis to Comparator_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22 15 ADC12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 15.2 ADC12 Description and Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
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15.3
15.4 15.5
15.6 15.7
15.8
15.9 A
15.2.1 ADC Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 15.2.2 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 Analog Inputs and Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 15.3.1 Analog Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 15.3.2 Input Signal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 15.3.3 Using the Temperature Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 Conversion Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8 Conversion Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9 15.5.1 Single-Channel, Single-Conversion Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9 15.5.2 Sequence-of-Channels Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12 15.5.3 Repeat-Single-Channel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16 15.5.4 Repeat-Sequence-of-Channels Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-17 15.5.5 Switching Between Conversion Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-19 15.5.6 Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-20 Conversion Clock and Conversion Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-21 Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-22 15.7.1 Sampling Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-22 15.7.2 Sample Signal Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-23 15.7.3 Sampling Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-24 15.7.4 Using the MSC Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-27 15.7.5 Sample Timing Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-29 ADC12 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-30 15.8.1 Control Registers ADC12CTL0 and ADC12CTL1 . . . . . . . . . . . . . . . . . . . . . . 15-31 15.8.2 Conversion-Memory Registers ADC12MEMx . . . . . . . . . . . . . . . . . . . . . . . . . 15-35 15.8.3 Control Registers ADC12MCTLx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-35 15.8.4 ADC12 Interrupt Flags ADC12IFG.x and Interrupt-Enable Registers ADC12IEN.x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-37 15.8.5 ADC12 Interrupt Vector Register ADC12IV . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-37 A/D Grounding and Noise Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-41
Peripheral File Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 A.2 Special Function Register of MSP430x1xx Family, Byte Access . . . . . . . . . . . . . . . . . . . A-3 A.3 Digital I/O, Byte Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3 A.4 Basic Clock Registers, Byte Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5 A.5 EPROM Control Register Byte Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5 A.6 Comparator_A Registers, Byte Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5 A.7 USART0, USART1, UART Mode (Sync=0), Byte Access . . . . . . . . . . . . . . . . . . . . . . . . . A-6 A.8 USART0, USART1, SPI Mode (Sync=1), Byte Access . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7 A.9 ADC12 Registers, Byte and Word Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8 A.10 Watchdog/Timer, Word Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-11 A.11 Flash Control Registers, Word Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-11 A.12 Hardware Multiplier, Word Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-12 A.13 Timer_A Registers, Word Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-13 A.14 Timer_B Registers, Word Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-15 Instruction Set Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.1 Instruction Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.1.1 Instruction Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.1.2 Conditional and Unconditional Jumps (Core Instructions) . . . . . . . . . . . . . . . . . B.1.3 Emulated Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 B-2 B-4 B-5 B-6
B
x
Contents
B.2 C
Instruction Set Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8
Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1 C.1 Flash Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2 C.1.1 Why Is a Flash Memory Module Divided Into Several Segments? . . . . . . . . . . C-5 C.2 Flash Memory Data Structure and Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-5 C.2.1 Flash Memory Basic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-6 C.2.2 Flash Memory Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-6 C.2.3 Flash Memory, Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-6 C.2.4 Flash Memory Status During Code Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . C-8 C.2.5 Flash Memory Status During Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-8 C.2.6 Flash Memory Status During Write (Programming) . . . . . . . . . . . . . . . . . . . . . . C-10 C.3 Flash Memory Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-13 C.3.1 Flash Memory Control Register FCTL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-13 C.3.2 Flash Memory Control Register FCTL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-15 C.3.3 Flash Memory Control Register FCTL3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-16 C.4 Flash Memory, Interrupt and Security Key Violation . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-18 C.4.1 Example of an NMI Interrupt Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-20 C.4.2 Protecting One-Flash Memory-Module Systems From Corruption . . . . . . . . . C-20 C.5 Flash Memory Access via JTAG and Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-22 C.5.1 Flash Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-22 C.5.2 Program Flash Memory Module via Serial Data Link Using JTAG Feature . . C-22 C.5.3 Programming a Flash Memory Module via Controller Software . . . . . . . . . . . C-22
Contents
xi
Running Title--Attribute Reference
Figures
2-1 2-2 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 4-1 4-2 4-3 4-4 4-5 4-6 4-7 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 6-1 6-2 6-3 7-1 7-2 7-3 7-4 7-5 7-6 MSP430 System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Bus Connection of Modules/Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Power-On Reset and Power-Up Clear Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Power-On Reset Timing on Fast VCC Rise Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Power-On Reset Timing on Slow VCC Rise Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Interrupt Priority Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 Block Diagram of NMI Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 RST/NMI Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Return From Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Status Register (SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 MSP430x1xx Operating Modes for Basic Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 Typical Current Consumption of 13x and 14x Devices vs Operating Modes . . . . . . . . . . 3-20 Memory Map of Basic Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Memory Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Bits, Bytes, and Words in a Byte-Organized Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 ROM Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Byte and Word Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Register-Byte/Byte-Register Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 Example of RAM/Peripheral Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 System Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Stack Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 PUSH SP and POP SP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 Operand Fetch Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 Double Operand Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 Single Operand Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 Conditional-Jump Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 Core Instruction Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 Connection of the Hardware Multiplier Module to the Bus System . . . . . . . . . . . . . . . . . . . 6-2 Block Diagram of the MSP430 16y16-Bit Hardware Multiplier . . . . . . . . . . . . . . . . . . . . . . . 6-3 Registers of the Hardware Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 Basic Clock Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 Principle of LFXT1 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 Off Signals for the LFXT1 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 Off Signals for Oscillator XT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 Oscillator-Fault-Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 Oscillator-Fault Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
xii
Figures
7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 8-1 8-2 8-3 8-4 9-1 9-2 9-3 9-4 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-31
Oscillator Fault in Oscillator Error Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 Oscillator Fault in Oscillator Error Condition at Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 NMI/OSCFault Interrupt Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 DCO Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 Principle Period Steps of the DCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11 On/Off Control of DCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11 Operation of the DCO Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12 Select Crystal Oscillator for MCLK, Example Uses LFXT1 for MCLK . . . . . . . . . . . . . . . . 7-15 Timing to Select Crystal Oscillator for MCLK, Example Uses LFXT1 in HF Mode for MCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17 Select Another Clock Source Signal, Example Switches From DCOCLK to LFXT1CLK for Clock MCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17 Port P1, Port P2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 Schematic of One Bit in Port P1, P2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 Ports P3-P6 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 Schematic of Bits PN-x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 Schematic of Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 Watchdog Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 Reading WDTCTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 Writing to WDTCTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 Timer_A Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 Schematic of 16-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 Schematic of Clock Source Select and Input Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 Timer Up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 Up Mode Flag Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 New Period > Old Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 New Period < Old Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 Timer Continuous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 Continuous Mode Flag Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 Output Unit in Continuous Mode for Time Intervals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 Timer Up/Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 Output Unit in Up/Down Mode (II) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11 Timer Up/Down Direction Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11 Up/Down Mode Flag Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12 Altering CCR0--Timer in Up/Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12 Capture/Compare Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13 Capture Logic Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14 Capture Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15 Capture Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16 Software Capture Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17 Output Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19 Output Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21 Output Examples--Timer in Up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23 Output Examples--Timer in Continuous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23 Output Examples--Timer in Up/Down Mode (I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24 Timer_A Control Register TACTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25 TAR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-26 Capture/Compare Control Register CCTLx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27 Capture/Compare Interrupt Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-29 Schematic of Capture/Compare Interrupt Vector Word . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30
Figures
xiii
Figures
10-32 10-33 10-34 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 11-15 11-16 11-17 11-18 11-19 11-20 11-21 11-22 11-23 11-24 11-25 11-26 11-27 11-28 11-29 11-30 11-31 11-32 12-1 12-2 12-3 12-4 12-5 12-6 12-7 12-8 12-9 12-10 12-11 12-12 12-13 12-14 12-15
Vector Word Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30 UART Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-34 Timer_A UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-35 Timer_B Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 Schematic of 16-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 Schematic of Clock Source Select and Input Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 Timer Up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 Up Mode Flag Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 New Period > Old Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 New Period < Old Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 Timer Continuous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 Continuous Mode Flag Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 Output Unit in Continuous Mode for Time Intervals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 Timer Up/Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12 Output Unit in Up/Down Mode (II) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12 Timer Up/Down Direction Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 Up/Down Mode Flag Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 Altering TBCL0--Timer in Up/Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14 Capture/Compare Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15 Capture Logic Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16 Capture Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16 Capture Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17 Software Capture Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19 Output Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23 Output Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-25 Output Examples--Timer in Up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27 Output Examples--Timer in Continuous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27 Output Examples--Timer in Up/Down Mode (I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-28 Timer_B Control Register TBCTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29 TBR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-32 Capture/Compare Control Register CCTLx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-32 Capture/Compare Interrupt Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-35 Schematic of Capture/Compare Interrupt Vector Word . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-36 Vector Word Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-36 Block Diagram of USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 Block Diagram of USART--UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 Asynchronous Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 Asynchronous Bit Format Example for n or n + 1 Clock Periods . . . . . . . . . . . . . . . . . . . . 12-4 Typical Baud-Rate Generation Other Than MSP430 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5 MSP430 Baud Rate Generation Example for n or n + 1 Clock Periods . . . . . . . . . . . . . . 12-6 Idle-Line Multiprocessor Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7 USART Receiver Idle Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8 Double-Buffered WUT and TX Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8 USART Transmitter Idle Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9 Address-Bit Multiprocessor Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10 State Diagram of Receiver Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11 State Diagram of Transmitter Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12 Receive Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13 Transmit Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14
xiv
Figures
12-16 12-17 12-18 12-19 12-20 12-21 12-22 12-23 12-24 12-25 12-26 12-27 12-28 12-29 13-1 13-2 13-3 13-4 13-5 13-6 13-7 13-8 13-9 13-10 13-11 13-12 13-13 13-14 13-15 13-16 13-17 13-18 13-19 13-20 13-21 13-22 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 14-10 14-11 14-12 14-13 14-14
USART Control Register UCTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16 Transmitter Control Register UTCTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17 Receiver-Control Register URCTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18 USART Baud Rate Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20 USART Modulation Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20 USART0 Receive Data Buffer URXBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21 Transmit Data Buffer UTXBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21 Receive-Start Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-22 Receive-Start Timing Using URXS Flag, Start Bit Accepted . . . . . . . . . . . . . . . . . . . . . . . 12-23 Receive-Start Timing Using URXS Flag, Start Bit Not Accepted . . . . . . . . . . . . . . . . . . . 12-23 Receive-Start Timing Using URXS Flag, Glitch Suppression . . . . . . . . . . . . . . . . . . . . . . 12-23 MSP430 Transmit Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-26 MSP430 Transmit Bit Timing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-26 Synchronization Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-29 Block Diagram of USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 Block Diagram of USART--SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 MSP430 USART as Master, External Device With SPI as Slave . . . . . . . . . . . . . . . . . . . . 13-5 Serial Synchronous Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 Data Transfer Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 MSP430 USART as Slave in Three-Pin or Four-Pin Configuration . . . . . . . . . . . . . . . . . . 13-7 State Diagram of Receiver Enable Operation--MSP430 as Master . . . . . . . . . . . . . . . . 13-10 State Diagram of Receive/Transmit Enable--MSP430 as Slave, Three-Pin Mode . . . . 13-10 State Diagram of Receive Enable--MSP430 as Slave, Four-Pin Mode . . . . . . . . . . . . . 13-11 State Diagram of Transmit Enable--MSP430 as Master . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11 State Diagram of Transmit Enable--MSP430 as Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12 Receive Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13 Receive Interrupt State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13 Transmit-Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14 USART Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16 Transmit Control Register UTCTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16 USART Clock Phase and Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18 Receive Control Register URCTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18 USART Baud-Rate Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19 USART Modulation Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19 Receive Data Buffer URXBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19 Transmit Data Buffer UTXBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-20 Schematic of Comparator_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 RC-Filter Response at the Output of the Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 Comparator_A Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5 Transfer Characteristic and Power Dissipation in a CMOS Inverter/Buffer . . . . . . . . . . . . 14-9 Transfer Characteristic and Power Dissipation in a CMOS Gate . . . . . . . . . . . . . . . . . . . . 14-9 Application Example With One Active(Driving R3) and Three Passive Pins With Applied Analog Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10 Temperature Measurement Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11 Timing for Temperature Measurement Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12 Two Independent Temperature Measurement Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13 Temperature Measurement Via Temperature Sensor R1(meas) . . . . . . . . . . . . . . . . . . . 14-14 Temperature Measurement Via Temperature Sensor R2(meas) . . . . . . . . . . . . . . . . . . . 14-15 Detect a Voltage Level Using an External Reference Level . . . . . . . . . . . . . . . . . . . . . . . 14-16 Detect a Current Level Using an Internal Reference Level . . . . . . . . . . . . . . . . . . . . . . . . 14-17 Measuring a Current Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18
Figures
xv
Figures
14-15 14-16 14-17 14-18 14-19 14-20 14-21 14-22 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 15-9 15-10 15-11 15-12 15-13 15-14 15-15 15-16 15-17 15-18 15-19 15-20 15-21 15-22 15-23 15-24 15-25 15-26 B-1 B-2 B-3 B-4 B-5 B-6 B-7 B-8 B-9 B-10 B-11 C-1 C-2 C-3 C-4 C-5
Timing for Measuring a Current Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18 A/D Converter for Voltage Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19 A/D Converter for Voltage Sources, Conversion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19 Measuring the Offset Voltage of the Comparator, CAEX = 0 . . . . . . . . . . . . . . . . . . . . . . 14-20 Offset Voltage of the Comparator, CAEX = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-20 Measuring the Offset Voltage of the Comparator, CAEX = 1 . . . . . . . . . . . . . . . . . . . . . . 14-21 Offset Voltage of the Comparator, CAEX = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-21 Use CAOUT at an External Pin to Add Hysteresis to the Reference Level . . . . . . . . . . 14-23 ADC12 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 ADC Core, Input Multiplexer, and Sample-and-Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 Analog Multiplexer Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 Stopping Conversion With ENC Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10 Single-Channel, Single-Conversion Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11 Example Conversion-Memory Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12 ENC Does Not Effect Active Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13 Sequence-of-Channels Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14 Sequence-of-Channels Mode Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15 Sequence-of-Channels Mode Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16 Repeat-Single-Channel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-17 Repeat-Sequence-of-Channels Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-19 The Conversion Clock ADC12CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-21 The Sample-and-Hold Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-22 Sample and Conversion, Basic Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-23 Synchronized Sample and Conversion Signal With Enable Conversion . . . . . . . . . . . . . 15-24 Conversion Timing, Pulse-Sample Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-25 Pulse-Sample Mode Example Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-25 Pulse-Sample Mode Example Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-26 Conversion Timing for Extended-Sample Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-26 Extended-Sample Mode Example Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-27 Extended-Sample Mode Example Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-27 Use of MSC Bit With Nonrepeated Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-28 Use of MSC Bit With Repeated Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-28 Equivalent Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-29 A/D Grounding and Noise Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-41 Double-Operand Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4 Single-Operand Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5 Conditional and Unconditional Jump Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5 Decrement Overlap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-26 Main Program Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-46 Destination Operand--Arithmetic Shift Left . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-47 Destination Operand--Carry Left Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-48 Destination Operand--Arithmetic Right Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-49 Destination Operand--Carry Right Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-51 Destination Operand Byte Swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-58 Destination Operand Sign Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-59 Interconnection of Flash Memory Module(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2 Flash Memory Module1 Disabled, Module2 Can Execute Code Simultaneously . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-3 Flash Memory Module Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-4 Segments in Flash Memory Module, 4K-Byte Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-5 Flash Memory Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-6
xvi
Figures
C-6 C-7 C-8 C-9 C-10 C-11
Block Diagram of the Timing Generator in the Flash Memory Module . . . . . . . . . . . . . . . . C-7 Basic Flash EEPROM Module Timing During the Erase Cycle . . . . . . . . . . . . . . . . . . . . . . C-9 Basic Flash Memory Module Timing During Write (Single Byte or Word) Cycle . . . . . . . C-11 Basic Flash Memory Module Timing During a Segment-Write Cycle . . . . . . . . . . . . . . . . C-11 Basic Flash Memory Module Timing During Segment Write Cycle . . . . . . . . . . . . . . . . . . C-19 Signal Connections to MSP430 JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-22
Figures
xvii
Running Title--Attribute Reference
Tables
3-1 3-2 3-3 3-4 3-5 3-6 4-1 4-2 4-3 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 6-1 6-2 8-1 8-2 8-3 9-1 10-1 10-2 10-3 10-4 10-5 10-6 Interrupt Control Bits in SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 Interrupt Enable Registers 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 Interrupt Flag Register 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 Module Enable Registers 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 Interrupt Sources, Flags, and Vectors of 14x Configurations . . . . . . . . . . . . . . . . . . . . . . . 3-15 Low Power Mode Logic Chart for Basic Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 Peripheral File Address Map--Word Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 Peripheral File Address Map--Byte Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 Special Function Register Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 Register by Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Description of Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 Values of Constant Generators CG1, CG2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 Source/Destination Operand Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 Register Mode Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 Indexed Mode Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 Symbolic Mode Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Absolute Mode Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Indirect Mode Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 Indirect Autoincrement Mode Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 Immediate Mode Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 Instruction Format I and Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 Instruction Format-II and Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 Miscellaneous Instructions or Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 Double Operand Instruction Format Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 Single Operand Instruction Format Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 Conditional-Jump Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 Emulated Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21 Sum Extension Register Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 Hardware Multiplier Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 Port P1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 Port P2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 Port P3-P6 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 WDTCNT Taps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 Timer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 State of OUTx at Next Rising Edge of Timer Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22 Timer_A Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24 Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25 Input Clock Divider Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-26 Clock Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-26
xviii
Tables
10-7 10-8 10-9 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 12-1 12-2 12-3 12-4 12-5 12-6 13-1 13-2 13-3 14-1 15-1 15-2 15-3 C-1 C-2
Capture/Compare Control Register Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-28 Capture/Compare Control Register Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-29 Vector Register TAIV Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31 Timer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 Shadow Register Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21 State of OUTx at Next Rising Edge of Timer Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-26 Timer_B Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29 Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-30 Input Clock Divider Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-30 Clock Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-30 Capture/Compare Control Register Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-34 Capture/Compare Control Register Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-35 Vector Register TBIV Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-37 USART Interrupt Control and Enable Bits--UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . 12-11 USART0 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15 USART1 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15 Interrupt Flag Set Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19 Receive Data Buffer Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21 Commonly Used Baud Rates, Baud Rate Data, and Errors . . . . . . . . . . . . . . . . . . . . . . . 12-28 USART Interrupt Control and Enable Bits--SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9 USART0 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15 USART1 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15 Comparator_A Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6 Reference Voltage Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 Conversion-Modes Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9 ADC12IV Interrupt-Vector Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-38 Control Bits for Write or Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-8 Conditions to Read Data From Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-12
Tables
xix
Running Title--Attribute Reference
Examples
12-1 4800 Baud . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6 12-2 19,200 Baud . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6 12-3 Error Example for 2400 Baud . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-27 12-4 Synchronization Error--2400 Baud . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-29
xx
Running Title--Attribute Reference
Notes, Cautions, and Warnings
Note: If desired, software can cause a PUC by simply writing to the watchdog timer control register with an incorrect password. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Word-Byte Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 Status Register Bits V, N, Z, and C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 Data in Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 Instruction Format II Immediate Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 Destination Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 Instructions CMP and SUB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 Control of DCOCLK Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 Writing to Read-Only Registers P1IN, P2IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 Port P1, Port P2 Interrupt Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 Function Select With P1SEL, P2SEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 Writing to Read-Only Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 Function Select With PnSEL Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 Watchdog Timer, Changing the Time Interval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 Capture With Timer Halted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16 Changing Timer_A Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-26 Modifying Timer A Register TAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27 Simultaneous Capture and Capture Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-29 Writing to Read-Only Register TAIV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31 Capture With Timer Halted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18 Changing Timer_B Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-32 Modifying Timer_B Register TBR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-32 Simultaneous Capture and Capture Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-35 Writing to Read-Only Register TBIV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-37 URXE Reenabled, UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11 Writing to UTXBUF, UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12 Write to UTXBUF/Reset of Transmitter, UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12 Mark and Space Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17 Receive Status Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20 Writing to UTXBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-22 Break Detect (BRK) Bit With Halted UART Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-24 USART Synchronous Master Mode, Receive Initiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7 USPIE Reenabled, SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10 Writing to UTXBUF, SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12 Write to UTXBUF/Reset of Transmitter, SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12 Caution! ADC12 Turnon Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 Warning ! Reference Voltage Settling Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 Caution! Do not power-down the converter or the reference generator while the converter is active. Conversion results will be false. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-20
Contents
xxi
Contents
Caution! The following must be considered when turning the ADC12 and voltage reference on or off. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-21 Availability of ADC12CLK During Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-22 Warning : Modifying ADC control register during active conversion . . . . . . . . . . . . . . . . . . . . . . . . 15-34 Warning : SOFTWARE WRITE TO REGISTER ADC12MEMx . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-35 Writing to Read Only Register ADC12IV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-38 Basic Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-40 Asterisked Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3 Operations Using the Status Register (SR) for Destination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4 Conditional and Unconditional Jumps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-6 Disable Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-28 Enable Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-29 Emulating No-Operation Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-42 The System Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-43 The System Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-44 RLA Substitution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-47 RLC and RLC.B Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-48 Borrow Is Treated as a .NOT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-52 Borrow Is Treated as a .NOT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-56 Borrow Is Treated as a .NOT. Carry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-57 Flash Memory Module(s) in MSP430 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2
xxii
Chapter 1
Introduction
This chapter outlines the features and capabilities of the Texas Instruments (TITM) MSP430x1xx family of microcontrollers. The MSP430 employs a von-Neumann architecture, therefore, all memory and peripherals are in one address space. The MSP430 devices constitute a family of ultralow-power, 16-bit RISC microcontrollers with an advanced architecture and rich peripheral set. The architecture uses advanced timing and design features, as well as a highly orthogonal structure to deliver a processor that is both powerful and flexible. The MSP430 consumes less than 400 A in active mode operating at 1 MHz in a typical 3-V system and can wake up from a <2-A standby mode to fully synchronized operation in less than 6 s. These exceptionally low current requirements, combined with the fast wake-up time, enable a user to build a system with minimum current consumption and maximum battery life. Additionally, the MSP430x1xx family has an abundant mix of peripherals and memory sizes enabling true system-on-a-chip designs. The peripherals include a 12-bit A/D, slope A/D, multiple timers (some with capture/compare registers and PWM output capability), on-chip clock generation, H/W multiplier, USART(s), Watchdog Timer, GPIO, and others. See http://www.ti.com for the latest device information and literature for the MSP430 family.
Topic
1.1 1.2 1.3 1.4 1.5
Page
Features and Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 11x Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 11x1 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 13x Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 14x Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Introduction
1-1
Features and Capabilities
1.1 Features and Capabilities
The TI MSP430x1xx family of controllers has the following features and capabilities:
-
Ultralow-power architecture: 0.1- 400 A nominal operating current @1 MHz 1.8 - 3.6 V operation (2.5-5.5 V for C11x, P11x, and E11x devices) 6 s wake-up from standby mode Extensive interrupt capability relieves need for polling Flexible and powerful processing capabilities: Seven source-address modes Four destination-address modes Only 27 core instructions Prioritized, nested interrupts No interrupt or subroutine level limits Large register file Ram execution capability Efficient table processing Fast hex-to-decimal conversion Extensive, memory-mapped peripheral set including: Integrated 12-bit A/D converter Integrated precision comparator Multiple timers and PWM capability Slope A/D conversion (all devices) Integrated USART(s) Watchdog Timer Multiple I/O with extensive interrupt capability Integrated programmable oscillator 32-kHz crystal oscillator (all devices) 450-kHz - 8-MHz crystal oscillator (selected devices) Powerful, easy-to-use development tools including: Simulator (including peripheral and interrupt simulation) C compiler Assembler Linker Emulators Flash emulator kit Evaluation kits Device programmer Application notes Example code
-
-
-
1-2
11x Devices
-
Versatile ultralow-power device options including: Masked ROM OTP (in-system programmable) Flash (in-system programmable) EPROM (UV-erasable, in-system programmable) -40C to +85C operating temperature range Up to 64K addressing space Memory mixes to support all types of applications
1.2 11x Devices
The 11x devices contain the following peripherals:
-
Basic Clock System (on-chip DCO + one or two crystal oscillators) Watchdog Timer/General Purpose Timer Timer_A3 (16-bit timer with 3 capture/compare registers and PWM output) I/O Port1, 2 (8 I/O's each, all with interrupt)
Available 11x devices are: MSP430C111 MSP430C112 MSP430P112 PMS430E112 MSP430F110 MSP430F112 2KB ROM, 128B RAM 4KB ROM, 256B RAM 4KB OTP, 256B RAM 4KB EPROM, 256B RAM 1KB +128B Flash, 128B RAM 4KB +256B Flash, 256B RAM
1.3 11x1 Devices
The 11x1 devices contain the following peripherals:
-
Basic Clock System (on-chip DCO + one or two crystal oscillators) Watchdog Timer/General Purpose Timer Timer_A3 (16-bit timer with 3 capture/compare registers and PWM output) I/O Port1, 2 (8 I/O's each, all with interrupt) Comparator_A (precision analog comparator, ideal for slope A/D conversion)
Available 11x1 devices are: MSP430C1111 MSP430C1121 MSP430F1101 MSP430F1121 2KB ROM, 128B RAM 4KB ROM, 256B RAM 1KB +128B Flash, 128B RAM 4KB +256B Flash, 256B RAM
Introduction
1-3
13x Devices
1.4 13x Devices
The 13x devices contain the following peripherals:
-
Basic Clock System (on-chip DCO + one or two crystal oscillators) Watchdog Timer/General Purpose Timer Timer_A3 (16-bit timer with 3 capture/compare registers and PWM output) Timer_B3 (16-bit timer with 3 capture/compare registers and PWM output) I/O Port1, 2 (8 I/O's each, all with interrupt) I/O Port3, 4, 5, 6 (8 I/O's each) Comparator_A (precision analog comparator, ideal for slope A/D conversion) ADC12 (12-bit A/D) USART0
13x devices include: MSP430F133 MSP430F135 8KB +256B Flash, 256B RAM 16KB +256B Flash, 512B RAM
1.5 14x Devices
The 14x devices contain the following peripherals:
-
Basic Clock System (on-chip DCO + one or two crystal oscillators) Watchdog Timer/General Purpose Timer Timer_A3 (16-bit timer with 3 capture/compare registers and PWM output) Timer_B7 (16-bit timer with 7 capture/compare registers and PWM output) I/O Port1, 2 (8 I/O's each, all with interrupt) I/O Port3, 4, 5, 6 (8 I/O's each) Comparator_A (precision analog comparator, ideal for slope A/D conversion) ADC12 (12-bit A/D) USART0 USART1 Hardware Multiplier
Available 14x devices are: MSP430F147 MSP430F148 MSP430F149 32KB +256B Flash, 1KB RAM 48KB +256B Flash, 2KB RAM 60KB +256B Flash, 2KB RAM
1-4
Chapter 2
Architectural Overview
This section describes the basic functions of an MSP430-based system. The MSP430 devices contain the following main elements:
-
Central processing unit Program memory Data memory Operation control Peripheral modules Oscillator and clock generator
Topic
2.1 2.2 2.3 2.4 2.5 2.6 2.7
Page
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Central Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Operation Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Oscillator and Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Architectural Overview
2-1
Introduction
2.1 Introduction
The architecture of the MSP430 family is based on a memory-to-memory architecture, a common address space for all functional blocks, and a reduced instruction set applicable to all functional blocks as illustrated in Figure 2-1. See specific device data sheets for complete block diagrams of individual devices.
Figure 2-1. MSP430 System Configuration
Oscillator System Clock
ACLK PROGRAM MCLK DATA I/O Port I/O Port I/O Port
MAB, 16 Bit
MAB, 4 Bit
CPU Incl. 16 Reg. MDB, 16 Bit Bus Conv.
R/W MDB, 8 Bit
Watchdog Random Logic Module Select
Timer_B
Comparator
USART
USART
2.2 Central Processing Unit
The CPU incorporates a reduced and highly transparent instruction set and a highly orthogonal design. It consists of a 16-bit arithmetic logic unit (ALU), 16 registers, and instruction control logic. Four of these registers are used for special purposes. These are the program counter (PC), stack pointer (SP), status register (SR), and constant generator (CGx). All registers, except the constant-generator registers R3/CG2 and part of R2/CG1, can be accessed using the complete instruction set. The constant generator supplies instruction constants, and is not used for data storage. The addressing mode used on CG1 separates the data from the constants. The CPU control over the program counter, the status register, and the stack pointer (with the reduced instruction set) allows the development of applications with sophisticated addressing modes and software algorithms.
2-2
Program Memory
2.3 Program Memory
Instruction fetches from program memory are always 16-bit accesses, whereas data memory can be accessed using word (16-bit) or byte (8-bit) instructions. Any access uses the 16-bit memory data bus (MDB) and as many of the least-significant address lines of the memory address bus (MAB) as required to access the memory locations. Blocks of memory are automatically selected through module-enable signals. This technique reduces overall current consumption. Program memory is integrated as programmable or mask-programmed memory. In addition to program code, data may also be placed in the ROM section of the memory map and may be accessed using word or byte instructions; this is useful for data tables, for example. This unique feature gives the MSP430 an advantage over other microcontrollers, because the data tables do not have to be copied to RAM for usage. Sixteen words of memory are reserved for reset and interrupt vectors at the top of the 64-kilobytes address space from 0FFFFh down to 0FFE0h.
2.4 Data Memory
The data memory is connected to the CPU through the same two buses as the program memory (ROM): the memory address bus (MAB) and the memory data bus (MDB). The data memory can be accessed with full (word) data width or with reduced (byte) data width. Additionally, because the RAM and ROM are connected to the CPU via the same busses, program code can be loaded into and executed from RAM. This is another unique feature of the MSP430 devices, and provides valuable, easy-to-use debugging capability.
2.5 Operation Control
The operation of the different MSP430 members is controlled mainly by the information stored in the special-function registers (SFRs). The different bits in the SFRs enable interrupts, provide information about the status of interrupt flags, and define the operating modes of the peripherals. By disabling peripherals that are not needed during an operation, total current consumption can be reduced. The individual peripherals are described later in this manual.
Architectural Overview
2-3
Peripherals
2.6 Peripherals
Peripheral modules are connected to the CPU through the MAB, MDB, and interrupt service and request lines. The MAB is usually a 5-bit bus for most of the peripherals. The MDB is an 8-bit or 16-bit bus. Most of the peripherals operate in byte format. Modules with an 8-bit data bus are connected by bus-conversion circuitry to the 16-bit CPU. The data exchange with these modules must be handled with byte instructions. The SFRs are also handled with byte instructions. The operation for 8-bit peripherals follows the order described in Figure 2-2.
Figure 2-2. Bus Connection of Modules/Peripherals
MAB MDB
Interrupt Request Module/Peripheral Interrupt Bus Grant
Interrupt Request Interrupt Bus Grant
PUC
2.7 Oscillator and Clock Generator
The LFXT1 oscillator is designed for the commonly used 32,768 Hz, low-current- consumption clock crystal or to be used with a high-speed crystal. All analog components for the 32,768 Hz oscillator are integrated into the MSP430; only the crystal needs to be connected with no other external components required. When using the LFXT1 oscillator with a high-speed crystal, additional load capacitors are required. Some MSP430 devices have an additional high-speed crystal oscillator (LFXT2). Refer to the clock chapter and the specific device data sheets for details. In addition to the crystal oscillator(s), all MSP430 devices contain a digitallycontrolled RC oscillator (DCO). The DCO is different from RC oscillators found on other microcontrollers because it is digitally controllable and tuneable. Clock source selection for peripherals and CPU is very flexible. Most peripherals are capable of using the 32768-Hz crystal oscillator clock, the high-speed crystal oscillator clock (where applicable), or the DCO clock. The CPU is capable of executing from the DCO clock or from either of the two crystal oscillator clocks. See Chapter 7 for details on the clock system.
2-4
Chapter 3
System Resets, Interrupts, and Operating Modes
This chapter discusses the MSP430x1xx system resets, interrupts, and operating modes.
Topic
3.1 3.2 3.3 3.4 3.5 3.6
Page
System Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Global Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 MSP430 Interrupt-Priority Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 Basic Hints for Low-Power Applications . . . . . . . . . . . . . . . . . . . . . . . 3-22
System Resets, Interrupts, and Operating Modes
3-1
System Reset and Initialization
3.1 System Reset and Initialization
3.1.1 Introduction
The MSP430 system reset circuitry (shown in Figure 3-1) sources two internal reset signals: power-on reset (POR) and power-up clear (PUC). Different events trigger these reset signals and different initial conditions exist depending on which signal was generated.
Figure 3-1. Power-On Reset and Power-Up Clear Schematic
VCC POR Detect 0V RST/MNI NMI(WDTCTL.5) TIMSEL WDTQn WDTIFG EQU
KEYV
VCC
POR Delay
S POR S Latch R 0V 0V Delay S S S POR S Latch S R
POR
PUC_DCO
Resetwd1
PUC
Resetwd2
(from flash module) MCLK
From watchdog timer peripheral module
A POR is a device reset. It is only generated by the two following events:
-
Powering up the device A low signal on the RST/NMI pin when configured in the reset mode
A PUC is always generated when a POR is generated, but a POR is not generated by a PUC. The following events trigger a PUC: A POR signal Watchdog timer expiration (in watchdog mode only) Watchdog timer security key violation A low signal on the RST/NMI pin when configured in the NMI mode A Flash memory security key violation
Note: If desired, software can cause a PUC by simply writing to the watchdog timer control register with an incorrect password.
3-2
System Reset and Initialization
Note: Generation of the POR/PUC signals does not necessarily generate a system reset interrupt. Anytime a POR is activated, a system reset interrupt is generated. However, when a PUC is activated, a system reset interrupt may or may not be generated. Instead, a lower priority interrupt vector may be generated, depending on what action caused the PUC. Each device data sheet gives a detailed table of what action generates each interrupt. This table should be consulted for the proper handling of all interrupts. When the VCC supply provides a fast rise time as shown in Figure 3-2, the POR delay provides enough active time on the POR signal to allow the signal to initialize the circuitry correctly after power up. When the VCC rise time is slow, as shown in Figure 3-3, the POR detector holds the POR signal active until Vcc has risen above the V(POR) level. This also ensures a correct initialization.
Figure 3-2. Power-On Reset Timing on Fast VCC Rise Time
V VCC POR
tPOR_Delay
t
If power to the chip is cycled, the supply voltage VCC must fall below the V(min) (see Figure 3-3) to ensure that another POR signal occurs when VCC is powered up again. If VCC does not fall below V(min) during a cycle or a glitch, a POR is not generated and power-up conditions do not set correctly.
Figure 3-3. Power-on Reset Timing on Slow VCC Rise Time
V VCC
V (POR) V (min) POR No POR POR
t
System Resets, Interrupts, and Operating Modes
3-3
System Reset and Initialization
3.1.2
Device Initialization After System Reset
After a device reset (POR/PUC combination), the initial system conditions are:
-
I/O pins switched to input mode (see note below). I/O flags are cleared as described in the I/O chapter (see note below). Other peripherals and registers initialized as described in their respective chapters. Status register is reset. Program counter is loaded with address contained at reset vector location (0FFFEh). CPU execution begins at that address.
Note: I/O pins and flags are only initialized after power-up. After the '430 is powered and running, if a reset is generated with RST/NMI pin (in reset mode), the I/O pins are unaffected. After a system reset, the user program can evaluate the various flags to determine the source of the reset and take appropriate action. The initial state of registers and peripherals is discussed in each applicable section of this manual. Each register is shown with a key indicating the accessibility of the register and the initial condition, for example, rw-(0), or rw-0. In these examples, the r indicates read, the w indicates write, and the value after the dash indicates the initial condition. If the value is in parenthesis, the initial condition takes effect only after a POR - a PUC alone will not effect the bit(s). If the value is not in parenthesis, it takes effect after a PUC alone or after a POR/PUC combination. Some examples follow: Type rw-(0) rw-0 r-1 r w Description Read/write, reset with POR Read/write, reset with POR or PUC Read only, set with POR or PUC Read only, no initial state Write only, no initial state
3-4
Global Interrupt Structure
3.2 Global Interrupt Structure
There are four types of interrupts:
-
System reset Maskable Non-maskable (Non)-maskable
System reset (POR/PUC) is discussed in section 3.1. Maskable interrupts are caused by: A watchdog-timer overflow (if timer mode is selected) Other modules with interrupt capability Non-maskable interrupts are not maskable in any way. No individual interrupt enable bit is implemented for them, and the general interrupt enable bit (GIE) has no effect on them. (Non)-maskable interrupts are not masked by the general interrupt enable bit (GIE) but are individually enabled or disabled by an individual interrupt enable bit. When a (non)-maskable interrupt is accepted, the corresponding interrupt enable bit is automatically reset, therefore disabling the interrupt for execution of the interrupt service routine (ISR). The RETI (return from interrupt) instruction has no effect on the individual enable bits of the (non)-maskable interrupts. So the software must set the corresponding interrupt enable bit in the ISR before execution of the RETI instruction for the interrupt to be re-enabled after the ISR. A (non)-maskable NMI interrupt can be generated by an edge on the RST/NMI pin (if NMI mode is selected), an oscillator fault occurs (if the oscillator fault interrupt is enabled), or an access violation to the flash memory takes place (if the access violation interrupt is enabled).
System Resets, Interrupts, and Operating Modes
3-5
MSP430 Interrupt-Priority Scheme
3.3 MSP430 Interrupt-Priority Scheme
The interrupt priority of the modules, as shown in Figure 3-4, is defined by the arrangement of the modules in the connection chain: the nearer a module is to the CPU/NMIRS, the higher the priority.
Figure 3-4. Interrupt Priority Scheme
Priority High Low
GMIRS
CPU
GIE NMIRS
Module 1 1 2
Module 2 1 2
WD Timer 1 2
Module m 1 2
Module n 1
PUC
Bus Grant
PUC OSCfault Flash ACCV Reset/NMI
Circuit
WDT Security Key Flash Security Key MAB - 5LSBs
Reset and NMI, as shown in Figure 3-5, can only be used as alternative interrupts because they use the same input pin. The associated control bits are located in the watchdog timer control register shown in Figure 3-6, and are password protected.
3-6
MSP430 Interrupt-Priority Scheme
Figure 3-5. Block Diagram of NMI Interrupt Sources
ACCV ACCVIFG
S FCTL1.1
ACCVIE IE1.5 Clear PUC RST/NMI
Flash Module Flash Module Flash Module
POR
PUC
KEYV
VCC
PUC System Reset Generator POR
S IFG1.4 Clear
NMIFG NMIRS
NMIES
TMSEL
NMI
WDTQn
EQU
PUC
POR
PUC NMIIE IE1.4 Clear PUC Counter OSCFault OFIFG IFG1.0 Clear WDT POR S WDTIFG IRQ
S IFG1.1
IRQA OFIE IE1.1 Clear NMI_IRQA PUC PUC IE1.0 Clear TIMSEL WDTIE
IRQA: Interrupt Request Accepted
Watchdog Timer Module
System Resets, Interrupts, and Operating Modes
3-7
MSP430 Interrupt-Priority Scheme
Figure 3-6. RST/NMI Mode Selection
7 WDTCTL 0120h HOLD rw-0 NMIES rw-0 NMI rw-0 TMSEL CNTCL rw-0 (w)-0 SSEL rw-0 IS1 rw-0 0 IS0 rw-0
BITS 0-4,7 See Watchdog Timer chapter. BIT 5: The NMI bit selects the function of the RST/NMI input pin. It is cleared after a PUC signal. NMI = 0: The RST/NMI input works as reset input. As long as the RST/NMI pin is held low, the internal PUC signal is active (level-sensitive). The RST/NMI input works as an edge-sensitive, nonmaskable interrupt input.
NMI = 1: BIT 6:
This bit selects the activating edge of the RST/NMI input if the NMI function is selected. It is cleared after a PUC signal. NMIES = 0: A rising edge triggers an NMI interrupt. NMIES = 1: A falling edge triggers an NMI interrupt.
3.3.1
Operation of Global Interrupt--Reset/NMI
If the RST/NMI pin is set to the reset function, the CPU is held in the reset state as long as the RST/NMI pin is held low. After the input changes to a high state, the CPU starts program execution at the word address stored in word location 0FFFEh (reset vector). If the RST/NMI pin is set to the NMI function, a signal edge (selected by the NMIES bit) will generate an interrupt if the NMIIE bit is set. When accepted, program execution begins at the address stored in location 0FFFCh. The RST/ NMI flag in the SFR IFG1.4 is also set. Note: When configured in the NMI mode, a signal generating an NMI event should not hold the RST/NMI pin low, unless it is intended to hold the processor in reset. When an NMI event occurs on the pin, the PUC signal is activated, thus resetting the bits in the WDTCTL register. This results in the RST/NMI pin being configured in the reset mode. If the signal on the RST/NMI pin that generated the NMI event remains low, the processor will be held in the reset state. When NMI mode is selected and the NMI edge select bit is changed, an NMI can be generated, depending on the actual level at RST/NMI pin. When the NMI edge select bit is changed before selecting the NMI mode, no NMI is generated. The NMI interrupt is maskable by the NMIIE bit.
3-8
Interrupt Processing
3.3.2
Operation of Global Interrupt--Oscillator Fault Control
The oscillator fault signal warns of a possible error condition with the crystal oscillator.
3.3.2.1
Oscillator Fault Control in the Basic Clock System
The oscillator-fault signal is triggered when the LFXT1 oscillator is configured to run in HF mode but is not running, stops running after being operational, or is switched off. The oscillator-fault signal is also triggered under the same conditions for the XT2 oscillator, present in some devices. Note that a PUC signal can trigger an oscillator fault, because the PUC switches the LFXT1 to LF mode, therefore switching off the HF mode. The PUC signal also switches off the XT2 oscillator. The oscillator fault signal can be enabled to generate an NMI by bit OFIE in the SFRs. The interrupt flag OFIFG in the SFRs can then be tested by the interrupt service routine to determine if the NMI was caused by an oscillator fault. See Basic Clock Module chapter for more details on the operation of the crystal oscillators LFXT1 and XT2.
3.4 Interrupt Processing
The MSP430 programmable interrupt structure allows flexible on-chip and external interrupt configurations to meet real-time interrupt-driven system requirements. Interrupts may be initiated by the processor's operating conditions such as watchdog overflow; or by peripheral modules or external events. Each interrupt source can be disabled individually by an interrupt enable bit, or all maskable interrupts can be disabled by the general interrupt enable (GIE) bit in the status register. Whenever an interrupt is requested and the appropriate interrupt enable bit and general interrupt enable (GIE) bit are set, the interrupt service routine becomes active as follows: 1) CPU active: The currently executing instruction is completed. 2) CPU stopped: The low-power modes are terminated. 3) The program counter pointing to the next instruction is pushed onto the stack. 4) The status register is pushed onto the stack. 5) The interrupt with the highest priority is selected if multiple interrupts occurred during the last instruction and are pending for service. 6) The appropriate interrupt request flag resets automatically on singlesource flags. Multiple source flags remain set for servicing by software. 7) The GIE bit is reset; the CPUOff bit, the OscOff bit, and the SCG1 bit are cleared; the status bits V, N, Z, and C are reset. SCG0 is left unchanged.
System Resets, Interrupts, and Operating Modes
3-9
Interrupt Processing
8) The content of the appropriate interrupt vector is loaded into the program counter: the program continues with the interrupt handling routine at that address. The interrupt latency is six cycles, starting with the acceptance of an interrupt request, and lasting until the start of execution of the appropriate interrupt-service routine first instruction, as shown in Figure 3-7.
Figure 3-7. Interrupt Processing
Before Interrupt After Interrupt
Item1 SP Item2 TOS
Item1 Item2 PC SP SR TOS
The interrupt handling routine terminates with the instruction:
RETI (return from an interrupt service routine)
which performs the following actions: 1) The status register with all previous settings pops from the stack. All previous settings of GIE, CPUOFF, etc. are now in effect, regardless of the settings utilized during the interrupt service routine. 2) The program counter pops from the stack and begins execution at the point where it was interrupted. The return from the interrupt is illustrated in Figure 3-8.
Figure 3-8. Return From Interrupt
Before Return From Interrupt Item1 Item2 PC SP SR TOS SP Item1 Item2 PC SR TOS After
A RETI instruction takes five cycles. Interrupt nesting is activated if the GIE bit is set inside the interrupt handling routine. The GIE bit is located in status register SR/R2, which is included in the CPU as shown in Figure 3-9.
3-10
Interrupt Processing
Figure 3-9. Status Register (SR)
15 Reserved For Future Enhancements 8 V 7 SCG1 SCG0 OSC CPU GIE Off Off N Z 0 C
rw-0
Apart from the GIE bit, other sources of interrupt requests can be enabled/ disabled individually or in groups. The interrupt enable flags are located together within two addresses of the special-function registers (SFRs). The program-flow conditions on interrupt requests can be easily adjusted using the interrupt enable masks. The hardware serves the highest priority within the empowered interrupt source.
3.4.1
Interrupt Control Bits in Special-Function Registers (SFRs)
Most of the interrupt control bits, interrupt flags, and interrupt enable bits are collected in SFRs under a few addresses, as shown in Table 3-1. The SFRs are located in the lower address range and are implemented in byte format. SFRs must be accessed using byte instructions.
Table 3-1. Interrupt Control Bits in SFRs
Address 000Fh 000Eh 000Dh 000Ch 000Bh 000Ah 0009h 0008h 0007h 0006h 0005h 0004h 0003h 0002h 0001h 0000h 7 0 Not yet defined or implemented Not yet defined or implemented Not yet defined or implemented Not yet defined or implemented Not yet defined or implemented Not yet defined or implemented Not yet defined or implemented Not yet defined or implemented Not yet defined or implemented Not yet defined or implemented Module enable 2 (ME2.x) Module enable 1 (ME1.x) Interrupt flag reg. 2 (IFG2.x) Interrupt flag reg. 1 (IFG1.x) Interrupt enable 2 (IE2.x) Interrupt enable 1 (IE1.x)
The MSP430 family supports SFRs by applying the correct logic and functions to each individual module. Each module interrupt source can be individually enabled or disable using the bits described in Table 3-2. The interrupt-flag registers are described in Table 3-3. The module-enable bits are described in Table 3-4.
System Resets, Interrupts, and Operating Modes
3-11
Interrupt Processing
Table 3-2. Interrupt Enable Registers 1 and 2
Bit Position IE1.0 Short Form Initial State WDTIE Reset Comments Watchdog timer enable signal. Inactive if watchdog mode is selected. Active if watchdog timer is configured as general-purpose timer. Oscillator fault interrupt enable Not implemented Not implemented NMIIE ACCVIE URXIE0 UTXIE0 Reset Reset Reset Reset NMI interrupt enable Flash access violation enable USART0 receive interrupt enable (13x, 14x devices) USART0 transmit interrupt enable (13x, 14x devices) Not implemented Not implemented Not implemented Not implemented URXIE1 UTXIE1 Reset Reset USART1 receive interrupt enable (14x devices) USART1 transmit interrupt enable (14x devices) Not implemented Not implemented
IE1.1 IE1.2 IE1.3 IE1.4 IE1.5 IE1.6 IE1.7 IE2.0 IE2.1 IE2.2 IE2.3 IE2.4 IE2.5 IE2.6 IE2.7
OFIE
Reset
The initial state is the logical state after the PUC signal.
3-12
Interrupt Processing
Table 3-3. Interrupt Flag Register 1 and 2
Bit Position IFG1.0 Short Form Initial State WDTIFG Set Or reset IFG1.1 IFG1.2 IFG1.3 IFG1.4 IFG1.5 IFG1.6 IFG1.7 IFG2.0 IFG2.1 IFG2.2 IFG2.3 IFG2.4 IFG2.5 IFG2.6 IFG2.7
Note:
Comments Set on watchdog timer overflow in watchdog mode or security key violation. Reset with VCC power-up, or a reset condition at the RST/NMI pin in reset mode. Flag set on oscillator fault Not implemented Not implemented
OFIFG
Set
NMIIFG
Reset
Set through the RST/NMI pin Not implemented
URXIFG0 UTXIFG0
Reset Set
USART0 receive flag (13x, 14x devices) USART0 transmitter ready (13x, 14x devices) Not implemented Not implemented Not implemented Not implemented
URXIFG1 UTXIFG1
Reset Set
USART1 receive flag (14x devices) USART1 transmitter ready (14x devices) Not implemented Not implemented
The configuration of some MSP430 devices may differ slightly from those in above table. Refer to specific device data sheets for individual configurations.
System Resets, Interrupts, and Operating Modes
3-13
Interrupt Processing
Table 3-4. Module Enable Registers 1 and 2
Bit Position ME1.0 ME1.1 ME1.2 ME1.3 ME1.4 ME1.5 ME1.6 ME1.7 ME2.0 ME2.1 ME2.2 ME2.3 ME2.4 ME2.5 ME2.6 ME2.7
Note:
Short Form
Initial State
Comments Reserved Reserved Reserved Reserved Reserved Reserved
URXE0 USPIE0 UTXE0
Reset Reset Reset
USART0 receiver enable (UART mode) USART0 transmit and receive enable (SPI mode) USART0 transmit enable (UART mode) Reserved Reserved Reserved Reserved
URXE1 USPIE1 UTXE1
Reset Reset Reset
USART1 receiver enable (UART mode) USART1 transmit and receive enable (SPI mode) USART1 transmit enable (UART mode) Reserved Reserved
The configuration of some MSP430 devices may differ slightly from those in above table. Refer to specific device data sheets for individual configurations.
3-14
Interrupt Processing
3.4.2
Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the ROM, using the address range 0FFFFh - 0FFE0h as described in Table 3-5. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. The interrupt vectors for 14x devices are shown in Table 3-5 in decreasing order of priority. See device data sheet for interrupt vectors for a specific device.
Table 3-5. Interrupt Sources, Flags, and Vectors of 14x Configurations
INTERRUPT SOURCE Power-up External Reset Watchdog Flash memory NMI Oscillator Fault Flash memory access violation Timer_B7 Timer_B7 Comparator_A Watchdog timer USART0 receive USART0 transmit ADC Timer_A3 Timer_A3 INTERRUPT FLAG WDTIFG KEYV (see Note 1) NMIIFG (see Notes 1 & 3) OFIFG (see Notes 1 & 3) ACCVIFG (see Notes 1 & 3) BCCIFG0 (see Note 2) BCCIFG1 to BCCIFG6 TBIFG (see Notes 1 & 2) CMPAIFG WDTIFG URXIFG0 UTXIFG0 ADCIFG (see Notes 1 & 2) CCIFG0 (see Note 2) CCIFG1, CCIFG2, TAIFG (see Notes 1 & 2) P1IFG.0 (see Notes 1 & 2) To P1IFG.7 (see Notes 1 & 2) URXIFG1 UTXIFG1 P2IFG.0 (see Notes 1 & 2) To P2IFG.7 (see Notes 1 & 2) Maskable SYSTEM INTERRUPT Reset WORD ADDRESS 0FFFEh PRIORITY 15, highest
(Non)maskable (Non)maskable (Non)maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable
0FFFCh 0FFFAh 0FFF8h 0FFF6h 0FFF4h 0FFF2h 0FFF0h 0FFEEh 0FFECh 0FFEAh
14 13 12 11 10 9 8 7 6 5
I/O port P1 (eight flags) USART1 receive USART1 transmit I/O port P2 (eight flags)
Maskable Maskable
0FFE8h 0FFE6h 0FFE4h 0FFE2h 0FFE0h
4 3 2 1 0, lowest
NOTES: 1. Multiple source flags 2. Interrupt flags are located in the module. 3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable can not disable it. Note: Some MSP430 devices have different implementations, See device datasheet for details.
3.4.2.1
External Interrupts
All eight bits of ports P1 and P2 are designed for interrupt processing of external events. All individual I/O bits are independently programmable. Any combinations of inputs, outputs, and interrupt conditions are possible. This allows easy adaptation to different I/O configurations. See Chapter I/O Ports for more details on I/O ports.
System Resets, Interrupts, and Operating Modes
3-15
Operating Modes
3.5 Operating Modes
The MSP430 family was developed for ultralow-power applications and uses different levels of operating modes. The MSP430 operating modes, shown in Figure 3-10, give advanced support to various requirements for ultralow power and ultralow energy consumption. This support is combined with an intelligent management of operations during the different module and CPU states. An interrupt event wakes the system from each of the various operating modes and the RETI instruction returns operation to the mode that was selected before the interrupt event. The ultra-low power system design which uses complementary metal-oxide semiconductor (CMOS) technology, takes into account three different needs:
-
The desire for speed and data throughput despite conflicting needs for ultra-low power Minimization of individual current consumption Limitation of the activity state to the minimum required by the use of low power modes
There are four bits that control the CPU and the main parts of the operation of the system clock generator: CPUOff, OscOff, SCG0, and SCG1. These four bits support discontinuous active mode (AM) requests, to limit the time period of the full operating mode, and are located in the status register. The major advantage of including the operating mode bits in the status register is that the present state of the operating condition is saved onto the stack during an interrupt service request. As long as the stored status register information is not altered, the processor continues (after RETI) with the same operating mode as before the interrupt event. Another program flow may be selected by manipulating the data stored on the stack or the stack pointer. Being able to access the stack and stack pointer with the instruction set allows the program structures to be individually optimized, as illustrated in the following program flow:
-
Enter interrupt routine
The interrupt routine is entered and processed if an enabled interrupt awakens the MSP430:
J J
The SR and PC are stored on the stack, with the content present at the interrupt event. Subsequently, the operation mode control bits OscOff, SCG1, and CPUOff are cleared automatically in the status register.
3-16
Operating Modes
-
Return from interrupt
Two different modes are available to return from the interrupt service routine and continue the flow of operation:
J J
Return with low-power mode bits set. When returning from the interrupt, the program counter points to the next instruction. The instruction pointed to is not executed, since the restored low power mode stops CPU activity. Return with low-power mode bits reset. When returning from the interrupt, the program continues at the address following the instruction that set the OscOff or CPUOff-bit in the status register. To use this mode, the interrupt service routine must reset the OscOff, CPUOff, SCGO, and SCG1 bits on the stack. Then, when the SR contents are popped from the stack upon RETI, the operating mode will be active mode (AM).
There are six operating modes that the software can configure:
-
Active mode AM; SCG1=0, SCG0=0, OscOff=0, CPUOff=0: CPU clocks are active Low power mode 0 (LPM0); SCG1=0, SCG0=0, OscOff=0, CPUOff=1:
CPU is disabled MCLK is disabled SMCLK and ACLK remain active
Low power mode 1 (LPM1); SCG1=0, SCG0=1, OscOff=0, CPUOff=1: CPU is disabled MCLK is disabled DCO's dc generator is disabled if the DCO is not used for MCLK or SMCLK when in active mode. Otherwise, it remains enabled. SMCLK and ACLK remain active
System Resets, Interrupts, and Operating Modes
3-17
Operating Modes
-
Low power mode 2 (LPM2); SCG1=1, SCG0=0, OscOff=0, CPUOff=1:
CPU is disabled MCLK is disabled SMCLK is disabled DCO oscillator automatically disabled because it is not needed for MCLK or SMCLK DCO's dc-generator remains enabled ACLK remains active
-
Low power mode 3 (LPM3); SCG1=1, SCG0=1, OscOff=0, CPUOff=1:
CPU is disabled MCLK is disabled SMCLK is disabled DCO oscillator is disabled DCO's dc-generator is disabled ACLK remains active
-
Low power mode 4 (LPM4); SCG1=X, SCG0=X, OscOff=1, CPUOff=1:
CPU is disabled ACLK is disabled MCLK is disabled SMCLK is disabled DCO oscillator is disabled DCO's dc-generator is disabled Crystal oscillator is stopped
Note: Peripheral operation is not halted by CPUOff. Peripherals are controlled by their individual control registers.
3-18
Operating Modes
Table 3-6. Low Power Mode Logic Chart for Basic Clock System
SCG1 LPM0 LPM1 LPM2 LPM3 LPM4 0 0 1 1 1 SCG0 0 1 0 1 1 OscOff 0 0 0 0 1 CPUOff 1 1 1 1 1
These modes are illustrated in Figure 3-11.
Figure 3-10. MSP430x1xx Operating Modes For Basic Clock System
RST/NMI Reset Active VCC On
POR WDT Active, Time Expired, Overflow WDTIFG = 1 WDTIFG = 1 WDT Active, Security Key Violation WDTIFG = 0 PUC RST/NMI is Reset Pin WDT is Active RST/NMI NMI Active
CPUOff = 1 SCG0,1 = 0 LP Mode LPM0 CPU Off, MCLK Off, SMCLK, ACLK On
Active Mode CPU Is Active Various Modules Are Active
CPUOff = 1 OscOff = 1 SG0,1 = 1 LP-Mode LPM4 CPU Off, MCLK Off, DCO Off, ACLK Off DC Generator Off
CPUOff = 1 SCG0 = 1 SCG1 = 0
LP Mode LPM1 CPU Off, MCLK Off, SMCLK, ACLK On DC Generator Off if DCO not used in active mode
CPUOff = 1 SCG0 = 0 SCG1 = 1
CPUOff = 1 SCG0,1 = 1
LP Mode LPM2 CPU Off, MCLK Off, SMCLK Off, DCO Off, ACLK On
LP Mode LPM3 CPU Off, MCLK Off, SMCLK Off, DCO Off ACLK On DC Generator Off
System Resets, Interrupts, and Operating Modes
3-19
Operating Modes
Figure 3-11. Typical Current Consumption of 13x and 14x Devices vs. Operating Modes
340
315 270 225 180 135 90 45 0
225
ICC/ A
VCC = 3 V VCC = 2.2 V
70 65 17 11 2 1 0.1 0.1
AM
LPM0
LPM2 LPM3 Operating Modes
LPM4
The low-power modes 1-4 enable or disable the CPU and the clocks. In addition to the CPU and clocks, enabling or disabling specific peripherals may further reduce total current consumption of the individual modes. The activity state of each peripheral is controlled by the control registers for the individual peripherals. In addition, the SFRs include module enable bits that may be used to enable or disable the operation of specific peripheral modules (see Table 3-4).
3.5.1
Low-Power Mode 0 and 1 (LPM0 and LPM1)
Low power mode 0 or 1 is selected if bit CPUOff in the status register is set. Immediately after the bit is set the CPU stops operation, and the normal operation of the system core stops. The operation of the CPU halts and all internal bus activities stop until an interrupt request or reset occurs. The system clock generator continues operation, and the clock signals MCLK, SMCLK, and ACLK stay active depending on the state of the other three status register bits, SCG0, SCG1, and OscOff. The peripherals are enabled or disabled with their individual control register settings, and with the module enable registers in the SFRs. All I/O port pins and RAM/registers are unchanged. Wake up is possible through all enabled interrupts. The following are examples of entering and exiting LPM0. The method shown is applicable to all low-power modes. The following example describes entering into low-power mode 0.
;===Main program flow with switch to CPUOff Mode============== ; BIS #18h,SR ;Enter LPM0 + enable general interrupt GIE ;(CPUOff=1, GIE=1). The PC is incremented ;during execution of this instruction and ;points to the consecutive program step. ...... ;The program continues here if the CPUOff ;bit is reset during the interrupt service ;routine. Otherwise, the PC retains its ;value and the processor returns to LPM0.
3-20
Operating Modes
The following example describes clearing low-power mode 0.
;===Interrupt service routine================================= ...... ;CPU is active while handling interrupts BIC #10h,0(SP) ;Clears the CPUOff bit in the SR contents ;that were stored on the stack. RETI ;RETI restores the CPU to the active state ;because the SR values that are stored on ;the stack were manipulated. This occurs ;because the SR is pushed onto the stack ;upon an interrupt, then restored from the ;stack after the RETI instruction.
3.5.2
Low-Power Modes 2 and 3 (LPM2 and LPM3)
Low-power mode 2 or 3 is selected if bits CPUOff and SCG1 in the status register are set. Immediately after the bits are set, CPU, MCLK, and SMCLK operations halt and all internal bus activities stop until an interrupt request or reset occurs. Peripherals that operate with the MCLK or SMCLK signal are inactive because the clock signals are inactive. Peripherals that operate with the ACLK signal are active or inactive according with the individual control registers and the module enable bits in the SFRs. All I/O port pins and the RAM/registers are unchanged. Wake up is possible by enabled interrupts coming from active peripherals or RST/NMI.
3.5.3
Low-Power Mode 4 (LPM4)
In low power mode 4 all activities cease; only the RAM contents, I/O ports, and registers are maintained. Wake up is only possible by enabled external interrupts. Before activating LPM4, the software should consider the system conditions during the low power mode period . The two most important conditions are environmental (that is, temperature effect on the DCO), and the clocked operation conditions. The environment defines whether the value of the frequency integrator should be held or corrected. A correction should be made when ambient conditions are anticipated to change drastically enough to increase or decrease the system frequency while the device is in LPM4.
System Resets, Interrupts, and Operating Modes
3-21
Basic Hints for Low-Power Applications
3.6 Basic Hints for Low-Power Applications
There are some basic practices to follow when current consumption is a critical part of a system application:
-
Switch off analog circuitry when possible. Select the lowest possible operating frequency for the core and the individual peripheral module. Use the interrupt driven software; the program starts execution rapidly. Tie all unused inputs to an applicable voltage level. The list below defines the correct termination for all unused pins.
Pin AVCC: AVSS: Xout: XIN XT2IN XT2OUT Px.0 to Px.7: RST/NMI: Test/VPP Test TDO: TDI: TMS: TCK: Refer to device specific datasheets for the correct termination of these pins.
Potential
DVCC DVSS open DVSS DVSS open open
Comment
13x and 14x devices 13x and 14x devices Unused ports switched to port function and output direction 11x devices 11x1 devices
DVCC resp.VCC Pullup resistor 100k DVSS DVSS
3-22
Chapter 4
Memory
MSP430 devices are configured as a von-Neumann architecture. It has code memory, data memory, and peripherals in one address space. As a result, the same instructions are used for code, data, or peripheral accesses. Also, code may be executed from RAM.
Topic
4.1 4.2 4.3 4.4
Page
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Data in the Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Internal ROM Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 RAM and Peripheral Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Memory
4-1
Introduction
4.1 Introduction
All of the physically separated memory areas (ROM, RAM, SFRs, and peripheral modules) are mapped into the common address space, as shown in Figure 4-1 for the MSP430 family. The addressable memory space is 64KB. Future expansion is possible.
Figure 4-1. Memory Map of Basic Address Space
Address (Hex.) 0FFFFh 0FFE0h 0FFDFh Function Access
Interrupt Vector Table Program Memory Branch Control Tables Data Tables...
ROM
Word/Byte
ROM
Word/Byte
0200h 01FFh
Data Memory
RAM Timer, ADC, . . . I/O, LCD 8bT/C, . . . SFR
Word/Byte Word
16-Bit Peripheral Modules 0100h 0FFh 010h 0Fh 0h 8-Bit Peripheral Modules Special Function Registers
Byte Byte
The memory data bus (MDB) is 16- or 8-bits wide. For those modules that can be accessed with word data the width is always 16 bits. For the other modules, the width is 8 bits, and they must be accessed using byte instructions only. The program memory (ROM) and the data memory (RAM) can be accessed with byte or word instructions.
Figure 4-2. Memory Data Bus
Address Range 0000h - 00FFh LCD USART High Byte Data Bus Low Byte SFRs COMPARATOR_A Byte/Word Access ADC WDT ROM RAM CPU
8-Bit Peripheral Modules, Byte Access
16-Bit Peripheral Modules, Word Access
4-2
Data in the Memory
4.2 Data in the Memory
Bytes are located at even or odd addresses as shown in Figure 4-3. However, words are only located at even addresses. Therefore, when using word instructions, only even addresses may be used. The low byte of a word is always at an even address. The high byte of a word is at the next odd address after the address of the word. For example, if a data word is located at address xxx2h, then the low byte of that data word is located at address xxx2h, and the high byte of that word is located at address xxx3h.
Figure 4-3. Bits, Bytes, and Words in a Byte-Organized Memory
xxxAh 15 7 14 6 . . Bits . . . . Bits . . Byte Byte Word (High Byte) Word (Low Byte) 9 1 8 0 xxx9h xxx8h xxx7h xxx6h xxx5h xxx4h xxx3h
Memory
4-3
Internal ROM Organization
4.3 Internal ROM Organization
Various sizes of ROM (OTP, masked-ROM, EPROM, or FLASH) are available within the 64-kB address space, as shown in Figure 4-4. The common address space is shared with SFRs, peripheral module registers, data and code memory. The SFRs and peripheral modules are mapped into the address range, starting with 0 and ending with 01FFh. The remaining address space, 0200h to 0FFFFh, is shared by data and code memory. The start address for ROM depends on the amount of ROM present. The interrupt vector table is mapped into the the upper 16 words of ROM address space, with the highest priority interrupt vector at the highest ROM word address (0FFFEh). See the individual data sheets for specific memory maps.
Figure 4-4. ROM Organization
0FFFEh 0FFE0h Vectors 4k 0F000h 0EFFFh 12 k Vectors Vectors Vectors
0D000h 0CFFFh
32 k xx k
08000h
4.3.1
Processing of ROM Tables
The MSP430 architecture allows for the storage and usage of large tables in ROM without the need to copy the tables to RAM before using them. This ROM accessing of tables allows fast and clear programming in applications where data tables are necessary. This offers the flexible advantages listed below, and saves on ROM and RAM requirements. To access these tables, all word and byte instructions can be used.
4-4
ROM storage of an output programmable logic array (OPLA) for display character conversion The use of as many OPLA terms as needed (no restriction on n terms) OTP version automatically includes OPLA programmability Computed table accessibility (for example, for a bar graph display) Table-supported program flows
Internal ROM Organization
4.3.2
Computed Branches and Calls
Computed branches and subroutine calls are possible using standard instructions. The call and branch instructions use the same addressing modes as the other instructions. The addressing modes allow indirect-indirect addressing that is ideally suited for computed branches and calls. This programming technique permits a program structure that is different from conventional 8- and 16-bit microcontrollers. Most of the routines can be handled easily by using software status handling instead of flag-type program-flow control. The computed branch and subroutine calls are valid throughout the entire ROM space.
Memory
4-5
RAM and Peripheral Organization
4.4 RAM and Peripheral Organization
The entire RAM can be accessed with byte or word instructions using the appropriate instruction suffix. The peripheral modules, however, are located in two different address spaces and must be accessed with the appropriate instruction length.
4.4.1
The SFRs are byte-oriented and mapped into the address space from 0h up to 0Fh. Peripheral modules that are byte-oriented are mapped into the address space from 010h up to 0FFh. Peripheral modules that are word-oriented are mapped into the address space from 100h up to 01FFh.
Random Access Memory
RAM can be used for both code and data memory. Code accesses are always performed on even byte addresses. The instruction mnemonic suffix defines the data as being word or byte data. Example:
MOV.B ADD ADDC TXDATA,&UTXBUF0 R5,SUM_A = SUM_B = ADD.W ADDC.W R5,SUM_A SUM_A ;Byte access ;Word access ;Word access
A word consists of two bytes: a high byte (bit 15 to bit 8), and a low byte (bit 7 to bit 0) as shown in Figure 4-5. It must always align to an even address.
Figure 4-5. Byte and Word Operation
xxxAh Byte1: 012h Byte2: 034h Word1 (High Byte): 056h Word1 (Low Byte): 078h Word2 (High Byte): 09Ah Word2 (Low Byte): 0BCh ADD.B Byte1, Byte2: xxx9h Byte2 = 012h + 034h = 046h xxx8h xxx7h xxx6h ADD.W Word1, Word2: xxx5h Word2 = 05678h + 09ABCh = 0F134h xxx4h xxx3h
All operations on the stack and PC are word operations and use even-aligned memory addresses.
4-6
RAM and Peripheral Organization
In the following examples, word-to-word and byte-to-byte operations show the results of the operation and the status bit information. Example Word-Word Operation R5 = 0F28Eh EDE .EQU 0212h Mem(0F28Eh) = 0FFFEh Mem(0212h) = 00112h ADD @R5,&EDE Example Byte-Byte Operation R5 = 0223h EDE .EQU 0202h Mem(0223h) = 05Fh Mem(0202h) = 043h ADD.B @R5,&EDE
Mem(0212h) = 00110h C = 1, Z = 0, N = 0
Mem(0202h) = 0A2h C = 0, Z = 0, N = 1
Figure 4-6 shows the register-byte and byte-register operations.
Figure 4-6. Register-Byte/Byte-Register Operations
Register-Byte Operation High Byte Unused Low Byte Register Byte-Register Operation High Byte Low Byte Byte Memory
Byte
Memory
0h
Register
The following examples describe the register-byte and byte-register operations. Example Register-Byte Operation Example Byte-Register Operation R5 = 0A28Fh R6 = 0203h Mem(0203h) = 012h ADD.B R5,0(R6) 08Fh + 012h 0A1h Mem (0203h) = 0A1h C = 0, Z = 0, N = 1 (Low byte of register) + (Addressed byte) ->(Addressed byte) R5 = 01202h R6 = 0223h Mem(0223h) = 05Fh ADD.B 05Fh + 002h 00061h R5 = 00061h C = 0, Z = 0, N = 0 (Addressed byte) + (Low byte of register) ->(Low byte of register, zero to High byte) ;Low byte of R5 ;->Store into R5 ;High byte is 0 @R6,R5
Memory
4-7
RAM and Peripheral Organization
Note: Word-Byte Operations Word-byte or byte-word operations on memory data are not supported. Each register-byte or byte-register is performed as a byte operation.
4.4.2
Peripheral Modules--Address Allocation
Some peripheral modules are accessible only with byte instructions, while others are accessible only with word instructions. The address space from 0100 to 01FFh is reserved for word modules, and the address space from 00h to 0FFh is reserved for byte modules. Peripheral modules that are mapped into the word address space must be accessed using word instructions (for example, MOV R5,&WDTCTL). Peripheral modules that are mapped into the byte address space must be accessed with byte instructions (MOV.B #1,&P1OUT). The addressing of both is through the absolute addressing mode or the 16-bit working registers using the indexed, indirect, or indirect autoincrement addressing mode. See Figure 4-7 for the RAM/peripheral organization.
Figure 4-7. Example of RAM/Peripheral Organization
Address (Hex.) 01FFh 16-Bit Peripheral Modules 0100h 0FFh 010h 0Fh 0h Function 7 0 Timer, ADC, . . . I/O, USART Comparator_A, . . . SFR Word Access
8-Bit Peripheral Modules Special Function Registers
Byte Byte
4.4.2.1
Word Modules
Word modules are peripherals that are connected to the 16-bit MDB. Word modules can be accessed with word or byte instructions. If byte instructions are used, only even addresses are permissible, and the high byte of the result is always '0'. The peripheral file address space is organized into sixteen frames with each frame representing eight words as described in Table 4-1.
4-8
RAM and Peripheral Organization
Table 4-1. Peripheral File Address Map--Word Modules
Address 1F0h - 1FFh 1E0h - 1EFh 1D0h - 1DFH 1C0h - 1CFH 1B0h - 1BFH 1A0h - 1AFH 190h - 19FH 180h - 18FH 170h - 17FH 160h - 16FH 150h - 15FH 140h - 14FH 130h - 13FH 120h - 12FH 110h - 11FH 100h - 10FH Description Reserved Reserved Reserved Reserved Reserved ADC12 control and interrupt Timer_B Timer_B Timer_A Timer_A ADC12 conversion ADC12 conversion Multiplier Watchdog Timer, Flash control Reserved Reserved
4.4.2.2
Byte Modules
Byte modules are peripherals that are connected to the reduced (eight LSB) MDB. Access to byte modules is always by byte instructions. The hardware in the peripheral byte modules takes the low byte (the LSBs) during a write operation. Byte instructions operate on byte modules without any restrictions. Read access to peripheral byte modules using word instructions results in unpredictable data in the high byte. Word data is written into a byte module by writing the low byte to the appropriate peripheral register and ignoring the high byte. The peripheral file address space is organized into sixteen frames as described in Table 4-2.
Memory
4-9
RAM and Peripheral Organization
Table 4-2. Peripheral File Address Map--Byte Modules
Address 00F0h - 00FFh 00E0h - 00EFh 00D0h - 00DFh 00C0h - 00CFh 00B0h - 00BFh 00A0h - 00AFh 0090h - 009Fh 0080h - 008Fh 0070h - 007Fh 0060h - 006Fh 0050h - 005Fh 0040h - 004Fh 0030h - 003Fh 0020h - 002Fh 0010h - 001Fh 0000h - 000Fh Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved ADC12 memory control USART0, USART1 Reserved System clock generator, Comparator A Reserved Digital I/O port P5, digital I/O port P6 Digital I/O port P1 and P2 control Digital I/O port P3, and P4 control Special function
4.4.3
Peripheral Modules-Special Function Registers (SFRs)
The system configuration and the individual reaction of the peripheral modules to the processor operation is configured in the SFRs as described in Table 4-3. The SFRs are located in the lower address range, and are organized by bytes. SFRs must be accessed using byte instructions only.
4-10
RAM and Peripheral Organization
Table 4-3. Special Function Register Address Map
Address 7 000Fh 000Eh 000Dh 000Ch 000Bh 000Ah 0009h 0008h 0007h 0006h 0005h 0004h 0003h 0002h 0001h 0000h Data Bus 0 Not yet defined or implemented Not yet defined or implemented Not yet defined or implemented Not yet defined or implemented Not yet defined or implemented Not yet defined or implemented Not yet defined or implemented Not yet defined or implemented Not yet defined or implemented Not yet defined or implemented Module enable 2; ME2.2 Module enable 1; ME1.1 Interrupt flag reg. 2; IFG2.x Interrupt flag reg.1; IFG1.x Interrupt enable 2; IE2.x Interrupt enable 1; IE1.x
The system power consumption is influenced by the number of enabled modules and their functions. Disabling a module from the actual operation mode reduces power consumption while other parts of the controller remain fully active (unused pins must be tied appropriately or power consumption will increase; see Basic Hints for Low Power Applications in section 3.6.
Memory
4-11
4-12
Chapter 5
16-Bit CPU
The MSP430 von-Neumann architecture has RAM, ROM, and peripherals in one address space, both using a single address and data bus. This allows using the same instruction to access either RAM, ROM, or peripherals and also allows code execution from RAM.
Topic
5.1 5.2 5.3 5.4
Page
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 Instruction Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 Instruction Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
16-Bit CPU
5-1
CPU Registers
5.1 CPU Registers
Sixteen 16-bit registers (R0, R1, and R4 to R15) are used for data and addresses and are implemented in the CPU. They can address up to 64 Kbytes (ROM, RAM, peripherals, etc.) without any segmentation. The complete CPU-register set is described in Table 5-1. Registers R0, R1, R2, and R3 have dedicated functions, which are described in detail later.
Table 5-1. Register by Functions
Program counter (PC) Stack pointer (SP) Status register (SR) Constant generator (CG1) Constant generator (CG2) Working register R4 Working register R5 : : Working register R13 Working register R14 Working register R15 R0 R1 R2 R3 R4 R5 : : R13 R14 R15
5.1.1
The Program Counter (PC)
The 16-bit program counter points to the next instruction to be executed. Each instruction uses an even number of bytes (two, four, or six), and the program counter is incremented accordingly. Instruction accesses are performed on word boundaries, and the program counter is aligned to even addresses. Figure 5-1 shows the program counter bits.
Figure 5-1. Program Counter
15 Program Counter Bits 15 to 1 1 0 0
5.1.2
The System Stack Pointer (SP)
The system stack pointer must always be aligned to even addresses because the stack is accessed with word data during an interrupt request service. The system SP is used by the CPU to store the return addresses of subroutine calls and interrupts. It uses a predecrement, postincrement scheme. The advantage of this scheme is that the item on the top of the stack is available. The SP can be used by the user software (PUSH and POP instructions), but the user should remember that the CPU also uses the SP. Figure 5-2 shows the system SP bits.
Figure 5-2. System Stack Pointer
15 System Stack Pointer Bits 15 to 1 1 0 0
5-2
CPU Registers
5.1.2.1
Examples for System SP Addressing (Refer to Figure 5-4)
MOV MOV MOV MOV MOV PUSH POP MOV SP,R4 @SP,R5 2(SP),R6 R7,0(SP) R8,4(SP) R12 R12 @SP+,R5 ; SP -> R4 ; Item I3 (TOS) -> R5 ; Item I2 -> R6 ; Overwrite TOS with R7 ; Modify item I1 ; Store R12 in address 0xxxh - 6; SP points to same address ; Restore R12 from address 0xxxh - 6; SP points to 0xxxh - 4 ; Item I3 -> R5 (popped from stack); same as POP instruction
Figure 5-3 shows stack usage.
Figure 5-3. Stack Usage
Address 0xxxh 0xxxh - 2 0xxxh - 4 0xxxh - 6 0xxxh - 8 I1 I2 I3 SP PUSH #1 I1 I2 I3 #1 SP POP R8 I1 I2 I3 SP
5.1.2.2
Special Cases--PUSH SP and POP SP
The special cases of using the SP as an argument to the PUSH and POP instructions are described below.
Figure 5-4. PUSH SP and POP SP
PUSH SP POP SP
SPold SP1 SP1 SP2 SP1
The stack pointer is changed after a PUSH SP instruction.
The stack pointer is not changed after a POP SP instruction.
After the sequence
PUSH SP I I POP SP ; SP1 is stack pointer after this instruction
; SP2 is stack pointer after this instruction
The stack pointer is two bytes lower than before this sequence.
16-Bit CPU
5-3
CPU Registers
5.1.3
The Status Register (SR)
The status register SR contains the following CPU status bits:
15
V SCG1 SCG0 OscOff CPUOff GIE N Z C
Overflow bit System clock generator control bit 1 System clock generator control bit 0 Crystal oscillator off bit CPU off bit General interrupt enable bit Negative bit Zero bit Carry bit
Figure 5-5 shows the SR bits.
Figure 5-5. Status Register Bits
9 8 V 7 SCG1 SCG0 OSC CPU GIE Off Off N Z 0 C Reserved For Future Enhancements
rw-0
Table 5-2 describes the status register bits.
Table 5-2. Description of Status Register Bits
Bit V Description Overflow bit. Set if the result of an arithmetic operation overflows the signed-variable range. The bit is valid for both data formats, byte and word: ADD(.B), ADDC(.B) Set when: Positive + Positive = Negative Negative + Negative = Positive, otherwise reset Set when: Positive - Negative = Negative Negative - Positive = Positive, otherwise reset
SUB(.B), SUBC(.B), CMP(.B)
SCG1, SCG0 OscOFF
These bits control four activity states of the system-clock generator and therefore influence the operation of the processor system. If set, the crystal oscillator enters off mode: all activities cease; however, the RAM contents, the port, and the registers are maintained. Wake up is possible only through enabled external interrupts when the GIE bit is set and from the NMI. If set, the CPU enters off mode: program execution stops. However, the RAM, the port registers, and especially the enabled peripherals (for example, Timer_A, UART, etc.) stay active. Wake up is possible through all enabled interrupts. If set, all enabled maskable interrupts are handled. If reset, all maskable interrupts are disabled. The GIE bit is cleared by interrupts and restored by the RETI instruction as well as by other appropriate instructions. Set if the result of an operation is negative. Word operation: Negative bit is set to the value of bit 15 of the result Byte operation: Negative bit is set to the value of bit 7 of the result Set if the result of byte or word operation is 0; cleared if the result is not 0. Set if the result of an operation produced a carry; cleared if no carry occurred. Some instructions modify the carry bit using the inverted zero bits.
CPU Off
GIE
N
Z C
5-4
CPU Registers
Note: Status Register Bits V, N, Z, and C The status register bits V, N, Z, and C are modified only with the appropriate instruction. For additional information, see the detailed description of the instruction set in Appendix B.
5.1.4
The Constant Generator Registers CG1 and CG2
Commonly-used constants are generated with the constant generator registers R2 and R3, without requiring an additional 16-bit word of program code. The constant used for immediate values is defined by the addressing mode bits (As) as described in Table 5-3. See Section 5.3 for a description of the addressing mode bits (As).
Table 5-3. Values of Constant Generators CG1, CG2
Register R2 R2 R2 R2 R3 R3 R3 R3 As 00 01 10 11 00 01 10 11 Constant ----- (0) 00004h 00008h 00000h 00001h 00002h 0FFFFh Remarks Register mode Absolute address mode +4, bit processing +8, bit processing 0, word processing +1 +2, bit processing -1, word processing
The major advantages of this type of constant generation are:
-
No special instructions required Reduced code memory requirements: no additional word for the six most used constants Reduced instruction cycle time: no code memory access to retrieve the constant
The assembler uses the constant generator automatically if one of the six constants is used as a source operand in the immediate addressing mode. The status register SR/R2, used as a source or destination register, can be used in the register mode only. The remaining combinations of addressing-mode bits are used to support absolute-address modes and bit processing without any additional code. Registers R2 and R3, used in the constant mode, cannot be addressed explicitly; they act like source-only registers.
16-Bit CPU
5-5
CPU Registers
The RISC instruction set of the MSP430 only has 27 instructions. However, the constant generator allows the MSP430 assembler to support 24 additional, emulated instructions. For example, the single-operand instruction: CLR dst
is emulated by the double-operand instruction with the same length: MOV R3,dst or the equivalent MOV #0,dst where #0 is replaced by the assembler, and R3 is used with As = 00, which results in:
-
One word instruction No additional control operation or hardware within the CPU Register-addressing mode for source: no additional fetch cycle for the constant (#0)
5-6
Addressing Modes
5.2 Addressing Modes
All seven addressing modes for the source operand and all four addressing modes for the destination operand can address the complete address space. The bit numbers in Table 5-4 describe the contents of the As and Ad mode bits. See Section 5.3 for a description of the source address As and the destination address Ad bits.
Table 5-4. Source/Destination Operand Addressing Modes
As/Ad 00/0 01/1 Addressing Mode Register mode Indexed mode Syntax Rn X(Rn) Description Register contents are operand (Rn + X) points to the operand X is stored in the next word 01/1 Symbolic mode ADDR (PC + X) points to the operand X is stored in the next word. Indexed mode X(PC) is used. 01/1 10/- 11/- Absolute mode Indirect register mode Indirect autoincrement Immediate mode &ADDR @Rn @Rn+ The word following the instruction contains the absolute address. Rn is used as a pointer to the operand. Rn is used as a pointer to the operand. Rn is incremented afterwards. The word following the instruction contains the immediate constant N. Indirect autoincrement mode @PC+ is used.
11/-
#N
The seven addressing modes are explained in detail in the following sections. Most of the examples show the same addressing mode for the source and destination, but any valid combination of source and destination addressing modes is possible in an instruction.
16-Bit CPU
5-7
Addressing Modes
5.2.1
Register Mode
The register mode is described in Table 5-5.
Table 5-5. Register Mode Description
Assembler Code MOV R10,R11 Content of ROM MOV R10,R11
Length: Operation: Comment: Example:
Before: R10 0A023h
One or two words Move the content of R10 to R11. R10 is not affected. Valid for source and destination MOV R10,R11
After: R10 0A023h
R11
0FA15h
R11
0A023h
PC
PCold
PC
PCold + 2
Note: Data in Registers The data in the register can be accessed using word or byte instructions. If byte instructions are used, the high byte is always 0 in the result. The status bits are handled according to the result of the byte instruction.
5-8
Addressing Modes
5.2.2
Indexed Mode
The indexed mode is described in Table 5-6.
Table 5-6. Indexed Mode Description
Assembler Code MOV 2(R5),6(R6) Content of ROM MOV X(R5),Y(R6) X=2 Y=6
Length: Operation:
Two or three words Move the contents of the source address (contents of R5 + 2) to the destination address (contents of R6 + 6). The source and destination registers (R5 and R6) are not affected. In indexed mode, the program counter is incremented automatically so that program execution continues with the next instruction. Valid for source and destination MOV 2(R5),6(R6):
Register After: Address Space 0xxxxh 0FF16h 00006h 0FF14h 0FF12h 00002h 04596h Register PC R5 01080h R6 0108Ch
Comment: Example:
Before: Address Space
0FF16h 0FF14h 0FF12h
00006h 00002h 04596h PC
R5 R6
01080h 0108Ch
01094h 01092h 01090h
0xxxxh 05555h 0xxxxh
0108Ch +0006h 01092h
01094h 01092h 01090h
0xxxxh 01234h 0xxxxh
01084h 01082h 01080h
0xxxxh 01234h 0xxxxh
01080h +0002h 01082h
01084h 01082h 01080h
0xxxxh 01234h 0xxxxh
16-Bit CPU
5-9
Addressing Modes
5.2.3
Symbolic Mode
The symbolic mode is described in Table 5-7.
Table 5-7. Symbolic Mode Description
Assembler Code MOV EDE,TONI Content of ROM MOV X(PC),Y(PC) X = EDE - PC Y = TONI - PC
Length: Operation:
Two or three words Move the contents of the source address EDE (contents of PC + X) to the destination address TONI (contents of PC + Y). The words after the instruction contain the differences between the PC and the source or destination addresses. The assembler computes and inserts offsets X and Y automatically. With symbolic mode, the program counter (PC) is incremented automatically so that program execution continues with the next instruction. Valid for source and destination MOV EDE,TONI ;Source address EDE = 0F016h, ;dest. address TONI=01114h
After: Address Space 0xxxxh 011FEh 0F102h 04090h Register PC
Comment: Example:
Before:
Address Space 011FEh 0F102h 04090h PC
Register
0FF16h 0FF14h 0FF12h
0FF16h 0FF14h 0FF12h
0F018h 0F016h 0F014h
0xxxxh 0A123h 0xxxxh
0FF14h +0F102h 0F016h
0F018h 0F016h 0F014h
0xxxxh 0A123h 0xxxxh
01116h 01114h 01112h
0xxxxh 01234h 0xxxxh
0FF16h +011FEh 01114h
01116h 01114h 01112h
0xxxxh 0A123h 0xxxxh
5-10
Addressing Modes
5.2.4
Absolute Mode
The absolute mode is described in Table 5-8.
Table 5-8. Absolute Mode Description
Assembler Code MOV &EDE,&TONI Content of ROM MOV X(0),Y(0) X = EDE Y = TONI
Length: Operation:
Two or three words Move the contents of the source address EDE to the destination address TONI. The words after the instruction contain the absolute address of the source and destination addresses. With absolute mode, the PC is incremented automatically so that program execution continues with the next instruction. Valid for source and destination MOV &EDE,&TONI ;Source address EDE = 0F016h, ;dest. address TONI=01114h
After: Address Space 0xxxxh 01114h 0F016h 04292h Register PC
Comment: Example:
Before:
Address Space 01114h 0F016h 04292h PC
Register
0FF16h 0FF14h 0FF12h
0FF16h 0FF14h 0FF12h
0F018h 0F016h 0F014h
0xxxxh 0A123h 0xxxxh
0F018h 0F016h 0F014h
0xxxxh 0A123h 0xxxxh
01116h 01114h 01112h
0xxxxh 01234h 0xxxxh
01116h 01114h 01112h
0xxxxh 0A123h 0xxxxh
This address mode is mainly for hardware peripheral modules that are located at an absolute, fixed address. These are addressed with absolute mode to ensure software transportability (for example, position-independent code).
16-Bit CPU
5-11
Addressing Modes
5.2.5
Indirect Mode
The indirect mode is described in table 5-9.
Table 5-9. Indirect Mode Description
Assembler Code MOV @R10,0(R11) Content of ROM MOV @R10,0(R11)
Length: Operation:
One or two words Move the contents of the source address (contents of R10) to the destination address (contents of R11). The registers are not modified. Valid only for source operand. The substitute for destination operand is 0(Rd). MOV.B @R10,0(R11)
Register After: Address Space 0xxxxh 0FF16h 0000h 0FF14h 0FF12h 04AEBh 0xxxxh Register PC R10 0FA33h R11 002A7h
Comment:
Example:
Before: Address Space 0xxxxh 0000h 04AEBh 0xxxxh
0FF16h 0FF14h 0FF12h
R10 PC R11
0FA33h 002A7h
0FA34h 0FA32h 0FA30h
0xxxxh 05BC1h 0xxxxh
0FA34h 0FA32h 0FA30h
0xxxxh 05BC1h 0xxxxh
002A8h 002A7h 002A6h
0xxh 012h 0xxh
002A8h 002A7h 002A6h
0xxh 05Bh 0xxh
5-12
Addressing Modes
5.2.6
Indirect Autoincrement Mode
The indirect autoincrement mode is described in Table 5-10.
Table 5-10.Indirect Autoincrement Mode Description
Assembler Code MOV @R10+,0(R11) Content of ROM MOV @R10+,0(R11)
Length: Operation:
One or two words Move the contents of the source address (contents of R10) to the destination address (contents of R11). Register R10 is incremented by 1 for a byte operation, or 2 for a word operation after the fetch; it points to the next address without any overhead. This is useful for table processing. Valid only for source operand. The substitute for destination operand is 0(Rd) plus second instruction INCD Rd. MOV @R10+,0(R11)
Register After: Address Space 0xxxxh 00000h 0xxxxh PC R10 0FA34h R11 010A8h Register
Comment: Example:
Before:
Address Space 0xxxxh 00000h 0xxxxh
0FF18h 0FF16h 0FF12h
R10 PC R11
0FA32h 010A8h
0FF18h 0FF16h 0FF12h
0FF14h 04ABBh
0FF14h 04ABBh
0FA34h 0FA32h 0FA30h
0xxxxh 05BC1h 0xxxxh
0FA34h 0FA32h 0FA30h
0xxxxh 05BC1h 0xxxxh
010AAh 010A8h 010A6h
0xxxxh 01234h 0xxxxh
010AAh 010A8h 010A6h
0xxxxh 05BC1h 0xxxxh
The autoincrementing of the register contents occurs after the operand is fetched. This is shown in Figure 5-6.
Figure 5-6. Operand Fetch Operation
Instruction Address Operand +1/ +2
16-Bit CPU
5-13
Addressing Modes
5.2.7
Immediate Mode
The immediate mode is described in Table 5-11.
Table 5-11. Immediate Mode Description
Assembler Code MOV #45,TONI Content of ROM MOV @PC+,X(PC) 45 X = TONI - PC
Length:
Two or three words It is one word less if a constant of CG1 or CG2 can be used. Move the immediate constant 45, which is contained in the word following the instruction, to destination address TONI. When fetching the source, the program counter points to the word following the instruction and moves the contents to the destination. Valid only for a source operand. MOV #45,TONI
Address Space 01192h 00045h 040B0h PC Register After: Address Space 0xxxxh 01192h 00045h 040B0h Register PC
Operation:
Comment: Example:
Before:
0FF16h 0FF14h 0FF12h
0FF18h 0FF16h 0FF14h 0FF12h
010AAh 010A8h 010A6h
0xxxxh 01234h 0xxxxh
0FF16h +01192h 010A8h
010AAh 010A8h 010A6h
0xxxxh 00045h 0xxxxh
5-14
Addressing Modes
5.2.8
Clock Cycles, Length of Instruction
The operating speed of the CPU depends on the instruction format and addressing modes. The number of clock cycles refers to the MCLK.
5.2.8.1
Format-I Instructions
Table 5-12 describes the CPU format-I instructions and addressing modes.
Table 5-12.Instruction Format I and Addressing Modes
Address Mode As 00, Rn 00, Rn Ad 0, Rm 0, PC 1, x(Rm) 1, EDE 1, &EDE 0, Rm No. of Cycles 1 2 4 Length of Instruction 1 1 2 2 2 2 2 2 3 3 3 3 1 2 2 2 1 1 2 2 2 3 2 3 MOV BR ADD XOR MOR MOV AND MOV ADD CMP MOV ADD AND XOR MOV XOR ADD BR MOV BR MOV ADD MOV ADD Example R5,R8 R9 R5,3(R6) R8,EDE R5,&EDE 2(R5),R7 EDE,R6 &EDE,R8 3(R4),6(R9) EDE,TONI 2(R5),&TONI EDE,&TONI @R4,R5 @R5,8(R6) @R5,EDE @R5,&EDE @R5+,R6 @R9+ #20,R9 #2AEh @R9+,2(R4) #33,EDE @R9+,&EDE #33,&EDE
01, x(Rn) 01, EDE 01, &EDE 01, x(Rn) 01, EDE 01, &EDE 10, @Rn 10, @Rn
3
1, x(Rm) 1, TONI 1, &TONI 0, Rm 1, x(Rm) 1, EDE 1, &EDE 0, Rm 0, PC 0, Rm 0, PC 1, x(Rm) 1, EDE 1, &EDE
6
2 5
11, @Rn+ 11, #N 11, @Rn+ 11, #N 11, @Rn+ 11, #N
2 3 2 3 5
16-Bit CPU
5-15
Addressing Modes
5.2.8.2
Format-II Instructions
Table 5-13 describes the CPU format II instructions and addressing modes.
Table 5-13.Instruction Format-II and Addressing Modes
No. of Cycles RRA RRC SWPB SXT 1 4 4 3 3 Length of Instruction (words) 1 2 2 1 1 2
Address Mode A(s/d) 00, Rn 01, X(Rn) 01, EDE 01, &EDE 10, @Rn 11, @Rn+ (see Note) 11, #N
PUSH/ CALL 3/4 5 5 4 4/5
Example SWPB R5 CALL 2(R7) PUSH EDE SXT &EDE RRC @R9 SWPB @R10+ CALL #81H
Note: Instruction Format II Immediate Mode Do not use instructions RRA, RRC, SWPB, and SXT with the immediate mode in the destination field. Use of these in the immediate mode will result in an unpredictable program operation.
5.2.8.3
Format-III Instructions
Format-III instructions are described as follows: Jxx--all instructions need the same number of cycles, independent of whether a jump is taken or not. Clock cycle: Two cycles Length of instruction: One word
5.2.8.4
Miscellaneous-Format Instructions
Table 5-14 describes miscellaneous-format instructions.
Table 5-14.Miscellaneous Instructions or Operations
Activity RETI Interrupt WDT reset Reset (RST/NMI)
Length of instruction
Clock Cycle 5 cycles 1 word 6 cycles 4 cycles 4 cycles
5-16
Instruction Set Overview
5.3 Instruction Set Overview
This section gives a short overview of the instruction set. The addressing modes are described in Section 5.2. Instructions are either single or dual operand or jump. The source and destination parts of an instruction are defined by the following fields: src dst As S-reg Ad D-reg B/W The source operand defined by As and S-reg The destination operand defined by Ad and D-reg The addressing bits responsible for the addressing mode used for the source (src) The working register used for the source (src) The addressing bits responsible for the addressing mode used for the destination (dst) The working register used for the destination (dst) Byte or word operation: 0: word operation 1: byte operation
Note: Destination Address Destination addresses are valid anywhere in the memory map. However, when using an instruction that modifies the contents of the destination, the user must ensure the destination address is writeable. For example, a masked-ROM location would be a valid destination address, but the contents are not modifiable, so the results of the instruction would be lost.
16-Bit CPU
5-17
Instruction Set Overview
5.3.1
Double-Operand Instructions
Figure 5-7 illustrates the double-operand instruction format.
Figure 5-7. Double Operand Instruction Format
15 14 13 12 11 10 9 8 7 Ad 6 B/W 5 4 As 3 2 1 0 Opcode S-Reg D-Reg
Table 5-15 describes the effects of an instruction on double operand instruction status bits.
Table 5-15.Double Operand Instruction Format Results
Mnemonic MOV ADD ADDC SUB SUBC CMP DADD AND BIT BIC BIS XOR S-Reg, D-Reg src,dst src,dst src,dst src,dst src,dst src,dst src,dst src,dst src,dst src,dst src,dst src,dst Operation V src -> dst src + dst -> dst src + dst + C -> dst dst + .not.src + 1 -> dst dst + .not.src + C -> dst dst - src src + dst + C -> dst (dec) src .and. dst -> dst src .and. dst .not.src .and. dst -> dst src .or. dst -> dst src .xor. dst -> dst - * * * * * * 0 0 - - * Status Bits N - * * * * * * * * - - * Z - * * * * * * * * - - * C - * * * * * * * * - - *
* - 0 1
The status bit is affected The status bit is not affected The status bit is cleared The status bit is set
Note: Instructions CMP and SUB The instructions CMP and SUB are identical except for the storage of the result. The same is true for the BIT and AND instructions.
5-18
Instruction Set Overview
5.3.2
Single-Operand Instructions
Figure 5-8 illustrates the single-operand instruction format.
Figure 5-8. Single Operand Instruction Format
15 14 13 12 11 Opcode 10 9 8 7 6 B/W 5 4 Ad 3 2 1 0 D/S-Reg
Table 5-16 describes the effects of an instruction on the single operand instruction status bits.
Table 5-16.Single Operand Instruction Format Results
Mnemonic S-Reg, D-Reg Operation V RRC RRA PUSH SWPB CALL dst dst src dst dst C -> MSB ->.......LSB -> C MSB -> MSB ->....LSB -> C SP - 2 -> SP, src -> @ SP swap bytes SP - 2 -> SP PC+2 -> stack, dst -> PC RETI TOS -> SR, SP <- SP + 2 TOS -> PC, SP <- SP + 2 SXT dst Bit 7 -> Bit 8........Bit 15 0 * * * X X X X * 0 - - - Status Bits N * * - - - Z * * - - - C * * - - -
* - 0 1
The status bit is affected The status bit is not affected The status bit is cleared The status bit is set
All addressing modes are possible for the CALL instruction. If the symbolic mode (ADDRESS), the immediate mode (#N), the absolute mode (&EDE) or the indexed mode X (RN) is used, the word that follows contains the address information.
16-Bit CPU
5-19
Instruction Set Overview
5.3.3
Conditional Jumps
Conditional jumps support program branching relative to the program counter. The possible jump range is from - 511 to +512 words relative to the program counter state of the jump instruction. The 10-bit program-counter offset value is treated as a signed 10-bit value that is doubled and added to the program counter. None of the jump instructions affect the status bits. The instruction code fetch and the program counter increment technique end with the formula: PCnew = PCold + 2 + PCoffset x 2 Figure 5-9 shows the conditional-jump instruction format.
Figure 5-9. Conditional-Jump Instruction Format
15 14 Opcode 13 12 11 C 10 9 8 7 6 5 4 3 2 1 0 10-Bit PC Offset
Table 5-17 describes these conditional-jump instructions.
Table 5-17.Conditional-Jump Instructions
Mnemonic S-Reg, D-Reg Operation
JEQ/JZ JNE/JNZ JC JNC
JN
Label Label Label Label
Label
Jump to label if zero bit is set Jump to label if zero bit is reset Jump to label if carry bit is set Jump to label if carry bit is reset Jump to label if negative bit is set Jump to label if (N .XOR. V) = 0 Jump to label if (N .XOR. V) = 1 Jump to label unconditionally
JGE JL JMP
Label Label Label
5-20
Instruction Set Overview
5.3.4
Short Form of Emulated Instructions
The basic instruction set, together with the register implementations of the program counter, stack pointer, status register, and constant generator, form the emulated instruction set; these make up the popular instruction set. The status bits are set according to the result of the execution of the basic instruction that replaces the emulated instruction. Table 5-18 describes these instructions.
Table 5-18.Emulated Instructions
Mnemonic Description Status Bits V ArIthmetic Instructions ADC[.W] ADC.B DADC[.W] DADC.B DEC[.W] DEC.B DECD[.W] DECD.B INC[.W] INC.B INCD[.W] INCD.B SBC[.W] SBC.B INV[.W] INV.B RLA[.W] RLA.B RLC[.W] RLC.B CLR[.W] CLR.B CLRC CLRN CLRZ POP SETC SETN SETZ dst dst dst dst dst dst dst dst dst dst dst dst dst dst dst dst dst dst dst dst dst Add carry to destination Add carry to destination Add carry decimal to destination Add carry decimal to destination Decrement destination Decrement destination Double-decrement destination Double-decrement destination Increment destination Increment destination Increment destination Increment destination Subtract carry from destination Subtract carry from destination Invert destination Invert destination Rotate left arithmetically Rotate left arithmetically Rotate left through carry Rotate left through carry Clear destination Clear destination Clear carry bit Clear negative bit Clear zero bit Item from stack Set carry bit Set negative bit Set zero bit * * * * * * * * * * * * * * * * * * * * - - - - - - - - - * * * * * * * * * * * * * * * * * * * * - - - 0 - - - 1 - * * * * * * * * * * * * * * * * * * * * - - - - 0 - - - 1 * * * * * * * * * * * * * * * * * * * * - - 0 - - - 1 - - ADDC ADDC.B DADD DADD.B SUB SUB.B SUB SUB.B ADD ADD.B ADD ADD.B SUBC SUBC.B XOR XOR.B ADD ADD.B ADDC ADDC.B MOV MOV.B BIC BIC BIC MOV BIS BIS BIS #0,dst #0,dst #0,dst #0,dst #1,dst #1,dst #2,dst #2,dst #1,dst #1,dst #2,dst #2,dst #0,dst #0,dst #0FFFFh,dst #-1,dst dst,dst dst,dst dst,dst dst,dst #0,dst #0,dst #1,SR #4,SR #2,SR @SP+,dst #1,SR #4,SR #2,SR N Z C Emulation
Logical Instructions
Data Instructions (common use)
16-Bit CPU
5-21
Instruction Set Overview
Table 5-18. Emulated Instructions (Continued)
Mnemonic Description Status Bits V Data Instructions (common use) (continued) TST[.W] TST.B BR DINT EINT NOP RET dst dst dst Test destination Test destination Branch to . . . Disable interrupt Enable interrupt No operation Return from subroutine 0 0 - - - - - * * - - - - - * * - - - - - * * - - - - - CMP CMP.B MOV BIC BIS MOV MOV #0,dst #0,dst dst,PC #8,SR #8,SR #0h,#0h @SP+,PC N Z C Emulation
Program Flow Instructions
5.3.5
Miscellaneous
Instructions without operands, such as CPUOff, are not provided. Their functions are switched on or off by setting or clearing the function bits in the status register or the appropriate I/O register. Other functions are emulated using dual operand instructions. Some examples are as follows:
BIS #28h,SR ; Enter OscOff mode ; + Enable general interrupt (GIE) BIS #18h,SR ; Enter CPUOff mode ; + Enable general interrupt (GIE)
5-22
Instruction Map
5.4 Instruction Map
The instruction map in Figure 5-10 is an example of how to encode instructions. There is room for more instructions, if needed.
Figure 5-10. Core Instruction Map
000 0x 04x 08x 0Cx 10x 14x 18x 1Cx 20x 24x 28x 2Cx 30x 34x 38x 3Cx 40x-4Fx 50x-5Fx 60x-6Fx 70x-7Fx 80x-8Fx 90x-9Fx A0x-AFx B0x-BFx C0x-CFx D0x-DFx E0x-EFx F0x-FFx 040 080 0C0 100 140 180 1C0 200 240 280 2C0 300 340 380 3C0
RRC RRC.B SWPB
RRA
RRA.B
SXT
PUSH
PUSH.B
CALL
RETI
JNE/JNZ JEQ/JZ JNC JC JN JGE JL JMP MOV, MOV.B ADD, ADD.B ADDC, ADDC.B SUBC, SUBC.B SUB, SUB.B CMP, CMP.B DADD, DADD.B BIT, BIT.B BIC, BIC.B BIS, BIS.B XOR, XOR.B AND, AND.B
16-Bit CPU
5-23
5-24
Chapter 6
Hardware Multiplier
The hardware multiplier is a 16-bit peripheral module. It is not integrated into the CPU. Therefore, it requires no special instructions and operates independent of the CPU. To use the hardware multiplier, the operands are loaded into registers and the results are available the next instruction--no extra cycles are required for a multiplication.
Topic
6.1 6.2 6.3 6.4 6.5
Page
Hardware Multiplier Module Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 Hardware Multiplier Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 Hardware Multiplier Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 Hardware Multiplier Special Function Bits . . . . . . . . . . . . . . . . . . . . . . 6-10 Hardware Multiplier Software Restrictions . . . . . . . . . . . . . . . . . . . . . 6-10
Hardware Multiplier
6-1
Hardware Multiplier Module Support
6.1 Hardware Multiplier Module Support
The hardware multiplier module expands the capabilities of the MSP430 family without changing the basic architecture. Multiplication is possible for:
-
16 x 16 bits 16 x 8 bits 8 x 16 bits 8 x 8 bits
The hardware multiplier module supports four types of multiplication: unsigned multiplication (MPY), signed multiplication (MPYS), unsigned multiplication with accumulation (MAC), and signed multiplication with accumulation (MACS). Figure 6-1 shows how the hardware multiplier module interfaces with the bus system to support multiplication operations.
Figure 6-1. Connection of the Hardware Multiplier Module to the Bus System
ROM RAM
TDI TDO MAB, 16 Bit
CPU Incl. 16 Reg.
Test JTAG MDB, 16 Bit
TMS TCK MPY MPYS MAC MACS Other Modules
6-2
Hardware Multiplier Operation
6.2 Hardware Multiplier Operation
The hardware multiplier has two 16-bit registers for both operands and three registers to store the results of the multiplication. The multiplication is executed correctly when the first operand is written to the operand register OP1 prior to writing the second operand to OP2. Writing the first operand to the applicable register selects the type of multiplication. Writing the second operand to OP2 starts the multiplication. Multiplication is completed before the result registers are accessed using the indexed address mode for the source operand. When indirect or indirect autoincrement address modes are used, another instruction is needed between the writing of the second operand and accessing the result registers. Both operands, OP1 and OP2, utilize all seven address mode capabilities. No instruction is necessary for the multiplication; as a result, the real-time operation does not require additional clock cycles and the interrupt latency is unchanged. The multiplier architecture is illustrated in Figure 6-2.
Figure 6-2. Block Diagram of the MSP430 16x16-Bit Hardware Multiplier
15 Operand 1 (address defines operation) rw MPY 130h MPYS 132h MAC 134h MACS 136h 31 Product Register Accessible Register 0 15 rw Operand 1 Mode 16 x 16 Multiplier 0 0 15 rw 0
Operand 2 138h
0000 32-Bit Adder MACS MPY MPYS MAC Mode Multiplexer MPY, MPYS 32-Bit Multiplexer MAC, MACS Mode
SumExt 13Eh 15 r 0
C
S 15
Accumulator ACC SumHi 13Ch SumLo 013Ah rw 0 15 rw 0
Hardware Multiplier
6-3
Hardware Multiplier Operation
The sum extension register contents differ, depending on the operation and on the results of the operation.
Table 6-1. Sum Extension Register Contents
Register Operand1 Operand2 SumExt
Note:
MPY x x 0000h
MPYS +- +- 0000h ++ -- 0FFFFh
MAC (OP1xOP2 + ACC) 0FFFFFFFFh 0000h (OP1xOP2 + ACC) > 0FFFFFFFFh 0001h
MACS, see Notes (OP1xOP2 + ACC) > 07FFFFFFFh 0FFFFh (OP1xOP2 + ACC) 07FFFFFFFh 0000h
The following two overflow conditions may occur when using the MACS function and should be handled by software or avoided. 1) The result of a MACS operation is positive and larger than 07FFF FFFFh. In this case, the SumExt register contains 0FFFFh and the ACC register contains a negative number (8000 0000h .... 0FFFF FFFFh). 2) The result of a MACS operation is negative and less than or equal to 07FFF FFFFh. In this case, the SumExt register contains 0000h and the ACC register contains a positive number (0000 0000h ... 07FFF FFFFh).
6-4
Hardware Multiplier Operation
6.2.1
Multiply Unsigned, 16x16 bit, 16x 8 bit, 8x 16 bit, 8 x 8 bit
The following multiplication operation shows 32 bytes of program code and 32 execution cycles (16 x16 bit multiplication).
********************************************************** * TRANSFER BOTH OPERANDS TO THE REGISTERS IN THE * * HARDWARE MULTIPLIER MODULE * * USE CONSTANT OPERAND1 AND OPERAND2 TO IDENTIFY * * BYTE DATA * ********************************************************** OPERAND1 .EQU OPERAND2 .EQU MPY MPYS MAC MACS OP2 RESLO RESHI SUMEXT .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .BSS .BSS .BSS 0 0 ; ; ; ; 0: 8: 0: 8: OPERAND1 OPERAND1 OPERAND2 OPERAND2 IS IS IS IS WORD BYTE WORD BYTE (16BIT) ( 8BIT) (16BIT) ( 8BIT)
0130H 0132H 0134H 0136H 0138H 013AH 013CH 013EH OPER1,2,200H OPER2,2 RAM,8
.IF OPERAND1=8 MOV.B &OPER1,&MPY ; LOAD 1ST OPERAND, ; DEFINES ADD. UNSIGNED MULTIPLY .ELSE MOV .ENDIF .IF OPERAND1=8 MOV.B &OPER2,&OP2 ; LOAD 2ND OPERAND AND START ; MULTIPLICATION .ELSE MOV .ENDIF ********************************************************** * EXAMPLE TO ADD THE RESULT OF THE HARDWARE * * MULTIPLICATION TO THE RAM DATA, 64BITS * ********************************************************** ADD ADDC ADC ADC &RESLO,&RAM &RESHI,&RAM+2 &RAM+4 &RAM+6 ; ; ; ; ADD LOW RESULT TO RAM ADD HIGH RESULT TO RAM+2 ADD CARRY TO EXTENSION WORD IF 64 BIT LENGTH IS USED &OPER2,&OP2 ; LOAD 2ND OPERAND AND START ; MULTIPLICATION &OPER1,&MPY ; LOAD 1ST OPERAND, ; DEFINES ADD. UNSIGNED MULTIPLY
Hardware Multiplier
6-5
Hardware Multiplier Operation
6.2.2
Multiply Signed, 16x16 bit, 16x8 bit, 8x16 bit, 8x8 bit
The following multiplication operation shows 36 bytes of program code and 36 execution cycles (16 x 16 bit multiplication).
********************************************************** * TRANSFER BOTH OPERANDS TO THE REGISTERS IN THE * * HARDWARE MULTIPLIER MODULE * * IF ONE OF THE OPERANDS IS 8 BIT, SIGN EXTENSION * * is NEEDED. USE CONSTANT OPERAND1 AND OPERAND2 TO * * IDENTIFY BYTE DATA * ********************************************************** OPERAND1 .EQU OPERAND2 .EQU MPY .EQU MPYS .EQU MAC .EQU MACS .EQU OP2 .EQU RESLO .EQU RESHI .EQU SUMEXT .EQU .BSS .BSS .BSS 0 0 0130H 0132H 0134H 0136H 0138H 013AH 013CH 013EH OPER1,2,200H OPER2,2 RAM,8 ; ; ; ; 0: 8: 0: 8: OPERAND1 OPERAND1 OPERAND2 OPERAND2 IS IS IS IS WORD BYTE WORD BYTE (16BIT) ( 8BIT) (16BIT) ( 8BIT)
.IF OPERAND1=0 MOV &OPER1,&MPYS ; LOAD 1ST (WORD) OPERAND, ; DEFINES ADD. SIGNED MULTIPLY .ELSE MOV.B &OPER1,&MPYS ; ; SXT &MPYS ; .ENDIF .IF OPERAND2=0 MOV &OPER2,&OP2 ; ; LOAD 1ST (BYTE) OPERAND, DEFINES ADD. SIGNED MULTIPLY EXPAND BYTE TO SIGNED WORD DATA
LOAD 2ND (WORD) OPERAND AND START SIGNED MULTIPLICATION
.ELSE MOV.B &OPER2,&OP2 ; LOAD 2ND (BYTE) OPERAND, SXT &OP2 ; RE-LOAD 2ND OPERAND AND START ; SIGNED `FINAL' MULTIPLICATION .ENDIF ********************************************************** * EXAMPLE TO ADD THE RESULT OF THE HARDWARE * * MULTIPLICATION TO THE RAM DATA, 64 BITS * ********************************************************** ADD ADDC ADDC ADDC &RESLO,&RAM ; &RESHI,&RAM+2 ; &SUMEXT,&RAM+4 ; &SUMEXT,&RAM+6 ; ADD LOW RESULT TO RAM ADD HIGH RESULT TO RAM+2 ADD SIGN WORD TO EXTENSION WORD IF 64 BIT LENGTH IS USED
6-6
Hardware Multiplier Operation
6.2.3
Multiply Unsigned and Accumulate, 16x16bit, 16x8bit, 8x16bit, 8x8bit
The following multiplication operation shows 32 bytes of program code and 32 execution cycles (16X16-bit multiplication).
********************************************************** * TRANSFER BOTH OPERANDS TO THE REGISTERS IN THE * * HARDWARE MULTIPLIER MODULE * * THE RESULT OF THE MULTIPLICATION IS ADDED TO THE * * CONTENT OF BOTH RESULT REGISTERS, RESLO AND RESHI * * USE CONSTANT OPERAND1 AND OPERAND2 TO IDENTIFY * * BYTE DATA * ********************************************************** OPERAND1 .EQU OPERAND2 .EQU MPY MPYS MAC MACS OP2 RESLO RESHI SUMEXT .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .BSS .BSS .BSS 0 0 ; ; ; ; 0: 8: 0: 8: OPERAND1 OPERAND1 OPERAND2 OPERAND2 IS IS IS IS WORD BYTE WORD BYTE (16BIT) ( 8BIT) (16BIT) ( 8BIT)
0130H 0132H 0134H 0136H 0138H 013AH 013CH 013EH OPER1,2,200H OPER2,2 RAM,8
.IF OPERAND1=8 MOV.B &OPER1,&MAC ; LOAD 1ST OPERAND, ; DEFINES ADD. UNSIGNED MULTIPLY .ELSE MOV .ENDIF .IF OPERAND1=8 MOV.B &OPER2,&OP2 ; LOAD 2ND OPERAND AND START ; MULTIPLICATION .ELSE MOV .ENDIF ********************************************************** * EXAMPLE TO ADD THE RESULT OF THE HARDWARE * * MULTIPLICATION TO THE RAM DATA, 64BITS * * THE RESULT OF THE MULTIPLICATION IS HELD IN RESLO* * AND RESHI REGISTERS. THE UPPER TWO WORDS IN THE * * EXAMPLE ARE FURTHER LOCATED IN THEIR RAM LOCATION* ********************************************************** ADDC ADC &SUMEXT,&RAM+4 &RAM+6 ; ADD SUMEXTENSTION TO RAM+4 ; IF 64 BIT LENGTH IS USED &OPER2,&OP2 ; LOAD 2ND OPERAND AND START ; MULTIPLICATION &OPER1,&MAC ; LOAD 1ST OPERAND, ; DEFINES ADD. UNSIGNED MULTIPLY
Hardware Multiplier
6-7
Hardware Multiplier Operation
6.2.4
Multiply Signed and Accumulate, 16x16bit, 16x8bit, 8x16bit, 8x8bit
******************************************************************** * TRANSFER BOTH OPERANDS TO THE REGISTERS IN THE HARDWARE * * MULTIPLIER MODULE * * USE CONSTANT OPERAND1 AND OPERAND 2 TO IDENTIFY BYTE DATA * ******************************************************************** OPERAND1 .EQU 0 ; 0: OPERAND1 IS WORD (16BIT) ; 8: OPERAND1 IS BYTE ( 8BIT) OPERAND2 .EQU 0 ; 0: OPERAND2 IS WORD (16BIT) ; 8: OPERAND2 IS BYTE ( 8BIT) MPY .EQU 0130H MPYS .EQU 0132H MAC .EQU 0134H MACS .EQU 0136H OP2 .EQU 0138H RESLO .EQU 013AH RESHI .EQU 013CH SUMEXT .EQU 013EH MAXMACS .EQU 32H ;NUMBER OF MACS FUNCTIONS WHICH COULD ;BE EXECUTED TILL AN OVERFLOW OR UNDERFLOW ;COULD OCCUR THE FIRST TIME .BSS OPER1,2,200H .BSS OPER2,2 .BSS RAM,8 .BSS MCOUNT,2 .IF OPERAND1=8 MOV.B &OPER1,&MACS ; LOAD 1ST OPERAND, ; DEFINES ADD. UNSIGNED MULTIPLY SXT &MACS ; EXPAND BYTE TO SIGNED WORD DATA .ELSE MOV &OPER1,&MACS ; LOAD 1ST OPERAND, ; DEFINES ADD. UNSIGNED MULTIPLY .ENDIF .IF OPERAND1=8 SXT &OPER2 ; OPER2 MEMORY LOCATION NEEDS ; 2 BYTES MOV.B &OPER2,&OP2 ; LOAD 2ND OPERAND AND START ; MULTIPLICATION .ELSE MOV &OPER2,&OP2 ; LOAD 2ND OPERAND AND START ; MULTIPLICATION .ENDIF ******************************************************************** * EXAMPLE TO ADD THE RESULT OF THE HARDWARE MULTIPLICATION * * TO THE RAM DATA IF NECESSARY * * THE RESULT OF THE MULTIPLICATION IS HELD IN RESLO AND * * RESHI REGISTERS. THE UPPER TWO WORDS IN THE EXAMPLE ARE * * FURTHER LOCATED IN THEIR RAM LOCATION * ******************************************************************** INC MCOUNT ; INC MACS COUNTER CMP #MAXMACS,MCOUNT ; ONLY ADD TO RAM IF NECESSARY JNE NEXTMACS ; ADDC &RESLO,&RAM+0 ; ADD SUMEXTENSION TO RAM+0 ADDC &RESHI,&RAM+2 ; ADD SUMEXTENSION TO RAM+2 ADDC &SUMEXT,&RAM+4 ; ADD SUMEXTENSION TO RAM+4 ADDC &SUMEXT,&RAM+6 ; IF 64 BIT LENGTH IS USED CLR MCOUNT NEXTMACS ...
6-8
Hardware Multiplier Registers
6.3 Hardware Multiplier Registers
Hardware multiplier registers are word structured, but can be accessed using word or byte processing instructions. Table 6-2 describes the hardware multiplier registers.
Table 6-2. Hardware Multiplier Registers
Register Multiply Unsigned (Operand1) Multiply Signed (Operand1) Multiply+Accumulate (Operand1) Multiply Signed+Accumulate (Operand1) Second Operand Result Low Word Result High Word Sum Extend Short Form MPY MPYS MAC MACS OP2 ResLo ResHi SumExt Register Type Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read Address 0130h 0132h 0134h 0136h 0138h 013Ah 013Ch 013Eh Initial State Unchanged Unchanged Unchanged Unchanged Unchanged Undefined Undefined Undefined
Two registers are implemented for both operands, OP1 and OP2, as shown in Figure 6-3. Operand 1 uses four different addresses to address the same register. The different address information is decoded and defines the type of multiplication operation used.
Figure 6-3. Registers of the Hardware Multiplier
15 MPY (130h),MPYS (132h) MAC (134h), MACS(136h) OP2 (138h) ResLo (13Ah) ResHi (13Ch) SumExt (13Eh) Operand 1, OP1 Operand 2, OP2 Result Low Word, ResLo Result High Word, ResHi Sum Extension Word, SumExt 0
The multiplication result is located in two word registers: result high (RESHI) and result low (RESLO). The sum extend register (SumExt) holds the result sign of a signed operation or the overflow of the multiply and accumulate (MAC) operation. See Section 6.5.3 for a description of overflow and underflow when using the MACS operations. All registers have the least significant bit (LSB) at bit0 and the most significant bit (MSB) at bit7 (byte data) or bit15 (word data).
Hardware Multiplier
6-9
Hardware Multiplier Special Function Bits
6.4 Hardware Multiplier Special Function Bits
Because the hardware multiplier module completes all multiplication operations quickly, without interrupt intervention, no special function bits are used.
6.5 Hardware Multiplier Software Restrictions
Two restrictions require attention when the hardware multiplier is used:
6.5.1
The indirect or indirect autoincrement address mode used to process the result The hardware multiplier used in an interrupt routine
Hardware Multiplier Software Restrictions--Address Mode
The result of the multiplication operation can be accessed in indexed, indirect, or indirect autoincrement mode. The result registers may be accessed without any restrictions if you use the indexed address mode including the symbolic and absolute address modes. However, when you use the indirect and indirect autoincrement address modes to access the result registers, you need at least one instruction between loading the second operand and accessing one of the result registers.
********************************************************** * EXAMPLE: MULTIPLY OPERAND1 AND OPERAND2 ********************************************************** RESLO .SET PUSH MOV MOV MOV 013AH R5 #RESLO,R5 ; RESLO = ADDRESS OF RESLO ; R5 WILL HOLD THE ADDRESS OF ; THE RESLO REGISTER LOAD 1ST OPERAND, DEFINES ADD. UNSIGNED MULTIPLY LOAD 2ND OPERAND AND START MULTIPLICATION
&OPER1,&MPY ; ; &OPER2,&OP2 ; ;
********************************************************** * EXAMPLE TO ADD THE RESULT OF THE HARDWARE * * MULTIPLICATION TO THE RAM DATA, 64BITS * ********************************************************** NOP ; ; ; ; @R5+,&RAM ; @R5,&RAM+2 ; &RAM+4 ; &RAM+6 ; R5 MIN. ONE CYCLES BETWEEN MOVING THE OPERAND2 TO HW-MULTIPLIER AND PROCESSING THE RESULT WITH INDIRECT ADDRESS MODE ADD LOW RESULT TO RAM ADD HIGH RESULT TO RAM+2 ADD CARRY TO EXTENSION WORD IF 64 BIT LENGTH IS USED
ADD ADDC ADC ADC POP
The previous example shows that the indirect or indirect autoincrement address modes, when used to transfer the result of a multiplication operation to the destination, need more cycles and code than the absolute address mode. There is no need to access the hardware multiplier using the indirect addressing mode.
6-10
Hardware Multiplier Software Restrictions
6.5.2
Hardware Multiplier Software Restrictions--Interrupt Routines
The entire multiplication routine requires only three steps: 1) Move operand OP1 to the hardware multiplier; this defines the type of multiplication. 2) Move operand OP2 to the hardware multiplier; the multiplication starts. 3) Process the result of the multiplication in the RESLO, RESHI, and SUMEXT registers. The following considerations describe the main routines that use hardware multiplication. If no hardware multiplication is used in the main routine, multiplication in an interrupt routine is protected from further interrupts, because the GIE bit is reset after entering the interrupt service routine. Typically, a multiplication operation that uses the entire data process occurs outside an interrupt routine and the interrupt routines are as short as possible. A multiplication operation in an interrupt routine has some feedback to the multiplication operation in the main routine.
6.5.2.1
Interrupt Following an OP1 Transfer
The two LSBs of the first operand address define the type of multiplication operation. This information cannot be recovered by any later operation. Therefore an interrupt must not be accepted between the first two steps: move operand OP1 and OP2 to the multiplier.
6.5.2.2
Interrupt Following an OP2 Transfer
After the first two steps, the multiplication result is in the corresponding registers RESLO, RESHI, and SUMEXT. It can be saved on the stack (using the PUSH instruction) and can be restored after completing another multiplication operation (using the POP instruction). However, this operation takes additional code and cycles in the interrupt routine. You can avoid this, by making an entire multiplication routine uninterruptible, by disabling any interrupt (DINT) before entering the multiplication routine, and by enabling interrupts (EINT) after the multiplication routine is completed. The negative aspect of this method is that the critical interrupt latency is increased drastically for events that occur during this period.
6.5.2.3
General Recommendation
In general, one should avoid a hardware multiplication operation within an interrupt routine when a hardware multiplication is already used in the main program. (This will depend upon the application-specific software, applied libraries, and other included software.) The methods previously discussed have some negative implications; therefore, the best practice is to keep interrupt routines as short as possible.
Hardware Multiplier
6-11
Hardware Multiplier Software Restrictions
6.5.3
Hardware Multiplier Software Restrictions--MACS
The multiplier does not automatically detect underflow or overflow in the MACS mode. An overflow occurs when the sum of the accumulator register and the result of the signed multiplication exceed the maximum binary range. The binary range of the accumulator for positive numbers is 0 to 231-1 (7FFF FFFFh) and for negative numbers is -1 (0FFFF FFFFh) to -231 (8000 0000h). An overflow occurs when the sum of two negative numbers yields a result that is in the range given above for a positive number. An underflow occurs when the sum of two positive numbers yields a result that is in the range for a negative number. The maximum number of successive MACS instructions without underflow or overflow is limited by the individual application and should be determined using a worst-case calculation. Care should then be exercised to not exceed the maximum number or to handle the conditions accordingly.
6-12
Chapter 7
Basic Clock Module
This chapter discusses the Basic Clock Module used in the MSP430x1xx families.
Topic
7.1 7.2 7.3 7.4 7.5
Page
Basic Clock Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 LXFT1 and XT2 Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 Digitally-Controlled Oscillator (DCO) . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 Basic Clock Module Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . 7-14 Basic Clock Module Control Registers . . . . . . . . . . . . . . . . . . . . . . . . 7-18
Basic Clock Module
7-1
7.1 Basic Clock Module
The Basic Clock Module (shown in Figure 7-1) follows the major targets of low system cost and low power consumption. Using three internal clock signals, the design engineer can select the best balance of performance and low power consumption. The Basic Clock Module can be configured to operate without any external components, with one external resistor, with one or two external crystals, with resonators, or with clock sources using any combination of the above. The Basic Clock Module is accessible to the CPU as a byte-wide peripheral module.
Figure 7-1. Basic Clock Schematic
DIVA 2 LFXT1CLK /1, /2, /4, /8 OSCOff XIN XTS LFXT1 Oscillator ACLKGEN ACLK Auxiliary Clock
SELM XOUT 3 XT2CLK XT2Off XT2IN 0,1 2 2
DIVM 2
CPUOff
/1, /2, /4, /8, Off MCLKGEN
MCLK Main System Clock
XT2OUT VCC VCC
XT2 Oscillator
DCOCLK
Rsel SCG0
DCO 3
MOD 5
SELS
DIVS 2
SCG1
0
DC Generator DCOR
1
Digital Controlled Oscillator DCO + Modulator MOD DCOMOD
0 1
/1, /2, /4, /8, Off SMCLKGEN
SMCLK Sub-System Clock
If the external resistor function is shared on a digital terminal, the DCOR control bit defines if the digital port of the DCO generator is connected to that terminal. Pn.x Note: The XT2 oscillator is implemented in MSP430F13x and MSP430F14x devices. The LFXT1 signal is used instead of XT2CLK signal in MSP430x11x and MSP430x11x1 devices without XT2 oscillator.
7-2
The Basic Clock Module includes two or three clock sources:
-
LFXT1CLK low-frequency/high-frequency clock source. One oscillator that can be used with low-frequency watch crystals, standard crystals, resonators, or external clock sources. See the device data sheet for the exact operating frequency range. XT2CLK high-frequency clock source. This optional high-frequency oscillator can also use standard crystals, resonators, or external clock sources in the 450-kHz to 8-MHz range. See the device data sheet for the exact operating frequency range and availability of this optional oscillator. DCOCLK clock source. One digitally controlled oscillator (DCO) with RC-type characteristics.
Three clock signals are available from the Basic Clock Module: ACLK auxiliary clock. The ACLK is the buffered LFXT1CLK clock source divided by 1, 2, 4, or 8. Software selects the division factor. ACLK is software selectable for individual peripheral modules. MCLK master clock. MCLK is software selectable as LFXT1CLK, XT2CLK (if available), or DCOCLK. MCLK is divided by 1, 2, 4, or 8. Software selects the division factor. MCLK is used by the CPU and system. SMCLK submain clock. SMCLK is software selectable as LFXT1CLK, XT2CLK (if available), or DCOCLK. SMCLK is divided by 1, 2, 4, or 8. Software selects the division factor. SMCLK is software selectable for individual peripheral modules.
Basic Clock Module
7-3
LFXT1 and XT2 Oscillators
7.2 LFXT1 and XT2 Oscillators
The Basic Clock Module includes the LFXT1 oscillator and, in some configurations, a second XT2 oscillator.
7.2.1
LFXT1 Oscillator
The LFXT1 oscillator starts operating on a valid PUC condition. A valid PUC condition resets the OscOff bit in the status register, which enables LFXT1. Software can disable LFXT1 by setting OscOff, if this signal does not source SMCLK or MCLK. The design of the LFXT1 oscillator (shown in Figure 7-2) supports the low-current consumption feature and the use of a 32,768-Hz watch crystal when in LF mode (XTS=0). A watch crystal connects to the clock module via two terminals without any other external components. Components necessary to stabilize the clock operation have been integrated into the MSP430. The design of the LFXT1 oscillator also supports high-speed crystals or resonators when in HF mode (XTS = 1). The crystal or resonator connects to the terminals and requires external capacitors on both terminals. These capacitors should be sized according to crystal or resonator specifications.
Figure 7-2. Principle of LFXT1 Oscillator
XIN OscOff XTS LFXT1CLK
0 LFOff 0
1 XT1Off 1
Oscillator Fault Detect
LFXT1_OscFault
XOUT
Low Power LF Oscillator, XTS = 0
The OscOff bit in the status register is used to turn off LFXT1CLK if this signal does not source MCLK or SMCLK.
7-4
LFXT1 and XT2 Oscillators
Figure 7-3. Off Signals for the LFXT1 Oscillator
XTS OscOff CPUOff SELM.1 SELM.0 XT2 LFoff
XT1off XT2 Is an Internal Signal XT2 = 0: MSP430x11x, MSP430x11x1 devices XT2 = 1: MSP430F13x, MSP430F14x devices
SCG1 SELS OscOff 0 1 1 CPUOff x 0 x SELM.x x 3 or 2+3 x SCG1 x x 0
SELS x x 1
LFXT1CLK on on on
Comment Oscillator Active Clock Signal Needed For MCLK Clock Signal Needed For SMCLK
Two oscillators: SELM.x = 3. Three oscillators: SELM.x = 3 and 2 LFXT1CLK is switched off for all other bit combinations
7.2.2
XT2 Oscillator
A second oscillator, XT2, is available in MSP430F13x and MSP430F14x devices. XT2 sources XT2CLK, and its characteristics are identical to LFXT1 in HF mode. The XT2Off control bit disables the XT2 oscillator if signal XT2CLK is not used for MCLK or SMCLK. If the CPUOff bit is reset and SELM = 2, XT2CLK sources MCLK . The XT2CLK sources SMCLK if SCG1 is reset and SELS = 1.
Figure 7-4. Off Signals for Oscillator XT2
XT2Off CPUOff SELM.1 SELM.0 SCG1 SELS XT2Off
OscOff 0 1 1
CPUOff x 0 x
SELM.x x 2 x
SCG1 x x 0
SELS x x 1
XT2CLK on on on
Comment Oscillator Active Clock Signal Needed For MCLK Clock Signal Needed For SMCLK
XT2CLK is switched off in all other bit combinations
Basic Clock Module
7-5
LFXT1 and XT2 Oscillators
7.2.3
Oscillator Fault Detection
An analog circuit controls the operation of oscillators LFXT1 and XT2 and flags an oscillator fault when approximately 100 cycles (at 1 MHz) of the crystal are missed. The active OSCFault signal sets the oscillator-fault-interrupt flag (OFIFG) and requests a non-maskable interrupt when the oscillator-fault interrupt enable bit (OFIE) is set. User software must clear the OFIFG flag.
Figure 7-5. Oscillator-Fault-Interrupt
XT1off XT_OscFault NMIFG OFIFG S IFG1.1 OFIE IE1.1 Oscillator Fault NMI Clear PUC IRQA
LFXT1_OscFault POR XT2off XT2_OscFault XT2
NMIRS
XTS SELM.1 XSELM.1
SELM.0 Fault_from XT2 Fault_from XT1 XDCOR DCOR Select DCO including Internal Resistor XT Oscillator Fails XT2 Is an internal signal XT2 = 0: Two oscillators - MSP430x11x and MSP430x11x1 devices XT2 = 1: Three oscillators - MSP430F13x and MSP430F14x devices IRQA: Interrupt request accepted
The XT2_OscFault signal of the XT2 oscillator, and the LFXT1_OscFault signal of the LFXT1 oscillator will set the oscillator-fault-interrupt flag (OFIFG) independently. During two-oscillator implementation, the oscillator-fault-interrupt flag can be reset by software if the LFXT1_OscFault signal is a logic low. During three-oscillator implementation, the oscillator-fault-interrupt flag can be reset by software only if both oscillator-fault signals, LFXT1_OscFault and XT2_OscFault, are low.
7-6
LFXT1 and XT2 Oscillators
After applying VCC the oscillator fault signal (XT_OscFault) becomes active. The XT_OscFault signal becomes inactive when XT2CLK and/or LFXT1CLK begin oscillating, which takes approximately 50 clock cycles (at 1 MHz).
Figure 7-6. Oscillator-Fault Signal
VCC
XT2CLK LFXT1CLK Oscillator Start-Up XT_OscFault
XT_OscFault becomes active after XT2CLK and/or LFXT1CLK stop oscillating. The delay associated with the XT_OscFault signal is approximately 50 clock cycles (at 1 MHz).
Figure 7-7. Oscillator Fault in Oscillator Error Condition
VCC
XT2CLK LFXT1CLK
Oscillator Error
XT_OscFault
The oscillator-fault signal returns to a logic low if the oscillator starts operating again. The delay is typically 50 clock cycles (at 1 MHz). When an XT oscillator has stopped and is then restarted, the oscillator fault signal (XT_OscFault) remains active until the oscillator starts operating, and becomes inactive after a delay of typically 50 clock cycles at (1 MHz).
Basic Clock Module
7-7
LFXT1 and XT2 Oscillators
Figure 7-8. Oscillator Fault in Oscillator Error Condition at Start-Up
VCC XT1Off/ XT2Off
XT2CLK LFXT1CLK
XT_OscFault
7.2.4
Select DCO Oscillator for MCLK on XT Oscillator Fault
The DCO oscillator is selected automatically for MCLK if either one of the oscillators LFXT1 (in HF mode only), or XT2 is selected for MCLK source and this oscillator fails. Since the DCO oscillator is now selected, the NMI requested by the oscillator fault can be processed. The DCO oscillator is switched on and the DCOCLK is switched to be the source for MCLK. An NMI is processed even if the CPU is switched off (CPUOFF=1). The MSP430 ultralow-power system allows any enabled interrupt to be serviced from any low-power mode, including LPM4. MCLK automatically becomes active inside of an interrupt service routine. An NMI interrupt routine written by the user, which handles the oscillator fault, has some important steps that should be used for proper handling of the fault situation. First, if the NMI interrupt routine detects the oscillator fault and selects the DCO as clock source for the system clock MCLK. Second, the user programs a proper algorithm to detect if the XT oscillator is working again and reselects an XT oscillator for the system clock MCLK if desired.
7-8
LFXT1 and XT2 Oscillators
Figure 7-9. NMI/OSCFault Interrupt Handler
Start of NMI Interrupt Handler Reset by HW: OFIE, NMIE, ACCIE
OFIFG = 1 Yes Select DCO For MCLK SELM.1 = 0
No
ACCVIFG = 1 Yes Reset ACCVIFG
No
NMIFG = 1 Yes Reset NMIIFG
No
User's Software, Oscillator Fault Handler
User's Software, Flash Access Violation Handler
User's Software, External NMI Handler
OFIFG = 0
OFIFG = 0
No
Yes Reselect Failed XT Oscillator Optional
Set NMIE, OFIE, ACCVIE Within One Instruction
Example1: BIS.B #(NMIIE+OGIE+ACCVIFG), &IE1 Example2: BIS.B Mask, &IE1 ; Mask Enables Only ; Interrupt Sources ; That are Needed
RETI End of NMI Int. Handler
Note: Example for MSP430F1xx device
Basic Clock Module
7-9
Digitally-Controlled Oscillator (DCO)
7.3 Digitally-Controlled Oscillator (DCO)
The DCO is an integrated RC-type oscillator in the Basic Clock Module. The DCO frequency can be tuned by software using the DCO, MOD, and RSEL bits. The DCO is absolutely monotonic. As with any RC-type oscillator, frequency varies with temperature, voltage, and from device to device. The digital control of the oscillator allows frequency stabilization despite its RC-type characteristics.
Figure 7-10. DCO Schematic
VCC VCC DCO 3 Rsel 0 1 2 SCG0 0 DC Generator 1 XDCOR DCO MOD 5
CPUOff SCG1 XSELM.1 Halt SELS
Modulator 3
DCOCLK
The dc generator, when switched off, requires some minimal start-up time (4 microsecond range) due to its low-current design. Once the current is switched on, the resistor injects current in the microampere range into the dc generator; the internal and external parasitic capacitances introduce the delay in the microsecond range. No delay occurs in operating modes that do not require to switch off the dc generator current. An internal or external resistor is connected to the dc generator, which determines the operating fundamental frequency of the DCOCLK. The frequency of DCOCLK is set by the following functions:
-
The current injected into the dc generator (DCGEN) by either the internal or external resistor defines the fundamental frequency. Control bit DCOR selects the internal or external resistor. Control bits Rsel2, Rsel1, and Rsel0 divide the fundamental frequency into eight nominal frequency ranges. These ranges are defined for an individual device in the appropriate data sheet. The three control bits, DCO0 to DCO2, adjust the DCOCLK frequency. The five modulation bits, MOD0 to MOD4, switch between the frequency selected by the DCO bits and the next higher frequency set by DCO+1.
The clock period of the DCOCLK signal changes approximately ten percent for each step of the control bit DCO.
7-10
Digitally-Controlled Oscillator (DCO)
Figure 7-11. Principle Period Steps of the DCO
fDCOCLK
Nominal
0
1
2
3
4
5
6
7
DCO
Five bits (SCG0, CPUOff, SELM.1, SCG1, and SELS) control the operation of the DCO.
Figure 7-12. On/Off Control of DCO
CPUOff XSELM.1 SCG1 D Q CL SMCLK SCG0
SCG0 x x 0 0 0 0 1 CPUOff 0 x 0 1
DCOCLK_on D Q 1: on 0: off
SELS
DCOCLK
POR
DCO_Gen_on 1: on 0: off
SELM.1 0 x 1 x
SCG1 x 0
SELS x 0
DCOCLK on on off off off off off
DCOCLK on on on on on on off
Comment DCO Clock Needed For MCLK DCO Clock Needed For SMCLK DCO Clock is Not Needed For MCLK (and SMCLK) DCO Clock is Not Needed For SMCLK (and MCLK) DCO Clock is Not Needed: SCG0 Bit Switches Off DCOGEN
(see Note A) 0 1 1 x
(see Note B)
(see Note C)
NOTES: A. SMCLK does not need the DCOCLK signal if: SMCLK is switched off (SCG1 = 1), or DOCCLK is not selected for SMCLK (SELS = 0). B. MCLK does not need the DCOCLK signal if: MCLK is switched off (CPUOff = 1), or DOCCLK is not selected for MCLK (SELM.1 = 1). C. MCLK and SMCLK does not need the DCOCLK signal if: The control bit SCG0 in the status register can switch off (SCG0 = 1) the DCOGEN.
Basic Clock Module
7-11
Digitally-Controlled Oscillator (DCO)
7.3.1
Operation of the DCO Modulator
The modulator is intended to reduce a long accumulating period variation by mixing adjacent DCO periods. On average, a longer period variation can be minimized by mixing DCO periods. The modulator accumulates a period of 32 DCOCLK clock cycles. The MOD control bits define the mixing ratio of the DCO+1 period. The remaining 32-MOD time slots use the DCO period. If the modulation constant is 0, the DCO data in the control register defines the period. The following formula defines the accumulating periods: t =(32- MOD) x tDCO + MOD x tDCO+1 The modulator selects fdco or fdco+1 individually for each DCO cycle. This is the highest possible rate that can be modulated between two discrete frequency steps. The following example illustrates the main operation of the modulator.
Figure 7-13. Operation of the DCO Modulator
Frequency Cycle Time Selected: f3: f4: MOD = 19 1000 kHz 943 kHz 1042 kHz 1000 ns 1060 ns 960 ns f0 f1 f2 f3 f4 f5 f6 f7 Frequency Selected
DCOCLK Modulation Period DCO 1 0
(ns) 40 Error of 20 tperiod 0 -20 -40 (%) 4 3 Error of 2 tperiod 1 0 -1 -2 -3 -4
7-12
Digitally-Controlled Oscillator (DCO)
The user should consider two factors when reviewing the timing accuracy generated from the DCOCLK signal:
-
Short term accuracy: Each individual cycle is as inaccurate as the DCO steps. Long term accuracy: The accumulated average of many individual cycles reduces the relative error down to less than 1/3 percent, assuming a step delta of 10% and a modulation period of 32.
Proper use of the modulation feature on the DCOCLK period increases the accuracy by averaging the periods. The selected frequency set using the control bits in the DCO and the modulation fraction defined by the control bits in MOD sets the DCOCLK periods. Note: Control of DCOCLK Frequency The frequency of the digitally-controlled oscillator varies with temperature and voltage and is different for each individual sample. The frequency can be controlled by software if an external reference (such as the ACLK signal) is used to measure the difference and to readjust the DCO frequency.
Basic Clock Module
7-13
Basic Clock Module Operating Modes
7.4 Basic Clock Module Operating Modes
Control bits SCG0, SCG1, OscOff, and CPUOff in the status register configure the operating mode, as discussed in Chapter 3, System Resets, Interrupts and Operating Modes. The digitally-controlled oscillator is disabled when not used for MCLK or SMCLK. The dc generator must be switched off separately, but is switched on automatically when the DCOCLK signal is used, either for MCLK or SMCLK.
7.4.1
Starting From Power Up Clear (PUC)
On a valid PUC, the internal resistor is selected for the dc generator, Rsel = 4, and DCO = 3, allowing the oscillator to operate at a medium frequency and independently from external conditions. ACLK is sourced from LFXT1 in the LF mode and configured to operate with a watch crystal; MCLK and SMCLK are sourced from DCOCLK. Because the CPU executes code from MCLK, which is sourced from the fast-starting DCO, code execution from PUC is fast, typically less than 6 s. After a PUC, user software selects the best basic clock configuration for the application.
7.4.2
Adjusting the Basic Clock
The control registers of the Basic Clock are under full software control. If clock requirements other than those of the default from PUC are necessary, the Basic Clock can be configured or reconfigured by software at any time during program execution.
-
ACLKGEN from LFXT1 crystal, resonator, or external-clock source and divided by 1, 2, 4, or 8. If no LFXTCLK clock signal is needed in the application, the OscOff bit should be set in the status register. SCLKGEN from LFXTCLK, DCOCLK, or XT2CLK (x13x and x14x only) and divided by 1, 2, 4, or 8. The SCG1 bit in the status register enables or disables SMCLK. MCLKGEN from LFXTCLK, DCOCLK, or XT2CLK (x13x and x14x only) and divided by 1, 2, 4, or 8. When set, the CPUOff bit in the status register enables or disables MCLK. DCOCLK frequency is adjusted using the RSEL, DCO, and MOD bits. The DCOCLK clock source is stopped when not used, and the dc generator can be disabled by the SCG0 bit in the status register (when set). The XT2 oscillator sources XT2CLK (x13x and x14x only) by clearing the XT2Off bit.
User software can modify the Basic Clock to meet the system requirements at any time using the full MSP430 instruction set. A few examples follow:
bis.b #007h,&BCSCTL1 mov.b #081h,&BCSCTL1 bis.b #070h,&BCSCTL1 bis.b #008h,&BCSCTL2 inc.b &DCOCTL dec.b &DCOCTL ; RSEL=7 ; XT2off, RSEL=1 ; ACLK= high-speed XTAL/8 ; SMCLK=LFXT1 ; Increase DCOCLK ; Decrease DCOCLK
7-14
Features for Low-Power Applications
7.4.3
Basic Clock Features for Low-Power Applications
Conflicting requirements typically exist in battery powered MSP430x1xx applications:
-
Low clock frequency for energy conservation and time keeping High clock frequency for fast reaction to events and fast burst processing capability
The Basic Clock Module addresses the above conflicting requirements by allowing the design engineer to select from the three available clock signals: ACLK, MCLK and SMCLK. For optimal low-power performance, the ACLK can be configured to oscillate with a low 32,786-Hz watch-crystal frequency, providing a stable time base for the system and low power stand-by operation. The MCLK can be configured to operate from the on-chip DCO which is only activated when requested by events. The SMCLK can be configured to operate from either the watch-crystal or the DCO, depending on peripheral requirements. A flexible clock distribution and divider system is provided to fine tune the individual clock requirements. All basic clock-module configurations are under full software control.
7.4.4
Selecting a Crystal Clock for MCLK
After power up, the basic clock module uses the DCO clock for the system clock MCLK. The LFXT1 oscillator starts in the low-frequency mode (XTS=0). Regardless of the configuration of the clock system the application uses, if all initial conditions are set, the software execution is ensured by the integrated DCO. Finally, the application may use a crystal for further software execution.
Figure 7-14. Select Crystal Oscillator for MCLK, Example Uses LFXT1 for MCLK
LFXT1CLK SELM 2 3 DCOCLk XT2CLk 0,1 2 MCLKGEN /1, /2, /4, /8, off MCLK Main System Clock DIVM 2 CPUOff
The sequence to switch the MCLK source from the DCO clock to the crystal clock (LFXT1CLK or XT2CLK) should be: 1) Switch on the crystal oscillator a) OscOff = 0, XTS is reset (LF mode is selected) or set (HF mode is selected)
BIS.B BIC #XTS,&BCSCTL1 #OSCOFF,SR ; Set XTS bit to select LFXT1 ; oscillator ; Turn on LFXT1 oscillator
Basic Clock Module
7-15
Features for Low-Power Applications
b) In x13x and x14x devices, the XT2 oscillator can also be used: XT2Off is reset
BIC.B #XT2Off,&BCSCTL1 ; Reset XT2Off to turn on LFXT1 ; oscillator
2) Wait until the oscillator, which will be used for MCLK, is settled. Three possibilities are: a) Always wait enough time so the oscillator is settled under all conditions. The time differs with the crystal type (watch crystal, standard crystal, resonator) and needs to be evaluated with the application.
PUSH Loop #Wait ; Load wait time constant onto stack
DEC JNZ
0 (SP) ; Count wait time down to zero Loop
; Wait time not completed > go to loop ; Wait time = t(MCLK) x (4+2)
BIC.B #OFIFG,&IFG1 BIS.B #(SELM1+SELM0),&BCSCTL2
; Clear osc. fault int. flag ; Select now LFXT1 clock
b) Wait until the oscillator-fault test (reset OFIFG and then test if OFIFG is reset) indicates that the oscillator has started. Then wait enough time so that the oscillator amplitude is settled.
TST_OF Loop
BIC.B #OFIFG,&IFG1 ; Clear osc. fault int. flag
DEC JNZ
BIT.B
0 (SP) ; Count wait time down to zero Loop
; Wait time not completed > go to loop ; Test oscillator fault flag
#OFIFG,&IFG1 TST_OF
JNZ PUSH
; Repeat test until flag remains reset ; Load wait time constant onto stack ; Clear osc. fault int. flag ; Select now LFXT1 clock
#Wait
BIC.B #OFIFG,&IFG1 BIS.B #(SELM1+SELM0),&BCSCTL2
c) Wait until the oscillator-fault test (reset OFIFG and then test if OFIFG is reset) indicates that the oscillator has started. Then count pulses from the oscillator. A typical number is 1024 pulses and needs to be verified under the final application conditions.
TST_OF
BIC.B #OFIFG,&IFG1 ; Clear oscillator fault interrupt ; flag ; Test oscillator fault flag
BIT_B #OFIFG,&IFG1 JNZ
TST_OF ; Repeat test until flag remains reset
;* Use Watchdog/Timer with ACLK/2, SSEL=1, IS1=1, IS0=0, RST/NMI is ;* reset pin and Watchdog/Timer in Timer function, counter is ;* cleared. BIS.B BIC.B #DIVA0,&BCSCTL1 ; Assumes that DIVA.1 bit is reset #WDTIE,&IE1 ; No interrupt from Watchdog/Timer ; Clear WDTIFG: it indicates 1024 ; pulses from XT1
BIC.B #WDTIFG,&IFG1 MOV Retest
#(WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1),&WDTCTL ; Test if 1024 pulses completed
BIT.B #WDTIFG,&IFG1
7-16
Features for Low-Power Applications
JNC
Retest ; Clear osc. fault int. flag ; Select now LFXT1 clock
BIC.B #OFIFG,&IFG1 BIS.B #(SELM1+SELM0),&BCSCTL2
Figure 7-15. Timing to Select Crystal Oscillator for MCLK, Example Uses LFXT1 in HF Mode for MCLK
Turn on the Crystal Oscillator
DCOCLK
XT1CLK MCLK DCOCLK If Crystal Oscillator settled XT1CLK Then Select Crystal Oscillator for MCLK
7.4.5
Synchronization of Clock Signals
The clock signals MCLK and SMCLK can be supplied by different clock sources. While switching from one clock source to the other, the switch is synchronized to avoid critical race conditions. When another clock source is selected the following occurs in order: 1) The current clock cycle continues until the next rising edge. 2) The clock then remains high until the next rising edge of the newly selected clock. 3) Now the new clock source is selected and continues with a full high period.
Figure 7-16. Select Another Clock Source Signal, Example Switches From DCOCLK to LFXT1CLK for Clock MCLK
Select LFXT1CLK DCOCLK
LFXT1CLK MCLK DCOCLK Wait for +LFXT1CLK LFXT1CLK
Basic Clock Module
7-17
Basic Clock Module Control Registers
7.5 Basic Clock Module Control Registers
The Basic Clock Module is configured using control registers DCOCTL, BCSCTL1, and BCSCTL2, and four bits from the CPU status register: SCG1, SCG0, OscOff, and CPUOFF. User software can modify these control registers from their default condition at any time. The Basic Clock Module control registers are located in the byte-wide peripheral map and should be accessed with byte (.B) instructions.
Register Short Form Register Type Read/write Read/write Read/write Address 056h 057h 058h Initial State 060h 084h reset
DCO control DCOCTL register Basic clock BCSCTL1 system control 1 Basic clock BCSCTL2 system control 1
7.5.1
Digitally-Controlled Oscillator (DCO) Clock-Frequency Control
DCOCTL is loaded with a value of 060h with a valid PUC condition.
7 DCOCTL 056h DCO.2 DCO.1 DCO.0 MOD.4 MOD.3 MOD.2 MOD.1 MOD.0 rw-0 rw-1 rw-1 rw-0 rw-0 rw-0 rw-0 rw-0 0
MOD.0 .. MOD.4: The MOD constant defines how often the discrete frequency fDCO+1 is used within a period of 32 DCOCLK cycles. During the remaining clock cycles (32-MOD) the discrete frequency fDCO is used. When the DCO constant is set to seven, no modulation is possible since the highest feasible frequency has then been selected. DCO.0 .. DCO.2: The DCO constant defines which one of the eight discrete frequencies is selected. The frequency is defined by the current injected into the dc generator.
7.5.2
Oscillator and Clock Control Register
BCSCTL1 is affected by a valid PUC or POR condition.
7 BCSCTL1 057h XT2Off XTS rw-(1) DIVA.1 DIVA.0 XT5V Rsel.2 Rsel.1 Rsel.0 rw-(0) rw-0 rw-1 rw-0 rw-0 rw-(0) rw-(0) 0
Bit0 to Bit2: The internal resistor is selected in eight different steps. Rsel.0 to Rsel.2 The value of the resistor defines the nominal frequency. The lowest nominal frequency is selected by setting Rsel=0. Bit3, XT5V: XT5V should always be reset.
Bit4 to Bit5: The selected source for ACLK is divided by: DIVA = 0: 1 DIVA = 1: 2 DIVA = 2: 4 DIVA = 3: 8
7-18
Basic Clock Module Control Registers
Bit6, XTS: The LFXT1 oscillator operates with a low-frequency clock crystal or with a high-frequency crystal: XTS = 0: The low-frequency oscillator is selected. XTS = 1: The high-frequency oscillator is selected. The oscillator selection must meet the external crystal's operating condition. Bit7, XT2Off: The XT2 oscillator is switched on or off: XT2Off = 0: the oscillator is on XT2Off = 1: the oscillator is off if it is not used for MCLK or SMCLK. BCSCTL2 is affected by a valid PUC or POR condition.
7 BCSCTL2 058h SELM.1 rw-(0) SELM.0 DIVM.1 DIVM.0 SELS DIVS.1 DIVS.0 DCOR rw-(0) rw-(0) rw-(0) rw-0 rw-0 rw-0 rw-0 0
Bit0, DCOR: The DCOR bit selects the resistor for injecting current into the dc generator. Based on this current, the oscillator operates if activated. DCOR = 0: Internal resistor on, the oscillator can operate. The failsafe mode is on. DCOR = 1: Internal resistor off, the current must be injected externally if the DCO output drives any clock using the DCOCLK. Bit1, Bit2: The selected source for SMCLK is divided by:
DIVS.1 .. DIVS.0 DIVS = 0: 1 DIVS = 1: 2 DIVS = 2: 4 DIVS = 3: 8 Bit3, SELS: Selects the source for generating SMCLK: SELS = 0: Use the DCOCLK SELS = 1: Use the XT2CLK signal (in three-oscillator systems) or LFXT1CLK signal (in two-oscillator systems) The selected source for MCLK is divided by:
Bit4, Bit5:
DIVM.0 .. DIVM.1 DIVM = 0: 1 DIVM = 1: 2 DIVM = 2: 4 DIVM = 3: 8 Bit6, Bit7: Selects the source for generating MCLK: SELM.0 .. SELM.1 SELM = 0: Use the DCOCLK SELM = 1: Use the DCOCLK SELM = 2: Use the XT2CLK (x13x and x14x devices) or Use the LFXT1CLK (x11x(1) devices) SELM = 3: Use the LFXT1CLK
Basic Clock Module
7-19
Basic Clock Module Control Registers
7.5.3
Special-Function Register Bits
The Basic Clock Module affects two bits in the special-function registers OFIFG and OFIE. The oscillator fault-interrupt enable bit (OFIE) is located in bit 1 of the interrupt-enable register IE1. The oscillator fault-interrupt flag bit (OFIFG) is located in bit 1 of the interrupt-flag register IFG1.
IE1 00h 7 6 5 4 3 2 1 OFIE rw-0 IFG1 02h 7 6 5 4 3 2 1 OFIFG rw-1 0 0
The oscillator fault signal XT_OscFault sets the OFIFG as long as the oscillator fault condition is active. The detection and effect of the oscillator fault condition is described in section 7.4.1. The oscillator fault interrupt requests a nonmaskable interrupt if the OFIE bit is set. The oscillator interrupt-enable bit is reset automatically if a non-maskable interrupt is accepted. The initial state of the OFIE bit is reset and no oscillator fault requests an interrupt even if a fault condition occurs.
7-20
Chapter 8
Digital I/O Configuration
This chapter describes the digital I/O configuration.
Topic
8.1 8.2 8.3
Page
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 General Ports P1, P2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 General Ports P3, P4, P5, P6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9
Digital I/O Configuration
8-1
Introduction
8.1 Introduction
The general-purpose I/O ports of the MSP430 are designed to give maximum flexibility. Each I/O line is individually configurable, and most have interrupt capability. There are two different types of I/O port modules in the MSP430x1xx family devices. Ports P1 and P2 are of one type, and ports P3 to P6 are of another type. Both types have the capability to control input/output direction and output level, to read the level applied to a pin, and to control if a port or module function is applied to a pin. The port module for P1 and P2 have interrupt capability; flag, enable, and edge sensitivity are available individually for each bit. MSP430x11x and MSP430x11x1 devices have ports P1 and P2 implemented; MSP430x13x and MSP430x14x have ports P1 to P6 implemented.
8-2
Ports P1, P2
8.2 Ports P1, P2
Each of the general-purpose ports P1 and P2 contain 8 general-purpose I/O lines and all of the registers required to control and configure them. Each I/O line is capable of being controlled independently. In addition, each I/O line is capable of producing an interrupt. Separate vectors are allocated to ports P1 and P2 modules. The pins for port P1 (P1.0-7) source one interrupt, and the pins for port P2 (P2.0-7) source another interrupt. Seven registers are used to control the port I/O pins (see Section 8.2.1). Ports P1 and P2 are connected to the processor core through the 8-bit MDB and the MAB. They should be accessed using byte instructions in the absolute address mode.
Figure 8-1. Port P1, Port P2 Configuration
MDB 8 R8
8 R/W 8 8 R/W 8 8 R/W R/W Function Select PnSEL n = 1: 026h n = 2: 02Eh
Input Register PnIN n = 1: 020h n = 2: 028h Output Register PnOUT n = 1: 021h n = 2: 029h R/W Direction Register PnDIR n = 1: 022h n = 2: 02Ah
Interrupt Flags PnIFG n = 1: 023h n = 2: 02Bh R/W Interrupt Edge Select PnIES n = 1: 024h n = 2: 02Ch
Interrupt Enable PnIE n = 1: 025h n = 2: 02Dh
MSB Pn.7
LSB Pn.0
Digital I/O Configuration
8-3
Ports P1, P2
8.2.1
Port P1, Port P2 Control Registers
The seven control registers give maximum digital input/output configuration flexibility:
-
All individual I/O bits are independently programmable. Any combination of input, output, and interrupt condition is possible. Interrupt processing of external events is fully implemented for all eight bits of ports P1 and P2.
The seven registers for port P1 and the seven registers for port P2 are shown in Table 8-1 and Table 8-2, respectively.
Table 8-1. Port P1 Registers
Register Input Output Direction Interrupt flags Interrupt edge select Interrupt enable Function select Short Form P1IN P1OUT P1DIR P1IFG P1IES P1IE P1SEL Register Type Read only Read/write Read/write Read/write Read/write Read/write Read/write Address 020h 021h 022h 023h 024h 025h 026h Initial State ----- Unchanged Reset Reset Unchanged Reset Reset
Table 8-2. Port P2 Registers
Short Form P2IN P2OUT P2DIR P2IFG P2IES P2IE P2SEL Register Type Read only Read/write Read/write Read/write Read/write Read/write Read/write
Register Input Output Direction Interrupt flags Interrupt edge select Interrupt enable Function select
Address 028h 029h 02Ah 02Bh 02Ch 02Dh 02Eh
Initial State ----- Unchanged Reset Reset Unchanged Reset Reset
These registers contain eight bits, and should be accessed using byte instructions in absolute-address mode.
8.2.1.1
Input Registers P1IN, P2IN
Both Input registers are read-only registers that reflect the signals at the I/O pins. Note: Writing to Read-Only Registers P1IN, P2IN Writing to these read-only registers results in increased current consumption while the write attempt is active.
8-4
Ports P1, P2
8.2.1.2
Output Registers P1OUT, P2OUT
Each output register shows the information of the output buffer. The output buffer can be modified by all instructions that write to a destination. If read, the contents of the output buffer are independent of pin direction. A direction change does not modify the output buffer contents.
8.2.1.3
Direction Registers P1DIR, P2DIR
The direction registers contain eight independent bits that define the direction of the I/O pin. All bits are reset by the PUC signal. When: Bit = 0: The port pin is switched to input direction (3-state) Bit = 1: The port pin is switched to output direction
8.2.1.4
Interrupt Flags P1IFG, P2IFG
Each interrupt flag register contains eight flags that reflect whether or not an interrupt is pending for the corresponding I/O pin, if the I/O is interrupt-enabled. When: Bit = 0: No interrupt is pending Bit = 1: An interrupt is pending due to a transition at the I/O pin or from software setting the bit. Note: Manipulating P1OUT and P1DIR, as well as P2OUT and P2DIR, can result in setting the P1IFG or P2IFG bits. Writing a zero to an interrupt flag resets it; writing a one to an interrupt flag sets it and generates an interrupt. Each group of interrupt flags P1FLG.0 to P1FLG.7 and P2FLG.0 to P2FLG.7 sources its own interrupt vector. Interrupt flags P1IFG.0 to P1IFG.7 and P2IFG.0 to P2IFG.7 are not reset automatically when an interrupt from these events is serviced. The software should determine the origin of the interrupt and reset the appropriate flag(s). Note: Any external interrupt event should be at least 1.5 times MCLK or longer, to ensure that it is accepted and the corresponding interrupt flag is set.
Digital I/O Configuration
8-5
Ports P1, P2
8.2.1.5
Interrupt Edge Select P1IES, P2IES
Each interrupt edge select register contains a bit for each corresponding I/O pin to select what type of transition triggers the interrupt flag. When: Bit = 0: The interrupt flag is set with a low-to-high transition Bit = 1: The interrupt flag is set with a high-to-low transition Note: Changing the P1IES and P2IES bits can result in setting the associated interrupt flags. PnIES.x 01 01 10 10 PnIN.x 0 1 0 1 PnIFG.x Unchanged May be set May be set Unchanged
8.2.1.6
Interrupt Enable P1IE, P2IE
Each interrupt enable register contains bits to enable the interrupt flag for each I/O pin in the port. Each of the sixteen bits corresponding to pins P1.0 to P1.7 and P2.0 to P2.7 is located in the P1IE and P2IE registers. When: Bit = 0: The interrupt request is disabled Bit = 1: The interrupt request is enabled Note: Port P1, Port P2 Interrupt Sensitivity Only transitions, not static levels, cause interrupts. If an interrupt flag is still set when the RETI instruction is executed (for example, a transition occurs during the interrupt service routine), an interrupt occurs again after RETI is completed. This ensures that each transition is acknowledged by the software.
8.2.1.7
Function Select Registers P1SEL, P2SEL
P1 and P2 port pins are often multiplexed with other peripheral modules to reduce overall pin count on MSP430 devices (see the specific device data sheet to determine which other peripherals also use the device pins). Control registers P1SEL and P2SEL are used to select the desired pin function--I/O port or other peripheral module. Each register contains eight bits corresponding to each pin, and each pin's function is individually selectable. All bits in these registers are reset by the PUC signal. The bit definitions are: Bit = 0: Port P1 or P2 function is selected for the pin Bit = 1: Other peripheral module function is selected for the pin
8-6
Ports P1, P2
Note: Function Select With P1SEL, P2SEL The interrupt-edge-select circuitry is disabled if control bit PnSEL.x is set. Therefore, the input signal can no longer generate an interrupt. When a port pin is selected to be used as an input to a peripheral module other than the I/O port (PnSEL.x = 1), the actual input signal to the peripheral module is a latched representation of the signal at the device pin (see Figure 8-2 schematic). The latch uses the PnSEL.x bit as its enable, so while PnSEL.x=1, the internal input signal simply follows the signal at the pin. However, if the PnSEL.x bit is reset, then the output of the latch (and therefore the input to the other peripheral module) represents the value of the signal at the device pin just prior to the bit being reset.
8.2.2
Port P1, Port P2 Schematic
The pin logic of each individual port P1 and port P2 signal is identical. Each bit can be read and written to as shown in Figure 8-2.
Figure 8-2. Schematic of One Bit in Port P1, P2
PnSEL.x PnDIR.x Direction Control From Module PnOUT.x Module X OUT Output MUX Pad Logic Output MUX
Pn.x
PnIN.x EN Module x IN Y A PnIRQ.x PnIE.x PnIFG.x PnIRQ.y Request Interrupt Pn.07 PnIRQ.z Interrupt Flag Interrupt Edge Select PnIES.x PnSEL.x
x = 0 to 7, according to bits 0 to 7 n = 1 for Port P1 and 2 for Port P2
Digital I/O Configuration
8-7
Ports P1, P2
8.2.3
Port P1, P2 Interrupt Control Functions
Ports P1 and P2 use eight bits for interrupt flags, eight bits to enable interrupts, eight bits to select the effective edge of an interrupt event, one interrupt vector address for port P1, and one interrupt vector address for port P2. Each signal uses three bits for configuration and interrupt:
-
Interrupt flag, P1IFG.0 to P1IFG.7 and P2IFG.0 to P2IFG.7 Interrupt enable bit, P1IE.0 to P1IE.7 and P2IE.0 to P2IE.7 Interrupt edge select bit, P1IES.0 to P1IES.7 and P2IES.0 to P2IES.7
The interrupt flags P1IFG.0 to P1IFG.7 source one interrupt and P2IFG.0 to P2IFG.7 source one interrupt. Any interrupt event on one or more pins of P1.0 to P1.7 or P2.0 to P2.7 requests an interrupt when two conditions are met: the appropriate individual bit PnIE.x is set, and the GIE bit is set. Interrupt flags P1IFG.0 to P1IFG.7 or P2IFG.0 to P2IFG.7 are not automatically reset. The software of the interrupt service routine should handle the detection of the source, and reset the appropriate flag when it is serviced.
8-8
Ports P3, P4, P5, P6
8.3 Ports P3, P4, P5, P6
General-purpose ports P3-P6 function as shown in Figure 8-3. Each pin can be selected to operate with the I/O port function, or to be used with a different peripheral module. This multiplexing of pins allows for a reduced pin count on MSP430 devices. Four registers control each of the ports (see Section 8.3.1). Ports P3-P6 are connected to the processor core through the 8-bit MDB and the MAB. They should be accessed with byte instructions using the absolute address mode.
Figure 8-3. Ports P3-P6 Configuration
MDB 8 R8
8 R/W 8
Input Register PnIN n = 3: 018h n = 4: 01Ch n = 5: 030h n = 6: 034h Output Register PnOUT n = 3: 019h n = 4: 01Dh n = 5: 031h n = 6: 035h R/W Direction Register PnDIR R/W n = 3: 01Ah Function Select n = 4: 01Eh Register PnSEL n = 5: 032h n = 3: 01Bh n = 6: 036h n = 4: 01Fh n = 5: 033h n = 6: 037h
MSB Pn.7
LSB Pn.0
8.3.1
Port P3-P6 Control Registers
The four control registers of each port give maximum configuration flexibility of digital I/O.
-
All individual I/O bits are programmed independently Any combination of input is possible Any combination of port or module function is possible
The four registers for each port are shown in Table 8-3. They each contain eight bits and should be accessed with byte instructions.
Digital I/O Configuration
8-9
Ports P3, P4, P5, P6
Table 8-3. Port P3-P6 Registers
Register Input Short Form P3IN P4IN P5IN P6IN Output P3OUT P4OUT P5OUT P6OUT Direction P3DIR P4DIR P5DIR P6DIR Port Select P3SEL P4SEL P5SEL P6SEL Address 018h 01Ch 030h 034h 019h 01Dh 031h 035h 01Ah 01Eh 032h 036h 01Bh 01Fh 033h 037h Register Type Read only Read only Read only Read only Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Initial State ----- ----- ----- ----- Unchanged Unchanged Unchanged Unchanged Reset Reset Reset Reset Reset Reset Reset Reset
8.3.1.1
Input Registers
The input registers are read-only registers that reflect the signal at the I/O pins. Note: Writing to Read-Only Register Any attempt to write to these read-only registers results in an increased current consumption while the write attempt is active.
8.3.1.2
Output Registers
The output registers show the information of the output buffers. The output buffers can be modified by all instructions that write to a destination. If read, the contents of the output buffer are independent of the pin direction. A direction change does not modify the output buffer contents.
8.3.1.3
Direction Registers
The direction registers contain eight independent bits that define the direction of each I/O pin. All bits are reset by the PUC signal. When: Bit = 0: The port pin is switched to input direction Bit = 1: The port pin is switched to output direction
8-10
Ports P3, P4, P5, P6
8.3.1.4
Function Select Registers PnSEL
Ports P3-P6 pins are often multiplexed with other peripheral modules to reduce overall pin count on MSP430 devices (see the specific device data sheet to determine which other peripherals also use the device pins). Control registers PnSEL are used to select the desired pin function--I/O port or other peripheral module. Each register contains eight bits corresponding to each pin, and each pin's function is individually selectable. All bits in these registers are reset by the PUC signal. The bit definitions are: Bit = 0: Port function is selected for the pin Bit = 1: Other peripheral module function is selected for the pin Note: Function Select With PnSEL Registers The interrupt-edge-select circuitry is disabled if control bit PnSEL.x is set. Therefore, the input signal can no longer generate an interrupt. When a port pin is selected to be used as an input to a peripheral module other than the I/O port (PnSEL.x=1), the actual input signal to the peripheral module is a latched representation of the signal at the device pin (see Figure 8-4 schematic). The latch uses the PnSEL.x bit as its enable, so while PnSEL.x=1, the internal input signal simply follows the signal at the pin. However, if the PnSEL.x bit is reset, then the output of the latch (and therefore the input to the other peripheral module) represents the value of signal at the device pin, just prior to the bit being reset.
8.3.2
Port P3-P6 Schematic
The pin logic of each individual port signal is shown in Figure 8-4.
Figure 8-4. Schematic of Bits Pn.x
PnSEL.x PnDIR.x Direction Control From Module PnOUT.x Module x OUT Output MUX Pad Logic Output MUX
Pn.x
PnIN.x EN Module x IN Y A n = 3 for Port3, 4 for Port P4, 5 for Port P5, and 6 for Port P6 x = 0 to 7, according to bits 0 to 7
Digital I/O Configuration
8-11
8-12
Chapter 9
Watchdog Timer
This chapter discusses the Watchdog Timer.
Topic
9.1
Page
The Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
Watchdog Timer
9-1
The Watchdog Timer
9.1 The Watchdog Timer
The primary function of the watchdog-timer module (WDT) is to perform a controlled-system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can work as an interval timer, to generate an interrupt after the selected time interval. The WDT diagram is shown in Figure 9-1.
Figure 9-1. Schematic of Watchdog Timer
See Interrupt Definition Int. Flag WDTQn Y 4 3 2 1 A Pulse Generator B Q6 Q9 Q13 Q15 16b Counter WDTCNT 0 1 0 1 1 0 1 Clear PUC (Asyn) EQU SMCLK ACLK 1 1 A EN CLK 0 EQU Write Enable Low Byte R/W HOLD NMIES NMI TMSEL CNTCL SSEL IS1 IS0 Watchdog Timer Control Register LSB PUC Password Cmp. 16 WDTCTL MDB MSB
Features of the Watchdog Timer include:
-
Eight software-selectable time intervals Two operating modes: as watchdog or interval timer Expiration of the time interval in watchdog mode, which generates a system reset; or in timer mode, which generates an interrupt request Safeguards which ensure that writing to the WDT control register is only possible using a password Support of ultralow-power using the hold mode
9-2
The Watchdog Timer
9.1.1
Watchdog Timer Register
The watchdog-timer counter (WDTCNT) is a 16-bit up-counter that is not directly accessible by software. The WDTCNT is controlled through the watchdog-timer control register (WDTCTL), shown in Figure 9-2, which is a 16-bit read/write register located at the low byte of word address 0120h. Any read or write access must be done using word instructions with no suffix or .w suffix. In both operating modes (watchdog or timer), it is only possible to write to WDTCTL using the correct password.
Figure 9-2. Watchdog Timer Control Register
15 WDTCTL 0120h WDTCTL read WDTCTL write 8 7 HOLD NMIES NMI rw-0 069h 05Ah rw-0 rw-0 TMSEL CNTCL SSEL rw-0 r0(w) rw-0 IS1 rw-0 0 IS0 rw-0
Bits 0, 1: Bits IS0 and IS1 select one of four taps from the WDTCNT, as described in Table 9-1. Assuming fcrystal = 32,768 Hz and fSystem = 1 MHz, the following intervals are possible:
Table 9-1. WDTCNT Taps
SSEL 0 0 1 0 1 0 1 1 IS1 1 1 1 0 1 0 0 0 IS0 1 0 1 1 0 0 1 0 Interval [ms] 0.064 0.5 1.9 8 16.0 32 250 1000 tSMCLK x 26 tSMCLK x 29 tACLK x 26 tSMCLK x 213 tACLK x 29 tSMCLK x 215 <- Value after PUC (reset) tACLK x 213 tACLK x 215
Bit 2:
The SSEL bit selects the clock source for WDTCNT. SSEL = 0: WDTCNT is clocked by SMCLK . SSEL = 1: WDTCNT is clocked by ACLK. Counter clear bit. In both operating modes, writing a 1 to this bit restarts the WDTCNT at 00000h. The value read is not defined. The TMSEL bit selects the operating mode: watchdog or timer. TMSEL = 0: Watchdog mode TMSEL = 1: Interval-timer mode
Bit 3:
Bit 4:
Watchdog Timer
9-3
The Watchdog Timer
Bit 5:
The NMI bit selects the function of the RST/NMI input pin. It is cleared by the PUC signal. NMI = 0: The RST/NMI input works as reset input. As long as the RST/NMI pin is held low, the internal signal is active (level sensitive). NMI = 1: The RST/NMI input works as an edge-sensitive nonmaskable interrupt input. If the NMI function is selected, this bit selects the activating edge of the RST/NMI input. It is cleared by the PUC signal. NMIES = 0: A rising edge triggers an NMI interrupt. NMIES = 1: A falling edge triggers an NMI interrupt. CAUTION: Changing the NMIES bit with software can generate an NMI interrupt. This bit stops the operation of the watchdog counter. The clock multiplexer is disabled and the counter stops incrementing. It holds the last value until the hold bit is reset and the operation continues. It is cleared by the PUC signal. HOLD = 0: The WDT is fully active. HOLD = 1: The clock multiplexer and counter are stopped.
Bit 6:
Bit 7:
9.1.1.1
Accessing the WDTCTL (Watchdog Timer Control Register)
The WDTCTL register can be read or written to. As illustrated in Figure 9-3, WDTCTL can be read without the use of a password. A read access is performed by accessing word address 0120h. The low byte contains the value of WDTCTL. The value of the high byte is always read as 069h.
Figure 9-3. Reading WDTCTL
15 WDTCTL 0120h
0 1 1 0 1 0 0
8
1
7
Read Data
0
r
r 6
r
r
r
r 9
r
r
rw-x, (w)
Write access to WDTCTL, illustrated in Figure 9-4, is only possible using the correct high-byte password. To change register WDTCTL, write to word address 0120h. The low byte contains the data to write to WDTCTL. The high byte is the password, which is 05Ah. A system reset (PUC) is generated if any value other than 05Ah is written to the high byte of address 0120h.
Figure 9-4. Writing to WDTCTL
15 WDTCTL 0120h
0 1 0 1 1 0 1
8
0
7
Write Data
0
(w) (w) (w) (w) (w) (w) (w) (w) 5 A
rw-x, (w)
9-4
The Watchdog Timer
9.1.2
Watchdog Timer Interrupt Control Functions
The Watchdog Timer (WDT) uses two bits in the SFRs for interrupt control.
-
The WDT interrupt flag (WDTIFG) (located in IFG1.0, initial state is reset) The WDT interrupt enable (WDTIE) (located in IE1.0, initial state is reset)
When using the watchdog mode, the WDTIFG flag is used by the reset interrupt service routine to determine if the watchdog caused the device to reset. If the flag is set, then the Watchdog Timer initiated the reset condition (either by timing out or by a security key violation). If the flag is cleared, then the PUC was caused by a different source. See chapter 3 for more details on the PUC and POR signals. When using the Watchdog Timer in interval-timer mode, the WDTIFG flag is set after the selected time interval and a watchdog interval-timer interrupt is requested. The interrupt vector address in interval-timer mode is different from that in watchdog mode. In interval-timer mode, the WDTIFG flag is reset automatically when the interrupt is serviced. The WDTIE bit is used to enable or disable the interrupt from the Watchdog Timer when it is being used in interval-timer mode. Also, the GIE bit enables or disables the interrupt from the Watchdog Timer when it is being used in interval-timer mode.
9.1.3
Watchdog Timer Operation
The WDT module can be configured in two modes: watchdog and the intervaltimer modes.
9.1.3.1
Watchdog Mode
When the WDT is configured to operate in watchdog mode, both a watchdog overflow and a security violation trigger the PUC signal, which automatically clears the appropriate system register bits. This results in a system configuration for the WDTCTL bits where the WDT is set into the watchdog mode and the RST/NMI pin is switched to the reset configuration. After a power-on reset or a system reset, the WDT module automatically enters the watchdog mode and all bits in the WDTCTL register and the watchdog counter (WDTCNT) are cleared. The initial conditions at register WDTCTL cause the WDT to start running at a relatively-low frequency, due to the range of the digitally-controlled oscillator (DCO) automatically being set in these situations. Since the WDTCNT is reset, the user software has ample time to set up or halt the WDT and to adjust the system frequency. Users must refer to the specific data sheets and the clock-system chapter of this manual to determine the details of the clocking circuit on the MSP430 device chosen.
Watchdog Timer
9-5
The Watchdog Timer
When the module is used in watchdog mode, the software should periodically reset the WDTCNT by writing a 1 to bit CNTCL of WDTCTL to prevent expiration of the selected time interval. If a software problem occurs and the time interval expires because the counter is no longer being reset, a system reset is generated and a system PUC signal is activated. The system restarts at the same program address that follows a power up. The cause of reset can be determined by testing bit 0 of interrupt flag register 1 in the SFRs. The appropriate time interval is selected by setting bits SSEL, IS0, and IS1 accordingly.
9.1.3.2
Timer Mode
Setting WDTCTL register bit TMSEL to 1 selects the timer mode. This mode provides periodic interrupts at the selected time interval. A time interval can also be initiated by writing a 1 to bit CNTCL in the WDTCTL register. When the WDT is configured to operate in timer mode, the WDTIFG flag is set after the selected time interval, and it requests a standard interrupt service. The WDT interrupt flag is a single-source interrupt flag and is automatically reset when it is serviced. The enable bit remains unchanged. In interval-timer mode, the WDT interrupt-enable bit and the GIE bit must be set to allow the WDT to request an interrupt. The interrupt vector address in timer mode is different from that in watchdog mode. Note: Watchdog Timer, Changing the Time Interval Changing the time interval without clearing the WDTCNT may result in an unexpected and immediate system reset or interrupt. The time interval must be changed together with a counter-clear command using a single instruction (for example, MOV #05A0Ah,&WDTCTL). Changing the clock source during normal operation may result in an incorrect interval. The timer should be halted before changing the clock source.
9.1.3.3
Operation in Low-Power Modes
The MSP430 devices have several low-power modes. Different clock signals are available in different low-power modes. The requirements of the user's application and the type of clocking circuit on the MSP430 device determine how the Watchdog Timer and clocking signals should be configured. Review the device data sheet and clock-system chapter to determine the clocking circuit, clock signals, and low-power modes available. For example, the WDT should not be configured in watchdog mode with SMCLK as its clock source if the user wants to use low-power mode 3 because SMCLK is not active in LPM3, therefore the WDT would not function properly. The WDT hold condition can also be used to support low power operation. The hold condition can be used in conjunction with low-power modes when needed.
9-6
The Watchdog Timer
9.1.3.4
Software Example
The following example illustrates the watchdog-reset operation.
; After RESET or power-up, the WDTCTL register and WDTCNT ; are cleared and the initial operating conditions are ; watchdog mode with a time interval of 32 ms. ; ;Constant definitions: ; WDTCTL .EQU 0120h ; Address of Watchdog Timer WDTPW .EQU 05A00h ; Password T250MS .EQU 5 ; SSEL, IS0, IS1 set to 250 ms T05MS .EQU 2 ; SSEL, IS0, IS1 set to 0.5 ms CNTCL .EQU 8 ; Bit position to reset WDTCNT TMSEL .EQU 010h ; Bit position to select timer mode ; ; As long as watchdog mode is selected, watchdog reset has ; to be done periodically through an instruction e.g.: ; ........ ........ MOV #WDTPW+CNTCL,&WDTCTL ; ; To change to timer mode and a time interval of 250 ms, ; the following instruction sequence can be used: ; MOV #WDTPW+CNTCL+TMSEL+T250MS,&WDTCTL ; Clear WDTCNT and ; select 250 ms and timer ; mode ........ ........ ; Note: The time interval and clear of WDTCNT should be ; modified within one instruction to avoid ; unexpected reset or interrupt ; ; Switching back to watchdog mode and a time interval of ; 0.5 ms is performed by: ; ........ ........ MOV #WDTPW+CNTCL,&WDTCTL ; Reset WDT counter ; MOV #WDTPW+T05MS,&WDTCTL ; Select watchdog mode ; and 0.5 ms ........
Watchdog Timer
9-7
9-8
Chapter 10
Timer_A
This section describes the basic functions of the MSP430 general-purpose 16-bit Timer_A. All capture/compare blocks (CCR) are identical. MSP430x11x, MSP430x11x1, and MSP430x13x have three CCRs (Timer_A3) and MSP430x14x has five CCRs (Timer_A5) implemented. Note: Throughout this chapter, the word count is used in the text. As used in these instances, it refers to the literal act of counting. It means that the counter must be in the process of counting for the action to take place. If a particular value is directly written to the counter, then the associated action will not take place. For example, the CCR0 interrupt flag is set when the timer counts up to the value in CCR0. The counter must count from CCR0-1 to CCR0. If the CCR0 value were simply written directly to the timer with software, the interrupt flag would not be set, even though the values in the timer and the CCR0 registers are the same.
Topic
Page
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.2 Time Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.3 Timer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 10.4 Capture/Compare Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13 10.5 The Output Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19 10.6 Timer_A Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24 10.7 Timer_A UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-33
Timer_A
10-1
Introduction
10.1 Introduction
Timer_A is an extremely versatile timer made up of :
-
16-bit counter with 4 operating modes Selectable and configurable clock source Three or five independently configurable capture/compare registers with configurable inputs Three or five individually configurable output modules with 8 output modes
Timer_A can support multiple, simultaneous, timings; multiple capture/ compares; multiple output waveforms such as PWM signals; and any combination of these. Also, each capture/compare register has hardware support for implementing serial communications such as UART protocol (see section 10.7). Additionally, Timer_A has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers on captures or compares. Each capture/compare block is individually configurable and can produce interrupts on compares or on rising, falling, or both edges of an external capture signal. The block diagram of Timer_A is shown in Figure 10-1.
10-2
Introduction
Figure 10-1. Timer_A Block Diagram
Timer Clock
TPSSEL1
TACLK ACLK SMCLK INCLK
TPSSEL0
0 1 2 3 15 Input Divider
Data 0 16-Bit Timer Mode Control
16-Bit Timer
CLK 1
POR/CLR
RC Carry/Zero Timer Bus
Equ0
Set_TAIFG
ID1 ID0
MC1
MC0
CCIS01 CCIS00
CCI0A CCI0B GND VCC 0 1 2 3 CCI0 Capture Mode Capture
0 15 Capture/Compare Register CCR0
Capture/Compare Register CCR0 OM02 OM01 OM00
Out 0
Output Unit 0 Comparator 0 EQU0
CCM01 CCM00 Capture/Compare Register CCR1 OM12 OM11 OM10
CCIS11 CCIS10
CCI1A CCI1B GND VCC 0 1 2 3 CCI1 Capture Capture Mode
0 15 Capture/Compare Register CCR1
Out 1
Output Unit 1 Comparator 1 EQU1
CCM11 CCM10 Capture/Compare Register CCR2 OM22 OM21 OM20
CCIS21 CCIS20
CCI2A CCI2B GND VCC 0 1 2 3 CCI2 Capture Capture Mode
0 15 Capture/Compare Register CCR2
Out 2
Output Unit 2 Comparator 2 EQU2
CCM21 CCM20 Capture/Compare Register CCR3 OM32 OM31 OM30
CCIS31 CCIS30
CCI3A CCI3B GND VCC 0 1 2 3 CCI3 Capture Capture Mode
15 Capture/Compare Register CCR3
0
Out 3
Output Unit 3
Comparator 3 EQU3 CCM31 CCM30 Capture/Compare Register CCR4 OM42 OM41 OM40
CCIS41 CCIS40
CCI4A CCI4B GND VCC 0 1 2 3 CCI4 Capture Capture Mode
15 Capture/Compare Register CCR4
0
Out 4
Output Unit 4
Comparator 4 EQU4 CCM41 CCM40
Timer_A
10-3
Timer_A Operation
10.2 Timer_A Operation
The 16-bit timer has 4 modes of operation selectable with the MC0 and MC1 bits in the TACTL register. The timer increments or decrements (depending on mode of operation) with each rising edge of the clock signal. The timer can be read or written to with software. Additionally, the timer can generate an interrupt with its ripple-carry output when it overflows.
10.2.1 Timer Mode Control
The timer has four modes of operation as shown in Figure 10-2 and described in Table 10-1: stop, up, continuous, and up/down. The operating mode is software selectable with the MC0 and MC1 bits in the TACTL register.
Figure 10-2. Mode Control
Data 15 Timer Clock 16-Bit Timer
CLK
0 Mode Control
Equ0
RC Carry/Zero
POR
MC1 0 0 1 1
MC0 0 1 0 1
Set_TAIFG Stop Mode Up Mode Continuous Mode Up/Down Mode
Table 10-1.Timer Modes
Mode Control MC1 0 0 1 1 MC0 0 1 0 1 Mode Stop Up Continuous Up/Down Description The timer is halted. The timer counts upward until value is equal to value of compare register CCR0. The timer counts upward continuously. The timer counts up until the timer value is equal to compare register 0 and then it counts down to zero.
10-4
Timer_A Operation
10.2.2 Clock Source Select and Divider
The timer clock can be sourced from internal clocks (i.e. ACLK or SMCLK) or from an external source (TACLK) as shown in Figure 10-3. The clock source is selectable with the SSEL0 and SSEL1 bits in the TACTL register. It is important to note that when changing the clock source for the timer, errant timings can occur. For this reason stopping the timer before changing the clock source is recommended. The selected clock source may be passed directly to the timer or divided by 2,4, or 8, as shown in Figure 10-4. The ID0 and ID1 bits in the TACTL register select the clock division. Note that the input divider is reset by a POR signal (see chapter 3, System, Resets, Interrupts, and Operating Modes for more information on the POR signal) or by setting the CLR bit in the TACTL register. Otherwise, the input divider remains unchanged when the timer is modified. The state of the input divider is invisible to software.
Figure 10-3. Schematic of 16-Bit Timer
SSEL1 SSEL0
Timer Clock 0 Input Divider
CLK
Data 15 16-Bit Timer RC Carry/Zero Mode Control
Equ0
TACLK ACLK SMCLK INCLK
0 1
2 ID1 3 0 0 1 1 ID0 0 1 0 1 Pass 1/2 1/4 1/8 POR/CLR
MC1 0 0 1 1
MC0 0 1 0 1
Set_TAIFG Stop Mode Up Mode Continuous Mode Up/Down Mode
Figure 10-4. Schematic of Clock Source Select and Input Divider
SSEL1 SSEL0 Input Divider
TACLK ACLK SMCLK INCLK
0 1
T
Q C
T
Q C
T
Q C
16-Bit Timer Clock
2 3 ID1 0 0 1 1 ID0 0 1 0 1 POR Pass 1/2 1/4 1/8 CLR
Timer_A
10-5
Timer_A Operation
10.2.3 Starting the Timer
The timer may be started or restarted in a variety of ways:
-
Release Halt Mode: The timer counts in the selected direction when a timer mode other than stop mode is selected with the MCx bits. Halted by CCR0 = 0, restarted by CCR0 > 0 when the mode is either up or up/down: When the timer mode is selected to be either up or up/down, the timer may be stopped by writing 0 to capture/compare register 0 (CCR0). The timer may then be restarted by writing a nonzero value to CCR0. In this scenario, the timer starts incrementing in the up direction from zero. Setting the CLR bit in TACTL register: Setting the CLR bit in the TACTL register clears the timer value and input clock divider value. The timer increments upward from zero with the next clock cycle as long as stop-mode is not selected with the MCx bits. TAR is loaded with 0: When the counter (TAR register) is loaded with zero with a software instruction the timer increments upward from zero with the next clock cycle as long as stop-mode is not selected with the MCx bits.
-
10-6
Timer Modes
10.3 Timer Modes
10.3.1 Timer--Stop Mode
Stopping and starting the timer is done simply by changing the mode control bits (MCx). The value of the timer is not affected. When the timer is stopped from up/down mode and then restarted in up/down mode, the timer counts in the same direction as it was counting before it was stopped. For example, if the timer is in up/down mode and counting in the down direction when the MCx bits are reset, when they are set back to the up/down direction, the timer starts counting in the down direction from its previous value. If this is not desired in an application, the CLR bit in the TACTL register can be used to clear this direction memory feature.
10.3.2 Timer--Up Mode
The up mode is used if the timer period must be different from the 65,536 (16-bit) clock cycles of the continuous mode period. The capture/compare register CCR0 data define the timer period. The counter counts up to the content of compare register CCR0, as shown in Figure 10-5. When the timer value and the value of compare register CCR0 are equal (or if the timer value is greater than the CCR0 value), the timer restarts counting from zero.
Figure 10-5. Timer Up Mode
0FFFFh CCR0
0h
Flag CCIFG0 is set when the timer equals the CCR0 value. The TAIFG flag is set when the timer counts from CCR0 to zero. All interrupt flags are set independently of the corresponding interrupt enable bit, but an interrupt is requested only if the corresponding interrupt enable bit and the GIE bit are set. Figure 10-6 shows the flag set cycle.
Figure 10-6. Up Mode Flag Setting
Timer Clock Timer Set Flag TAIFG Set Flag CCIFG0
CCR0-1 CCR0 0h 1h CCR0-1 CCR0 0h 1h
Timer_A
10-7
Timer Modes
10.3.2.1 Timer in Up Mode--Changing the Period Register CCR0 Value
Changing the timer period register CCR0 while the timer is running can be a little tricky. When the new period is greater than or equal to the old period, the timer simply counts up to the new period and no special attention is required (see Figure 10-7). However, when the new period is less than the old period, the phase of the timer clock during the CCR0 update affects how the timer reacts to the new period. If the new, smaller period is written to CCR0 during a high phase of the timer clock, then the timer rolls to zero (or begins counting down when in the up/down mode) on the next rising edge of the timer clock. However, if the new, smaller period is written during a low phase of the timer clock, then the timer continues to increment with the old period for one more clock cycle before adopting the new period and rolling to zero (or beginning counting down). This is shown in Figure 10-8.
Figure 10-7. New Period > Old Period
Timer Register 3 2 1 0 CCR0old = 2 CCR0new = 3
CCR0
2
Figure 10-8. New Period < Old Period
Timer Register 5 4 3 2 1 0
CCR0old = 5 CCR0new = 2
0 12 3 45 01 2 3 01 2 01 2 01 CCR0 5 2 CCR0
CCR0 Loaded With 2 During High Clock Phase Timer Clock Timer CCR0 CCRold n 0 or n-1 CCRnew
Load New CCR0 During High Phase of Clock
Up mode: 0; up/down mode: n-1
10-8
IIIII IIIII
5 4 3 2 1 0
0
1
2
0
1
2
3
0 3
1
2
3
0
1
Timer Register
CCR0old = 5 CCR0new = 2
012 3 45 012 3 401 201 201 5 2
CCR0 Loaded With 2 During Low Clock Phase
Timer Clock Timer CCR0 n CCRold n+1 CCRnew 0 or n
Load New CCR0 During Low Phase of Clock
Up mode: 0; up/down mode: n
Timer Modes
10.3.3 Timer--Continuous Mode
The continuous mode is used if the timer period of 65,536 clock cycles is used for the application. A typical application of the continuous mode is to generate multiple, independent timings. In continuous mode, the capture/compare register CCR0 works in the same way as the other compare registers. The capture/compare registers and different output modes of each output unit are useful to capture timer data based on external events or to generate various different types of output signals. Examples of the different output modes used with timer-continuous mode are shown in Figure 10-25. In continuous mode, the timer starts counting from its present value. The counter counts up to 0FFFFh and restarts by counting from zero as shown in Figure 10-9.
Figure 10-9. Timer--Continuous Mode
0FFFFh
0h
The TAIFG flag is set when the timer counts from 0FFFFh to zero. The interrupt flag is set independently of the corresponding interrupt enable bit, as shown in Figure 10-10. An interrupt is requested if the corresponding interrupt enable bit and the GIE bit are set.
Figure 10-10. Continuous Mode Flag Setting
Timer Clock Timer Set Interrupt Flag TAIFG
FFFE FFFF 0h 1h FFFE FFFF 0h 1h
Timer_A
10-9
Timer Modes
10.3.3.1 Timer--Use of the Continuous Mode
The continuous mode can be used to generate time intervals for the application software. Each time an interval is completed, an interrupt can be generated. In the interrupt service routine of this event, the time until the next event is added to capture/compare register CCRx as shown in Figure 10-11. Up to five independent time events can be generated using all five capture/compare blocks.
Figure 10-11.Output Unit in Continuous Mode for Time Intervals
0FFFFh
CCR0f CCR0e CCR0d CCR0c CCR0b CCR0a CCR0h CCR0g CCR0m CCR0l CCR0k CCR0j CCR0i
0h
Interrupt Events
t
t
t
t
t
t
t
t
t
t
t
t
Time intervals can be produced with other modes as well, where CCR0 is used as the period register. Their handling is more complex since the sum of the old CCRx data and the new period can be higher than the CCR0 value. When the sum CCRxold plus t is greater than the CCR0 data, the CCR0 value must be subtracted to obtain the correct time interval. The period is twice the value in the CCR0 register.
10.3.4 Timer--Up/Down Mode
The up/down mode is used if the timer period must be different from the 65,536 clock cycles, and if symmetrical pulse waveform generation is needed. In up/down mode, the timer counts up to the content of compare register CCR0, then back down to zero, as shown in Figure 10-12. The period is twice the value in the CCR0 register.
Figure 10-12. Timer Up/Down Mode
CCR0
0h
10-10
Timer Modes
The up/down mode also supports applications that require dead times between output signals. For example, to avoid overload conditions, two outputs driving an H-bridge must never be in a high state simultaneously. In the following example (see Figure 10-13), the tdead is: tdead = ttimer x (CCR1 - CCR3)= With: tdead ttimer Time during which both outputs need to be inactive Cycle time of the timer clock
CCRx Content of capture/compare register x
Figure 10-13. Output Unit in Up/Down Mode (II)
0FFFFh CCR0 CCR1 CCR3 0h Dead Time Output Mode 6: PWM Toggle/Set Output Mode 2: PWM Toggle/Reset TAIFG EQU1 EQU1 TAIFG EQU1 EQU1 EQU3 EQU0 EQU3 EQU3 EQU0 EQU3 Interrupt Events
The count direction is always latched with a flip-flop (Figure 10-14). This is useful because it allows the user to stop the timer and then restart it in the same direction it was counting before it was stopped. For example, if the timer was counting down when the MCx bits were reset, then it will continue counting in the down direction if it is restarted in up/down mode. If this is not desired, the CLR bit in the TACTL register must be used to clear the direction. Note that the CLR bit affects other setup conditions of the timer. Refer to Section 10.6 for a discussion of the Timer_A registers.
Figure 10-14. Timer Up/Down Direction Control
POR CLR in TACTL
Up/Down Mode TAR => CCR0 Timer Clock
Set D Reset Q
Up/Down For 16-Bit Timer TAR Low: Down Direction High: Up Direction
Timer_A
10-11
Timer Modes
In up/down mode, the interrupt flags (CCIFG0 and TAIFG) are set at equal time intervals (Figure 10-15). Each flag is set only once during the period, but they are separated by 1/2 the timer period. CCIFG0 is set when the timer counts from CCR0-1 to CCR0, and TAIFG is set when the timer completes counting down from 0001h to 0000h. Each flag is capable of producing a CPU interrupt when enabled.
Figure 10-15. Up/Down Mode Flag Setting
Timer Clock Timer Up/Down Set CCIFG0 Set TAIFG
CCR0-1 CCR0 CCR0-1 CCR0-2 2h 1h 0h 1h
10.3.4.1 Timer In Up/Down Mode--Changing the Value of Period Register CCR0
Changing the period value while the timer is running in up/down mode is even trickier than in up mode. Like in up mode, the phase of the timer clock when CCR0 is changed affects the timer's behavior. Additionally, in up/down mode, the direction of the timer also affects the behavior. If the timer is counting in the up direction when the new period is written to CCR0, the conditions in the up/down mode are identical to those in the up mode. See Section 10.3.2.1 for details. However, if the timer is counting in the down direction when CCR0 is updated, it continues its descent until it reaches zero. The new period takes effect only after the counter finishes counting down to zero. See Figure 10-16.
Figure 10-16. Altering CCR0--Timer in Up/Down Mode
Timer Register 5 4 3 2 1 0
0 123 4 5 432 1 01 234 3 2 1 012 3 21 012 1 0123 4 5 4 3 2 1 01 2 1 CCR0 5 2 4 2 5 2
10-12
Timer Modes
10.4 Capture/Compare Blocks
Three or five (depending on device) identical capture/compare blocks (shown in Figure 10-17) provide flexible control for real-time processing. Any one of the blocks may be used to capture the timer data at an applied event, or to generate time intervals. Each time a capture occurs or a time interval is completed, interrupts can be generated from the applicable capture/compare register. The mode bit CAPx, in control word CCTLx, selects the compare or capture operation and the capture mode bits CCMx1 and CCMx0 in control word CCTLx define the conditions under which the capture function is performed. Both the interrupt enable bit CCIEx and the interrupt flag CCIFGx are used for capture and compare modes. CCIEx enables the corresponding interrupt. CCIFGx is set on a capture or compare event. The capture inputs CCIxA and CCIxB are connected to external pins or internal signals. MSP430x1xx devices may have different signals connected to CCIxA and CCIxB. The data sheet should always be consulted to determine the Timer_A connections for a particular device.
Figure 10-17. Capture/Compare Blocks
Overflow x Logic
CCISx1 CCISx0
COVx Timer Bus 15 0
CCIxA CCIxB GND VCC
0 1 2 3
CAPx Capture Mode Capture
Capture/Compare Register CCRx
CCMx1 CCMx0 0 0 1 1 0 1 0 1 Disabled Positive Edge Negative Edge Both Edges Comparator x EQUx CAPx 0 1 Set_CCIFGx
EN A Y
SCCIx
CCIx
Timer_A
10-13
Timer Modes
10.4.1 Capture/Compare Block--Capture Mode
The capture mode is selected if the mode bit CAPx, located in control word CCTLx, is set. The capture mode is used to fix time events. It can be used for speed computations or time measurements. The timer value is copied into the capture register (CCRx) with the selected edge (positive, negative, or both) of the input signal. Captures may also be initiated by software as described in section 10.4.1.1. If a capture is performed:
-
The interrupt flag CCIFGx, located in control word CCTLx, is set. An interrupt is requested if both interrupt enable bits CCIEx and GIE are set.
The input signal to the capture/compare block is selected using control bits CCISx1 and CCISx0, as shown in Figure 10-18. The input signal can be read at any time by the software by reading bit CCIx. The input signal may also be latched with compare signal EQUx (see SCCIx bit below) when in compare mode. This feature was designed specifically to support implementing serial communications with Timer_A. See section 10.7 for more details on using Timer_A as a UART.
Figure 10-18. Capture Logic Input Signal
CCISx1 CCISx0
CAPx CMPx Capture Mode Timer Clock Synchronize Capture EQUx 0 1 SCSx Capture 1 0 Set_CCIFGx
CCIxA CCIxB GND VCC
0 1 2 3
CCMx1 CCMx0 0 0 1 1 CCIx 0 1 0 1
Disabled Positive Edge Negative Edge Both Edges
EN A
Y
SCCIx
The capture signal can also be synchronized with the timer clock to avoid race conditions between the timer data and the capture signal. This is illustrated in Figure 10-19. The bit SCSx in capture/compare control register CCTLx selects the capture signal synchronization.
10-14
Timer Modes
Figure 10-19. Capture Signal
Timer Clock Timer CCIx Capture Set CCIFGx
n-2 n-1 n n+1 n+2 n+3 n+4 n+5 n+6
Applications with slow timer clocks can use the nonsynchronized capture signal. In this scenario the software can validate the data and correct it if necessary as shown in the following example:
; Software example for the handling of asynchronous ; capture signals ; ; The data of the capture/compare register CCRx are taken ; by the software in the according interrupt routine ; - they are taken only after a CCIFG was set. ; The timer clock is much slower than the system clock ; MCLK. ; CCRx_Int_hand ... ; Start of interrupt ; handler ... ... CMP &CCRx,&TAR ; Test if the data ; CCRX = TAR JEQ Data_Valid MOV &TAR,&CCRx ; The data in CCRx is ; wrong, use the timer data
Data_Valid ... ... ; The data in CCRx are valid
;
Overflow logic is provided with each capture/compare register to flag the user if a second capture is performed before data from the first capture was read successfully. Bit COVx in register CCTLx is set when this occurs as shown in Figure 10-20.
III III
... ... RETI
Timer_A
10-15
Timer Modes
Figure 10-20. Capture Cycle
Idle Capture Capture Read
No Capture Taken
Capture Taken
Capture
Read Taken Capture
Capture Read and No Capture
Capture
Clear Bit COV in Register CCTL Second Capture Taken COV = 1
Idle
Overflow bit COVx is reset by the software as described in the following example:
; Software example for the handling of captured data ; looking for overflow condition ; ; The data of the capture/compare register CCRx are taken ; by the software and immediately with the next ; instruction the overflow bit is tested and a decision is ; made to proceed regularly or with an error handler ; CCRx_Int_hand ... ; Start of handler Interrupt ... ... MOV &CCRx,RAM_Buffer BIT #COV,&CCTLx JNZ Overflow_Hand ... ... ... RETI Overflow_Hand BIC #COV,&CCTLx ; reset capture ; overflow flag ; get back to lost ; synchronization ... ... ; RETI
Note: Capture With Timer Halted The capture should be disabled when the timer is halted. The sequence to follow is: stop the capture, then stop the timer. When the capture function is restarted, the sequence should be: start the capture, then start the timer.
10-16
Timer Modes
10.4.1.1 Capture/Compare Block, Capture Mode--Capture Initiated by Software
In addition to internal and external signals, captures can be initiated by software. This is useful for various purposes, such as:
-
To measure time used by software routines To measure time between hardware events To measure the system frequency
Two bits, CCISx1 and CCISx0, and the capture mode selected by bits CCMx1 and CCMx0 are used by the software to initiate the capture. The simplest realization is when the capture mode is selected to capture on both edges of CCIx and bit CCISx1 is set. Software then toggles bit CCISx0 to switch the capture signal between VCC and GND, initiating a capture each time the input is toggled, as shown in Figure 10-21.
Figure 10-21. Software Capture Example
CCISx1 CCISx0 CCIx Capture
CCISx1 CCISx0
CCIxA CCIxB GND VCC
0 1 2 3
CMPx Capture Mode CCIx CCMx1 CCMx0
1 1
Capture
Both Edges Selected
The following is a software example of a capture performed by software:
; ; ; ; ; The data of capture/compare register CCRx are taken by the software. It is assumed that CCMx1, CCMx0, and CCISx1 bits are set. Bit CCIS0 selects the CCIx signal to be high or low. ... ... XOR ... ... ...
#CCISx0, &CCTLx
Timer_A
10-17
Timer Modes
10.4.2 Capture/Compare Block--Compare Mode
The compare mode is selected if the CAPx bit, located in control word CCTLx, is reset. In compare mode all the capture hardware circuitry is inactive and the capture-mode overflow logic is inactive. The compare mode is most often used to generate interrupts at specific time intervals or used in conjunction with the output unit to generate output signals such as PWM signals. If the timer becomes equal to the value in compare register x, then:
-
Interrupt flag CCIFGx, located in control word CCTLx, is set. An interrupt is requested if interrupt enable bits CCIEx and GIE are set. Signal EQUx is output to the output unit. This signal affects the output OUTx, depending on the selected output mode.
The EQU0 signal is true when the timer value is greater or equal to the CCR0 value. The EQU1 to EQU4 signals are true when the timer value is equal to the corresponding CCR1 to CCR4 values.
10-18
Timer Modes
10.5 The Output Unit
Each capture/compare block contains an output unit shown in Figure 10-22. The output unit is used to generate output signals such as PWM signals. Each output unit has 8 operating modes that can generate a variety of signals based on the EQU0 and EQUx signals. The output mode is selected with the OMx bits located in the CCTLx register.
Figure 10-22. Output Unit
OUTx
EQU0 EQUx
Output Control Block
D
Set Reset
OUTx Signal
Q
Timer Clock
POR OUTx OMx2 OMx1 OMx0
0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Output mode: OUTx signal reflects the value of the OUTx bit Set mode: OUT x signal reflects the value of signal EQUx PWM toggle/reset: EQUx toggles OUTx. EQU0 resets OUTx. PWM set/reset: EQUx sets OUTx. EQU0 resets OUTx Toggle: EQUx toggles OUTx signal. Reset: EQUx resets OUTx. PWM toggle/set: EQUx toggles OUTx. EQU0 sets OUTx. PWM reset/set: EQUx resets OUTx. EQUx sets OUTx. Note: OUTx signal updates with rising edge of timer clock for all modes except mode 0. Modes 2, 3, 6, 7 not useful for output unit 0.
Timer_A
10-19
Timer Modes
10.5.1 Output Unit--Output Modes
The output modes are defined by the OMx bits and are discussed below. The OUTx signal is changed with the rising edge of the timer clock for all modes except mode 0. Output modes 2, 3, 6, and 7 are not useful for output unit 0. Output mode 0: Output mode: The output signal OUTx is defined by the OUTx bit in control register CCTLx. The OUTx signal updates immediately upon completion of writing the bit information. Output mode 1: Set mode: The output is set when the timer value becomes equal to capture/compare data CCRx. It remains set until a reset of the timer, or until another output mode is selected that controls the output. Output mode 2: PWM toggle/reset mode: The output is toggled when the timer value becomes equal to capture/compare data CCRx. It is reset when the timer value becomes equal to CCR0. Output mode 3: PWM set/reset mode: The output is set when the timer value becomes equal to capture/compare data CCRx. It is reset when the timer value becomes equal to CCR0. Output mode 4: Toggle mode: The output is toggled when the timer value becomes equal to capture/compare data CCRx. The output period is double the timer period. Output mode 5: Reset mode: The output is reset when the timer value becomes equal to capture/compare data CCRx. It remains reset until another output mode is selected that controls the output. Output mode 6: PWM toggle/set mode: The output is toggled when the timer value becomes equal to capture/compare data CCRx. It is set when the timer value becomes equal to CCR0. Output mode 7: PWM toggle/set mode: The output is reset when the timer value becomes equal to capture/compare data CCRx. It is set when the timer value becomes equal to CCR0.
10-20
Timer Modes
10.5.2 Output Control Block
The output control block prepares the value of the OUTx signal, which is latched into the OUTx flip-flop with the next positive timer clock edge, as shown in Figure 10-23 and Table 10-2. The equal signals EQUx and EQU0 are sampled during the negative level of the timer clock, as shown in Figure 10-23.
Figure 10-23. Output Control Block
OUTx
EQU0 EQUx
Output Control Block
D
Set Reset
OUTx Signal
Q
Timer Clock
POR OUTx OMx2 OMx1 OMx0
The timer is Incremented with the rising edge of the timer clock. Timer Clock
Timer TAR
n-2
n-1 TAR = n
n
n+1
FFFF or CCR0
0
1
EQUx
CCRx = n
EQU0
TAR = 0 or TAR = CCR0
EQU0, Delayed Used in Up Mode Only
EQU0 delayed is used in up mode, not EQU0. EQU0 is active high when TAR = CCR0. EQU0 delayed is active high when TAR = 0.
Timer_A
10-21
Timer Modes
Table 10-2.State of OUTx at Next Rising Edge of Timer Clock
Mode 0 1 2 EQU0 x x x 0 0 1 1 0 0 1 1 x x x x 0 0 1 1 0 0 1 1 EQUx x 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D x(OUTx bit) OUTx (no change) 1 (set) OUTx (no change) OUTx (toggle) 0 (reset) 1 (set) OUTx (no change) 1 (set) 0 (reset) 1 (set) OUTx (no change) OUTx (toggle) OUTx (no change) 0 (reset) OUTx (no change) OUTx (toggle) 1 (set) 0 (reset) OUTx (no change) 0 (reset) 1 (set) 0 (reset)
3
4 5 6
7
10.5.3 Output Examples
The following are some examples of possible output signals using the various timer and output modes.
10.5.3.1 Output Examples--Timer in Up Mode
The OUTx signal is changed when the timer counts up to the CCRx value, and rolls from CCR0 to zero, depending on the output mode, as shown in Figure 10-24.
10-22
Timer Modes
Figure 10-24. Output Examples--Timer in Up Mode
0FFFFh CCR0 CCR1 Example, EQU1 Used
0h Output Mode 1: Set Output Mode 2: PWM Toggle/Reset Output Mode 3: PWM Set/Reset Output Mode 4: Toggle Output Mode 5: Reset Output Mode 6: PWM Toggle/Set Output Mode 7: PWM Reset/Set EQU0 EQU1 EQU0 EQU1 EQU0 Interrupt Events
10.5.3.2 Output Examples--Timer in Continuous Mode
The OUTx signal is changed when the timer reaches the CCRx and CCR0 values, depending on the output mode, as shown in Figure 10-25.
Figure 10-25. Output Examples--Timer in Continuous Mode
0FFFFh CCR0 CCR1
0h
Output Mode 1: Set Output Mode 2: PWM Toggle/Reset Output Mode 3: PWM Set/Reset Output Mode 4: Toggle Output Mode 5: Reset Output Mode 6: PWM Toggle/Set Output Mode 7: PWM Reset/Set TAOV EQU1 EQU0 TAOV EQU1 EQU0 Interrupt Events
Timer_A
10-23
Timer_A Registers
10.5.3.3
Output Examples--Timer in Up/Down Mode
The OUTx signal changes when the timer equals CCRx in either count direction and when the timer equals CCR0, depending on the output mode, as shown in Figure 10-26.
Figure 10-26. Output Examples--Timer in Up/Down Mode (I)
0FFFFh CCR0
CCR3 0h Output Mode 1: Set Output Mode 2: PWM Toggle/Reset Output Mode 3: PWM Set/Reset Output Mode 4: Toggle Output Mode 5: Reset Output Mode 6: PWM Toggle/Set Output Mode 7: PWM Reset/Set TIMOV EQU3 EQU0 EQU3 TIMOV EQU3 EQU0 EQU3 Interrupt Events
10.6 Timer_A Registers
The Timer_A registers, described in Table 10-3, are word-structured and must be accessed using word instructions.
Table 10-3.Timer_A Registers
Register Timer_A control Timer_A register Cap/com control 0 Capture/compare 0 Cap/com control 1 Capture/compare 1 Cap/com control 2 Capture/compare 2 Cap/com control 3 Capture/compare 3 Cap/com control 4 Capture/compare 4 Interrupt vector
14x devices only
Short Form TACTL TAR CCTL0 CCR0 CCTL1 CCR1 CCTL 2 CCR2 CCTL3 CCR3 CCTL4 CCR4 TAIV
Register Type Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read
Address 160h 170h 162h 172h 164h 174h 166h 176h 168h 178h 16Ah 17Ah 12Eh
Initial State POR reset POR reset POR reset POR reset POR reset POR reset POR reset POR reset POR reset POR reset POR reset POR reset (POR reset)
10-24
Timer_A Registers
10.6.1 Timer_A Control Register TACTL
The timer and timer operation control bits are located in the timer control register (TACTL) shown in Figure 10-27. All control bits are reset automati- cally by the POR signal, but are not affected by the PUC signal. The control register must be accessed using word instructions.
Figure 10-27. Timer_A Control Register TACTL
15 TACTL 160h rw(0) rw(0)
Unused Input Select Input Divider Mode Control
0
UnCLR TAIE TAIFG used
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
rw (0)
rw(0)
w(0)
rw(0)
rw(0)
Bit 0:
TAIFG: This flag indicates a timer overflow event. Up mode: TAIFG is set if the timer counts from CCR0 value to 0000h. Continuous mode: TAIFG is set if the timer counts from 0FFFFh to 0000h. Up/down mode: TAIFG is set if the timer counts down from 0001h to 0000h. Timer overflow interrupt enable (TAIE) bit. An interrupt request from the timer overflow bit is enabled if this bit is set, and is disabled if reset. Timer clear (CLR) bit. The timer and input divider are reset with the POR signal, or if bit CLR is set. The CLR bit is automatically reset and is always read as zero. The timer starts in the upward direction with the next valid clock edge, unless halted by cleared mode control bits. Not used
Bit 1:
Bit 2:
Bit 3:
Bits 4, 5: Mode control: Table 10-4 describes the mode control bits.
Table 10-4.Mode Control
MC1 0 0 1 1 MC0 0 1 0 1 Count Mode Stop Up to CCR0 Continuous up Up/down Description Timer is halted. Timer counts up to CCR0 and restarts at 0. Timer counts up to 0FFFFh and restarts at 0. Timer continuously counts up to CCR0 and back down to 0.
Bits 6, 7: Input divider control bits. Table 10-5 describes the input divider control bits.
Timer_A
10-25
Timer_A Registers
Table 10-5.Input Clock Divider Control Bits
ID1 0 0 1 1 ID0 0 1 0 1 Operation /1 /2 /4 /8 Description Input clock source is passed to the timer. Input clock source is divided by two. Input clock source is divided by four. Input clock source is divided by eight.
Bits 8, 9: Clock source selection bits. Table 10-6 describes the clock source selections.
Table 10-6.Clock Source Selection
SSEL1 0 0 1 1 SSEL0 0 1 0 1 O/P Signal TACLK ACLK SMCLK INCLK Comment See data sheet device description. Auxiliary clock ACLK is used. System clock SMCLK. See device description in data sheet.
Bits 10 to 15:
Unused
Note: Changing Timer_A Control Bits If the timer operation is modified by the control bits in the TACTL register, the timer should be halted during this modification. Critical modifications are the input select bits, input divider bits, and the timer clear bit. Asynchronous clocks, input clock, and system clock can result in race conditions where the timer reacts unpredictably. The recommended instruction flow is: 1) Modify the control register and stop the timer. 2) Start the timer operation. For example: MOV #01C6,&TACTL BIS #10h,&TACTL ; ACLK/8, timer stopped, timer cleared ; Start timer with up mode
10.6.2 Timer_A Register TAR
The TAR register is the value of the timer.
Figure 10-28. TAR Register
15 TAR 170h
Timer Value
0
rw-(0) rw-(0) rw-(0) rw-(0)rw-(0) rw-(0) rw-(0)rw-(0)rw-(0)rw-(0)rw-(0) rw-(0) rw-(0)rw-(0)rw-(0) rw-(0)
10-26
Timer_A Registers
Note: Modifying Timer A Register TAR When ACLK, SMCLK, or the external clock TACLK or INCLK is selected for the timer clock, any write to timer register TAR should occur while the timer is not operating; otherwise, the results may be unpredictable. In this case, the timer clock is asynchronous to the CPU clock MCLK and critical race conditions exist.
10.6.3 Capture/Compare Control Register CCTLx
Each capture/compare block has its own control word CCTLx, shown in Figure 10-29. The POR signal resets all bits of CCTLx; the PUC signal does not affect these bits.
Figure 10-29. Capture/Compare Control Register CCTLx
15 CCTLx 162h to 16Ah
Capture Mode Input Select SCS SCCI Unused CAP OUTMODx CCIE CCI
0
OUT COV CCIFG
rw-(0) rw-(0) rw-(0) rw-(0)rw-(0) rw-(0) r-(0) rw-(0)rw-(0)rw-(0)rw-(0) rw-(0)
r
rw-(0)rw-(0) rw-(0)
Bit 0:
Capture/compare interrupt flag CCIFGx Capture mode: If set, it indicates that a timer value was captured in the CCRx register. Compare mode: If set, it indicates that a timer value was equal to the data in the CCRx register. CCIFG0 flag: CCIFG0 is automatically reset when the interrupt request is accepted. CCIFG1 to CCIFG4 flags: The flag that caused the interrupt is automatically reset after the TAIV word is accessed. If the TAIV register is not accessed, the flags must be reset with software. No interrupt is generated if the corresponding interrupt enable bit is reset, but the flag will be set. In this scenario, the flag must be reset by the software. Setting the CCIFGx flag with software will request an interrupt if the interrupt-enable bit is set.
Bit 1:
Capture overflow flag COV Compare mode selected, CAP = 0: Capture signal generation is reset. No compare event will set COV bit. Capture mode selected, CAP = 1: The overflow flag COV is set if a second capture is performed before the first capture value is read. The overflow flag must be reset with software. It is not reset by reading the capture value. The OUTx bit determines the value of the OUTx signal if the output mode is 0.
Bit 2:
Timer_A
10-27
Timer_A Registers
Bit 3:
Capture/compare input signal CCIx: The selected input signal (CCIxA, CCIxB, VCC. or GND) can be read by this bit. See Figure 10-18. Interrupt enable CCIEx: Enables or disables the interrupt request signal of capture/compare block x. Note that the GIE bit must also be set to enable the interrupt. 0: Interrupt disabled 1: Interrupt enabled Output mode select bits: Table 10-7 describes the output mode selections.
Bit 4:
Bits 5 to 7:
Table 10-7.Capture/Compare Control Register Output Mode
Bit Value 0 1 2 3 4 5 6 7
Note:
Output Mode Output only Set PWM toggle/reset PWM set/reset Toggle Reset PWM toggle/set PWM reset/set
Description The OUTx signal reflects the value of the OUTx bit EQUx sets OUTx EQUx toggles OUTx. EQU0 resets OUTx. EQUx sets OUTx. EQU0 resets OUTx EQUx toggles OUTx signal. EQUx resets OUTx. EQUx toggles OUTx. EQU0 sets OUTx. EQUx resets OUTx. EQU0 sets OUTx.
OUTx updates with rising edge of timer clock for all modes except mode 0. Modes 2, 3, 6, 7 not useful for output unit 0.
Bit 8:
CAP sets capture or compare mode. 0: Compare mode 1: Capture mode Read only, always read as 0. SCCIx bit: The selected input signal (CCIxA, CCIxB, VCC, or GND) is latched with the EQUx signal into a transparent latch and can be read via this bit. SCSx bit: This bit is used to synchronize the capture input signal with the timer clock. 0: asynchronous capture 1: synchronous capture
Bit 9: Bit 10:
Bit 11:
Bits 12, 13: Input select, CCIS0 and CCIS1: These two bits define the capture signal source. These bits are not used in compare mode. 0 Input CCIxA is selected 1 Input CCIxB is selected 2 GND 3 VCC
10-28
Timer_A Registers
Bits 14, 15: Capture mode bits: Table 10-8 describes the capture mode selections.
Table 10-8.Capture/Compare Control Register Capture Mode
Bit Value 0 1 2 3 Capture Mode Disabled Positive Edge Negative Edge Both Edges Description The capture mode is disabled. Capture is done with rising edge. Capture is done with falling edge. Capture is done with both rising and falling edges.
Note: Simultaneous Capture and Capture Mode Selection Captures must not be performed simultaneously with switching from compare to capture mode. Otherwise, the result in the capture/compare register will be unpredictable. The recommended instruction flow is: 1) Modify the control register to switch from compare to capture. 2) Capture For example: BIS #CAP,&CCTL2 XOR #CCIS1,&CCTL2 ; Select capture with register CCR2 ; Software capture: ; CCIS0 = 0 Capture mode = 3
10.6.4 Timer_A Interrupt Vector Register
Two interrupt vectors are associated with the 16-bit Timer_A module:
-
CCR0 interrupt vector (highest priority) TAIV interrupt vector for flags CCIFG1-CCIFGx and TAIFG.
10.6.4.1 CCR0 Interrupt Vector
The interrupt flag associated with capture/compare register CCR0, as shown in Figure 10-30, is set if the timer value is equal to the compare register value.
Figure 10-30. Capture/Compare Interrupt Flag
Capture
CCIE0
EQ0 CCR0 = Timer CAP Timer Clock
IRQ, Interrupt_Service_Requested
Set D Q Reset
IRACC, Interrupt_Request_Accepted
Capture/compare register 0 has the highest Timer_A interrupt priority, and uses its own interrupt vector.
Timer_A
10-29
Timer_A Registers
10.6.4.2 Vector Word, TAIFG, CCIFG1 to CCIFG4 Flags
The CCIFGx (other than CCIFG0) and TAIFG interrupt flags are prioritized and combined to source a single interrupt as shown in Figure 10-31. The interrupt vector register TAIV (shown in Figure 10-32) is used to determine which flag requested an interrupt.
Figure 10-31. Schematic of Capture/Compare Interrupt Vector Word
CCI1 EQ1 CMP1 Timer Clock
S S Sel CCIFG1
CCIE1
R
IRACC
CCI2 EQ2 CMP2 Timer Clock
S S Sel
CCIFG2
CCIE2
R
IRACC Interrupt_Service_Request CCIFG3 Priority and Vector Word Generator Interrupt_Vector_Address CCIFG4
CCI3 EQ3 CMP3 Timer Clock
S S Sel
CCIE3
R
IRACC
14x Devices Only
CCI4 EQ4 CMP4 Timer Clock
S S Sel
CCIE4
R
IRACC
Timer FFFF Timer = CCR0 XXX Timer Clock
S S Sel
TAIFG
TAIE
R
IRACC
Figure 10-32. Vector Word Register
15 TAIV 12Eh r0
0 0 0 0 0 0 0 0 0 0 0 0 Interrupt Vector
0
0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r-(0) r-(0) r-(0) r0
The flag with the highest priority generates a number from 2 to 12 in the TAIV register as shown in Table 10-9. (If the value of the TAIV register is 0, no interrupt is pending.) This number can be added to the program counter to automatically enter the appropriate software routine without the need for reading and evaluating the interrupt vector. The software example in section 10.6.4.3 shows this technique.
10-30
Timer_A Registers
Table 10-9.Vector Register TAIV Description
Interrupt Priority Highest Interrupt Source Capture/compare 1 Capture/compare 2 Capture/compare 3 Capture/compare 4 Timer overflow Reserved Lowest Reserved No interrupt pending Short Form CCIFG1 CCIFG2 CCIFG3 CCIFG4 TAIFG Vector Register TAIV Contents 2 4 6 8 10 12 14 0
Highest pending interrupt other than CCIFG0. CCIFG0 is always the highest priority Timer_A interrupt. 14x devices only
Accessing the TAIV register automatically resets the highest pending interrupt flag. If another interrupt flag is set, then another interrupt will be immediately generated after servicing the initial interrupt. For example, if both CCIFG2 and CCIFG3 are set, when the interrupt service routine accesses the TAIV register (either by reading it or by adding it directly to the PC), CCIFG2 will be reset automatically. After the RETI instruction of the interrupt service routine is executed, the CCIFG3 flag will generate another interrupt. Note: Writing to Read-Only Register TAIV Register TAIV should not be written to. If a write operation to TAIV is performed, the interrupt flag of the highest-pending interrupt is reset. Therefore, the requesting interrupt event is missed. Additionally, writing to this read-only register results in increased current consumption as long as the write operation is active.
10.6.4.3 Timer Interrupt Vector Register, Software Example
The following software example describes the use of vector word TAIV and the handling overhead. The numbers at the right margin show the necessary cycles for every instruction. The example is written for continuous mode: the time difference to the next interrupt is added to the corresponding compare register.
; Software example for the interrupt part Cycles ; ; Interrupt handler for Capture/Compare Module 0. ; The interrupt flag CCIFG0 is reset automatically ; TIMMOD0 ... ; Start of handler Interrupt latency 6 RETI 5 ; ; Interrupt handler for Capture/Compare Modules 1 to 4. ; The interrupt flags CCIFGx and TAIFG are reset by ; hardware. Only the flag with the highest priority ; responsible for the interrupt vector word is reset. TIM_HND $ ; Interrupt latency 6 ADD &TAIV,PC ; Add offset to Jump table 3 RETI ; Vector 0: No interrupt 5
Timer_A
10-31
Timer_A Registers
JMP JMP JMP JMP
TIMMOD1 TIMMOD2 TIMMOD3 TIMMOD4
; ; ; ;
Vector Vector Vector Vector
2: 4: 6: 8:
Module Module Module Module
1 2 3 4
2 2 2 2
; ; Module 5. Timer Overflow Handler: the Timer Register is ; expanded into the RAM location TIMEXT (MSBs) ; TIMOVH ; Vector 10: TIMOV Flag INC TIMEXT ; Handle Timer Overflow 4 RETI 5 ; TIMMOD2 ; Vector 4: Module 2 ADD #NN,&CCR2 ; Add time difference 5 ... ; Task starts here RETI ; Back to main program 5 ; ; TIMMOD1 ; Vector 2: Module 1 ADD #MM,&CCR1 ; Add time difference 5 ... ; Task starts here RETI ; Back to main program 5 ; If all five CCR registers are not implemented on a ; device, the interrupt vectors for the register that are ; present must still be handled. TIMMOD4 RETI ; Simply return 5 ; The Module 3 handler shows a way to look if any other ; interrupt is pending: 5 cycles have to be spent, but ; 9 cycles may be saved if another interrupt is pending ; TIMMOD3 ; Vector 6: Module 3 ADD #PP,&CCR3 ; Add time difference 5 ... ; Task starts here JMP TIM_HND ; Look for pending interrupts 2 ; .SECT "VECTORS",0FFF0h ; Interrupt Vectors ; The vector address may be different for different ; devices. ; .WORD TIM_HND ; Vector for Capture/Compare ; Module 1..4 and timer overflow ; TAIFG .WORD TIMMOD0 ; Vector for Capture/Compare ; Module 0
If the CPU clock MCLK was turned off (CPUOFF=1), then two or three additional cycles need to be added for synchronous start of the CPU. The delta of one clock cycle is caused when clocks are asynchronous to the restart of CPU clock MCLK. The software overhead for different interrupt sources includes interrupt latency and return-from-interrupt cycles (but not the task handling itself), as described:
10-32
Capture/compare block CCR0 Capture/compare blocks CCR1 to CCR4 Timer overflow TAIFG
11 cycles 16 cycles 14 cycles
Timer_A UART
10.6.4.4 Timing Limits
With the TAIV register and the previous software, the shortest repetitive time distance tCRmin between two events using a compare register is: tCRmin = ttaskmax + 16 x tcycle With: ttaskmax Maximum (worst case) time to perform the task during the interrupt routine (for example, incrementing a counter) tcycle Cycle time of the system frequency MCLK
The shortest repetitive time distance tCLmin between two events using a capture register is: tCLmin = ttaskmax + 16 x tcycle
10.7 Timer_A UART
The Timer_A is uniquely capable of implementing a UART function, with the following features:
-
Automatic start-bit detection - even from ultralow-power modes Hardware baud-rate generation Hardware latching of RXD and TXD data Baud rates of 75 to 115,200 baud Full-duplex operation
This UART implementation is different from other microcontroller implementations where a UART may be implemented with general-purpose I/O and manual bit manipulation via software polling. Those implementations require great CPU overhead and therefore increase power consumption and decrease the usability of the CPU. The transmit feature uses one compare function to shift data through the output unit to the selected pin. The baud rate is ensured by reconfiguring the compare data with each interrupt.
Timer_A
10-33
Timer_A UART
The receive feature uses one capture/compare function to shift pin data into memory through bit SCCIx. The receive start time is recognized by capturing the timer data with the negative edge of the input signal. The same capture/compare block is then switched to compare mode and the receive bits are latched automatically with the EQUx signal. The interrupt routine collects the bits for later software processing. Figure 10-33 illustrates the UART implementation.
Figure 10-33. UART Implementation
Overflow x Logic CCISx1 CCISx0 CCIxA CCIxB GND VCC 0 1 2 3 CCMx1 0 0 1 1 CCMx0 0 1 0 1 Disabled Positive Edge Negative Edge Both Edges Comparator x CAPx 15 Capture Mode Capture Capture/Compare Register CCRx 0 COVx Timer Bus
CAPx EQUx 0 1 Set_CCIFGx Receive Data Path EN A CCIx Y SCCIx
D Timer Clock
Set Reset
OUTx Signal Q
Transmit Data Path OMx2 OMx1 OMx0 0 1 0 0 1 Set, EQUx set OUTx signal clock synchronized with timer clock 1 Reset, EQUx resets OUTx signal clock synchronized with timer clock
10-34
Timer_A UART
One capture/compare block is used when half-duplex communication mode is desired. Two capture/compare blocks are used for full-duplex mode. Figure 10-34 illustrates the capture/compare timing for the UART.
Figure 10-34. Timer_A UART Timing
URXD Signal Capture Compare Receive Capture Compare Compare Compare Compare UTXD Signal Transmit Compare Compare Compare Compare Compare Compare Compare Compare Compare Compare Compare
A complete application note including connection diagrams and complete software listing may be found at www.ti.com/sc/msp430.
Timer_A
10-35
10-36
Chapter 11
Timer_B
This section describes the basic functions of the MSP430 general-purpose 16-bit Timer_B. Timer_B implementation differs among MSP430 devices. Always check the device's data sheet to determine the connections and the number of identical capture/compare registers. Also, the data sheets use additional nomenclature to indicate the number of capture/compare registers implemented for a specific device. For example, if Timer_B3 is discussed in a data sheet, then that device's implementation of Timer_B contains 3 capture/compare registers. In its default condition, Timer_B operates identically to Timer_A, except the SCCI bit is not implemented on Timer_B. Note: Throughout this chapter, the word count is used in the text. As used in these instances, it refers to the literal act of counting. It means that the counter must be in the process of counting for the action to take place. If a particular value is directly written to the counter, then the associated action will not take place. For example, the CCR0 interrupt flag is set when the timer counts up to the value in CCR0 compare latch TBCL0. The counter must count from TBCL0 -1 to TBCL0. If the TBCL0 value were simply written directly to the timer with software, the interrupt flag would not be set, even though the values in the timer and TBCL0 would be the same.
Topic
Page
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.2 Timer_B Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.3 Timer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 11.4 Capture/Compare Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15 11.5 The Output Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23 11.6 Timer_B Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29
Timer_B
11-1
Introduction
11.1 Introduction
Timer_B is an extremely versatile timer made up of :
-
16-bit counter with 4 operating modes and four selectable lengths (8-bit, 10-bit, 12-bit, or 16-bit) Selectable and configurable clock source Up to seven independently-configurable capture/compare registers with configurable inputs and double-buffered compare registers. Up to seven individually-configurable output modules with eight output modes
Timer_B can support multiple, simultaneous, timings; multiple capture/ compares; multiple output waveforms such as PWM signals; and any combination of these. In addition, with the double-buffering of compare data, multiple PWM periods can be updated simultaneously. Additionally, Timer_B has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers on captures or compares. Each capture/compare block is individually configurable and can produce interrupts on compares or on rising, falling or both edges of an external capture signal. The block diagram of Timer_B is shown in Figure 11-1.
11.1.1 Similarities and Differences From Timer_A
Timer_B is almost identical to Timer_A (except for a few enhancements noted below) and operates identically to Timer_A in it's default condition. Timer_B is different from Timer_A in the following ways: 1) The length of Timer_B is programmable to be 8, 10, 12, or 16 bits, whereas Timer_A is only a 16-bit timer.
2) The SCCI bit functionality of the capture/compare registers of Timer_A is not implemented in Timer_B. 3) The function of the capture/compare registers for the compare mode of Timer_B has changed slightly. 4) On some devices a pin is implemented to put all Timer_B outputs into a high-impedance state. Check the device data sheet for the presence of this pin. On Timer_A, the capture/compare register CCRx holds the data for the comparison to the timer value. On Timer_B, each CCRx acts as a buffer for a compare latch, and the compare latch holds the data used for the comparison. So, compare data is written to each CCRx in both timers; however, in Timer_B, the compare data is then transferred to the compare latch for the comparison. The timing of the transfer of the compare data from
11-2
Introduction
each CCRx register to the corresponding compare latch (TBCLx) is userselectable to be either immediate, or on a timer event. See section 11.4.2.1 for a complete discussion on using and configuring the compare latches. The addition of the compare latch gives the user more control over when exactly a compare period updates. In addition, multiple compare latches may be grouped together allowing the compare period of multiple compare registers to be updated simultaneously. This is useful for example when there is a need to change the period or duty cycle of multiple PWM signals simultaneously. It is useful to note that in Timer_B's default condition, the compare data is immediately transferred from each CCRx register to the corresponding compare latch. Therefore, in the default condition, the compare mode of Timer_B functions identically to the compare mode of Timer_A.
Timer_B
11-3
Introduction
Figure 11-1. Timer_B Block Diagram
TPSSEL1
TBCLK ACLK SMCLK INCLK
TPSSEL0
0 1 2 3
Timer Clock 15 Input Divider
Data 0 Mode Control
16-Bit Timer
8, 10, 12. or 16-Bit
16-Bit Timer CLK1 RC
Equ0
ID1 ID0
Carry/Zero POR/CLR Timer Bus
MC1
MC0
Set_TBIFG
CCIS01 CCIS00
CCI0A CCI0B GND VCC 0 1 2 3 CCI0 Capture Mode Capture
0 15 Capture/Compare Register CCR0 15 TBCL0 Compare Latch Comparator 0 0
Capture/Compare Register CCR0 OM02 OM01 OM00
Out 0
Output Unit 0
CCM01 CCM00 EQU0 EQU0
CCIS11 CCIS10
CCI1A CCI1B GND VCC 0 1 2 3 CCI1 Capture Capture Mode
0 15 Capture/Compare Register CCR1 15 TBCL1 Comparator Latch 0
Capture/Compare Register CCR1 OM12 OM11 OM10
Out 1
Output Unit 1
CCM11 CCM10 Comparator 1 EQU1 EQU0
Module 2 Module 3 Module 4 Module 5 Capture/Compare Register CCR6 OM62 OM61 OM60
CCIS61 CCIS60
CCI6A CCI6B GND VCC 0 1 2 3 CCI6 Capture Capture Mode
15 Capture/Compare Register CCR6 15 TBCL6 Compare Latch Comparator 6
0
0
Out 6
Output Unit 6
CCM61 CCM60 EQU6 EQU0
11-4
Timer_B Operation
11.2 Timer_B Operation
The 16-bit timer has four modes of operation selectable with the MC0 and MC1 bits in the TBCTL register and four selectable lengths, also configured in the TBCTL register. The timer increments or decrements (depending on mode of operation) with each rising edge of the clock signal. The timer can be read or written to with software. Additionally, the timer can generate an interrupt with its ripple-carry output when it overflows.
11.2.1 Timer Length
Timer_B is configurable to operate as a true 8-bit, 10-bit, 12-bit, or 16-bit timer. The length of the counter is configured in the TBCTL register. Leading bits are read as zero in 8-bit, 10-bit, and 12-bit mode. Data written to the TBR register in 8-bit, 10-bit, and 12-bit mode will show leading 0s. The maximum count value, TBR(max), for the various lengths is:
Timer_B Config ration Timer B Configuration 16-bit 12-bit 10-bit 8-bit TBR(max) 0FFFFh 0FFFh 03FFh 0FFh
11.2.2 Timer Mode Control
The timer has four modes of operation as shown in Figure 11-2 and described in Table 11-1: stop, up, continuous, and up/down. The operating mode is software selectable with the MC0 and MC1 bits in the TBCTL register.
Figure 11-2. Mode Control
Data 15 Timer Clock 16-Bit Timer
CLK
0 Mode Control
Equ0
RC Carry/Zero
POR
MC1 0 0 1 1
MC0 0 1 0 1
Set_TBIFG Stop Mode Up Mode Continuous Mode Up/Down Mode
Length is selectable for 8-, 10-, 12-, or 16-bit operation.
Timer_B
11-5
Timer_B Operation
Table 11-1. Timer Modes
Mode Control MC1 0 0 MC0 0 1 Mode Stop Up Description The timer is halted. The timer counts upward until its value is equal to the value of compare latch TBCL0. Note: If TBCL0 > TBR(max), the counter counts to zero with the next rising edge of timer clock. The timer counts upward continuously. The maximum value of TBR [TBR(max)] is: 0FFFFh for 16-bit configuration 00FFFh for 12-bit configuration 003FFh for 10-bit configuration 000FFh for 8-bit configuration The timer counts up until the timer value is equal to compare latch 0 and then it counts down to zero. Note: If TBCL0 > TBR(max), the counter operates as if it were configured for continuous mode. It will not count down from TBR(max) to zero.
1
0
Continuous
1
1
Up/Down
11.2.3 Clock Source Select and Divider
The timer clock can be sourced from internal clocks (i.e. ACLK, MCLK or SMCLK) or from an external source (TBCLK) as shown in Figure 11-3. The clock source is selectable with the SSEL0 and SSEL1 bits in the TBCTL register. It is important to note, that when changing the clock source for the timer, errant timings can occur. For this reason stopping the timer before changing the clock source is recommended. The selected clock source may be passed directly to the timer or divided by 2,4, or 8, as shown in Figure 11-4. The ID0 and ID1 bits in the TBCTL register select the clock division. Note that the input divider is reset by a POR signal or by setting the CLR bit in the TBCTL register (see chapter 3, System Resets, Interrupts, and Operating Modes, for more information on the POR signal). Otherwise, the input divider remains unchanged when the timer is modified. The state of the input divider is invisible to software.
Figure 11-3. Schematic of 16-Bit Timer
SSEL1 SSEL0
Timer Clock 0 Input Divider
CLK
Data 15 16-Bit Timer RC Carry/Zero Mode Control
Equ0
TBCLK ACLK SMCLK INCLK
0 1
2 ID1 3 0 0 1 1 ID0 0 1 0 1 Pass 1/2 1/4 1/8 POR/CLR
MC1 0 0 1 1
MC0 0 1 0 1
Set_TBIFG Stop Mode Up Mode Continuous Mode Up/Down Mode
Length is selectable for 8-, 10-, 12-, or 16-bit operation.
11-6
Timer_B Operation
Figure 11-4. Schematic of Clock Source Select and Input Divider
SSEL1 SSEL0 Input Divider
TBCLK ACLK SMCLK INCLK
0 1
T
Q C
T
Q C
T
Q C
16-Bit Timer Clock
2 3 ID1 0 0 1 1 ID0 0 1 0 1 POR Pass 1/2 1/4 1/8 CLR
11.2.4 Starting the Timer
The timer may be started or restarted in a variety of ways:
-
Release Halt Mode: The timer counts in the selected direction when a timer mode other than stop mode is selected with the MCx bits. Halted by TBCL0 = 0, restarted by TBCL0 > 0 when the mode is either up or up/down: When the timer mode is selected to be either up or up/down, the timer may be stopped by loading 0 in compare latch 0 (TBCL0) via capture/compare register (CCR0). The timer may then be restarted by loading a nonzero value to TBCL0. In this scenario, the timer starts incrementing in the up direction from zero. Setting the CLR bit in TBCTL register: Setting the CLR bit in the TBCTL register clears the timer value and input clock divider value. The timer increments upward from zero with the next clock cycle as long as stop-mode is not selected with the MCx bits. TBR is loaded with 0: When the counter (TBR register) is loaded with zero with a software instruction the timer increments upward from zero with the next clock cycle as long as stop-mode is not selected with the MCx bits.
-
Timer_B
11-7
Timer Modes
11.3 Timer Modes
11.3.1 Timer--Stop Mode
Stopping and starting the timer is done simply by changing the mode control bits (MCx). The value of the timer is not affected. When the timer is stopped from up/down mode and then restarted in up/down mode, the timer counts in the same direction as it was counting before it was stopped. For example, if the timer is in up/down mode and counting in the down direction when the MCx bits are reset, when they are set back to the up/down direction, the timer starts counting in the down direction from its previous value. If this is not desired in an application, the CLR bit in the TBCTL register can be used to clear this direction memory feature.
11.3.2 Timer--Up Mode
The up mode is used if the timer period must be different from the TBR(max) clock cycles of the continuous mode periods. The capture/compare register CCR0 data defines the timer period. The counter counts up to the content of compare latch TBCL0, as shown in Figure 11-5. When the timer value and the value of compare latch TBCL0 are equal (or if the timer value is greater than the TBCL0 value), the timer restarts counting from zero.
Figure 11-5. Timer Up Mode
TBR(max) TBCL0
0h
Flag CCIFG0 is set when the timer equals the TBCL0 value. The TBIFG flag is set when the timer counts from TBCL0 to zero. All interrupt flags are set independently of the corresponding interrupt enable bit, but an interrupt is requested only if the corresponding interrupt enable bit and the GIE bit are set. Figure 11-6 shows the flag set cycle.
Figure 11-6. Up Mode Flag Setting
Timer Clock Timer Set Flag TBIFG Set Flag CCIFG0
TBCL0-1 TBCL0 0h 1h TBCL0-1 TBCL0 0h 1h
11-8
Timer Modes
11.3.2.1 Timer in Up Mode--Changing the Period Register TBCL0 Value, Immediate Mode for TBCL0
Changing the timer period register TBCL0 while the timer is running and when the transfer mode from CCR0 is immediate can be a little tricky. When the new period is greater than or equal to the old period, the timer simply counts up to the new period and no special attention is required (see Figure 11-7). However, when the new period is less than the old period, the phase of the timer clock during the TBCL0 update affects how the timer reacts to the new period. If the new, smaller period is transferred from CCR0 to TBCL0 during a high phase of the timer clock, then the timer rolls to zero (or begins counting down when in the up/down mode) on the next rising edge of the timer clock. However, if the new, smaller period is written during a low phase of the timer clock, then the timer continues to increment with the old period for one more clock cycle before adopting the new period and rolling to zero (or beginning counting down). This is shown in Figure 11-8. Note: If TBCL0 > TBR(max), the counter rolls to zero with the next rising edge of timer clock.
Figure 11-7. New Period > Old Period
Timer Register 3 2 1 0 TBCL0old = 2 TBCL0new = 3
TBCL0
2
IIII IIII
0
1
2
0
1
2
3
0 3
1
2
3
0
1
Timer_B
11-9
Timer Modes
Figure 11-8. New Period < Old Period
Timer Register 5 4 3 2 1 0
TBCL0old = 5 TBCL0new = 2
Timer Register 5 4 3 2 1 0
TBCL0old = 5 TBCL0new = 2
0 12 3 45 01 2 3 01 2 01 2 01 TBCL0 5 2 TBCL0
012 3 45 012 3 401 201 201 5 2
TBCL0 Loaded With 2 During High Clock Phase Timer Clock Timer TBCL0 TBCLold n 0 or n-1 TBCLnew Timer Clock Timer TBCL0
TBCL0 Loaded With 2 During Low Clock Phase
n TBCLold
n+1 TBCLnew
0 or n
Load New TBCL0 During High Phase of Clock
Load New TBCL0 During Low Phase of Clock
Up mode: 0; up/down mode: n-1
Up mode: 0; up/down mode: n
11.3.3 Timer--Continuous Mode
The continuous mode is used if the timer period of TBR(max) clock cycles is used for the application. A typical application of the continuous mode is to generate multiple, independent timings. In continuous mode, the capture/ compare block 0 works in the same way as the other capture/compare blocks. The capture/compare blocks and different output modes of each output unit are useful to capture timer data based on external events or to generate various different types of output signals. Examples of the different output modes used with timer-continuous mode are shown in Figure 11-25. In continuous mode, the timer starts counting from its present value. The counter counts up to TBR(max) and restarts by counting from zero as shown in Figure 11-9. The maximum value of TBR [TBR(max)] in continuous mode is: 0FFFFh for 16-bit configuration 00FFFh for 12-bit configuration 003FFh for 10-bit configuration 000FFh for 8-bit configuration
Figure 11-9. Timer Continuous Mode
TBR(max)
0h
11-10
Timer Modes
The TBIFG flag is set when the timer counts from TBR(max) to zero. The interrupt flag is set independently of the corresponding interrupt enable bit, as shown in Figure 11-10. An interrupt is requested if the corresponding interrupt enable bit and the GIE bit are set.
Figure 11-10.Continuous Mode Flag Setting
Timer Clock
TBR(max)-1
Timer Set Interrupt Flag TBIFG
TBR(max)
0h
1h
TBR(max)
0h
1h
TBR(max)-1
11.3.3.1 Timer--Use of the Continuous Mode
The continuous mode can be used to generate time intervals for the application software. Each time an interval is completed, an interrupt can be generated. In the interrupt service routine of this event, the time until the next event is added to capture/compare register CCRx (and subsequently compare latch TBCLx) as shown in Figure 11-11. Up to seven independent time events can be generated using all seven capture/compare blocks.
Figure 11-11. Output Unit in Continuous Mode for Time Intervals
TBR(max)
TBCL0f TBCL0e TBCL0d TBCL0c TBCL0b TBCL0a TBCL0h TBCL0g TBCL0m TBCL0l TBCL0k TBCL0j TBCL0i
0h
Interrupt Events
t
t
t
t
t
t
t
t
t
t
t
t
Time intervals can be produced with other modes as well, where capture/ compare block 0 is used to determine the period. Their handling is more complex since the sum of the old CCRx data and the new period can be higher than the TBCL0 value. When the sum CCRxold plus t is greater than the TBCL0 data, the old CCR0 value must be subtracted to obtain the correct time interval.
Timer_B
11-11
Timer Modes
11.3.4 Timer--Up/Down Mode
The up/down mode is used if the timer period must be different from the TBR(max) clock cycles, and if symmetrical pulse waveform generation is needed. In up/down mode, the timer counts up to the content of compare latch TBCL0, then back down to zero, as shown in Figure 11-12. The period is twice the value in the TBCL0 latch. Note: If TBCL0 > TBR(max), the counter operates as if it were configured for continuous mode. It will not count down from TBR(max) to zero.
Figure 11-12.Timer Up/Down Mode
TBCL0
0h
The up/down mode also supports applications that require dead times between output signals. For example, to avoid overload conditions, two outputs driving an H-bridge must never be in a high state simultaneously. In the following example (see Figure 11-13), the tdead is: tdead = ttimer x (TBCL1 - TBCL3)= With: tdead ttimer Time during which both outputs need to be inactive Cycle time of the timer clock
TBCLx Content of compare latch x Note: The dead time is ensured by the ability to simultaneously load the compare latches.
Figure 11-13.Output Unit in Up/Down Mode (II)
TBR(max)
TBCL0 TBCL1 TBCL3 0h Dead Time Output Mode 6: PWM Toggle/Set Output Mode 2: PWM Toggle/Reset TBIFG EQU1 TBIFG EQU1 EQU1 EQU1 EQU3 EQU0 EQU3 EQU3 EQU0 EQU3 Interrupt Events
11-12
Timer Modes
The count direction is always latched with a flip-flop (Figure 11-14). This is useful because it allows the user to stop the timer and then restart it in the same direction it was counting before it was stopped. For example, if the timer was counting down when the MCx bits were reset, then it will continue counting in the down direction if it is restarted in up/down mode. If this is not desired, the CLR bit in the TBCTL register must be used to clear the direction. Note that the CLR bit affects other setup conditions of the timer. Refer to Section 11.6 for a discussion of the Timer_B registers.
Figure 11-14.Timer Up/Down Direction Control
POR CLR in TBCTL
Up/Down Mode TBR => TBCL0 Timer Clock
Set D Reset Q
Up/Down For Timer TBR Low: Down Direction High: Up Direction
In up/down mode, the interrupt flags (CCIFG0 and TBIFG) are set at equal time intervals (Figure 11-15). Each flag is set only once during the period, but they are separated by 1/2 the timer period. CCIFG0 is set when the timer counts from TBCL0-1 to TBCL0, and TBIFG is set when the timer completes counting down from 0001h to 0000h. Each flag is capable of producing a CPU interrupt when enabled.
Figure 11-15.Up/Down Mode Flag Setting
Timer Clock Timer Up/Down Set CCIFG0 Set TBIFG
TBCL0-1 TBCL0 TBCL0-1 TBCL0-2 2h 1h 0h 1h
11.3.4.1 Timer In Up/Down Mode--Changing the Value of Period Register TBCL0, Immediate Mode for TBCL0
Changing the period value while the timer is running in up/down mode and the transfer mode for TBCL0 is immediate is even trickier than in up mode. Like in up mode, the phase of the timer clock when TBCL0 is changed affects the timer's behavior. Additionally, in up/down mode, the direction of the timer also affects the behavior. If the timer is counting in the up direction when the new period is transferred from CCR0 to TBCL0, the conditions in the up/down mode are identical to
Timer_B
11-13
Timer Modes
those in the up mode. See Section 11.3.2.1 for details. However, if the timer is counting in the down direction when TBCL0 is updated, it continues its descent until it reaches zero. The new period takes effect only after the counter finishes counting down to zero. See Figure 11-16. Note: If TBCL0 > TBR(max), the counter operates as if it were configured for continuous mode. It will not count down from TBR(max) to zero.
Figure 11-16.Altering TBCL0--Timer in Up/Down Mode
Timer Register 5 4 3 2 1 0
0 123 4 5 432 1 01 234 3 2 1 012 3 21 012 1 0123 4 5 4 3 2 1 01 2 1 TBCL0 5 2 4 2 5 2
11-14
Timer Modes
11.4 Capture/Compare Blocks
Seven identical capture/compare blocks (shown in Figure 11-17) provide flexible control for real-time processing. Any one of the blocks may be used to capture the timer data at an applied event, or to generate time intervals. Each time a capture occurs or a time interval is completed, interrupts can be generated from the applicable capture/compare register. The mode bit CAPx, in control word CCTLx, selects the compare or capture operation and the capture mode bits CCMx1 and CCMx0 in control word CCTLx define the conditions under which the capture function is performed. Both the interrupt enable bit CCIEx and the interrupt flag CCIFGx are used for capture and compare modes. CCIEx enables the corresponding interrupt. CCIFGx is set on a capture or compare event. The capture inputs CCIxA and CCIxB are connected to external pins or internal signals. Different MSP430 devices may have different signals connected to CCIxA and CCIxB. The data sheet should always be consulted to determine the Timer_B connections for a particular device.
Figure 11-17.Capture/Compare Blocks
Logic CCISx1 CCISx0 CCIxA CCIxB GND VCC CCMx1 CCMx0 0 0 1 1 0 1 0 1 Disabled Positive Edge Negative Edge Both Edges High Zero EQU0 Up/Down CCIx EQUx 0 1 Set_CCIFGx CLLD0 CLLD1 0 1 2 3 CCMx1 CCMx0 CAP 15 Reset Load Compare Latch TBCLx CAPx 15 Capture Mode Capture Capture/Compare Register CCRx Reset POR 0 0 Overflow x COVx
Comparator x CAPx
Timer_B
11-15
Timer Modes
11.4.1 Capture/Compare Block--Capture Mode
The capture mode is selected if the mode bit CAPx, located in control word CCTLx, is set. The capture mode is used to fix time events. It can be used for speed computations or time measurements. The timer value is copied into the capture register (CCRx) with the selected edge (positive, negative, or both) of the input signal. Captures may also be initiated by software as described in section 11.4.1.1. If a capture is performed:
-
The interrupt flag CCIFGx, located in control word CCTLx, is set. An interrupt is requested if both interrupt enable bits CCIEx and GIE are set.
The input signal to the capture/compare block is selected using control bits CCISx1 and CCISx0, as shown in Figure 11-18. The input signal can be read at any time by the software by reading bit CCIx.
Figure 11-18.Capture Logic Input Signal
CCISx1 CCISx0
CAPx CMAx Capture Mode Timer Clock Synchronize Capture EQUx 0 1 SCSx Capture 1 0 Set_CCIFGx
CCIxA CCIxB GND VCC
0 1 2 3
CCMx1 CCMx0 0 0 1 1 CCIx 0 1 0 1
Disabled Positive Edge Negative Edge Both Edges
The capture signal can also be synchronized with the timer clock to avoid race conditions between the timer data and the capture signal. This is illustrated in Figure 11-19. The bit SCSx in capture/compare control register CCTLx selects the capture signal synchronization.
Figure 11-19.Capture Signal
Timer Clock Timer CCIx Capture Set CCIFGx
n-2 n-1 n n+1 n+2 n+3 n+4 n+5 n+6
11-16
III
Timer Modes
Applications with slow timer clocks can use the nonsynchronized capture signal. In this scenario the software can validate the data and correct it if necessary as shown in the following example:
; Software example for the handling of asynchronous ; capture signals ; ; The data of the capture/compare register CCRx are taken ; by the software in the according interrupt routine ; - they are taken only after a CCIFG was set. ; The timer clock is much slower than the system clock ; MCLK. ; CCRx_Int_hand ... ; Start of interrupt ; handler ... ... CMP &CCRx,&TBR ; Test if the data ; CCRX = TBR JEQ Data_Valid MOV &TBR,&CCRx ; The data in CCRx is ; wrong, use the timer data
Data_Valid ... ... ; The data in CCRx are valid
... ... RETI ;
Overflow logic is provided with each capture/compare register to flag the user if a second capture is performed before data from the first capture was read successfully. Bit COVx in register CCTLx is set when this occurs as shown in Figure 11-20.
Figure 11-20.Capture Cycle
Idle Capture Capture Read
No Capture Taken
Capture Taken
Capture
Read Taken Capture
Capture Read and No Capture
Capture
Clear Bit COV in Register CCTL Second Capture Taken COV = 1
Idle
Timer_B
11-17
Timer Modes
Overflow bit COVx is reset by the software as described in the following example:
; Software example for the handling of captured data ; looking for overflow condition ; ; The data of the capture/compare register CCRx are taken ; by the software and immediately with the next ; instruction the overflow bit is tested and a decision is ; made to proceed regularly or with an error handler ; CCRx_Int_hand ... ; Start of handler Interrupt ... ... MOV &CCRx,RAM_Buffer BIT #COV,&CCTLx JNZ Overflow_Hand ... ... ; correct capture data ... RETI Overflow_Hand BIC #COV,&CCTLx ; reset capture ; overflow flag ; get back to lost ; synchronization ... ; RETI ; Proceed
Note: Capture With Timer Halted The capture should be disabled when the timer is halted. The sequence to follow is: stop the capture, then stop the timer. When the capture function is restarted, the sequence should be: start the capture, then start the timer.
11.4.1.1 Capture/Compare Block, Capture Mode--Capture Initiated by Software
In addition to internal and external signals, captures can be initiated by software. This is useful for various purposes, such as:
-
To measure time used by software routines To measure time between hardware events To measure the system frequency
Two bits, CCISx1 and CCISx0, and the capture mode selected by bits CCMx1 and CCMx0 are used by the software to initiate the capture. The simplest realization is when the capture mode is selected to capture on both edges of CCIx and bit CCISx1 is set. Software then toggles bit CCISx0 to switch the capture signal between VCC and GND, initiating a capture each time the input is toggled, as shown in Figure 11-21.
11-18
Timer Modes
Figure 11-21.Software Capture Example
CCISx1 CCISx0 CCIx Capture
CCISx1 CCISx0
CCIxA CCIxB GND VCC
0 1 2 3
CMPx Capture Mode CCIx CCMx1 CCMx0
1 1
Capture
Both Edges Selected
The following is a software example of a capture performed by software:
; ; ; ; ; ; The data of capture/compare register CCRx are taken by the software. It is assumed that CCMx1, CCMx0, and CCISx1 bits are set. Bit CCIS0 selects the CCIx signal to be high or low.
... ... XOR ... ... ...
#CCISx0, &CCTLx
11.4.2 Capture/Compare Block--Compare Mode
The compare mode is selected if the CAPx bit, located in control word CCTLx, is reset. In compare mode all the capture hardware circuitry is inactive and the capture-mode overflow logic is inactive. The compare mode is most often used to generate interrupts at specific time intervals or used in conjunction with the output unit to generate output signals such as PWM signals. The compare data is double-buffered. The software writes the compare data to the capture/compare register, but the data is transferred to the compare latch TBCLx to be compared by the compare logic. The transfer of the compare data from the CCRx register to the compare latch is user-selectable to be either immediate or dependent upon a timer event. This double buffering allows the user to update multiple compare values simultaneously. This is useful for example with PWM signals where the period or duty cycle of multiple signals needs to be updated simultaneously. See section 11.4.2.1 for more discussion on how to use and configure the compare latches. If the timer becomes equal to the value in compare latch TBCLx, then:
Timer_B
11-19
Timer Modes
-
Interrupt flag CCIFGx, located in control word CCTLx, is set. An interrupt is requested if interrupt enable bits CCIEx and GIE are set. Signal EQUx is output to the output unit. This signal affects the output OUTx, depending on the selected output mode.
The EQU0 signal is true when the timer value is greater or equal to the TBCL0 value. The EQU1 to EQUx signals are true when the timer value is equal to the corresponding TBCL1 to TBCLx values.
11.4.2.1 Capture/Compare Block--Compare Mode--Compare Latch TBCLx
The compare logic uses the data in the compare latch for its comparison with the timer value. The compare data is first written by software to the capture/ compare register CCRx and then automatically transferred to the compare latch on a user-selectable load event. The load event is selected with the CLLDx bits in each CCTLx register. In addition, the compare latches may be grouped together so that each compare latch in a group is updated simultaneously on the load event. All compare latches may be grouped together in a single group, or they may be grouped in groups of two or three compare latches. The grouping is configured with the TBCLGRP bits in the TBCTL register. When using groups, the CLLDx bits of the lowest numbered CCRx register in the group determine the load event for each compare latch of the group except when all 7 compare latches are grouped together (TBCLGRP=3). For example, if a user selects the compare latches to be grouped in groups of three, then there are two groups of three: TBCL1, TBCL2, and TBCL3 form one group, and TBCL4, TBCL5, and TBCL6 form the other group. In this scenario, the CLLDx bits for TBCL1 determine the load event for the first group, and the CLLDx bits for TBCL4 determine the load event for the second group. The CLLDx bits in CCTL2, CCTL3, CCTL5, and CCTL6 are unused. When all compare latches are grouped together (TBCLGRP=3), then the CLLDx bits in TBCL1 determine the load event. When using groups, two conditions must exist for the compare latches to be loaded. First, all CCRx registers of the group must be updated (except when using immediate mode); second, the load event must occur. This means that if a user intends to retain any CCRx register data of a group when updating the group, the old data must be written to the CCRx register again. Otherwise, the compare latches will not be updated. The CLLDx bits in the applicable CCTLx register select the load event. There are four choices for the load event:
11-20
Immediate When TBR counts to 0 Continuous mode or up mode - when TBR counts to 0 Up/down mode - when TBR counts to TBCL0 or counts to 0 When TBR counts to TBCLx
The groupings and load conditions are summarized below in Table 11-2
Table 11-2. Shadow Register Operating Modes
CLLDx From Lowest CCTLx in Group (see Note 1) 0 1 0 Counter Mode MCx 0-3 1-3 1,2 2 3 3 1-3 Load Conditions 0 Immediate TBR counts to 0 TBR counts to 0 TBR counts to 0 or to TBCL0 TBR counts to TBCL0 Immediate 1 Immediate TBR counts to 0 TBR counts to 0 TBR counts to 0 or to TBCL0 TBR counts to TBCL1 2 Immediate TBR counts to 0 TBR counts to 0 TBR counts to 0 or to TBCL0 TBR counts to TBCL2 3 Immediate TBR counts to 0 TBR counts to 0 TBR counts to 0 or to TBCL0 TBR counts to TBCL3 4 Immediate TBR counts to 0 TBR counts to 0 TBR counts to 0 or to TBCL0 TBR counts to TBCL4 5 Immediate TBR counts to 0 TBR counts to 0 TBR counts to 0 or to TBCL0 TBR counts to TBCL5 6 Immediate TBR counts to 0 TBR counts to 0 TBR counts to 0 or to TBCL0 TBR counts to TBCL6
TBCLGRP
0
0-3
TBCL1, TBCL2 loaded immediately when the corresponding CCRx register is loaded TBCL1, TBCL2 updated simultaneously when TBR counts to 0 TBCL1, TBCL2 updated simultaneously when TBR counts to 0 TBCL1, TBCL2 updated simultaneously when TBR counts to 0 or to TBCL0 TBR counts to TBCL1 TBR counts to TBCL2
TBCL3, TBCL4 loaded immediately when the corresponding CCRx register is loaded TBCL3, TBCL4 updated simultaneously when TBR counts to 0 TBCL3, TBCL4 updated simultaneously when TBR counts to 0 TBCL3, TBCL4 updated simultaneously when TBR counts to 0 or to TBCL0 TBR counts to TBCL3 TBR counts to TBCL4
TBCL5, TBCL6 loaded immediately when the corresponding CCRx register is loaded TBCL5, TBCL6 updated simultaneously when TBR counts to 0 TBCL5, TBCL6 updated simultaneously when TBR counts to 0 TBCL5, TBCL6 updated simultaneously when TBR counts to 0 or to TBCL0 TBR counts to TBCL5 TBR counts to TBCL6
1
1-3
TBR counts to 0
1 2
1,2
TBR counts to 0
3
TBR counts to 0 or to TBCL0 TBR counts to TBCL0
3
1-3
Timer_B
11-21
Timer Modes
11-22
Timer Modes
Table 11-2. Shadow Register Operating Modes (Continued)
CLLDx From Lowest CCTLx in Group (see Note 1) 0 1 2 2 3 3 0 1 3 2 3 Notes: 1-3 0-3 1-3 1,2 3 1-3 Counter Mode MCx Load Conditions 0 Immediate TBR counts to 0 TBR counts to 0 TBR counts to 0 or to TBCL0 TBR counts to TBCL0 1 2 3 4 5 6
TBCLGRP
Timer_B
0-3 1-3 1,2
TBCL1, TBCL2, TBCL3 loaded immediately when the corresponding CCRx register is loaded TBCL1, TBCL2, TBCL3 updated simultaneously when TBR counts to 0 TBCL1, TBCL2, TBCL3 updated simultaneously when TBR counts to 0 TBCL1, TBCL2, TBCL3 updated simultaneously when TBR counts to 0 or to TBCL0 TBR counts to TBCL1 TBR counts to TBCL2 TBR counts to TBCL3
TBCL4, TBCL5, TBCL6 loaded immediately when the corresponding CCRx register is loaded TBCL4, TBCL5, TBCL6 updated simultaneously when TBR counts to 0 TBCL4, TBCL5, TBCL6 updated simultaneously when TBR counts to 0 TBCL4, TBCL5, TBCL6 updated simultaneously when TBR counts to 0 or to TBCL0 TBR counts to TBCL4 TBR counts to TBCL5 TBR counts to TBCL6
TBCL0, TBCL1, TBCL2, TBCL3, TBCL4, TBCL5, TBCL6 Loaded immediately when the corresponging CCRx register is loaded. TBCL0,TBCL1, TBCL2, TBCL3, TBCL4, TBCL5, TBCL6 updated simultaneously when TBR counts to 0 TBCL0,TBCL1, TBCL2, TBCL3, TBCL4, TBCL5, TBCL6 updated simultaneously when TBR counts to 0 TBCL0,TBCL1, TBCL2, TBCL3, TBCL4, TBCL5, TBCL6 updated simultaneously when TBR counts to 0 or to TBCL0 TBR counts to TBCL0 TBR counts to TBCL1 TBR counts to TBCL2 TBR counts to TBCL3 TBR counts to TBCL4 TBR counts to TBCL5 TBR counts to TBCL6
1) When using groups, load mode for the group is selected with the CLLDx bits of the lowest numbered CCTLx register in the group (except when TBCLGRP=3). For example, when grouped by 2, the CLLDx bits of CCTL3 determine the load mode for TBCL3 and TBCL4. When grouped by 3, the CLLDx bits of CCTL4 determine the load mode for TBCL4, TBCL5, and TBCL6, etc. When TBCLGRP=3 the CLLDx bits from TBCTL1 are used. 2) When using groups, all CCRx registers must be updated with new data before the load will take place (except when using immediate mode), even if new data = old data. When using immediate mode, each compare latch is updated immediately when its corresponding CCRx register is updated. 3) When using groups, different load modes may be selected for each group. For example, when grouped by 3, immediate mode may be selected (via CLLDx bits in CCTL1) for TBCL1, TBCL2, and TBCL3, and mode 2 may be selected (via CLLDx bits in CCTL4) for TBCL4, TBCL5, and TBCL6.
The Output Unit
11.5 The Output Unit
Each capture/compare block contains an output unit shown in Figure 11-22. The output unit is used to generate output signals such as PWM signals. Each output unit has 8 operating modes that can generate a variety of signals based on the EQU0 and EQUx signals. The output mode is selected with the OMx bits located in the CCTLx register.
Figure 11-22.Output Unit
OUTx
EQU0 EQUx
Output Control Block
D
Set Reset
OUTx Signal
Q
Timer Clock
POR OUTx OMx2 OMx1 OMx0
0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Output mode: OUTx signal reflects the value of the OUTx bit Set mode: OUT x signal reflects the value of signal EQUx PWM toggle/reset: EQUx toggles OUTx. EQU0 resets OUTx. PWM set/reset: EQUx sets OUTx. EQU0 resets OUTx Toggle: EQUx toggles OUTx signal. Reset: EQUx resets OUTx. PWM toggle/set: EQUx toggles OUTx. EQU0 sets OUTx. PWM reset/set: EQUx resets OUTx. EQUx sets OUTx. Note: OUTx signal updates with rising edge of timer clock for all modes except mode 0. Modes 2, 3, 6, 7 not useful for output unit 0.
Timer_B
11-23
11.5.1
Output Unit - Output Modes
The output modes are defined by the OMx bits and are discussed below. The OUTx signal is changed with the rising edge of the timer clock for all modes except mode 0. Output modes 2, 3, 6, and 7 are not useful for output unit 0. Output mode 0: Output mode: The output signal OUTx is defined by the OUTx bit in control register CCTLx. The OUTx signal updates immediately upon completion of writing the bit information. Output mode 1: Set mode: The output is set when the timer value becomes equal to compare data TBCLx. It remains set until a reset of the timer, or until another output mode is selected and controls the output. Output mode 2: PWM toggle/reset mode: The output is toggled when the timer value becomes equal to compare data TBCLx. It is reset when the timer value becomes equal to TBCL0. Output mode 3: PWM set/reset mode: The output is set when the timer value becomes equal to compare data TBCLx. It is reset when the timer value becomes equal to TBCL0. Output mode 4: Toggle mode: The output is toggled when the timer value becomes equal to compare data TBCLx. The output period is double the timer period. Output mode 5: Reset mode: The output is reset when the timer value becomes equal to compare data TBCLx. It remains reset until another output mode is selected and controls the output. Output mode 6: PWM toggle/set mode: The output is toggled when the timer value becomes equal to compare data TBCLx. It is set when the timer value becomes equal to TBCL0. Output mode 7: PWM toggle/set mode: The output is reset when the timer value becomes equal to compare data TBCLx. It is set when the timer value becomes equal to TBCL0.
11-24
11.5.2 Output Control Block
The output control block prepares the value of the OUTx signal, which is latched into the OUTx flip-flop with the next positive timer clock edge, as shown in Figure 11-23 and Table 11-3. The equal signals EQUx and EQU0 are sampled during the negative level of the timer clock, as shown in Figure 11-23.
Figure 11-23.Output Control Block
OUTx
EQU0 EQUx
Output Control Block
D
Set Reset
OUTx Signal
Q
Timer Clock
POR OUTx OMx2 OMx1 OMx0
The timer is Incremented with the rising edge of the timer clock. Timer Clock
Timer TBR
n-2
n-1 TBR = n
n
n+1
TBR(max) or TBCL0
0
1
EQUx
TBCLx = n
EQU0
TBR = 0 or TBR = TBCL0
EQU0, Delayed Used in Up Mode Only EQU0 delayed is used in up mode, not EQU0. EQU0 is active high when TBR = TBCL0. EQU0 delayed is active high when TBR = 0.
Timer_B
11-25
Table 11-3. State of OUTx at Next Rising Edge of Timer Clock
Mode 0 1 2 EQU0 x x x 0 0 1 1 0 0 1 1 x x x x 0 0 1 1 0 0 1 1 EQUx x 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D x(OUTx bit) OUTx (no change) 1 (set) OUTx (no change) OUTx (toggle) 0 (reset) 1 (set) OUTx (no change) 1 (set) 0 (reset) 1 (set) OUTx (no change) OUTx (toggle) OUTx (no change) 0 (reset) OUTx (no change) OUTx (toggle) 1 (set) 0 (reset) OUTx (no change) 0 (reset) 1 (set) 0 (reset)
3
4 5 6
7
11.5.3 Output Examples
The following are some examples of possible output signals using the various timer and output modes.
11.5.3.1 Output Examples--Timer in Up Mode
The OUTx signal is changed when the timer counts up to the TBCLx value, and rolls from TBCL0 to zero, depending on the output mode, as shown in Figure 11-24.
11-26
Figure 11-24.Output Examples--Timer in Up Mode
TBR(max) TBCL0 TBCL1 Example, EQU1 Used
0h Output Mode 1: Set Output Mode 2: PWM Toggle/Reset Output Mode 3: PWM Set/Reset Output Mode 4: Toggle Output Mode 5: Reset Output Mode 6: PWM Toggle/Set Output Mode 7: PWM Reset/Set EQU0 EQU1 EQU0 EQU1 EQU0 Interrupt Events
11.5.3.2 Output Examples--Timer in Continuous Mode
The OUTx signal is changed when the timer reaches the TBCLx and TBCL0 values, depending on the output mode, as shown in Figure 11-25.
Figure 11-25.Output Examples--Timer in Continuous Mode
TBR(max) TBCL0 TBCL1
0h
Output Mode 1: Set Output Mode 2: PWM Toggle/Reset Output Mode 3: PWM Set/Reset Output Mode 4: Toggle Output Mode 5: Reset Output Mode 6: PWM Toggle/Set Output Mode 7: PWM Reset/Set TBOV EQU1 EQU0 TBOV EQU1 EQU0 Interrupt Events
Timer_B
11-27
11.5.3.3
Output Examples - Timer in Up/Down Mode
The OUTx signal changes when the timer equals TBCLx in either count direction and when the timer equals TBCL0, depending on the output mode, as shown in Figure 11-26.
Figure 11-26.Output Examples - Timer in Up/Down Mode (I)
TBR(max) TBCL0
TBCL3 0h Output Mode 1: Set Output Mode 2: PWM Toggle/Reset Output Mode 3: PWM Set/Reset Output Mode 4: Toggle Output Mode 5: Reset Output Mode 6: PWM Toggle/Set Output Mode 7: PWM Reset/Set TIMOV EQU3 EQU0 EQU3 TIMOV EQU3 EQU0 EQU3 Interrupt Events
11-28
Timer_B Registers
11.6 Timer_B Registers
The Timer_B registers, described in Table 11-4, are word structured and must be accessed using word instructions.
Table 11-4. Timer_B Registers
Register Timer_B control Timer_B register Cap/com control 0 Capture/compare 0 Cap/com control 1 Capture/compare 1 Cap/com control 2 Capture/compare 2 Cap/com control 3 Capture/compare 3 Cap/com control 4 Capture/compare 4 Capture/compare 5 Capture/compare 5 Capture/compare 6 Capture/compare 6 Interrupt vector Short Form TBCTL TBR CCTL0 CCR0 CCTL1 CCR1 CCTL 2 CCR2 CCTL3 CCR3 CCTL4 CCR4 CCTL5 CCR5 CCTL6 CCR6 TBIV Register Type Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read Address 180h 190h 182h 192h 184h 194h 186h 196h 188h 198h 18Ah 19Ah 18Ch 19Ch 18Eh 19Eh 11Eh Initial State POR reset POR reset POR reset POR reset POR reset POR reset POR reset POR reset POR reset POR reset POR reset POR reset POR reset POR reset POR reset POR reset (POR reset)
11.6.1 Timer_B Control Register TBCTL
The timer and timer operation control bits are located in the timer control register (TBCTL) shown in Figure 11-27. All control bits are reset automatically by the POR signal, but are not affected by the PUC signal. The control register must be accessed using word instructions.
Figure 11-27.Timer_B Control Register TBCTL
15 TBCTL 180h rw(0)
Group TBCL Counter Length UnInput Select Input Divider used Mode Control
0
Unused CLR TBIE TBIFG
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
rw(0)
rw (0)
rw(0)
w(0)
rw(0)
rw(0)
Bit 0:
TBIFG: This flag indicates a timer overflow event. Up mode: TBIFG is set if the timer counts from TBCL0 value to 0000h. Continuous mode: TBIFG is set if the timer counts from TBR(max) to 0000h. Up/down mode: TBIFG is set if the timer counts down from 0001h to 0000h. Timer overflow interrupt enable (TBIE) bit. An interrupt request from the timer overflow bit is enabled if this bit is set, and is disabled if reset.
Bit 1:
Timer_B
11-29
Timer_B Registers
Bit 2:
Timer clear (CLR) bit. The timer and input divider are reset with the POR signal, or if bit CLR is set. The CLR bit is automatically reset and is always read as zero. The timer starts in the upward direction with the next valid clock edge, unless halted by cleared mode control bits. Not used
Bit 3:
Bits 4, 5: Mode control: Table 11-5 describes the mode control bits.
Table 11-5. Mode Control
MC1 0 0 MC0 0 1 Count Mode Stop Up to CCR0 Description Timer is halted. Timer counts up to TBCL0 and restarts at 0. Note: If TBCL0 > TBR(max), the counter counts to zero with the next rising edge of timer clock. Timer counts up to TBR(max) and restarts at 0. The maximum value of TBR [TBR(max)] is: 0FFFFh for 16-bit configuration 00FFFh for 12-bit configuration 003FFh for 10-bit configuration 000FFh for 8-bit configuration Timer continuously counts up to CCR0 and back down to 0. Note: If CCR0 > TBR(max), the counter operates as if it were configured for continuous mode. It will not count down from TBR(max) to zero.
1
0
Continuous up
1
1
Up/down
Bits 6, 7: Input divider control bits. Table 11-6 describes the clock-divider bits.
Table 11-6. Input Clock Divider Control Bits
ID1 0 0 1 1 ID0 0 1 0 1 Operation /1 /2 /4 /8 Description Input clock source is passed to the timer. Input clock source is divided by two. Input clock source is divided by four. Input clock source is divided by eight.
Bits 8, 9: Clock source selection bits. Table 11-7 describes the clock source selections.
Table 11-7. Clock Source Selection
SSEL1 0 0 1 1 SSEL0 0 1 0 1 O/P Signal TBCLK ACLK SMCLK INCLK Comment See data sheet device description Auxiliary clock ACLK is used System clock SMCLK See device description in data sheet
11-30
Timer_B Registers
Bit 10: Bits 11, 12:
Unused Configure 16-bit timer (TBR) for 8-bit, 10-bit, 12-bit, or 16-bit operation CNTL = 0: 16-bit length, TBR(max) is 0FFFFH CNTL = 1: 12-bit length, TBR(max) is 0FFFH CNTL = 2: 10-bit length, TBR(max) is 03FFH CNTL = 3: 8-bit length, TBR(max) is 0FFH
Bits 13, 14: Load compare latches, individually or in groups. The load signal is controlled via the CLLDx bits located in the appropriate capture/compare control register CCTLx. TBCLGRP = 0: load individually Load of the shadow registers is defined in each individual CCTLx register by bits CLLDx. The CLLD bits in each CCTLx register define the operating mode for the shadow registers. TBCLGRP = 1: Three groups are selected (TBCL1 + TBCL2, TBCL3 + TBCL4, TBCL5 + TBCL6): TBCL1 + TBCL2: The CLLD bits in CCTL1 define the operating mode. TBCL3 + TBCL4: The CLLD bits in CCTL3 define the operating mode. TBCL5 + TBCL6: The CLLD bits in CCTL5 define the operating mode. TBCLGRP = 2: Two groups are selected (TBCL1 + TBCL2 + TBCL3, TBCL4 + TBCL5 + TBCL6): TBCL1 + TBCL2 + TBCL3: The CLLD bits in CCTL1 define the operating mode. TBCL4 + TBCL5 + TBCL6: The CLLD bits in CCTL4 define the operating mode. TBCLGRP = 3: One group is selected (all TBCLx registers): The CLLD bits in CCTL1 define the operating mode for all shadow registers. Bit 15: Unused
Timer_B
11-31
Timer_B Registers
Note: Changing Timer_B Control Bits If the timer operation is modified by the control bits in the TBCTL register, the timer should be halted during this modification. Critical modifications are the input select bits, input divider bits, and the timer clear bit. Asynchronous clocks, input clock, and system clock can result in race conditions where the timer reacts unpredictably. The recommended instruction flow is: 1) Modify the control register and stop the timer with one instruction. 2) Start the timer operation. For example: MOV #0286h,&TBCTL BIS #10h,&TBCTL ; ACLK/8, timer stopped, timer cleared ; Start timer with up mode
11.6.2 Timer_B Register TBR
The TBR register is the value of the timer.
Figure 11-28.TBR Register
15 TBR 190h
Timer Value
0
rw-(0) rw-(0) rw-(0) rw-(0)rw-(0) rw-(0) rw-(0)rw-(0)rw-(0)rw-(0)rw-(0) rw-(0) rw-(0)rw-(0)rw-(0) rw-(0)
Note: Modifying Timer_B Register TBR When ACLK, SMCLK, or the external clock TBCLK or INCLK is selected for the timer clock, any write to timer register TBR should occur while the timer is not operating; otherwise, the results may be unpredictable. In this case, the timer clock is asynchronous to the CPU clock MCLK and critical race conditions exist.
11.6.3 Capture/Compare Control Register CCTLx
Each capture/compare block has its own control word CCTLx, shown in Figure 11-29. The POR signal resets all bits of CCTLx; the PUC signal does not affect these bits.
Figure 11-29.Capture/Compare Control Register CCTLx
15 CCTLx 182h to 19Ah
Capture Mode Input Select SCS CLLD CAP OUTMODx CCIE CCI
0
OUT COV CCIFG
rw-(0) rw-(0) rw-(0) rw-(0)rw-(0) rw-(0) rw-(0) rw-(0)rw-(0)rw-(0)rw-(0) rw-(0)
r
rw-(0)rw-(0) rw-(0)
11-32
Timer_B Registers
Bit 0:
Capture/compare interrupt flag CCIFGx Capture mode: If set, it indicates that a timer value was captured in the CCRx register. Compare mode: If set, it indicates that a timer value was equal to the data in the TBCLx latch. CCIFG0 flag: CCIFG0 is automatically reset when the interrupt request is accepted. CCIFG1 to CCIFGx flags: The flag that caused the interrupt is automatically reset after the TBIV word is accessed. If the TBIV register is not accessed, the flags must be reset with software. No interrupt is generated if the corresponding interrupt enable bit is reset, but the flag will be set. In this scenario, the flag must be reset by the software. Setting the CCIFGx flag with software will request an interrupt if the interrupt-enable bit is set.
Bit 1:
Capture overflow flag COV Compare mode selected, CAP = 0: Capture signal generation is reset. No compare event will set COV bit. Capture mode selected, CAP = 1: The overflow flag COV is set if a second capture is performed before the first capture value is read. The overflow flag must be reset with software. It is not reset by reading the capture value. The OUTx bit determines the value of the OUTx signal if the output mode is 0. Capture/compare input signal CCIx: The selected input signal (CCIxA, CCIxB, VCC. or GND) can be read by this bit. See Figure 11-18. Interrupt enable CCIEx: Enables or disables the interrupt request signal of capture/compare block x. Note that the GIE bit must also be set to enable the interrupt. 0: Interrupt disabled 1: Interrupt enabled Output mode select bits: Table 11-7 describes the output mode selections.
Bit 2:
Bit 3:
Bit 4:
Bits 5 to 7:
Timer_B
11-33
Timer_B Registers
Table 11-8. Capture/Compare Control Register Output Mode
Bit Value 0 1 2 3 4 5 6 7
Note:
Output Mode Output only Set PWM toggle/reset PWM set/reset Toggle Reset PWM toggle/set PWM reset/set
Description The OUTx signal reflects the value of the OUTx bit EQUx sets OUTx EQUx toggles OUTx. EQU0 resets OUTx. EQUx sets OUTx. EQU0 resets OUTx EQUx toggles OUTx signal. EQUx resets OUTx. EQUx toggles OUTx. EQU0 sets OUTx. EQUx resets OUTx. EQUx sets OUTx.
OUTx updates with rising edge of timer clock for all modes except mode 0. Modes 2, 3, 6, 7 not useful for output unit 0.
Bit 8:
CAP sets capture or compare mode. 0: Compare mode 1: Capture mode CLLD: Select load source for compare latch TBCLx (also see description of bits TBCLGRP, 13 and 14, in TBCTL) CLLD = 0: Immediate CLLD = 1: Load CCRx data to TBCLx when TBR counts to 0 CLLD = 2: UP/DOWN mode: load CCRx data to TBCLx when TBR counts to TBCL0 or to 0 Continuous mode or UP-mode: load CCRx data to TBCLx when TBR counts to 0 CLLD = 3: CCRx data are loaded to TBCLx when TBR counts to TBCLx SCSx bit: This bit is used to synchronize the capture input signal with the timer clock. 0: asynchronous capture 1: synchronous capture
Bits 9, 10:
Bit 11:
Bits 12, 13: Input select, CCIS0 and CCIS1: These two bits define the capture signal source. These bits are not used in compare mode. 0 Input CCIxA is selected 1 Input CCIxB is selected 2 GND 3 VCC Bits 14, 15: Capture mode bits: Table 11-8 describes the capture mode selections.
11-34
Timer_B Registers
Table 11-9. Capture/Compare Control Register Capture Mode
Bit Value 0 1 2 3 Capture Mode Disabled Pos. Edge Neg. Edge Both Edges Description The capture mode is disabled. Capture is done with rising edge. Capture is done with falling edge. Capture is done with both rising and falling edges.
Note: Simultaneous Capture and Capture Mode Selection Captures must not be performed simultaneously with switching from compare to capture mode. Otherwise, the result in the capture/compare register will be unpredictable. The recommended instruction flow is: 1) Modify the control register to switch from compare to capture. 2) Capture For example: BIS #CAP,&CCTL2 XOR #CCIS1,&CCTL2 ; Select capture with register CCR2 ; Software capture: ; CCIS0 = 0 Capture mode = 3
11.6.4 Timer_B Interrupt Vector Register
Two interrupt vectors are associated with the 16-bit Timer_B module:
-
CCR0 interrupt vector (highest priority) TBIV interrupt vector for flags CCIFG1-CCIFGx and TBIFG.
11.6.4.1 CCR0 Interrupt Vector
The interrupt flag associated with capture/compare register CCR0, as shown in Figure 11-30, is set if the timer value is equal to the compare register value.
Figure 11-30.Capture/Compare Interrupt Flag
Capture
CCIE0
EQ0 TBCL0 = Timer CAP Timer Clock
IRQ, Interrupt_Service_Requested
D
Set
Q
Reset
IRACC, Interrupt_Request_Accepted
Capture/compare register 0 has the highest Timer_B interrupt priority, and uses its own interrupt vector.
Timer_B
11-35
Timer_B Registers
11.6.4.2 Vector Word, TBIFG, CCIFG1 to CCIFGx Flags
The CCIFGx (other than CCIFG0) and TBIFG interrupt flags are prioritized and combined to source a single interrupt as shown in Figure 11-31. The interrupt vector register TBIV (shown in Figure 11-32) is used to determine which flag requested an interrupt.
Figure 11-31.Schematic of Capture/Compare Interrupt Vector Word
CCI1 EQ1 CMP1 Timer Clock
S S Sel CCIFG1
CCIE1
R
IRACC
CCI2 EQ2 CMP2 Timer Clock
S S Sel
CCIFG2
CCIE2
R
IRACC Module 3 Module 4 Module 5 Interrupt_Vector_Address Interrupt_Service_Request
Priority and Vector Word Generator
CCI6 EQ6 CMP6 Timer Clock
S S Sel
CCIFG6
CCIE6
R
IRACC
TBR(MAX) Timer = TBCL0 XXX Timer Clock
S S Sel
TBIFG
TBIE
R
IRACC
Figure 11-32.Vector Word Register
15 TBIV 11Eh r0
0 0 0 0 0 0 0 0 0 0 0 0 Interrupt Vector
0
0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r-(0) r-(0) r-(0) r0
The flag with the highest priority generates a number from 2 to 14 in the TBIV register as shown in Table 11-9. (If the value of the TBIV register is 0, no interrupt is pending.) This number can be added to the program counter to automatically enter the appropriate software routine without the need for reading and evaluating the interrupt vector. The software example in section 11.6.4.3 shows this technique.
11-36
Timer_B Registers
Table 11-10. Vector Register TBIV Description
Interrupt Priority Highest Interrupt Source Capture/compare 1 Capture/compare 2 Capture/compare 3 Capture/compare 4 Capture/compare 5 Capture/compare 6 Lowest Timer overflow No interrupt pending Short Form CCIFG1 CCIFG2 CCIFG3 CCIFG4 CCIFG5 CCIFG6 TBIFG Vector Register TBIV Contents 2 4 6 8 10 12 14 0
Highest pending interrupt other than CCIFG0. CCIFG0 is always the highest priority Timer_B interrupt. 14x devices only
Accessing the TBIV register automatically resets the highest pending interrupt flag. If another interrupt flag is set, then another interrupt will be immediately generated after servicing the initial interrupt. For example, if both CCIFG2 and CCIFG3 are set, when the interrupt service routine accesses the TBIV register (either by reading it or by adding it directly to the PC), CCIFG2 will be reset automatically. After the RETI instruction of the interrupt service routine is executed, the CCIFG3 flag will generate another interrupt. Note: Writing to Read-Only Register TBIV Register TBIV should not be written to. If a write operation to TBIV is performed, the interrupt flag of the highest-pending interrupt is reset. Therefore, the requesting interrupt event is missed. Additionally, writing to this read-only register results in increased current consumption as long as the write operation is active.
Timer_B
11-37
Timer_B Registers
11.6.4.3 Timer Interrupt Vector Register, Software Example, Timer_B7
The following software example describes the use of vector word TBIV of Timer_B3 and the handling overhead. The numbers at the right margin show the necessary cycles for every instruction. The example is written for continuous mode: the time difference to the next interrupt is added to the corresponding compare register.
; Software example for the interrupt part
;
Cycles
; Interrupt handler for Capture/Compare Module 0. ; The interrupt flag CCIFG0 is reset automatically
;
TIMMOD0
;
... RETI
; Start of handler Interrupt latency
6 5
; Interrupt handler for Capture/Compare Modules 1 to 6. ; The interrupt flags CCIFGx and TBIFG are reset by ; hardware. Only the flag with the highest priority ; responsible for the interrupt vector word is reset. TIM_HND $ ; Interrupt latency ADD &TBIV,PC ; Add offset to Jump table RETI ; Vector 0: No interrupt JMP TIMMOD1 ; Vector 2: Module 1 JMP TIMMOD2 ; Vector 4: Module 2 JMP TIMMOD3 ; Vector 6: Module 3 JMP TIMMOD4 ; Vector 8: Module 4 JMP TIMMOD5 ; Vector 10: Module 5 JMP TIMMOD6 ; Vector 12: Module 6
;
6 3 5 2 2 2 2 2 2
; Module 7. Timer Overflow Handler: the Timer Register is ; expanded into the RAM location TIMEXT (MSBs)
;
TIMOVH INC RETI
;
TIMEXT
; Vector 14: TIMOV Flag ; Handle Timer Overflow ; Vector 4: Module 2 ; Add time difference ; Task starts here ; Back to main program Vector 2: Module 1 Add time difference Task starts here Back to main program
4 5 5 5 5 5
TIMMOD2 ADD ... RETI
;
#NN,&CCR2
TIMMOD1 ADD ... RETI
; #MM,&CCR1 ; ; ;
; The Module 3 handler shows a way to look if any other ; interrupt is pending: 5 cycles have to be spent, but ; 9 cycles may be saved if another interrupt is pending
;
TIMMOD3 ADD ... JMP
;
; #PP,&CCR3 ; ; TIM_HND ;
Vector 6: Module 3 Add time difference Task starts here Look for pending interrupts ; Interrupt Vectors
5 2
.SECT "VECTORS",0FFF0h
;
; The vector address may be different for different devices.
.WORD TIM_HND
.WORD TIMMOD0
; ; ; ; ;
Vector Module TBIFG Vector Module
for Capture/Compare 1..6 and timer overflow for Capture/Compare 0
11-38
Timer_B Registers
11.6.4.4 Timer Interrupt Vector Register, Software Example, Timer_B3
The following software example describes the use of vector word TBIV of Timer_B3 and the handling overhead. The numbers at the right margin show the necessary cycles for every instruction. The example is written for continuous mode: the time difference to the next interrupt is added to the corresponding compare register.
; Software example for the interrupt part
;
Cycles
; Interrupt handler for Capture/Compare Module 0. ; The interrupt flag CCIFG0 is reset automatically
;
TIMMOD0
;
... RETI
; Start of handler Interrupt latency
6 5
; Interrupt handler for Capture/Compare Modules 1 to 6. ; The interrupt flags CCIFGx and TBIFG are reset by ; hardware. Only the flag with the highest priority ; responsible for the interrupt vector word is reset. TIM_HND $ ; Interrupt latency ADD &TBIV,PC ; Add offset to Jump table RETI ; Vector 0: No interrupt JMP TIMMOD1 ; Vector 2: Module 1 JMP TIMMOD2 ; Vector 4: Module 2 RETI ; Vector 6 RETI ; Vector 8 RETI ; Vector 10 RETI ; Vector 12
;
6 3 5 2 2
; Timer Overflow Handler: the Timer Register is expanded ; into the RAM location TIMEXT (MSBs)
;
TIMOVH INC RETI
;
TIMEXT
; Vector 14: TIMOV Flag ; Handle Timer Overflow ; ; ; ; Vector 4: Module 2 Add time difference Task starts here Back to main program
4 5 5 5
TIMMOD2 ADD ... RETI #NN,&CCR2
; The Module 1 handler shows a way to look if any other ; interrupt is pending: 5 cycles have to be spent, but ; 9 cycles may be saved if another interrupt is pending
;
TIMMOD1 ADD ... JMP
;
; #PP,&CCR1 ; ; TIM_HND ;
Vector 6: Module 3 Add time difference Task starts here Look for pending interrupts ; Interrupt Vectors
5 2
.SECT "VECTORS",0FFF0h
;
; The vector address may be different for different devices.
.WORD TIM_HND
.WORD TIMMOD0
; ; ; ; ;
Vector Module TBIFG Vector Module
for Capture/Compare 1..6 and timer overflow for Capture/Compare 0
If the FLL (on applicable devices) is turned off, then two additional cycles need to be added for a synchronous start of the CPU and system clock MCLK. If the CPU clock MCLK was turned off in devices with the Basic Clock Module (CPUOFF=1), then 2 or 3 additional cycles need to be added for synchronous start of the CPU. The delta of one clock cycle is caused when clocks are asynchronous to the restart of CPU clock MCLK.
Timer_B
11-39
Timer_B Registers
The software overhead for different interrupt sources includes interrupt latency and return-from-interrupt cycles (but not the task handling itself), as described:
11.6.4.5 Timing Limits
Capture/compare block CCR0 Capture/compare blocks CCR1 to CCR6 Timer overflow TBIFG
11 cycles 16 cycles 14 cycles
With the TBIV register and the previous software, the shortest repetitive time distance tCRmin between two events using a compare register is: tCRmin = ttaskmax + 16 x tcycle With: ttaskmax Maximum (worst case) time to perform the task during the interrupt routine (for example, incrementing a counter) tcycle Cycle time of the system frequency MCLK
The shortest repetitive time distance tCLmin between two events using a capture register is: tCLmin = ttaskmax + 16 x tcycle
11-40
Chapter 12
USART Peripheral Interface, UART Mode
The universal synchronous/asynchronous receive/transmit (USART) serialcommunication peripheral supports two serial modes with one hardware configuration. These modes shift a serial bit stream in and out of the MSP430 at a programmed rate or at a rate defined by an external clock. The first mode is the universal asynchronous receive/transmit (UART) communication protocol; the second is the serial peripheral interface (SPI) protocol (discussed in Chapter 13). Bit SYNC in control register UCTL selects the required mode: SYNC = 0: UART - asynchronous mode selected SYNC = 1: SPI - synchronous mode selected This chapter addresses the UART mode.
Topic
Page
12.1 USART Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12.2 USART Peripheral Interface, UART Mode . . . . . . . . . . . . . . . . . . . . . . 12-3 12.3 Asynchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 12.4 Interrupt and Enable Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11 12.5 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15 12.6 Utilizing Features of Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . 12-22 12.7 Baud Rate Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-25
USART Peripheral Interface, UART Mode
12-1
USART Peripheral Interface
12.1 USART Peripheral Interface
The USART peripheral interface connects to the CPU as a byte peripheral module. It connects the MSP430 to the external system environment with three or four external pins. Figure 12-1 shows the USART peripheral interface module.
Figure 12-1. Block Diagram of USART
Receive Status Receive Buffer URXBUF SYNC RXE
Listen 0 1
MM 1 0
SYNC SOMI SYNC 0 STE
Receive Shift Register SSEL1 SSEL0 UCLKI ACLK SMCLK SMCLK 0 1 2 3 Baud Rate Generator URXD
SYNC
Baud Rate Register UBR SYNC UCLKS 1 0 UTXD
Baud Rate Generator
WUT
Transmit Shift Register
SIMO
TXWake
Transmit Buffer UTXBUF
CKPH
SYNC
CKPL UCLK
UCLKI UCLKS
Clock Phase and Polarity
12-2
USART Peripheral Interface, UART Mode
12.2 USART Peripheral Interface, UART Mode
The USART peripheral interface is a serial channel that shifts a serial bit stream of 7 or 8 bits in and out of the MSP430. The UART mode is chosen when control bit SYNC in the USART control register (UCTL) is reset.
12.2.1 UART Serial Asynchronous Communication Features
Some of the UART features include:
-
Asynchronous formats that include idle line/address bit-communication protocols Two shift registers that shift a serial data stream into URXD and out of UTXD Data that is transmitted/received with the LSB first Programmable transmit and receive bit rates Status flags
Figure 12-2 shows the USART in UART mode.
Figure 12-2. Block Diagram of USART--UART Mode
Receive Status Receive Buffer URXBUF RXE SYNC = 0 URXD
Listen 0 1
Receive Shift Register SSEL1 SSEL0 UCLKI ACLK SMCLK SMCLK 0 1 2 3 Baud Rate Generator UCLKS
Baud Rate Register UBR
Baud Rate Generator
WUT
Transmit Shift Register
LSB First UTXD
TXWake
Transmit Buffer UTXBUF
CKPL Clock Polarity UCLK
UCLKI UCLKS
USART Peripheral Interface, UART Mode
12-3
Asynchronous Operation
12.3 Asynchronous Operation
In the asynchronous mode, the receiver synchronizes itself to frames but the external transmitting and receiving devices do not use the same clock source; the baud rate is generated locally.
12.3.1 Asynchronous Frame Format
The asynchronous frame format, shown in Figure 12-3, consists of a start bit, seven or eight data bits, an even/odd/no parity bit, an address bit in address bit mode, and one or two stop bits. The bit period is defined by the selected clock source and the data in the baud rate registers.
Figure 12-3. Asynchronous Frame Format
ST D0 D6 D7 AD PA SP SP Mark Space [2nd Stop Bit, SP = 1] [Parity Bit, PENA = 1] [Address Bit, MM = 1] [Optional Bit, Condition] [8th Data Bit, CHAR = 1]
The receive (RX) operation is initiated by the receipt of a valid start bit. It begins with a negative edge at URXD, followed by the taking of a majority vote from three samples where two of the samples must be zero. These samples occur at n/2-X, n/2, and n/2+X of the BRCLK periods following the negative edge. This sequence provides false start-bit rejection, and also locates the center of the bits in the frame, where the bits can be read on a majority basis. The timing of X is 1/32 to 1/63 times that of the BRCLK, depending on the division rate of the baud rate generator and provides complete coverage of at least two BRCLK periods. Figure 12-4 shows an asynchronous bit format.
Figure 12-4. Asynchronous Bit Format. Example for n or n + 1 Clock Periods
Falling Edge on UEXD Indicates Start bit 1 2 3 Majority Vote Taken From URXD Data Line n/2-x n/2 n/2+x n-1 n-1 n 1 n n+1 2 1 3 2
H BRCLK L H UTXD L
Data Bit Period = n or n+1 BRCLK Periods URXD H L Data Bit Period = n or n+1 BRCLK Periods
12-4
Asynchronous Operation
12.3.2 Baud Rate Generation in Asynchronous Communication Format
Baud rate generation in the MSP430 differs from other standard serial-communication interface implementations.
12.3.2.1 Typical Baud Rate Generation
Typical baud-rate generation uses a prescaler from any clock source and a fixed, second-clock divider that is usually divide-by-16. Figure 12-5 shows a typical baud-rate generation.
Figure 12-5. Typical Baud-Rate Generation Other Than MSP430
0 Select Clock Source Clock1 BRCLK UBR0 8 70 UBR1 8 15 RC BRSCLK :16 BITCLK 7 Start
16-Bit Prescaler/Divider
Clockn Start BRSCLK H L H L 1 2 3 4 5 6 7
8
9
10 11
12 13
14 15
16
1
Take Majority Vote of Receive Bit H BITCLK L
Baud rate = BRCLK n 16 Typical baud-rate schemes often require specific crystal frequencies or cannot generate some baud rates required by some applications. For example, division factors of 18 are not possible, nor are noninteger factors such as 13.67.
12.3.2.2 MSP430 Baud Rate Generation
The MSP430 baud rate generator uses one prescaler/divider and a modulator as shown in Figure 12-6. This combination works with crystals whose frequencies are not multiples of the standard baud rates, allowing the protocol to run at maximum baud rate with a watch crystal (32,768 Hz). This technique results in power advantages because sophisticated, MSP430 low-power operations are possible.
USART Peripheral Interface, UART Mode
12-5
Asynchronous Operation
Figure 12-6. MSP430 Baud Rate Generation. Example for n or n + 1 Clock Periods
SSEL1 SSEL0 UCLKI ACLK SMCLK SMCLK 0 1 2 3 BRCLK 0 UBR0 1 7 7 0 UBR1 8 15 7 Start
15-Bit Prescaler/Divider Q1 Compare 0 or 1 Q15 Toggle FF
BITCLK
Shift Modulation Register Data m Shift_out Shift_in 7 Modulation Register UMOD H L H BRCLK L Counter Start
0
n/2 n/2-1 n/2-2
1 1 1
0 n/2 n/2
n/2 n/2-1 n/2-1 n/2-2 n/2-1 n/2-2
2 1 1
n/2 0 1 n/2 n/2-1 0 n/2 n/2-1 n/2-2
H BITCLK L INT(n/2), m = 0 INT(n/2)+m(=1) Divide By n(Even), m = 0 n(Odd) or n(Even)+m(=1) n(Odd)+m(=1)
The modulation register LSB is first used for modulation, which begins with the start bit. A set modulation bit increases the division factor by one.
Example 12-1. 4800 Baud
Assuming a clock frequency of 32,768 Hz for the BRCLK signal and a required baud rate of 4800, the division factor is 6.83. The baud rate generation in the MSP430 USART uses a factor of six plus a modulation register load of 6Fh (0110 1111). The divider runs the following sequence: 7 - 7 - 7 - 7 - 6 - 7 - 7 - 6 and so on. The sequence repeats after all eight bits of the modulator are used.
Example 12-2. 19,200 Baud
Assuming a clock frequency of 1.04 MHz (32 x 32,768 Hz) for the BRCLK signal and a required baud rate of 19,200, the division factor is 54.61. The baud rate generation in the MSP430 USART uses a factor of 54 (36h) plus a modulation register load of 0D5h. The divider runs the following sequence: 55 - 54 - 55 - 54 - 55 - 54 - 55 - 55, and so on. The sequence repeats after all eight bits of the modulator are used.
12-6
Asynchronous Operation
12.3.3 Asynchronous Communication Formats
The USART module supports two multiprocessor communication formats when asynchronous mode is used. These formats can transfer information between many microcomputers on the same serial link. Information is transferred as a block of frames from a particular source to one or more destinations. The USART has features that identify the start of blocks and suppress interrupts and status information from the receiver until a block start is identified. In both multiprocessor formats, the sequence of data exchanged with the USART module is based on data polling, or on the use of the receive interrupt features. Both of the asynchronous multiprocessor formats--idle-line and address-bit --allow efficient data transfer between multiple communication systems. They can also minimize the activity of the system to save current consumption or processing resources. The control register bit MM defines the address bit or idle-line multiprocessor format. Both use the wake-up-on-transfer mode by activating the TXWake bit (address feature function) and RXWake bit. The URXWIE and URXIE bits control the transmit and receive features of these asynchronous communication formats.
12.3.4 Idle-Line Multiprocessor Format
In the idle-line multiprocessor format, shown in Figure 12-7, blocks of data are separated by an idle time. An idle-receive line is detected when ten or more 1s in a row are received after the first stop bit of a character.
Figure 12-7. Idle-Line Multiprocessor Format
Block of Frames
UTXD/URXD
Idle Periods of 10 Bits or More UTXD/URXD Expanded
UTXD/URXD
ST
Address
SP ST
Data
SP
ST
Data
SP
First Frame Within Block is Address. It Follows Idle Period of 10 Bits or More
Frame Within Block
Frame Within Block
Idle Period Less Than 10 Bits
USART Peripheral Interface, UART Mode
12-7
Asynchronous Operation
When two stop bits are used for the idle line, as shown in Figure 12-8, the second one is counted as the first mark bit of the idle period. The first character received after an idle period is an address character. The RXWake bit can be used as an address tag for the character. In the idle-line multiprocessor format, the RXWake bit is set when a received character is an address character and is transferred into the receive buffer.
Figure 12-8. USART Receiver Idle Detect
Example: One Stop Bit Mark XXXX Space SP ST XXXXXXX 10-Bit Idle Period
Example: Two Stop Bits Mark XXXX Space SP: Stop Bit ST: Start Bit SP SP
10-Bit Idle Period ST XXXXXXX
Normally, if the USART URXWIE bit is set in the receive control register, characters are assembled as usual by the receiver. They are not, however, transferred to the receiver buffer, URXBUF, nor are interrupts generated. When an address character is received, the receiver is temporarily activated to transfer the character to URXBUF and to set the URXIFG interrupt flag. Applicable error status flags are set. The application software can validate the received address. If there is a match, the application software further processes the data and executes the operation. If there is no match, the processor waits for the next address character to arrive. The URXWIE bit is not modified by the USART: it must be modified manually to receive nonaddress or address characters. In idle-line multiprocessor format, a precise idle period can be generated to create efficient address character identifiers. The wake-up temporary (WUT) flag is an internal flag and is double-buffered with TXWake. When the transmitter is loaded from UTXBUF, WUT is loaded from TXWake, and the TXWake bit is reset as shown in Figure 12-9.
Figure 12-9. Double-Buffered WUT and TX Shift Register
TXWake TX Buffer UTXBUF Start Bit WUT TX Shift Register Parity Bit TX Signal
12-8
Asynchronous Operation
The following procedure sends out an idle frame to identify an address character: 1) Set the TXWake bit and then write any word (don't care) to the UTXBUF (UTXIFG must be set). When the transmitter shift register is empty, the contents of UTXBUF are shifted to the transmit shift register and the TXWake value is shifted to WUT. 2) Set bit WUT, which suppresses the start, data, and parity bits and transmits an idle period of exactly 11 bits, as shown in Figure 12-10. The next data word, shifted out of the serial port after the addresscharacter identifying idle period, is the second word written to the UTXBUF after the TXWake bit has been set. The first data word written is suppressed while the address identifier is sent out and ignored thereafter. Writing the first don't care word to UTXBUF is necessary to shift the TXWAKE bit to WUT and generate an idle-line condition.
Figure 12-10. USART Transmitter Idle Generation
Example: One Stop Bit Mark XXXX Space Example: Two Stop Bits Mark XXXX Space SP: Stop Bit ST: Start Bit SP SP ST XXXXXXX 11-Bit Idle Period SP ST XXXXXXX 11-Bit Idle Period
12.3.5 Address-Bit Multiprocessor Format
In the address-bit multiprocessor format shown in Figure 12-11, characters contain an extra bit used as an address indicator. The first character in a block of data carries an address bit which indicates that the character is an address. The RXWake bit is set when a received character is an address character. It is transferred into the receive buffer (receive conditions are true). Usually, if the USART URXWIE bit is set, data characters are assembled by the receiver but are not transferred to the receiver buffer URXBUF, nor are interrupts generated. When a character that has an address bit set is received, the receiver is temporarily activated to transfer the character to URXBUF and to set the URXIFG. Error status flags are set as applicable. The application software processes the succeeding operation to optimize resource handling or reduce current consumption. The application software can validate the received address. If there is a match, the processor can read the remainder of the data block. If there is not a match, the processor waits for the next address character to arrive.
USART Peripheral Interface, UART Mode
12-9
Asynchronous Operation
Figure 12-11.Address-Bit Multiprocessor Format
Block of Frames
UTXD/URXD
Idle Periods of No Significance TXD/RXD Expanded
UTXD/URXD
ST
Address
1 SP ST
Data
0 SP
ST
Data
0 SP
First Frame Within Block Is an Address. The ADDR/DATA Bit is 1
ADDR/DATA Bit is 0 for Data Within Block. Idle Time Is of No Significance
In the address-bit multiprocessor mode, the address bit of a character can be controlled by writing to the TXWake bit. The value of the TXWake bit is loaded into the address bit of that character each time a character is transferred from transmit buffer UTXBUF to the transmitter. The TXWake bit is then cleared by the USART.
12-10
Interrupt and Enable Functions
12.4 Interrupt and Enable Functions
The USART peripheral interface serves two main interrupt sources for transmission and reception. Two interrupt vectors serve receive and transmit events. The interrupt control bits and flags and enable bits of the USART peripheral interface are located in the SFR registers. They are discussed in Table 12-1. See the peripheral file map in Appendix A for the exact bit locations.
Table 12-1.USART Interrupt Control and Enable Bits - UART Mode
Receive interrupt flag Receive interrupt enable Receive enable (see note) Transmit interrupt flag Transmit interrupt enable Transmit enable.(see note)
Note:
URXIFG URXIE URXE UTXIFG UTXIE UTXE
Initial state reset (by PUC/SWRST) Initial state reset (by PUC/SWRST) Initial state reset (by PUC) Initial state set (by PUC/SWRST) Initial state reset (by PUC/SWRST) Initial state reset (by PUC)
Different for SPI mode, see Chapter 13.
The USART receiver and transmitter operate independently, but use the same baud rate.
12.4.1 USART Receive Enable Bit
The receive enable bit URXE, shown in Figure 12-12, enables or disables receipt of the bit stream on the URXD data line. Disabling the USART receiver stops the receive operation after completion of receiving the character, or stops immediately if no receive operation is active. Start-bit detection is also disabled.
Figure 12-12. State Diagram of Receiver Enable
No Valid Start Bit URXE = 0 Not Completed URXE = 1 Valid Start Bit
URXE = 1 Receive Disable URXE = 0
Idle State (Receiver Enabled)
Receiver Collects Character
Handle Interrupt Conditions Character Received
URXE = 1 URXE = 0
Note: URXE Reenabled, UART Mode Because the receiver is completely disabled, reenabling the receiver is asynchronous to any data stream on the communication line. Synchronization can be performed by looking for an idle line condition before receiving a character.
USART Peripheral Interface, UART Mode
12-11
Interrupt and Enable Functions
12.4.2 USART Transmit Enable Bit
The transmit enable bit UTXE, shown in Figure 12-13, enables or disables a character transmission on the serial-data line. If this bit is reset, the transmitter is disabled but any active transmission does not halt until the data in the transmit shift register and the transmit buffer are transmitted. Data written to the transmit buffer before UTXE has been reset may be modified or overwritten--even after UTXE is reset--until it is shifted to the transmit shift register. For example, if software writes a byte to the transmit buffer and then resets UTXE, the byte written to the transmit buffer will be transmitted and may be modified or overwritten until it is transferred into the transmit shift register. However, after the byte is transferred to the transmit shift register, any subsequent writes to UTXBUF while UTXE is reset will not result in transmission, but UTXBUF will be updated with the new value.
Figure 12-13. State Diagram of Transmitter Enable
UTXE = 0 No Data Written to Transmit Buffer Not Completed
UTXE = 1 Transmit Disable UTXE = 0
UTXE = 1 Data Written to Idle State Transmit Buffer Transmission (Transmitter Active Enabled) UTXE = 1
Handle Interrupt Conditions Character Transmitted
UTXE = 0 And Last Buffer Entry Is Transmitted
When UTXE is reset and the current transmission is completed, new data written to the transmit buffer will not be transmitted. Once the UTXE bit is set, the data in the transmit buffer are immediately loaded into the transmit shift register and character transmission is started. Note: Writing to UTXBUF, UART Mode Data should never be written to transmit buffer UTXBUF when the buffer is not ready and when the transmitter is enabled (UTXE is set). Otherwise, the transmission will have errors.
Note: Write to UTXBUF/Reset of Transmitter, UART Mode Disabling the transmitter should be done only if all data to be transmitted has been moved to the transmit shift register.
MOV.B BIC.B #....,&UTXBUF #UTXE,&ME2 ; ; ; ; ; If BITCLK < MCLK then the transmitter might be stopped before the buffer is loaded into the transmitter shift register
12-12
Interrupt and Enable Functions
12.4.3 USART Receive Interrupt Operation
In the receive interrupt operation, shown in Figure 12-14, the receive interrupt flag URXIFG is set or is unchanged each time a character is received and loaded into the receive buffer:
-
Erroneous characters (parity, frame, or break error) do not set interrupt flag URXIFG when URXEIE is reset: URXIFG is unchanged. All types of characters (URXWIE = 0), or only address characters (URXWIE = 1), set the interrupt flag URXIFG. When URXEIE is set, erroneous characters can also set the interrupt flag URXIFG.
Figure 12-14. Receive Interrupt Operation
SYNC Valid Start Bit Receiver Collects Character URXSE From URXD Erroneous Character Will Not Set Flag URXIFG SYNC URXEIE (S) URXIFG URXWIE RXWake Each Character or Address Will Set Flag URXIFG Character Received or Break Detected Clear SWRST PUC URXBUF URXSE IRQA URXS
Clear URXIE
PE FE BRK
Request_ Interrupt_Service
URXIFG is reset by a system reset PUC signal, or with a software reset (SWRST). URXIFG is reset automatically if the interrupt is served (URXSE = 0) or the receive buffer URXBUF is read. A set receive interrupt flag URXIFG indicates that an interrupt event is waiting to be served. A set receive interrupt enable bit URXIE enables serving a waiting interrupt request. Both the receive interrupt flag URXIFG and the receive interrupt enable bit URXIE are reset with the PUC signal and a SWRST. Signal URXIFG can be accessed by the software, whereas signal URXS cannot. When both interrupt events--character receive action and receive start detection--are enabled by the software, the flag URXIFG indicates that a character was received but the start-detect interrupt was not. Because the interrupt software handler for the receive start detection resets the URXSE bit, this clears the URXS bit and prevents further interrupt requests from URXS. The URXIFG should already be reset since no set condition was active during URXIFG latch time.
USART Peripheral Interface, UART Mode
12-13
Interrupt and Enable Functions
12.4.4 USART Transmit Interrupt Operation
In the transmit interrupt operation, shown in Figure 12-15, the transmit interrupt flag UTXIFG is set by the transmitter to indicate that the transmitter buffer UTXBUF is ready to accept another character. This bit is automatically reset if the interrupt request service is started or a character is written into the UTXBUF. This flag asserts a transmitter interrupt if the local (UTXIE) and general interrupt enable (GIE) bits are set. The UTXIFG is set after a system reset PUC signal, or removal of a SWRST.
Figure 12-15. Transmit Interrupt Operation
Q UTXIE
Clear PUC or SWRST Set UTXIFG DQ SWRST Clear URXBUF Written Into Transmit Shift Register IRQA Request_ Interrupt_Service
VCC Character Moved From Buffer to Shift Register
The transmit interrupt enable UTXIE bit controls the ability of the UTXIFG to request an interrupt, but does not prevent the flag UTXIFG from being set. The UTXIE is reset with a PUC signal or a software reset (SWRST) bit. The UTXIFG bit is set after a system reset PUC signal or software reset (SWRST), but the UTXIE bit is reset to ensure full interrupt-control capability.
12-14
Control and Status Registers
12.5 Control and Status Registers
The USART control and status registers are byte-structured and should be accessed using byte processing instructions (suffix B). Tables 12-2 and 12-3 list the registers and their access modes.
Table 12-2.USART0 Control and Status Registers
Register USART control Transmit control Receive control Modulation control Baud rate 0 Baud rate 1 Receive buffer Transmit buffer Short Form UCTL0 UTCTL0 URCTL0 UMCTL0 UBR00 UBR10 Register Type Read/write Read/write Read/write Read/write Read/write Read/write Address Initial State 070h 071h 072h 073h 074h 075h 076h 077h See section 12.5.1. See section 12.5.2. See section 12.5.3. Unchanged Unchanged Unchanged Unchanged Unchanged
URXBUF0 Read/write UTXBUF0 Read
Table 12-3.USART1 Control and Status Registers
Register USART control Transmit control Receive control Modulation control Baud rate 0 Baud rate 1 Receive buffer Transmit buffer Short Form UCTL1 UTCTL1 URCTL1 UMCTL1 UBR01 UBR11 Register Type Read/write Read/write Read/write Read/write Read/write Read/write Address Initial State 078h 079h 07Ah 07Bh 07Ch 07Dh 07Eh 07Fh See section 12.5.1. See section 12.5.2. See section 12.5.3. Unchanged Unchanged Unchanged Unchanged Unchanged
URXBUF1 Read/write UTXBUF1 Read
All bits are random after a PUC signal, unless otherwise noted by the detailed functional description. The reset of the USART peripheral interface is performed by a PUC signal or a SWRST. After a PUC signal, the SWRST bit remains set and the USART interface remains in the reset condition until it is disabled by resetting the SWRST bit. The USART module operates in asynchronous or synchronous mode as defined by the SYNC bit. The bits in the control registers can have different functions in the two modes. All bits in this section are described with their functions in the asynchronous mode (SYNC = 0). Their functions in the synchronous mode are described in Chapter 13, USART Peripheral Interface, SPI Mode.
USART Peripheral Interface, UART Mode
12-15
Control and Status Registers
12.5.1 USART Control Register UCTL
The information stored in the USART control register (UCTL), shown in Figure 12-16, determines the basic operation of the USART module. The register bits select the communications protocol, communication format, and parity bit. All bits must be programmed according to the selected mode before resetting the SWRST bit to disable the reset.
Figure 12-16. USART Control Register UCTL
7 UCTL0, 070h UCTL1, 078h
PENA PEV SP CHAR Listen SYNC MM
0
SWRST
rw-0
rw-0
rw-0
rw-0 rw-0
rw-0
rw-0
rw-1
Bit 0:
The USART state machines and operating flags are initialized to the reset condition (URXIFG = URXIE = UTXIE = 0, UTXIFG = 1) if the software reset bit is set. Until the SWRST bit is reset, all affected logic is held in the reset state. This implies that after a system reset the USART must be reenabled by resetting this bit. The receive and transmit enable flags URXE and UTXE are not altered by SWRST. The SWRST bit resets the following bits and flags: URXIE, UTXIE, URXIFG, RXWAKE, TXWAKE, RXERR, BRK, PE, OE, and FE The SWRST bit sets the following bits: UTXIFG, TXEPT
Bit 1:
Multiprocessor mode (address/idle-line wake up) Two multiprocessor protocols, idle-line and address-bit, are supported by the USART module. The choice of multiprocessor mode affects the operation of the automatic address decoding functions. MM = 0: Idle-line multiprocessor protocol MM = 1: Address-bit multiprocessor protocol The conventional asynchronous protocol uses MM-bit reset. Mode or function of USART module selected The SYNC bit selects the function of the USART peripheral interface module. Some of the USART control bits have different functions in UART and SPI mode. SYNC = 0: UART function is selected SYNC = 1: SPI function is selected The listen bit selects if the transmitted data is fed back internally to the receiver. Listen = 0: No feedback Listen = 1: Transmit signal is internally fed back to the receiver. This is commonly known as loopback mode. Character length This register bit selects the length of the character to be transmitted as either 7 or 8 bits. 7-bit characters do not use the eighth bit in URXBUF and UTXBUF. This bit is padded with 0.
Bit 2:
Bit 3:
Bit 4:
12-16
Control and Status Registers
CHAR = 0: 7-bit data CHAR = 1: 8-bit data Bit 5: Number of stop bits This bit determines the number of stop bits transmitted. The receiver checks for one stop bit only. SP = 0: one stop bit SP = 1: two stop bits Parity odd/even If the PENA bit is set (parity bit is enabled), the PEV bit defines odd or even parity according to the number of odd or even 1 bits (in both the transmitted and received characters), the address bit (address-bit multiprocessor mode), and the parity bit. PEV = 0: odd parity PEV = 1: even parity Parity enable If parity is disabled, no parity bit is generated during transmission or expected during reception. A received parity bit is not transferred to the URXBUF with the received data as it is not considered one of the data bits. In address-bit multiprocessor mode, the address bit is included in the parity calculation. PEN = 0: Parity disable PEN = 1: Parity enable
Bit 6:
Bit 7:
Note: Mark and Space Definitions The mark condition is identical to the signal level in the idle state. Space is the opposite signal level: the start bit is always space.
12.5.2 Transmit Control Register UTCTL
The transmit control register (UTCTL), shown in Figure 12-17, controls the USART hardware associated with the transmit operation.
Figure 12-17. Transmitter Control Register UTCTL
7 UTCTL1, 07Bh UTCTL0, 071h
Unused CKPL SSEL1
0
SSEL0 URXSE TXWake Unused TXEPT
rw-0
rw-0
rw-0
rw-0 rw-0
rw-0
rw-0
rw-1
Bit 0:
The transmitter empty (TXEPT) flag is set when the transmitter shift register and UTXBUF are empty, and is reset when data is written to UTXBUF. It is set by a SWRST. Unused The TXWake bit controls the transmit features of the multiprocessor communication modes. Each transmission --started by loading the UTXBUF--uses the state of the TXWake bit to initialize the address-identification feature. It must not be cleared--the USART hardware clears this bit once it is transferred to the WUT; a SWRST also clears the TXWake bit.
Bit 1: Bit 2:
USART Peripheral Interface, UART Mode
12-17
Control and Status Registers
Bit 3:
The receive-start edge-control bit, if set, requests a receive interrupt service. For a successful interrupt service, the corresponding enable bits URXIE and GIE must be set. The advantage of this bit is that it starts the controller clock system, including MCLK, along with the interrupt service, and keeps it running by modifying the mode control bits. Source select 0 and 1 The source select bit defines which clock source is used for baud-rate generation: SSEL1, SSEL0 0 External clock, UCLKI 1 ACLK 2, 3 SMCLK Clock polarity CKPL The CKPL bit controls the polarity of the UCLKI signal. CKPL = 0: The UCLKI signal has the same polarity as the UCLK signal. CKPL = 1: The UCLKI signal has an inverted polarity to the UCLK signal. Unused
Bits 4, 5:
Bit 6:
Bit 7:
12.5.3 Receiver Control Register URCTL
The receiver-control register (URCTL), shown in Figure 12-18, controls the USART hardware associated with the receiver operation and holds error and wake-up conditions modified by the latest character written to the receive buffer (URXBUF). Once any one of the bits FE, PE, OE, BRK, RXERR, or RXWake is set, none are reset by receiving another character. The bits are reset by accessing the receive buffer, by a USART software reset (SWRST), by a system reset PUC signal, or by an instruction.
Figure 12-18. Receiver-Control Register URCTL
7 URCTL0, 072h URCTL1, 07Ah
FE PE OE BRK
0
URXEIE URXWIE RXWake RXERR
rw-0 rw-0
rw-0 rw-0 rw-0
rw-0
rw-0
rw-0
Bit 0:
The receive error bit (RXERR) indicates that one or more error flags (FE, PE, OE, or BRK) is set. It is not reset when the error flags are cleared by instruction. Receiver wake-up detect The RXWake bit is set when a received character is an address character and is transferred into the receive buffer. Address-bit multiprocessor mode: RXWake is set when the address bit is set in the character received. Idle-line multiprocessor mode: RXWake is set if an idle URXD line is detected (11 bits of mark level) in front of the received character.
Bit 1:
12-18
Control and Status Registers
RXWake is reset by accessing the receive buffer (URXBUF), by a USART software reset, or by a system-reset PUC signal. Bit 2: The receive wake-up interrupt-enable bit (URXWIE) selects the type of character to set the interrupt flag (URXIFG): URXWIE = 0: Each character received sets the URXIFG URXWIE = 1: Only characters that are marked as address characters set the interrupt flag URXIFG. It operates identically in both multiprocessor modes. The wake-up interrupt enable feature depends on the receive erroneous-character feature. See also Bit 3, URXEIE. The receive erroneous-character interrupt-enable bit URXEIE selects whether an erroneous character is to set the interrupt flag URXIFG. URXEIE = 0: Each erroneous character received does not alter the interrupt flag URXIFG. URXEIE = 1: All characters can set the interrupt flag URXIFG as described in Table 12-4, depending on the conditions set by the URXWIE bit.
Bit 3:
Table 12-4.Interrupt Flag Set Conditions
URXEIE 0 0 0 0 1 1 1 URXWIE X 0 1 1 0 1 1 Char. w/Error 1 0 0 0 X X X Char. Address X X 0 1 X 0 1 Description Flag URXIFG After a Character is Received Unchanged Set Unchanged Set Set (Receives all characters) Unchanged Set
Bit 4:
The break detect bit (BRK) is set when a break condition occurs and the URXEIE bit is set. The break condition is recognized if the RXD line remains continuously low for at least 10 bits, beginning after a missing first stop bit. It is not cleared by receipt of a character after the break is detected, but is reset by a SWRST, a system reset, or by reading the URXBUF. The receive interrupt flag URXIFG is set if a break is detected. The overrun error flag bit OE is set when a character is transferred into the URXBUF before the previous character is read out. The previous character is overwritten and lost. OE is reset by a SWRST, a system reset, or by reading the URXBUF. The parity error flag bit PE is set when a character is received with a mismatch between the number of 1s and its parity bit, and is loaded into the receive buffer. The parity checker includes the address bit, used in the address-bit multiprocessor mode, in the
Bit 5:
Bit 6:
USART Peripheral Interface, UART Mode
12-19
Control and Status Registers
calculation. The flag is disabled if parity generation and detection are not enabled. In this case the flag is read as 0. It is reset by a SWRST, a system reset, or by reading the URXBUF. Bit 7: The framing error flag bit FE is set when a character is received with a 0 stop bit and is loaded into the receive buffer. Only the first stop bit is checked when more than one is used. The missing stop bit indicates that the start-bit synchronization is lost and the character is incorrectly framed. FE is reset by a SWRST, a system reset, or by reading the URXBUF.
Note: Receive Status Control Bits The receive status control bits FE, PE, OE, BRK, and RXWake are set by the hardware according to the conditions of the characters received. Once the bits are set, they remain set until the software resets them directly, or there is a reading of the receive buffer. False character interpretation or missinginterrupt capability can result in uncleared error bits.
12.5.4 Baud Rate Select and Modulation Control Registers
The baud-rate generator uses the content of the baud-rate select registers UBR0 and UBR1 shown in Figure 12-19, with the modulation control register to generate the serial data-stream bit timing.
Figure 12-19. USART Baud Rate Select Register
7 UBR00, 074h UBR01, 07Ch
27 rw 26 rw 25 rw 24 rw 23 rw 22 rw 21 rw
0
20 rw
7 UBR10, 075h UBR11, 07Dh
215 rw 214 rw 213 rw 212 rw 211 rw 210 rw 29 rw
0
28 rw
Baud rate =
BRCLK UBR
)
1 n
S mi i+0
n-1
with UBR= [UBR1,UBR0] 3 UBR < 0FFFFh
The baud-rate control register range is: Note:
Unpredictable receive and transmission occur if UBR <3. The modulation control register, shown in Figure 12-20, ensures proper timing generation with the UBR0 and UBR01, even with crystal frequencies that are not integer multiples of the required baud rate.
Figure 12-20. USART Modulation Control Register
7 UMCTL0, 073h UMCTL1, 07Bh
m7 m6 m5 m4 m3 m2 m1
0
m0
rw
rw
rw
rw
rw
rw
rw
rw
12-20
Control and Status Registers
The timing of the running bit is expanded by one clock cycle of the baud-ratedivider input clock if bit mi is set. Each time a bit is received or transmitted, the next bit in the modulation control register determines the present bit timing. The first bit time in the protocol--the start bit time--is determined by UBR plus m0; the next bit is determined by UBR plus m1, and so on. The modulation sequence is: m0 - m1 - m2 - m3 - m4 - m5 - m6 - m7 - m0 - m1 - m2 - .....
12.5.5 Receive-Data Buffer URXBUF
The receive-data buffer (URXBUF), shown in Figure 12-21, contains previous data from the receiver shift register. Reading URXBUF resets the receive-error bits, the RXWake bit, and the interrupt flag (URXIFG).
Figure 12-21. USART0 Receive Data Buffer URXBUF
7 URXBUF0, 076h URXBUF1, 07Eh
27 r 26 r 25 r 24 r 23 r 22 r 21 r
0
20 r
In seven-bit length mode, the MSB of the URXBUF is always reset. The receive data buffer is loaded with the recently-received character as described in Table 12-5, when receive and control conditions are true.
Table 12-5.Receive Data Buffer Characters
URXEIE 0 1 0 1 URXWIE 1 1 0 0 Load URXBUF With: Error-free address characters All address characters Error-free characters All characters PE 0 X 0 X FE 0 X 0 X BRK 0 X 0 X
12.5.6 Transmit Data Buffer UTXBUF
The transmit data buffer (UTXBUF), shown in Figure 12-22, contains current data to be transmitted.
Figure 12-22. Transmit Data Buffer UTXBUF
7 UTXBUF0, 077h UTXBUF1, 07Fh
27 rw 26 rw 25 rw 24 rw 23 rw 22 rw 21 rw
0
20 rw
The UTXIFG flag indicates that the UTXBUF buffer is ready to accept another character for transmission. The transmission is initialized by writing data to UTXBUF. The transmission of this data is started immediately if the transmitter shift register is empty or is going to be empty.
USART Peripheral Interface, UART Mode
12-21
Utilizing Features of Low-Power Modes
Note: Writing to UTXBUF Writing data to the transmit-data buffer must only be done if buffer UTXBUF is empty; otherwise, an unpredictable character can be transmitted.
12.6 Utilizing Features of Low-Power Modes
There are several functions or features of the USART that support the ultralow power architecture of the MSP430. These include:
-
Support system start up from any processor mode by sensing of UART frame-start condition Use the lowest input clock frequency for the required baud rate Support multiprocessor modes to reduce use of MSP430 resources
12.6.1 Receive-Start Operation From UART Frame
The most effective use of start detection in the receive path is achieved when the baud-rate clock runs from SMCLK. In this configuration, the MSP430 can be put into a low-power mode with SMCLK disabled. The receive-start condition is the negative edge from the signal on pin URXD. Each time the negative edge triggers the interrupt flag URXS, it requests a service when enable bits URXIE and GIE are set. This wakes the MSP430 and the system returns to active mode, supporting the USART transfer.
Figure 12-23. Receive-Start Conditions
SYNC Valid Start Bit Receiver Collects Character URXSE From URXD Erroneous Character Will Not Set Flag URXIFG URXEIE SYNC (S) URXIFG URXWIE RXWake Each Character or Address Will Set Flag URXIFG Character Received or Break Detected Clear SWRST PUC URXBUF Read URXSE IRQA URXS D Q
Clear URXIE
PE FE BRK
Request_ Interrupt_Service
Three character streams do not set the interrupt flag (URXIFG):
-
Erroneous characters (URXEIE = 0) Address characters (URXWIE = 1) Invalid start-bit detection
The interrupt software should handle these conditions.
12-22
Utilizing Features of Low-Power Modes
12.6.1.1 Start Conditions
The URXD signal feeds into the USART module by first going into a deglitch circuit. Glitches cannot trigger the receive-start condition flag URXS, which prevents the module from being started from small glitches on the URXD line. Because glitches do not start the system or the USART module, current consumption is reduced in noisy environments. Figure 12-24 shows the accepted receive-start timing condition.
Figure 12-24. Receive-Start Timing Using URXS Flag, Start Bit Accepted
Majority Vote URXD URXS t URXS Is Reset in the Interrupt Handler Using Control Bit URXSE
The UART stops receiving a character when the URXD signal exceeds the deglitch time t but the majority vote on the signal fails to detect a start bit, as shown in Figure 12-25. The software should handle this condition and return the system to the appropriate low-power mode. The interrupt flag URXIFG is not set.
Figure 12-25. Receive-Start Timing Using URXS Flag, Start Bit Not Accepted
Majority Vote URXD URXS t URXS Is Reset in the Interrupt Handler Using Control Bit URXSE
Glitches at the URXD line are suppressed automatically and no further activity occurs in the MSP430 as shown in Figure 12-26. The data for the deglitch time t is noted in the corresponding device specification.
Figure 12-26. Receive-Start Timing Using URXS Flag, Glitch Suppression
Majority Vote URXD URXS t
The interrupt handler must reset the URXSE bit in control register UCTL to prevent further interrupt service requests from the URXS signal and to enable the basic function of the receive interrupt flag URXIFG.
USART Peripheral Interface, UART Mode
12-23
Utilizing Features of Low-Power Modes
********************************************************** * Interrupt handler for frame start condition and * * Character receive * ********************************************************** IFG2 UTCTL UTXIFG URXSE URX_Int .EQU .EQU .EQU .EQU 3 71h 0 8 ; ; ; ; ; ; ; ; ; URXIFG and UTXIFG in address 3
BIT.B #URXIFG,&IFG2 JNE ST_COND ..... ..... BIC.B #URXSE,&UTCTL
test URXIFG signal to check if frame start condition
ST_COND
BIS.B #URXSE,&UTCTl ..... .....
; ; ; ; ; ; ;
clear ff/signal URXS, stop further interrupt requests Prepare FF_URXS for next frame start bits and set the conditions to run the clock needed for UART RX
Note: Break Detect (BRK) Bit With Halted UART Clock If the UART operates with the wake-up-on-start-condition mode and switches off the UCLK whenever a character is completely received, a communication line break cannot be detected automatically by the UART hardware. The break detection requires the baud-rate generator BRSCLK, but it is stopped upon the missing UCLK.
12.6.2 Maximum Utilization of Clock Frequency vs Baud Rate UART Mode
The current consumption increases linearly with the clock frequency. It should be kept to the minimum required to meet application conditions. Fast communication speed is needed for calibration and testing in manufacturing processes, alarm responses in critical applications, and response time to human requests for information. The MSP430 USART can generate baud rates up to one third of the clock frequency. An additional modulation of the baud-rate timing adjusts timing for individual bits within a frame. The timing is adjusted from bit to bit to meet timing requirements even when a noninteger division is needed. Baud rates up to 4800 baud can be generated from a 32,768 Hz crystal with maximum errors of 11 percent. Standard UARTs--even with the worst maximum error (-14.6 percent)--can obtain maximum baud rates of 75 baud.
12-24
Baud Rate Considerations
12.6.3 Support of Multiprocessor Modes for Reduced Use of MSP430 Resources
Communication systems can use multiprocessor modes with multiplecharacter idle-line or address-bit protocols. The first character can be a target address, a message identifier, or can have another definition. This character is interpreted by the software and, if it is of any significance to the application, the succeeding characters are collected and further activities are defined. An insignificant first character would stop activity for the processing device. This application is supported by the wake-up interrupt feature in the receive operation, and sends wake-up conditions along with a transmission. Avoiding activity on insignificant characters reduces consumption of MSP430 resources and the system can remain in the most efficient power-conserving mode. In addition to the multiprocessor modes, rejecting erroneous characters saves MSP430 resources. This practice prevents interrupt handling of the erroneous characters. The processor waits in the most efficient power-conserving mode until a character is processed.
12.7 Baud Rate Considerations
The MSP430 baud-rate generator uses a divider and a modulator. A given crystal frequency and a required baud rate determines the required division factor N:
N=
BRCLK baud rate
The required division factor N usually has an integer part and a fraction. The divider in the baud rate generator realizes the integer portion of the division factor N, and the modulator meets the fractional part as closely as possible. The factor N is defined as:
N
+ UBR ) 1 S mi n
n-1 i+0
Where:
N: UBR: i: n: mi :
Target division factor 16-bit representation of registers UBR1 and UBR0 Actual bit in the frame Number of bits in the frame Data of the actual modulation bit
Baud rate
+ BRCLK + N
BRCLK UBR
)
1 n
n*1 i+0
mi
12.7.1 Bit Timing in Transmit Operation
The timing for each individual bit in one frame or character is the sum of the actual bit timings as shown in Figure 12-27. The baud-rate generation error shown in Figure 12-28 in relation to the required ideal timing, is calculated for each individual bit. The relevant error information is the error relative to the actual bit, not the overall relative error.
USART Peripheral Interface, UART Mode
12-25
Baud Rate Considerations
Figure 12-27. MSP430 Transmit Bit Timing
i BRCLK ti URXD t0 t1 t2 t3 t4 t5 t6 t7 D6 t8 D7 t9 t10 t11 t12 Mark Space [2nd Stop Bit, SP = 1] [Parity Bit, PE = 1] [Address Bit, MM = 1] [8th Data Bit, Char = 1] 0 1 2 3 4 5 6 7 8 9 10 11 12
ST D0
Figure 12-28. MSP430 Transmit Bit Timing Errors
i ttarget terror URXD tactual 0 t0 ST t0 1 t1 D0 t1 8 t8 D7 t8 t9 PA t9 t10 t11 9 t10 10 t11 Mark Space 11
Even small errors per bit (relative errors) can result in large cumulative errors. They must be considered to be cumulative, not relative. The error of an individual bit can be calculated by:
Error[%]
or,
+
n-1
i+0
S t actuali
* St
n-1 i+0
target i
t baud rate
100%
Error [%]
With:
+
baud rate BRCLK
(i
) 1)
UBR
) S m * (i ) 1)
n-1 i+0 i
100%
baud rate: Required baud rate BRCLK: Input frequency - selected for UCLK, ACLK, or SMCLK i = 0 for the start bit, 1 for the data bit D0, and so on UBR: Division factor in registers UBR1 and UBR0
12-26
Baud Rate Considerations
Example 12-3. Error Example for 2400 Baud
The following data are assumed: Baud rate = BRCLK = UBR = m = 6Bh: 2400 32,768 Hz (ACLK) 13, since the ideal division factor is 13.67 m7 = 0, m6 = 1, m5 = 1, m4 = 0, m3 = 1, m2 = 0, m1 = 1 and m0 = 1 The LSB (m0) of the modulation register is used first.
((0
+ baud rate BRCLK Data bit D0 Error [%] + baud rate BRCLK Data bit D1 Error [%] + baud rate BRCLK Data bit D2 Error [%] + baud rate BRCLK Data bit D3 Error [%] + baud rate BRCLK Data bit D4 Error [%] + baud rate BRCLK baud rate Data bit D5 Error [%] + BRCLK baud rate Data bit D6 Error [%] + BRCLK Data bit D7 Error [%] + baud rate BRCLK Parity bit Error [%] + baud rate BRCLK Stop bit 1 Error [%] + baud rate BRCLK Stop bit 2 Error [%] + baud rate BRCLK
Start bit Error [%]
) 1) ((1 ) 1) ((2 ) 1) ((3 ) 1) ((4 ) 1) ((5 ) 1) ((6 ) 1) ((7 ) 1) ((8 ) 1) ((9 ) 1) ((10 ) 1) ((11 ) 1)
UBR
) 1)-1 UBR ) 2)-2 UBR ) 2)-3 UBR ) 3)-4 UBR ) 3)-5 UBR ) 4)-6 UBR ) 5)-7 UBR ) 5)-8 UBR ) 6)-9 UBR ) 7)-10 UBR ) 7)-11 UBR ) 8)-12
100%
+ 2.54% 100% + 5.08% 100% + 0.29% 100% + 2.83% 100% +*1.95% 100% + 0.59% 100% + 3.13% 100% + *1.66% 100% + 0.88% 100% + 3.42% 100% + *1.37% 100% + 1.17%
12.7.2 Typical Baud Rates and Errors
The standard baud rate data needed for the baud rate registers and the modulation register are listed in Table 12-6 for the 32,768-Hz watch crystal (ACLK) and SMCLK, assumed to be 32 times the ACLK frequency. The error listed is calculated for the transmit and receive paths. In addition to the error for the receive operation, the synchronization error must be considered.
USART Peripheral Interface, UART Mode
12-27
Baud Rate Considerations
Table 12-6.Commonly Used Baud Rates, Baud Rate Data, and Errors
Divide by Baud Rate 75 110 150 300 600 1200 2400 4800 9600 19,200 38,400 76,800 115,200 ACLK (32,768 Hz) Max. TX Error % -0.1/0.3 0/0.5 0/0.4 -0.3/0.7 - 1/1 - 4/3 6/3 - 9/11 - 21/12 Max. RX Error % -0.1/0.3 0/0.5 0/0.4 -0.3/0.7 - 1/1 - 4/3 - 6/3 - 9/11 - 21/12 Synchr. RX Error % 2 3 2 2 2 2 4 7 15 MCLK (1,048,576 Hz) Max. TX Error% 0/0.1 0/0.1 0/0.1 -0.1/0 0/0.3 0/0.3 0/0.3 0/0.4 -0.4/1 -0.2/2 - 4/3 - 6/3 - 5/7 Max. RX Error % 2 3 2 2 2 2 2 2 2 2 2 4 7
ACLK 436.91 297.89 218.45 109.23 54.61 27.31 13.65 6.83 3.41
MCLK 13,981 9532.51 6990.5 3495.25 1747.63 873.81 436.91 218.45 109.23 54.61 27.31 13.65 9.10
UBR1 1 1 0 0 0 0 0 0 0
UBR0 B4 29 DA 6D 36 1B 0D 06 03
UMOD FF FF 55 22 D5 03 6B 6F 4A
UBR1 36 25 1B 0D 06 03 01 0 0 0 0 0 0
UBR0 9D 3C 4E A7 D3 69 B4 DA 6D 36 1B 0D 09
UMOD FF FF FF 00 FF FF FF 55 03 6B 03 6B 08
The maximum error is calculated for the receive and transmit modes. The receive-mode error is the accumulated time versus the ideal scanning time in the middle of each bit. The transmit error is the accumulated timing error versus the ideal time of the bit period. The MSP430 USART peripheral interface allows baud rates nearly as high as the clock rate. It has a low error accumulation as a result of modulating the individual bit timing. In practice, an error margin of 20% to 30% supports standard serial communication.
12.7.3 Synchronization Error
The synchronization error, shown in Figure 12-29, results from the asynchronous timing between the URXD pin data signal and the internal clock system. The receive signal is synchronized with the BRSCLK clock. The BRSCLK clock is sixteen to thirty-one times faster than the bit timing, as described. BRSCLK = BRCLK BRSCLK = BRCLK/2 BRSCLK = BRCLK/4 BRSCLK = BRCLK/8 BRSCLK = BRCLK/16 BRSCLK = BRCLK/32 BRSCLK = BRCLK/64 BRSCLK = BRCLK/128 BRSCLK = BRCLK/256 BRSCLK = BRCLK/512 BRSCLK = BRCLK/1024 BRSCLK = BRCLK/2048 for for for for for for for for for for for for N N N N N N N N N N N N 1F 3Fh 7Fh FFh 1FF 3FFh 7FFh FFFh 1FFFh 3FFFh 7FFFh FFFFh
20h 40h 80h 100 200 400 800h 1000h 2000h 4000h 8000h
12-28
Baud Rate Considerations
Figure 12-29. Synchronization Error
i ttarget
BRSCLK URXD URXDS ST ST
t0 Synchronization Error 0.5x BLSCLK 0 t0 12345678 1 t1 9 10 11 12 13 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 2
D0 D0
t1
D2 D2
t2
tactual
Sample URXDS
Int(UBR/2)+m0 = Int (13/2)+1 = 6+1 = 7
UBR +m1 = 13+1 = 14
UBR +m2 = 13+0 = 13
Majority Vote Taken
Majority Vote Taken
Majority Vote Taken
The target start-bit detection-baud-rate timing ttarget(0) is half the baud-rate timing tbaud rate because the bit is tested in the middle of its period. The target baud rate timing ttargeti for all of the other succeeding bits is the baud rate timing tbaud rate.
Error [%]
OR
+ +
t actual0
0.5
)t
target 0
t target0
)
n-1
i+1
S t actuali
* St
n-1 i+1
target i
t targeti
2
100%
Error [%]
Where:
baud rate BRCLK
m0
) int
UBR 2
)
i
UBR
) S m * 1-i
n-1 i+1 i
100%
baud rate is the required baud rate BRCLK is the input frequency--selected for UCLK, ACLK, or SMCLK i = 0 for the start bit, 1 for data bit D0, and so on UBR is the division factor in registers UBR1 and BRB0
Example 12-4. Synchronization Error--2400 Baud
The following data are assumed: Baud rate = BRCLK = UBR = m = 6Bh: 2400 32,768 Hz (ACLK) 13, since the ideal division factor is 13.67 m7 = 0, m6 = 1, m5 = 1, m4 = 0, m3 = 1, m2 = 0, m1 = 1 and m0 = 1 The LSB (m0) of the modulation register is used first.
+ baud rate BRCLK Data bit D0 Error [%] + baud rate BRCLK
Start bit Error [%]
) 6) ) (0 [2x(1 ) 6) ) (1
[2x(1
) 0 -0)]-1 UBR ) 1)]-1-1
UBR
+ 2.54% 100% + 5.08%
100% 12-29
USART Peripheral Interface, UART Mode
Baud Rate Considerations
+ Data bit D2 Error [%] + Data bit D3 Error [%] + Data bit D4 Error [%] + Data bit D5 Error [%] + Data bit D6 Error [%] + Data bit D7 Error [%] + Parity bit Error [%] + Stop bit 1 Error [%] + Stop bit 2 Error [%] +
Data bit D1 Error [%]
baud rate BRCLK baud rate BRCLK baud rate BRCLK baud rate BRCLK baud rate BRCLK baud rate BRCLK baud rate BRCLK baud rate BRCLK baud rate BRCLK baud rate BRCLK
) 6) ) (2 [2x(1 ) 6) ) (3 [2x(1 ) 6) ) (4 [2x(1 ) 6) ) (5 [2x(1 ) 6) ) (6 [2x(1 ) 6) ) (7 [2x(1 ) 6) ) (8 [2x(1 ) 6) ) (9 [2x(1 ) 6) ) (10 [2x(1 ) 6) ) (11
[2x(1
) 1)]-1-2 UBR ) 2)]-1-3 UBR ) 2)]-1-4 UBR ) 3)]-1-5 UBR ) 4)]-1-6 UBR ) 4)]-1-7 UBR ) 5)]-1-8 UBR ) 6)]-1-9 UBR ) 6)]-1-10 UBR ) 7)]-1-11
UBR
+ 0.29% 100% + 2.83% 100% + -1.95% 100% + 0.59% 100% + 3.13% 100% + -1.66% 100% + 0.88% 100% + 3.42% 100% + -1.37% 100% + -1.17%
100%
12-30
Chapter 13
USART Peripheral Interface, SPI Mode
The universal synchronous/asynchronous receive/transmit (USART) serialcommunication peripheral supports two serial modes with one hardware configuration. These modes shift a serial-bit stream in and out of the MSP430 at a programmed rate or at a rate defined by an external clock. The first mode is the universal asynchronous-receive/transmit (UART) communication protocol (discussed in Chapter 12); the second is the serial peripheralinterface (SPI) protocol. Bit SYNC in control register UCTL selects the required mode: SYNC = 0: UART--asynchronous mode selected SYNC = 1: SPI--synchronous mode selected This chapter describes the SPI mode.
Topic
Page
13.1 USART Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.2 USART Peripheral Interface, SPI Mode . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 13.3 Synchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13.4 Interrupt and Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9 13.5 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15
USART Peripheral Interface, SPI Mode
13-1
13.1 USART Peripheral Interface
The USART peripheral interface connects to the CPU as a byte-peripheral module. It connects the MSP430 to the external system environment with three or four external pins. Figure 13-1 shows the USART peripheral-interface module
Figure 13-1. Block Diagram of USART
Receive Status Receive Buffer URXBUF SYNC RXE
Listen 0 1
MM 1 0
SYNC SOMI SYNC 0 STE
Receive Shift Register SSEL1 SSEL0 UCLKI ACLK SMCLK SMCLK 0 1 2 3 Baud-Rate Generator URXD
SYNC
Baud-Rate Register UBR SYNC UCLKS 1 0 UTXD
Baud-Rate Generator
WUT
Transmit Shift Register
SIMO
TXWake
Transmit Buffer UTXBUF
CKPH
SYNC
CKPL UCLK
UCLKI UCLKS
Clock Phase and Polarity
13-2
13.2 USART Peripheral Interface, SPI Mode
The USART peripheral interface is a serial channel that shifts a serial bit stream of 7 or 8 bits in and out of the MSP430. The SPI mode is chosen when control bit SYNC in the USART control register (UCTL) is set.
13.2.1 SPI Mode Features
The features of the SPI mode are:
-
Supports three-pin and four-pin SPI operations via SOMI, SIMO, UCLK, and STE Master or slave mode Separate shift registers for receive (URXBUF) and transmit (UTXBUF) Double buffers for receiving and transmitting Has clock-polarity and clock-phase control Has clock-frequency control in master mode Supports a character length of seven or eight bits per character
Figure 13-2 shows the USART module in SPI mode.
Figure 13-2. Block Diagram of USART--SPI Mode
SYNC = 1 Receive Status Receive Buffer URXBUF Listen 0 1 SSEL1 SSEL0 UCLKI ACLK SMCLK SMCLK 0 1 2 3 Baud-Rate Generator SYNC STE Baud-Rate Register SYNC UCLKS MSB First 1 0 Transmit Buffer UTXBUF CKPH SYNC CKPL UCLK Clock Phase and Polarity SIMO MM 1 0 SOMI
Receive Shift Register
MSB First
Baud-Rate Generator
Transmit Shift Register
(UCLKI) UCLKS
USART Peripheral Interface, SPI Mode
13-3
Synchronous Operation
13.3 Synchronous Operation
In USART synchronous mode, data and clock signals transmit and receive serial data. The master supplies the clock and data. The slaves use this clock to shift serial information in and out. The four-pin SPI mode also uses a control line to enable a slave to receive and transmit data. The line is controlled by the master. Three or four signals are used for data exchange:
-
SIMO
Slave in, master out The direction is defined by SIMODIR (SIMODIR=0, input direction) SIMODIR = [SYNC .and. MM .and. (STC .or. STE)] Output direction is selected when SPI + Master Mode is selected. When 4-pin SPI is selected (STC=0) input direction is forced by a low level on external STE pin. Slave out, master in The direction is defined by SOMIDIR (SIMODIR=0 input direction) SOMIDIR = [SYNC .and. .not.(MM)] .or. [STC .or. .not.(STE)] Output direction is selected when SPI + Slave Mode is selected. When 4-pin SPI is selected (STC=0) input direction is forced by a low level on external STE pin. USART clock. The master drives this signal and the slave uses it to receive and transmit data. The direction is defined by UCLKDIR (UCLKDIR=0 input direction) UCLKDIR = [SYNC .and. MM .and. (STC .or. STE)] Output direction is selected when SPI + Master Mode is selected. When 4-pin SPI is selected (STC=0) input direction is forced by a low level on external STE pin. Slave transmit enable. Used in four-pin mode to control more than one slave in a multiple master and slave system.
-
SOMI
-
UCLK
-
STE
The interconnection of the USART in synchronous mode to another device's serial port with one common transmit/receive shift register is shown in Figure 13-3, where MSP430 is master or slave. The operation of both devices is identical.
13-4
Synchronous Operation
Figure 13-3. MSP430 USART as Master, External Device With SPI as Slave
MASTER SIMO SIMO SLAVE
Receive Buffer URXBUF
Transmit Buffer UTXBUF Px.x STE STE SS Port.x SOMI
SPI Receive Buffer
Receive Shift Register MSB LSB
Transmit Shift Register MSB LSB
SOMI
Data Shift Register (DSR) MSB LSB COMMON SPI
UCLK MSP430 USART
SCLK
The master initiates the transfer by sending the UCLK signal. For the master, data is shifted out of the transmit shift register on one clock edge, and shifted into the receive shift register on the opposite edge. For the slave, the data shifting operation is the same and uses one common register for transmitting and receiving data. Master and slave send and receive data at the same time. Whether the data is meaningful or dummy data depends on the application software:
-
Master sends data and slave sends dummy data Master sends data and slave sends data Master sends dummy data and slave sends data
Figures 13-4 and 13-5 show an example of a serial synchronous data transfer for a character length of seven bits. The initial content of the receive shift register is 00. The following events occur in order: A) Slave writes 98h to the data shift register (DSR) and waits for the master to shift data out. B) Master writes B0h to UTXBUF, which is immediately transferred to the transmit shift register, and starts the transmission. C) First character is finished and sets the interrupt flags. D) Slave reads 58h from the receive buffer (right justified). E) Slave writes 54h to the DSR and waits for the master to shift out data. F) Master reads 4Ch from the receive buffer URXBUF (right justified). G) Master writes E8h to the transmit buffer UTXBUF and starts the transmission. Note: If USART is in slave mode, no UCLK is needed after D), until G). However, in master mode, two clocks are used internally (not on UCLK signal) to end transmit/receive of first character and prepare the transmit/receive of the next character.
USART Peripheral Interface, SPI Mode
13-5
Synchronous Operation
H) Second character is finished and sets the interrupt flag. I) Master receives 2Ah and slave receives 74h (right justified).
Figure 13-4. Serial Synchronous Data Transfer
CKPL = 0 CKPLH= 0 CKPL = 1 CKPLH= 0 SIMO From Master SOMI From Slave STE Master Interrupt UTXIFG Slave Interrupt URXIFG Shift Data Out Shift Data In AB 7 6 5 4 3 2 CD EF G 1 7 6 5 4 3 2 HI 1
Figure 13-5. Data Transfer Cycle
MSB A: 98h> DSR LSB S B: B0h> UTXBUF MSB LSB M 10011000 10110000
C,F: URXBUF
01001100 M
C,D: DSR
01011000
S
from Initial State E: 54h> DSR 01010100 S G:E8h> UTXBUF 11101000 M
H,I: URXBUF
00101010
M
H,I: DSR
01110100
S
In 7 bit mode, the MSB of RXBUF is always read as 0. S: Slave M: Master
13-6
Synchronous Operation
Figure 13-6 illustrates the USART module functioning as a slave in a three or four-pin SPI configuration.
Figure 13-6. MSP430 USART as Slave in Three-Pin or Four-Pin Configuration
MASTER SIMO SIMO SLAVE
SPI Receive Buffer Px.x STE STE SS Port.x SOMI
Transmit Buffer UTXBUF
Receive Buffer URXBUF
Data Shift Register DSR MSB LSB
SOMI
Transmit Shift Register MSB LSB
Receive Shift Register MSB LSB
SCLK COMMON SPI
UCLK MSP430 USART
13.3.1 Master SPI Mode
The master mode is selected when the master-mode bit (MM) in control register UCTL is set. The USART module controls the serial-communication network by providing UCLK at the UCLK pin. Data is output on the SIMO pin during the first UCLK period and latched from the SOMI pin in the middle of the corresponding UCLK period. The data written to the transmit buffer (UTXBUF) is moved to the transmit shift register as soon as the shift register is empty. This initiates the data transfer on the SIMO pin starting with the most-significant bit. At the same time, received data is shifted into the receive shift register and, upon receiving the selected number of bits, the data is transferred to the receive buffer (URXBUF) setting the receive interrupt flag (URXIFG). Data is shifted into the receive shift register starting with the most-significant bit. It is stored and right-justified in the receive buffer (URXBUF). When previous data is not read from the receive buffer (URXBUF), the overrun error bit (OE) is set. Note: USART Synchronous Master Mode, Receive Initiation The master writes data to the transmit buffer UTXBUF to receive a character. The receive starts when the transmit shift register is empty and the data is transferred to it. Receive and transmit operations always take place together, at opposite clock edges. The protocol can be controlled using the transmit-interrupt flag UTXIFG, or the receive-interrupt flag URXIFG. By using UTXIFG immediately after sending the shift-register data to the slave, the buffer data is transferred to the shift register and the transmission starts. The slave receive timing should ensure that there is a timely pick-up of the data. The URXIFG flag indicates when the data shifts out and in completely. The master can use URXIFG to ensure that the slave is ready to correctly receive the next data.
USART Peripheral Interface, SPI Mode
13-7
Synchronous Operation
13.3.1.1 Four-Pin SPI Master Mode
The signal on STE is used by the active master to prevent bus conflicts with another master. The STE pin is an input when the corresponding PnSEL bit (in the I/O registers) selects the module function. The master operates normally while the STE signal is high. Whenever the STE signal is low, for example, when another device makes a request to become master, the actual master reacts such that:
-
The pins that drive the SPI bus lines SIMO and UCLK are set to inputs. The error bit FE and the interrupt flag URXIFG in register URCTL are set.
The bus conflict is then removed: SIMO and UCLK do not drive the bus lines, and the error flag indicates the system integrity violation to the software. Pins SIMO and UCLK are forced to the input state while STE is in a low state, and they return to the conditions defined by the corresponding control bits when STE returns to a high state. In the three-pin mode, the STE input signal is not relevant.
13.3.2 Slave SPI Mode
The slave mode is selected when bit MM of the control register is reset and synchronous mode is selected. The UCLK pin is used as the input for the serial-shift clock supplied by an external master. The data-transfer rate is determined by this clock and not by the internal bit-rate generator. The data, loaded into the transmit shift register through the transmit buffer (UTXBUF) before the start of UCLK, is transmitted on the SOMI pin using the UCLK supplied from the master. Simultaneously, the serial data applied to the SIMO pin are shifted into the receive shift register on the opposite edge of the clock. The receive-interrupt flag URXIFG indicates when the data is received and transferred into the receive buffer. The overrun-error bit is set when the previously-received data is not read before the new data is written to the receive buffer.
13.3.2.1 Four-Pin SPI Slave Mode
In the four-pin SPI mode, the STE signal is used by the slave to enable the transmit and receive operations. It is applied from the SPI master. The receive and transmit operations are disabled when the STE signal is high, and enabled when it is low. Whenever the STE signal becomes high, any receive operation in progress is halted and then continues when the STE signal is low again. The STE signal enables one slave to access the data lines. The SOMI is input if STE is set high.
13-8
Interrupt and Control Functions
13.4 Interrupt and Control Functions
The USART peripheral interface serves two main interrupt sources for transmission and reception. Two interrupt vectors serve receive and transmit interrupt events. The interrupt control bits and flags and enable bits of the USART peripheral interface are located in the SFR address range. The bit functions are described below in Table 13-1. See the peripheral-file map in Appendix A for the exact bit locations.
Table 13-1.USART Interrupt Control and Enable Bits--SPI Mode
Receive interrupt flag Receive interrupt enable Receive/transmit enable (see Note) Transmit interrupt flag Transmit interrupt enable
Note:
URXIFG URXIE USPIE UTXIFG UTXIE
Initial state reset (by PUC/SWRST) Initial state reset (by PUC/SWRST) Initial state reset (by PUC) Initial state set (by PUC/SWRST) Initial state reset (by PUC/SWRST)
Different for UART mode, see Chapter 12.
The USART receiver and transmitter operate in parallel and use the same baud-rate generator in synchronous master mode. In synchronous slave mode, the external clock applied to UCLK is used for the receiver and the transmitter. The receiver and transmitter are enabled and disabled together with the USPIE bit.
13.4.1 USART Receive/Transmit Enable Bit, Receive Operation
The receive/transmit enable bit (USPIE) enables or disables collection of the bit stream on the URXD/SOMI data line. Disabling the USART receiver (USPIE = 0) stops the receive operation after completion, or stops a pending operation if no receive operation is active. In synchronous mode, UCLK does not shift any data into the receiver shift register.
13.4.1.1 Receive/Transmit Enable Bit--MSP430 as Master
The receive operation functions identically for three-pin and four-pin modes, as shown in Figure 13-7, when the MSP430 USART is selected to be the SPI master.
USART Peripheral Interface, SPI Mode
13-9
Interrupt and Control Functions
Figure 13-7. State Diagram of Receiver Enable Operation--MSP430 as Master
USPIE = 0 No Data Written to UTXBUF Not Completed
USPIE = 1 Receive Disable USPIE = 0 SWRST PUC
Idle State (Receiver Enabled)
USPIE = 1
Receiver Collects Character
Handle Interrupt Conditions Character Received
USPIE = 1 USPIE = 0
13.4.1.2 Receive/Transmit Enable Bit--MSP430 as Slave, Three-Pin Mode
The receive operation functions differently for three-pin and four-pin modes when the MSP430 USART module is selected to be the SPI slave. In the three-pin mode, shown in Figure 13-8, no external SPI receive-control signal stops an active receive operation. A PUC signal, a software reset (SWRST), or a receive/transmit enable (USPIE) signal can stop a receive operation and reset the USART.
Figure 13-8. State Diagram of Receive/Transmit Enable--MSP430 as Slave, Three-Pin Mode
USPIE = 0 No Clock at UCLK Not Completed
USPIE = 1 Receive Disable USPIE = 0 SWRST PUC
Idle State (Receive Enabled)
USPIE = 1 External Clock Present USPIE = 1
Receiver Collects Character
Handle Interrupt Conditions Character Received
USPIE = 0
Note: USPIE Re-enabled, SPI Mode After the receiver is completely disabled, a reenabling of the receiver is asynchronous to any data stream on the communication line. Synchronization to the data stream is handled by the software protocol in three-pin SPI mode.
13.4.1.3 Receive/Transmit Enable Bit--MSP430 as Slave, Four-Pin Mode
In the four-pin mode, shown in Figure 13-9, the external SPI receive-control signal applied to pin STE stops a started receive operation. A PUC signal, a software reset (SWRST), or a receive/transmit enable (USPIE) can stop a receive operation and reset the operation-control state machine. Whenever the STE signal is set to high, the receive operation is halted.
13-10
Interrupt and Control Functions
Figure 13-9. State Diagram of Receive Enable--MSP430 as Slave, Four-Pin Mode
USPIE = 0 USPIE = 1 and STE = 0 Receive Disable USPIE = 0 SWRST PUC USPIE = 0 No Clock at UCLK Not Completed USPIE = 1 Receiver Collects Character
Idle State (Receive Enabled)
USPIE = 1 External Clock Present USPIE = 1
Handle Interrupt Conditions Character Received
13.4.2 USART Receive/Transmit Enable Bit, Transmit Operation
The receive/transmit enable bit USPIE, shown in Figures 13-10 and 13-11, enables or disables the shifting of a character on the serial data line. If this bit is reset, the transmitter is disabled, but any active transmission does not halt until all data previously written to the transmit buffer is transmitted. If the transmission is completed, any further write operation to the transmitter buffer does not transmit. When the UTXBUF is ready, any pending request for transmission remains, which results in an immediate start of transmission when USPIE is set and the transmitter is empty. A low state on the STE signal removes the active master (four-pin mode) from the bus. It also indicates that another master is requesting the active-master function.
13.4.2.1 Receive/Transmit Enable--MSP430 as Master
Figure 13-10 shows the transmit-enable activity when the MSP430 is master.
Figure 13-10. State Diagram of Transmit Enable--MSP430 as Master
USPIE = 0 No Data Written to Transfer Buffer Not Completed USPIE = 1
USPIE = 1 Transmit Disable USPIE = 0 SWRST PUC
USPIE = 1, Data Written to Idle State Transmit Buffer Transmission (Transmitter Active Enabled) USPIE = 1
Handle Interrupt Conditions Character Transmitted
USPIE = 0 And Last Buffer Entry Is Transmitted
USART Peripheral Interface, SPI Mode
13-11
Interrupt and Control Functions
13.4.2.2 Receive/Transmit Enable, MSP430 is Slave
Figure 13-11 shows the receive/transmit-enable-bit activity when the MSP430 is slave.
Figure 13-11.State Diagram of Transmit Enable--MSP430 as Slave
USPIE = 0 No Clock at UCLK Not Completed USPIE = 1
USPIE = 1 Transmit Disable USPIE = 0 SWRST
Idle State (Transmitter Enabled)
Transmission Active External Clock Present USPIE = 1
USPIE = 1
Handle Interrupt Conditions Character Transmitted
PUC
USPIE = 0
When USPIE is reset, any data can be written regularly into the transmit buffer, but no transmission is started. Once the USPIE bit is set, the data in the transmit buffer are immediately loaded into the transmit shift register and character transmission is started. Note: Writing to UTXBUF, SPI Mode Data should never be written to transmit buffer UTXBUF when the buffer is not ready (UTXIFG = 0) and the transmitter is enabled (USPIE is set). If data is written, character shifting can be random.
Note: Write to UTXBUF/Reset of Transmitter, SPI Mode Disabling of the transmitter should be done only if all data to be transmitted have been moved to the transmit shift register.
MOV.B BIC.B #....,&UTXBUF #USPIE,&ME2 ; ; ; ; ; If BITCLK < MCLK then the transmitter might be stopped before the buffer is loaded into the transmitter shift register
13-12
Interrupt and Control Functions
13.4.3 USART Receive-Interrupt Operation
In the receive-interrupt operation shown in Figure 13-12, the receive-interrupt flag URXIFG is set each time a character is received and loaded into the receive buffer.
Figure 13-12. Receive Interrupt Operation
SYNC Valid Start Bit Receiver Collects Character URXSE From URXD URXS SYNC = 1
Clear URXIE
PE FE BRK URXEIE URXWIE RXWake
SYNC (S) URXIFG Clear Character Received or Master Overrun
Request_ Interrupt_Service
SWRST PUC URXBUF Read USPIE IRQA
URXIFG is reset by a system reset PUC signal, or by a software reset (SWRST). URXIFG is reset automatically if the interrupt is served or the receive buffer URXBUF is read. The receive interrupt enable bit (USPIE), if set, enables a CPU interrupt request as shown in Figure 13-13. The receive interrupt flag bits URXIFG and USPIE are reset with a PUC signal or a SWRST.
Figure 13-13. Receive Interrupt State Diagram
Wait For Next Start USPIE = 1 Receive Character Completed URXIFG = 0 SWRST = 1 PUC USPIE = 0 USPIE = 1 and GIE = 1 and Priority Valid Interrupt Service Started, GIE = 0 URXIFG = 0
URXIFG = 1
Priority Too GIE = 0 Low
USART Peripheral Interface, SPI Mode
13-13
Interrupt and Control Functions
13.4.4 Transmit-Interrupt Operation
In the transmit-interrupt operation shown in Figure 13-14, the transmitinterrupt flag UTXIFG is set by the transmitter to indicate that the transmitter buffer UTXBUF is ready to accept another character. This bit is automatically reset if the interrupt-request service is started or a character is written to the UTXBUF. This flag activates a transmitter interrupt if bits USPIE and GIE are set. The UTXIFG is set after a system reset PUC signal, or removal of SWRST.
Figure 13-14. Transmit-Interrupt Operation
Q USPIE SYNC = 1
Clear PUC or SWRST Set UTXIFG DQ SWRST Clear UTXBUF Written Into Transmit Shift Register IRQA Request_ Interrupt_Service
VCC Character Moved From Buffer to Shift Register
The transmit-interrupt enable bit UTXIE controls the ability of the UTXIFG to request an interrupt, but does not prevent the UTXIFG flag from being set. The USPIE is reset with a PUC signal or a SWRST. The UTXIFG bit is set after a system reset PUC signal or a SWRST, but the USPIE bit is reset to ensure full interrupt-control capability.
13-14
Control and Status Registers
13.5 Control and Status Registers
The USART registers, shown in Tables 13-2 and 13-3, are byte structured and should be accessed using byte instructions.
Table 13-2.USART0 Control and Status Registers
Register USART control Transmit control Receive control Modulation control Baud rate 0 Baud rate 1 Receive buffer Transmit buffer Short Form UCTL0 UTCTL0 URCTL0 UMCTL0 UBR00 UBR10 Register Type Read/write Read/write Read/write Read/write Read/write Read/write Address 070h 071h 072h 073h 074h 075h 076h 077h Initial State See Section 13.5.1 See Section 13.5.2 See Section 13.5.3 Unchanged Unchanged Unchanged Unchanged Unchanged
URXBUF0 Read/write UTXBUF0 Read
Table 13-3.USART1 Control and Status Registers
Register USART control Transmit control Receive control Modulation control Baud rate 0 Baud rate 1 Receive buffer Transmit buffer Short Form UCTL1 UTCTL1 URCTL1 UMCTL1 UBR01 UBR11 Register Type Read/write Read/write Read/write Read/write Read/write Read/write Address 078h 079h 07Ah 07Bh 07Ch 07Dh 07Eh 07Fh Initial State See Section 13.5.1 See Section 13.5.2 See Section 13.5.3 Unchanged Unchanged Unchanged Unchanged Unchanged
URXBUF1 Read/write UTXBUF1 Read
All bits are random following the PUC signal, unless otherwise noted by the detailed functional description. Reset of the USART module is performed by the PUC signal or a SWRST. After a PUC signal, the SWRST bit remains set and the USART module remains in the reset condition. It is disabled by resetting the SWRST bit. The SPI mode is disabled after the PUC signal. The USART module operates in asynchronous or synchronous mode as defined by the SYNC bit. The bits in the control registers can have different functions in the two modes. All bits are described with their function in the synchronous mode--SYNC = 1. Their function in the asynchronous mode is described in Chapter 12.
USART Peripheral Interface, SPI Mode
13-15
Control and Status Registers
13.5.1 USART Control Register
The information stored in the control register, shown in Figure 13-15, determines the basic operation of the USART module. The register bits select the communication mode and the number of bits per character. All bits should be programmed to the desired mode before resetting the SWRST bit.
Figure 13-15. USART Control Register
7 UCTL0, 070h UCTL1, 078h
Unused Unused Unused CHAR Listen SYNC MM
0
SWRST
rw-0
rw-0
rw-0
rw-0 rw-0
rw-0
rw-0
rw-1
Bit 0:
The USART state machines and operating flags are initialized to the reset condition (URXIFG=USPIE=0, UTXIFG=1) if the software reset bit is set. Until the SWRST bit is reset, all affected logic is held in the reset state. This implies that after a system reset the USART must be reenabled by resetting this bit. Master mode is selected when the MM bit is set. The USART module slave mode is selected when the MM bit is reset. Peripheral module mode select The SYNC bit sets the function of the USART peripheralinterface module. Some of the USART control bits have different functions in UART and SPI modes. SYNC = 0: UART function is selected SYNC = 1: SPI function is selected The listen bit determines the transmitted data to feed back internally to the receiver. This is commonly called loopback mode. Character length This register bit sets the length of the character to be transmitted as either seven or eight bits. CHAR = 0: 7-bit data CHAR = 1: 8-bit data Unused Unused Unused
Bit 1: Bit 2:
Bit 3:
Bit 4:
Bit 5: Bit 6: Bit 7:
13.5.2 Transmit Control Register UTCTL
The transmit control register (UTCTL), shown in Figure 13-16, controls the USART hardware associated with transmitter operations.
Figure 13-16. Transmit Control Register UTCTL
7 UTCTL0, 071h UTCTL1, 079h
CKPH CKPL SSEL1 SSEL0 Unused Unused STC
0
TXEPT
rw-0
rw-0
rw-0
rw-0 rw-0
rw-0
rw-0
rw-1
13-16
Control and Status Registers
Bit 0:
Master mode: The transmitter-empty flag TXEPT is set when the transmitter shift register and UTXBUF are empty, and reset when data are written to UTXBUF. It is set again by a SWRST. Slave mode: The transmitter-empty flag TXEPT is not set when the transmitter shift register and UTXBUF are empty.
Bit 1:
The slave transmit-control bit STC selects if the STE pin is used for master and slave mode: STC = 0: The four-pin mode of SPI is selected. The STE signal is used by the master to avoid bus conflicts, or is used in slave mode to control transmit and receive enable. STC = 1: The three-pin SPI mode is selected. STE is not used in master or slave mode. Unused Unused Source select 0 and 1 The source-select bits define which clock source is used for baud-rate generation only when master mode is selected: SSEL1,SSEL0 0 External clock UCLK selected 1 Auxiliary clock ACLK selected 2, 3 SMCLK selected In master mode (MM = 1), an external clock at UCLK cannot be selected since the master supplies the UCLK signal for any slave. In slave mode, bits SSEL1 and SSEL0 are not relevant. The external clock UCLK is always used.
Bit 2: Bit 3: Bits 4, 5:
Bits 6, 7:
Clock polarity CKPL and clock phase CKPH The CKPL bit controls the polarity of the SPICLK signal. CKPL = 0: The inactive level is low; data is output with the rising edge of UCLK; input data is latched with the falling edge of UCLK. CKPL = 1: The inactive level is high; data is output with the falling edge of UCLK; input data is latched with the rising edge of SPICLK. The CKPH bit controls the polarity of the SPICLK signal as shown in Figure 13-17. CKPH = 0: Normal UCLK clocking scheme CKPH = 1: UCLK is delayed by one half cycle
USART Peripheral Interface, SPI Mode
13-17
Control and Status Registers
Figure 13-17. USART Clock Phase and Polarity
CKPL CKPH 0 0 0 1 1 0 1 1 x x Cycle# UCLK UCLK UCLK UCLK LSB LSB 1 2 3 4 5 6 7 8
SIMO/ MSB 0 SOMI * SIMO/ 1 SOMI * MSB Data to TXBUF Receive Sample Points
*Previous Data Bit
When operating with the CKPH bit set, the USART (synchronous mode) makes the first bit of data available after the transmit shift register is loaded and before the first edge of the UCLK. In this mode, data is latched on the first edge of UCLK and transmitted on the second edge.
13.5.3 Receive Control Register URCTL
The receive control register (URCTL), shown in Figure 13-18, controls the USART hardware associated with the receiver operation and holds error conditions.
Figure 13-18. Receive Control Register URCTL
7 URCTL0, 072h URCTL1, 07Ah
FE Undef. OE Undef. Unused Unused Undef.
0
Undef.
rw-0
rw-0
rw-0 rw-0
rw-0
rw-0
rw-0 rw-0
Bit 0: Bit 1: Bit 2: Bit 3: Bit 4: Bit 5:
Undefined, driven by USART hardware Undefined, driven by USART hardware Unused Unused Undefined, driven by USART hardware The overrun-error-flag bit (OE) is set when a character is transferred to URXBUF before the previous character is read. The previous character is overwritten and lost. OE is reset by a SWRST, a system reset, by reading the URXBUF, or by an instruction. Undefined, driven by USART hardware Frame error. The FE bit is set when four-pin mode is selected and a bus conflict stops an active master by applying a negative
Bit 6: Bit 7:
13-18
Control and Status Registers
transition signal to pin STE. FE is reset by a SWRST, a system reset, by reading the URXBUF, or by an instruction.
13.5.4 Baud-Rate Select and Modulation Control Registers
The baud-rate generator uses the content of baud-rate select registers UBR1 and UBR0, shown in Figure 13-19, to generate the serial-data-stream bit timing. The smallest division factor is two.
Figure 13-19. USART Baud-Rate Select Register
7 UBR00, 074h UBR01, 07Ch
27 rw 26 rw 25 rw 24 rw 23 rw 22 rw 21 rw
0
20 rw
7 UBR10, 075h UBR11, 07Dh
215 rw 214 rw 213 rw 212 rw 211 rw 210 rw 29 rw
0
28 rw
Baud rate =
BRCLK UBR
)
1 n
Smi i
n
with UBR= [UBR1,UBR0]
The maximum baud rate that can be selected for transmission in master mode is half of the clock-input frequency of the baud-rate generator. In slave mode, the rate is determined by the external clock applied to UCLK. The modulation control register, shown in Figure 13-20, is not used for serial synchronous communication. It is best kept in reset mode (bits m0 to m7 = 0).
Figure 13-20. USART Modulation Control Register
7 UMCTL0, 073h UMCTL1, 07Bh
m7 m6 m5 m4 m3 m2 m1
0
m0
rw
rw
rw
rw
rw
rw
rw
rw
13.5.5 Receive Data Buffer URXBUF
The receive data buffer (URXBUF), shown in Figure 13-21, contains previous data from the receiver shift register. URXBUF is cleared with a SWRST or a PUC signal. Reading URXBUF resets the receive-error bits and the receiveinterrupt flag URXIFG.
Figure 13-21. Receive Data Buffer URXBUF
7 URXBUF0, 076h URXBUF1, 07Eh
27 rw 26 rw 25 rw 24 rw 23 rw 22 rw 21 rw
0
20 rw
The MSB of the URXBUF is always reset in seven-bit-length mode.
USART Peripheral Interface, SPI Mode
13-19
Control and Status Registers
13.5.6 Transmit Data Buffer UTXBUF
The transmit data buffer (UTXBUF), shown in Figure 13-22, contains current data for the transmitter to transmit.
Figure 13-22. Transmit Data Buffer UTXBUF
7 UTXBUF0, 077h UTXBUF1, 07Fh
27 rw 26 rw 25 rw 24 rw 23 rw 22 rw 21 rw
0
20 rw
The UTXIFG bit indicates that UTXBUF is ready to accept another character for transmission. In master mode, the transmission is initialized by writing data to UTXBUF. The transmission of this data is started immediately if the transmit shift register is empty. When seven-bit character-length is used, the data moved into the transmit buffer must be left-justified since the MSB is shifted out first.
13-20
Chapter 14
Comparator_A
The Comparator_A peripheral module is used to compare analog signals to support various forms of analog-to-digital conversion. The Comparator_A module includes:
-
Comparator with on/off capability and no input hysteresis Internal analog voltage reference generator Internal reference levels available externally Input multiplexer to exchange the comparator terminals Software-selectable RC-filter at the comparator output One interrupt vector
The Comparator_A is implemented in MSP430x11x1, MSP430x13x, and MSP430x14x devices.
Topic
Page
14.1 Comparator_A Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 14.2 Comparator_A Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 14.3 Comparator_A Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6 14.4 Comparator_A in Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9
Comparator_A
14-1
Comparator_A Overview
14.1 Comparator_A Overview
The primary function of the comparator module is to support precision A/D slope-conversion applications, battery-voltage supervision, and monitoring of external analog signals. The comparator is controlled via twelve control bits in registers CACTL1 and CACTL2.
Figure 14-1. Schematic of Comparator_A
0 V VCC P2CA0 0 CA0 1 1 0 CA1 1 1 0V 0 V VCC P2CA1 0 1 CAON 0V 2.0 s Set CAIFG Flag CA1 + _ 0 0 1 CA0 CAEX 0 1 CAON CAF
0
Low Pass Filter 0 1
CAOUT to Internal Module
CAOUT to External Pin
3
2
1
0 CAREF
CARSEL 1 0 VCAREF
0 2 1 3
0.5 x VCC
0.25 x VCC
0V
0V
The input and output pins of Comparator_A are often multiplexed with other pin functions on the MSP430. Additionally, the internal connections to Comparator_A can differ among MSP430 devices. The data sheet of a desired device should always be consulted to determine the specific connection implementations.
14-2
Comparator_A Description
14.2 Comparator_A Description
The comparator_A peripheral module is comprised of several major blocks. These blocks are described in this section.
14.2.1 Input Analog Switches
The input analog switches connect or disconnect the comparator input terminals to associated port pins using the P2CA0 and P2CA1 control bits. Both terminal inputs can be controlled individually. P2CA0 and P2CA1 allow:
-
Application of an external signal to the + and - terminals of the comparator, or Routing of an internal reference voltage (if applied) to a comparator-input terminal as an output on an associated port pin. In this way, the internal reference voltage can be used to bias external circuitry.
Internally, the input switch is constructed as a T-switch to suppress distortion in the signal path. When a comparator terminal is not connected to an external pin, it should be connected to an internal reference-voltage level. Note: Ensure that the comparator input terminals are connected to signal, power, or ground level. Otherwise, floating levels may cause unexpected interrupts and current consumption may increase.
14.2.2 Input Multiplexer
Control bit CAEX controls the input multiplexer to select which input signals are connected to the comparator's + and - terminals. Additionally, when the comparator terminals are exchanged, the output signal from the comparator is inverted. This allows the user to determine or compensate for the comparator offset.
14.2.3 The Comparator
The comparator compares the analog voltages at the + and - input terminals. If the + terminal is more positive than the - terminal, the comparator output will be high (note that the value of signal CAOUT also depends on the value of CAEX). The comparator can be switched on or off using control bit CAON. The comparator should be switched off when not in use to stop its current consumption. When the comparator is switched off, the output is low (note that the value of CAOUT still depends on the value of CAEX, even when the comparator is off).
14.2.4 The Output Filter
The output of the comparator can be used with or without internal filtering. When control bit CAF is set, the output is filtered with an-chip RC-filter. The filter is bypassed when CAF is reset.
Comparator_A
14-3
Comparator_A Description
A comparator output will oscillate if the voltage difference across the input terminals is small. Internal and external parasitic effects and cross coupling on and between signal lines, power-supply lines, and other parts of the system are responsible for this behavior (see Figure 14-2). The comparator output oscillation reduces accuracy and resolution of the comparison result. Selecting the output filter can reduce errors associated with comparator oscillation.
Figure 14-2. RC-Filter Response at the Output of the Comparator
+ Terminal - Terminal Comparator Inputs Comparator Output Unfiltered at CAOUT Comparator Output Filtered at CAOUT
14.2.5 The Voltage Reference Generator
The voltage reference generator is used to generate VCAREF. VCAREF can be applied to either of the comparator input terminals. Control bits CAREF0 and CAREF1 control the output of the voltage generator. Control bit CARSEL selects the comparator terminal to which VCAREF is applied. If external signals are applied to the comparator input terminals, the internal reference generator should be shut off to reduce current consumption. The divider in the voltage reference generator can generate a fraction of the device's VCC, or a fixed transistor-threshold voltage. This threshold voltage tolerance is specified in the specific device's data sheet. Ratiometric measurement principles that compare unknown values, such as resistive or capacitive sensors, with a known value such as a precision resistor or capacitor, can use an internal reference and achieve accurate results without an absolute VCC. VCC needs to be stable, but not necessarily known. The accuracy of ratiometric measurements is determined by the accuracy of the known resistor or capacitor value. Absolute measurement principles require a stable VCC to ensure that the voltage reference generated produces accurate reference-voltage levels.
14-4
Comparator_A Description
14.2.6 Comparator_A Interrupt Circuitry
One interrupt and one interrupt vector are associated with the Comparator_A (see Figure 14-3). The interrupt flag CAIFG is set on either the rising or falling edge of the comparator output. The interrupt edge-select bit, CAIES, determines which edge of the output signal sets the CAIFG flag. The interrupt-enable bit, CAIE, along with the general interrupt-enable bit (GIE) control if the CAIFG bit generates a CPU interrupt. If both the CAIE and the GIE bits are set, then the CAIFG flag will generate a CPU interrupt request. The CAIFG flag is automatically reset when the CPU interrupt request is serviced. The CAIFG, CAIES, and CAIE bits are all located in the CACTL1 register.
Figure 14-3. Comparator_A Interrupt System
CAF 0 CCI1B CAOUT Set CAIFG VCC CAIES 0 Reset POR IRACC, Interrupt Request Accepted D Set Q IRQ, Interrupt Service Request CAIE
1
2 s
1
Comparator_A
14-5
Comparator_A Control Registers
14.3 Comparator_A Control Registers
The Comparator_A module is configured with three module registers as shown in Table 14-1. The module registers are mapped into the lower peripheral file address range where all byte modules are located and should be accessed with byte instructions (suffix B).
Table 14-1.Comparator_A Control Registers
Register * C_A control register 1: * C_A control register 2: Short Form CACTL1 CACTL2 Register Type Read/write Read/write Read/write Address 059h 05Ah 05Bh Initial State Reset Reset Reset
* C_A port dissipation reg: CAPD
14.3.1 Comparator_A, Control Register CACTL1
The control register CACTL1 is shown and described below.
7 CACTL1 059h CAEX rw-(0) CA RSEL rw-(0) CA REF1 rw-(0) CA REF0 rw-(0) CAON rw-(0) CAIES rw-(0) CAIE rw-(0) 0 CAIFG rw-(0)
CAIFG, bit0: CAIE, bit1: CAIES, bit2:
The Comparator_A interrupt flag The Comparator_A interrupt enable The Comparator_A interrupt edge select bit 0: The rising edge of the comparator output sets the Comparator_A interrupt flag CAIFG 1: The falling edge of the comparator output sets the Comparator_A interrupt flag CAIFG The comparator is switched on or off. When off, the current consumption of the comparator is stopped. The current consumption of the reference circuitry is enabled or disabled independently. 0: The comparator is disabled, current consumption is stopped and the output of the comparator is low. 1: The comparator is enabled and active.
CAON, bit3:
CAREF, bit4,5: 0: Internal reference is switched off. An external reference can be applied. 1: 0.25*Vcc reference is selected 2: 0.50*Vcc reference is selected 3: Diode reference is selected. The diode reference varies with each individual device, temperature and supply voltage. See device data sheet.
14-6
Comparator_A Control Registers
CARSEL, bit6:
CAEX, bit7:
The internal reference VCAREF, selected by CAREF bits, is applied to the +terminal or -terminal. 0: Reference is selected to the +terminal (CAEX = 0) or -terminal (CAEX = 1) 1: Reference is selected to the -terminal (CAEX = 0) or +terminal (CAEX = 1) The inputs of the comparator are exchanged. This is used to measure or compensate for the offset of the comparator.
14.3.2 Comparator_A, Control Register CACTL2
The control register CACTL2 is shown and described below.
7 CACTL2 05Ah CACTL 2.7 rw-(0) CACTL 2.6 rw-(0) CACTL 2.5 rw-(0) CACTL 2.4 rw-(0) P2CA1 rw-(0) P2CA0 rw-(0) CAF rw-(0) 0 CAOUT r-(0)
CAOUT, bit0:
The comparator output. Writing to this bit, for example when writing a new register value, has no affect or negative impact. The comparator output filter is bypassed (CAF=0) or switched into the output path (CAF=1). Pin to CA0 0: The external, pin signal is not connected to the Comparator_A 1: The external, pin signal is connected to the Comparator_A Pin to CA1 0: The external, pin signal is not connected to the Comparator_A 1: The external, pin signal is connected to the Comparator_A See device data sheet for implementation.
CAF, bit1: P2CA0, bit2:
P2CA1, bit3:
Bits 4-7:
14.3.3 Comparator_A, Port Disable Register CAPD
Typically, the comparator input and output functions are multiplexed with digital I/O port pins to save pin count on a device. Also, slope A/D applications often utilize multiple digital I/O ports (for charging and discharging) to provide multiple channels of slope A/D conversion. In these multichannel applications, a useful feature of the digital I/O pins is the ability to disable the input buffer. Typically, all channels except the one being converted are disabled, providing a high-impedance input and avoiding current consumption caused by throughput current. (See section 14.4.1) The typical digital I/O ports on MSP430 do not have the ability to disable the input buffer. However, on devices with the Comparator_A, the capability has been added and is controlled with the CAPD.x bits.
Comparator_A
14-7
Comparator_A Control Registers
The control bits CAPD.0 to CAPD.7 are initially reset, enabling all the input buffers for the associated port. The port input buffer is disabled if the according CAPD.x bit is set. See device data sheet for port associations. The ability to disable the input buffer for the device pin applies to up to eight inputs of the associated digital I/O port (check device data sheet for implementation details). For example, the x11x1 devices have CA1 multiplexed on pin P2.4 and CA0 multiplexed on pin P2.3, so the Comparator_A is associated with port P2. On this device, all input buffers associated with all P2 pins (P2.x) may have the capability to be disabled with the CAPD register.
7 CAPD 05Bh 0
CAPD.7 CAPD.6 CAPD.5 CAPD.4 CAPD.3 CAPD.2 CAPD.1 CAPD.0 rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)
CAPD.x:
0: The input buffer for the pin enabled. 1: The input buffer for the pin is disabled.
14-8
Comparator_A in Applications
14.4 Comparator_A in Applications
The Comparator_A can be used to:
-
Measure resistive elements Detect external voltage or current levels Measure external voltage and current sources Measure the voltage of a battery used in the system
14.4.1 Analog Signals at Digital Inputs
Typically, Comparator_A inputs are multiplexed with digital I/O pins. When analog signals are applied to these digital CMOS gates, parasitic current can flow from the positive terminal (VDD, VCC) to the negative terminal (VSS, GND). See Figure 14-4. This parasitic current occurs if the input voltage is around the transition level of the input gate.
Figure 14-4. Transfer Characteristic and Power Dissipation in a CMOS Inverter/Buffer
VCC ICC VI VO VI VSS 0 VCC
Figure 14-5. Transfer Characteristic and Power Dissipation in a CMOS Gate
VCC
VI ICC
VO
ICC
VCC
VI 0 VCC
CAPD.x = 1
VSS
MSP430 devices with the Comparator_A module have additional circuitry on the associated digital I/O port pins to allow the input buffers to be disabled (see Figure 14-5). The buffers are enabled or disabled with the CAPD.x bits (see section 14.3.3). Note that the circuitry is added to all pins of the associated I/O port, not just the pins for the Comparator_A inputs. Disabling the input buffer for a specific pin will disable the parasitic current flow and therefore reduce overall current consumption. It is important to disable the buffer for any I/O pin that is not being actively driven if current consumption is critical (see Figure 14-6).
Comparator_A
14-9
Comparator_A in Applications
Figure 14-6. Application Example With One Active(Driving R3) and Three Passive Pins With Applied Analog Signals
Control1 = 0
R1
CAPD.x = 0 Control2 = 0
R2
CAPD.x = 0 Control3 = 1
R3
CAPD.x = 0 or 1 Control4 = 0
R4 C CAPD.x = 1
The specific implementation (which digital inputs/outputs can be controlled by CAPD.x) varies with each MSP430 device configuration. Refer to the specific device's data sheet to see which I/O port is associated with Comparator_A.
14-10
Comparator_A in Applications
14.4.2 Comparator_A Used to Measure Resistive Elements
The Comparator_A can be used to measure resistive elements. For example, temperature can be converted into digital data via a thermistor, by comparing the thermistor's discharge time to that of a reference resistor. See Figure 14-7.
Figure 14-7. Temperature Measurement Systems
VCC VCC
R(ref) R(meas)
P2CA0 0 0 1
0 V VCC 0 1 CAON CAF 0 0 1 2 s 0 V VCC 0 1 CAON 3210 CAREF e.g. Capture Input of Timer_A CAOUT to External Pin Set CAIFG
CA0 1 0
C
0 CA1 1 P2CA1 1
+ _
1
CARSEL 1 0 VCAREF
0 2 1 3
0.5 x VCC 0.25 x VCC
The resistive elements are compared using a capacitor charge-discharge cycle, as shown in Figure 14-8. This is based on a ratiometric conversion principle, as the ratio of two capacitor-discharge times is compared. Absolute VCC and the actual capacitor value are not critical, as the ratiometric principle cancels these values out. VCC and the capacitor value should simply remain constant during the conversion.
N meas N ref N meas N ref R meas
+
-R meas -R ref
C C
ln ln
V ref VCC
V ref V CC
meas + RR ref
+ Rref
N meas N ref
Comparator_A
14-11
Comparator_A in Applications
Figure 14-8. Timing for Temperature Measurement Systems
VC VCC
0.25 x VCC
Rmeas Rref
Phase I: Charge-Up Phase II: Discharge C tref Phase III: Charge-Up Phase IV: Discharge C tmeas
t
MSP430 resources used to calculate the temperature sensed by R(meas): Digital I/O:
-
Two digital outputs to charge and discharge the capacitor. Port pins are set to provide a VCC output (charge a capacitor), reset to discharge a capacitor, and switched to high-impedance (including correct state of CAPD.x bit) when not in use. One output discharges the capacitor via reference resistor R(ref), the other output discharges it via R(meas).
Comparator_A:
-
The - terminal is connected to a reference level, for example 0.25 x VCC. The + terminal is connected to the positive terminal of the capacitor. CAOUT or CAIFG utilized to measure the discharge time. The output filter should be used to minimize multiple switching when the voltages at the comparator inputs are close together.
If CAOUT is available as an input to a timer-capture register such as Timer_A, the capacitor discharge time can be measured very precisely, without software polling for a change of CAOUT, by using the timer capture function.
R meas
+ Rref
N meas N ref
T meas
+
R meas
14-12
Comparator_A in Applications
14.4.3 Measuring Two Independent Resistive Element Systems
It is possible to measure two independent systems with one comparator. The input multiplexer, which is controlled via CAEX, allows the two independent systems to be isolated. See Figure 14-9. An example could be if one temperature sensor has a resistor range of 10 k to 200 k. The other sensor is in the range of 1 k to 1.5 k. Two independent measurement paths are used to optimize individual measurement performance. The conversion principle is identical to the one described in the previous section.
Figure 14-9. Two Independent Temperature Measurement Systems
VCC VCC
R1(meas)
R1(ref) 0 CA0 1
P2CA0
0 V VCC 0 1
CAEX 0 1 + _ 0 0
CAON
CAF
e.g. Capture Input of Timer_A CAOUT to External Pin
Set CAIFG
C1
0 0 CA11 P2CA1 1
1
1 2 s
VCC
VCC
0 V VCC 0 1 CAON
R2(meas) R2(ref) 3210 CAREF
C2 CARSEL 1 0 VCAREF 0 2 1 3 0.5 x VCC 0.25 x VCC
Comparator_A
14-13
Comparator_A in Applications
In Figure 14-10, the active signal paths are shown when the upper independent system is selected for conversion. This example uses the 0.25xVCC internal reference, and shows the software selectable RC-filter as active.
Figure 14-10. Temperature Measurement Via Temperature Sensor R1(meas)
VCC VCC
R1(meas)
R1(ref) 0 CA0 1
P2CA0
0 V VCC 0 1
CAEX 0 1 + _ 0 0
CAON
CAF
e.g. Capture Input of Timer_A CAOUT to External Pin
Set CAIFG
C1
0 0 CA11 P2CA1 1
1
1 2 s
VCC
VCC
0 V VCC 0 1 CAON
R2(meas) R2(ref) 3210 CAREF
C2
CARSEL 1 0 VCAREF
0 2 1 3
0.5 x VCC 0.25 x VCC
14-14
Comparator_A in Applications
Figure 14-11 shows the active signal paths for the lower independent system. This example uses the 0.25xVCC internal reference and shows the software selectable RC-filter as active.
Figure 14-11.Temperature Measurement Via Temperature Sensor R2(meas)
VCC VCC
R1(meas)
R1(ref) 0 CA0 1
P2CA0
0 V VCC 0 1
CAEX 0 1 + _ 0 0
CAON
CAF
e.g. Capture Input of Timer_A CAOUT to External Pin
Set CAIFG
C1
0 0 1 CA1 P2CA1 1
1
1 2 s
VCC
VCC
0 V VCC 0 1 CAON
R2(meas) R2(ref) 3210 CAREF
C2 CARSEL 1 0 VCAREF 0 2 1 3 0.5 x VCC 0.25 x VCC
Comparator_A
14-15
Comparator_A in Applications
14.4.4 Comparator_A Used to Detect a Current or Voltage Level
Comparator_A can be used to detect current or voltage levels if they are below or above a reference level (shown in Figure 14-12). The reference level can be selected from the internal reference-voltage generator, or by applying an external reference level. Application software can poll the CAOUT bit for the status of the comparator, or use the interrupt flag CAIFG to determine if the level of the current or voltage source has crossed the comparator threshold. In Figure 14-12, two external voltages are compared. Application software can poll the CAOUT bit: CAOUT = 0: V(signal < V(ref) CAOUT = 1: V(signal > V(ref)
Figure 14-12. Detect a Voltage Level Using an External Reference Level
0 V VCC 0 1 CAON CAF 0 0 1 2 s 0 V VCC 0 1 CAON 3210 CAREF e.g. Capture Input of Timer_A CAOUT to External Pin Set CAIFG
P2CA0 0 CA0 1 V Signal Voltage 0
CAEX 0 1 0
+ _
CA11 P2CA1
1
1
V
Reference Voltage
CARSEL 1 0 VCAREF
0 2 1 3
0.5 x VCC 0.25 x VCC
14-16
Comparator_A in Applications
In Figure 14-13 current is transferred to an input voltage by I x R(sense). The current limit is set for example to 0.25xVCC. The current is below the limit as long as CAOUT is reset.
Figure 14-13. Detect a Current Level Using an Internal Reference Level
VCC P2CA0 0 CA0 1 R(sense) 0 0 CA11 P2CA1 Optional R(hyst) Px.y 3210 CAREF 1 2 s 0 V VCC 0 1 CAON 0 1 + _ 0 0 1 CAEX 0 V VCC 0 1 CAON CAF e.g. Capture Input of Timer_A CAOUT to External Pin Set CAIFG
1
CARSEL 1 0 VCAREF
0 2 1 3
0.5 x VCC 0.25 x VCC
14.4.5 Comparator_A Used to Measure a Current or Voltage Level
In addition to detecting levels, the comparator can be used to measure currents or voltages. To measure a voltage, a known, stable voltage source is used to charge up an RC combination. The time required to charge the combination to a threshold value set by the voltage to be measured is then used to calculate the voltage level (see Figure 14-16). VCAREF can be used as the known stable voltage source if VCC in the user's system meets the required stability and accuracy. A similar approach is used to measure a current. A known, stable voltage source is again used to charge an RC combination to a threshold value. In this case, the threshold voltage is created by passing the current to be measured through a known resistance (see Figure 14-14).
Comparator_A
14-17
Comparator_A in Applications
Figure 14-14. Measuring a Current Source
VCC P2CA0 0 CA0 1 R(sense) 0 0 CA11 P2CA1
VCC
I
CAEX 0 1
0 V VCC 0 1 CAON CAF 0 0 1 2 s 0 V VCC 0 1 CAON e.g. Capture Input of Timer_A CAOUT to External Pin Set CAIFG
+ _
1
1
R(meas)
3210 CAREF
CARSEL 1 0 VCAREF
0 2 1 3
0.5 x VCC 0.25 x VCC
The equation for the current I is: 1 + R(sense)
t 1 ln 0.3 t 1- e 1 2
I
V CC
)t
Figure 14-15. Timing for Measuring a Current Source
Vc VCC 0.5 x VCC
IxR t1 t2
Phase I: Phase II: Charge-Up Charge-Up: Determine Tau, RC
14-18
Comparator_A in Applications
Figure 14-16. A/D Converter for Voltage Sources
V(meas)
P2CA0 R1 0 CA0 1 0
0 V VCC 0 1 CAEX 0 1 + _ 0 0 1 2 s CAON CAF e.g. Capture Input of Timer_A CAOUT to External Pin Set CAIFG
R2
0 CA1 1 P2CA1 1
1
VCC
0 V VCC 0 1 CAON 3210 CAREF C CARSEL 1 0 VCAREF 0.5 x VCC 0.25 x VCC
0 2 1 3
The equation for the voltage Vmeas is:
V(meas)
) + R1 R2 R2
V CC
t 1 ln 0.3 t 1-e 1 2
)t
Figure 14-17. A/D Converter for Voltage Sources, Conversion Timing
Vc VCC 0.5 x VCC
VR t1 t2
Phase I: Phase II: Charge-Up Charge-Up: Determine Tau, RC
Note:
During phase I, control bit P2CA0 = 1 and CAREF = 0. During phase II, control bit P2CA0 = 0, CARSEL = 0, and CAREF= 1.
Comparator_A
14-19
Comparator_A in Applications
14.4.6 Measuring the Offset Voltage of Comparator_A
The input offset voltage of the comparator varies with each device and also with temperature, supply voltage, and input voltage. If the input voltage is stable (reference voltage), it will not influence the offset voltage significantly. To increase the precision of voltage measurements, the comparator offset voltage can be measured by the following steps. To simply compensate for the offset without measuring it, see section 14.4.7 First, execute a conversion with CAEX = 0. VCA0 is applied to the + terminal of the comparator, and Vref is applied to the - terminal of the comparator as shown in Figure 14-18.
Figure 14-18. Measuring the Offset Voltage of the Comparator, CAEX = 0
0 V VCC 0 1 CAEX 0 1 0 0 CA1 1 P2CA1 Vref 1 2 s + _ 0 0 1 CAON CAF e.g. Capture Input of Timer_A CAOUT to External Pin Set CAIFG
P2CA0 0 CA0 1
1
The Voffset in this configuration is in series with Vref as shown in Figure 14-19. VCA0 = Vref + Voffset
Figure 14-19. Offset Voltage of the Comparator, CAEX = 0
0 V VCC 0 1 CAON CAEX 0 CAF 0 1 2 s e.g. Capture Input of Timer_A CAOUT to External Pin Set CAIFG
+ _ Voffset
1 VCA0 Vref
Next, execute a conversion with CAEX = 1. VCA0 is applied to the - terminal of the comparator, and Vref is applied to the + terminal of the comparator as shown in Figure 14-20.
14-20
Comparator_A in Applications
Figure 14-20. Measuring the Offset Voltage of the Comparator, CAEX = 1
0 V VCC 0 1 CAEX 0 1 0 0 CA1 1 P2CA1 Vref 1 2 s + _ 0 0 1 CAON CAF e.g. Capture Input of Timer_A CAOUT to External Pin Set CAIFG
P2CA0 0 CA0 1
1
The Voffset in this configuration is in series with VCA0 as shown in Figure 14-21. Vref = VCA0 + Voffset VCA0 = Vref - Voffset
Figure 14-21. Offset Voltage of the Comparator, CAEX = 1
0 V VCC 0 1 CAON CAEX + _ Voffset 2 s 0 CAF 0 1 e.g. Capture Input of Timer_A CAOUT to External Pin Set CAIFG
1 Vref VCA0
Finally, calculate Vref from the below formulas.
N1
+ -RVCA0 + -RVCA0 + VCC
C
ln
Vref
) Voffset
V CC
f osc f osc
N2
C
ln
Vref-V offset V CC
This leads to:
V N1)N2 ln ref V 2N1 CC -V e ref
V offset
N = timer counts
Comparator_A
14-21
Comparator_A in Applications
14.4.7 Compensating for the Offset Voltage of Comparator_A
Another way to improve the accuracy is to compensate for the effect of input offset voltage without actually measuring it. When CAEX = 0, the Voffset is in series with Vref: VCA0 = Vref + Voffset When CAEX = 1, the Voffset is in series with VCA0: Vref = VCA0 + Voffset VCA0 = Vref - Voffset Adding the result of two conversions (one with each input configuration) and dividing by two will cancel the effect of the offset voltage.
+ Vref ) Voffset ) VCA0 + Vref * Voffset 2 V CA0 + 2 V ref
V CA0
a
N1
) N2 + Conversion without offset
2
N = Timer count
14.4.8 Adding Hysteresis to Comparator_A
When the voltage level applied to the + terminal is close to the voltage level at the - terminal, the output of the comparator may oscillate. This can cause the following two situations:
-
The current consumption increases, since the signal path driven by the comparator output is constantly charged and discharged. The software receives constant requests for service either via interrupt service requests, or after successful polling of CAOUT or CAIFG.
14-22
Comparator_A in Applications
Figure 14-22 shows how to add hysteresis to the comparator to prevent output oscillation.
Figure 14-22. Use CAOUT at an External Pin to Add Hysteresis to the Reference Level
If Feedback is Possible
P2CA0 R1 R2 Reference Voltage 0 CA0 1 0
0 V VCC 0 1 CAEX 0 1 + _ 0 0 1 2 s 0 V VCC 0 1 CAON 3210 CAREF CAON CAF e.g. Capture Input of Timer_A CAOUT to External Pin Set CAIFG
V
0 CA11 P2CA1 1
1
V
Signal Voltage
CARSEL 1 0 VCAREF
0 2 1 3
0.5 x VCC 0.25 x VCC
Adding hysteresis can only be done if CAOUT is available externally. Refer to the device's data sheet to determine if CAOUT is available at an external pin. The hysteresis can be calculated as follows:
V (hyst)
+" R1 R2 R2 )
V CC
Comparator_A
14-23
14-24
Chapter 15
ADC12
The ADC12 12-bit analog-to-digital converter is a high-speed, extremely versatile analog-to-digital converter implemented on MSP430x13x and MSP430x14x devices. This chapter discusses the ADC12 and how to use it.
Topic
Page
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 15.2 ADC Description and Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 15.3 Analog Inputs and Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 15.4 Conversion Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8 15.5 Conversion Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9 15.6 Conversion Clock and Conversion Speed . . . . . . . . . . . . . . . . . . . . . 15-21 15.7 Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-22 15.8 ADC12 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-30
ADC12
15-1
Introduction
15.1 Introduction
The ADC12 12-bit analog-to-digital converter (shown in Figure 15-1) has five main functional blocks that can be individually configured and optimized:
VeREF +
ADC core with sample-and-hold Conversion memory and configuration Reference voltage and configuration Conversion clock source select and control Sample timing and conversion control
Figure 15-1. ADC12 Schematic
2_5V REFON INCH= 0Ah on AVCC
VREF+ VREF- / Ve REF-
ADC12CTLx.0..3
VREF+
1.5V or 2.5V AVSS AVCC Ref_X
on
Reference
AVSS a0 a1 a2 a3 a4 a5 a6 a7
S/H
ADC12SSEL ADC12DIV
Internal
Oscillator ADC12OSC ACLK MCLK SMCLK
ADC12CTLx.4..6
ADC12ON
Analog Multiplexer 12 : 1
VR-
Sample and Hold
VR+
ADC12CLK
Divide by 1,2,3,4,5,6,7,8
12-bit A/D converter core SHP
SHT0 SHT1
Sampling ISSH SYNC MSC ENC 080h 081h 082h 083h 084h 085h 086h 087h 088h 089h 08Ah 08Bh 08Ch 08Dh 08Eh 08Fh SHS
a8 a9 a10 a11 12-bit S A R AVCC Ref_X 0140h 0142h 0144h 0146h 0148h 014Ah ADC12MEM0 ADC12MEM1 ADC12MEM2 ADC12MEM3 ADC12MEM4 ADC12MEM5 ADC12MEM6 ADC12MEM7 ADC12MEM8 ADC12MEM9 ADC12MEM10 ADC12MEM11 ADC12MEM12 ADC12MEM13 ADC12MEM14 ADC12MEM15 16 x 12-bit ADC Memory SAMPCON
ADC12SC Timer_A.OUT1 Timer_B.OUT0 Timer_B.OUT1
Timer
SHI
Conversion CTL
ADC12CTL0 ADC12CTL1 ADC12CTL2 ADC12CTL3 ADC12CTL4 ADC12CTL5 ADC12CTL6 ADC12CTL7 ADC12CTL8 ADC12CTL9 ADC12CTL10 ADC12CTL11 ADC12CTL12 ADC12CTL13 ADC12CTL14 ADC12CTL15 16 x 8-bit ADC Memory Control
T
AVSS
014Ch 014Eh 0150h 0152h 0154h 0156h 0158h 015Ah 015Ch 015Eh
The ADC12 can convert one of eight external analog inputs, or one of four internal voltages. The four internal channels are used for temperature measurement (via on-chip temperature diode), and for measurement of Vcc (via Vcc/2) and the positive and negative references applied on VeREF+ and VREF-/VeREF-. The ADC12 can use its internal reference, or it can use external reference(s) or a combination of internal and external reference-voltage levels.
15-2
Introduction
The ADC12 has versatile sample-and-hold circuitry giving the user many options for control of the sample timing. The sample timing may be directly controlled by software (via a control bit), or any one of three internal or external signals (depending on device configuration - see Sampling section and check the data sheet for details). Typically, the internal timing signals come from other MSP430 timers such as Timer_A. Additionally, the sample timing may be programmed as a multiple of the ADC12 conversion clock. As with sample timing, the user has several choices for the ADC12 conversion clock. The ADC12 conversion clock may be chosen from any available internal MSP430 clock, or may be selected from a dedicated oscillator contained in the ADC12 peripheral. Additionally, the chosen clock source may be divided by any factor from 1 to 8. The ADC12 has four operating modes. It can be configured to perform a single conversion on a single channel, or multiple conversions on a single channel. The ADC12 can also be configured to perform conversions on a sequence-ofchannels, running through the sequence once, or repeatedly. When performing conversions on a sequence-of-channels, the sequence is completely definable by the user. For example, a possible sequence-ofchannels could be a1-a3-a1-a6-a2, etc. In addition, each channel may be individually configured for which reference(s) are to be used for the conversion. Conversion results are stored in 16 conversion-memory registers. Each of these registers has its own configuration and control register allowing the user to select the input channel and the reference(s) used for the conversion result that is stored in that register. Some key and unique features of the ADC12 are:
-
200-ksps maximum conversion rate 12-bit converter with 1LSB differential nonlinearity (DNL) and 1LSB integral nonlinearity (INL) Built-in sample-and-hold with selectable sampling periods controlled by software (via a control bit), a sampling timer, or by other MSP430 timers On-chip, dedicated RC oscillator - used as an option for sample-andconversion timing Integrated diode for temperature measurement Eight individually configurable channels for conversion of external signals Four internal channels for conversion of temperature, AVcc, and external references On-chip reference voltages - 1.5 V or 2.5 V, selected by software Selectable internal or external sources for both positive and negative reference-voltage levels (selectable for each channel independently) Selectable conversion clock source
ADC12
15-3
ADC12 Description and Operation
15.2.1 ADC Core
Versatile conversion modes including single-channel, repeated singlechannel, sequence, and repeated sequence. Sixteen 12-bit registers for storage of conversion results. Each register is individually accessible by software and individually configurable to define the channel and references for its conversion result. ADC core and reference voltage powered down separately
15.2 ADC12 Description and Operation
The ADC core (shown in Figure 15-2) converts the analog input to its 12-bit representation and stores the results in the conversion memory. The core uses two programmable/selectable voltage levels (VR+ and VR-) to define the upper and lower limits of the conversion range, and to define the full-scale and zero-scale readings. The digital output is full scale when the input signal is equal to or higher than VR+, and zero when the input signal is equal to or lower than VR-. The input channel and the reference voltage levels (VR+ and VR-) are defined in the conversion-control memory. The conversion formula is: NADC
+ 4095
Vin - V R- V R)- V R-
Figure 15-2. ADC Core, Input Multiplexer, and Sample-and-Hold
ADC12MCTLx.0..3 ADC12MCTLx.4..6
a0 a1 a2 a3 a4 a5 a6 a7
from Reference ADC12ON
VR-
VR+
ADC12CLK
Analog Multiplexer
12 : 1 a8 a9 a10 a11
Sample and Hold
12-bit A/D converter core
VeREF+ VeREF-/ VREF-
Temperature
S/H
SAMPCON
SAR
AVCC/2
to ADC12MEMx
It is important to note that the 3 LSBs of the conversion are resolved resistively. Therefore, when the 3 LSBs are being resolved during a conversion, approximately 200 A will be required from the reference. The user should keep this in mind when choosing and decoupling an external reference. Refer to the device data sheet for more details on ADC12 specifications.
15-4
ADC12 Description and Operation
Caution! ADC12 Turnon Time When the ADC12 is turned on with the ADC12ON bit, the turnon time noted in the data sheet (tADC12ON) must be observed before a conversion is started. Otherwise, the results will be false.
15.2.2 Reference
The ADC12 A/D converter contains a built-in reference with two selectable reference-voltage levels (1.5 V and 2.5 V). Either of these reference voltages may be applied to VR+ of the A/D core and also may be available externally on pin VREF+ (check device data sheet for availability of VREF+ pin). Additionally, an external reference may be supplied for VR+ through pin VeREF+ (check data sheet for availability of VeREF+ pin). The reference-voltage level for VR- can be selected to be AVSS or may be supplied externally through the VREF-/VeREF- pin (check device data sheet for VREF-/VeREF- pin). If the VREF-/VeREF- pin is not available, then VR- is connected to AVSS. Configuration of the reference voltage(s) is done with the Sref bits (bits 4, 5, and 6) in the ADC12MCTLx registers. Up to six combinations of positive and negative reference voltages are supported as described in Table 15-1. If only external references are used, the internal-reference generator can be turned off with the REFON bit to conserve power.
Table 15-1.Reference Voltage Configurations
Sref 0 1 2,3 4 5 6,7 Voltage at VR+ AVCC VREF+ (internal) VeREF+ (external) AVCC VREF+ (internal) VeREF+ (external) Voltage at VR- AVSS AVSS AVSS VREF-/ VeREF- (internal or external) VREF-/ VeREF- (internal or external) VREF-/ VeREF- (internal or external)
The voltage levels VR+ and VR- establish the upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading, respectively. The values of VR+, VR-, and the analog input should not exceed the positive supply or be lower than AVSS, consistent with the absolute maximum ratings specified in the device data sheet. The digital output is full scale when the input signal is equal to or higher than VR+, and zero when the input signal is equal to or lower than VR-.
ADC12
15-5
Analog Inputs and Multiplexer
Warning ! Reference Voltage Settling Time When the built-in reference is turned on with the VREFON bit, the settling timing noted in the data sheet must be observed before starting a conversion. Otherwise, the results will be false until the reference settles. Once all internal and external references have settled, no additional settling time is required when selecting or changing the conversion range for each channel.
15.3 Analog Inputs and Multiplexer
15.3.1 Analog Multiplexer
The eight external analog input channels and four internal signals are selected as the channel for conversion by the analog multiplexer. Channel selection is made for each conversion-memory register with the corresponding ADC12MCTLx register. The input multiplexer is a break-before-make type (shown in Figure 15-3) to reduce input-to-input noise injection resulting from channel switching. The input multiplexer is also a T-switch to minimize the coupling between channels. Channels that are not selected are isolated from the A/D and the intermediate node is connected to analog ground (AVSS) so that the stray capacitance is grounded to help eliminate crosstalk.
Figure 15-3. Analog Multiplexer Channel
R ~ 100Ohm ADC12MCTLx.0-3 Input
ESD protection
Crosstalk can exist because there is always some parasitic coupling capacitance across the switch and between switches. This can take several forms, such as coupling from the input to the output of an off switch, or coupling from an off analog input channel to the output of an adjacent on channel. For highaccuracy conversions, crosstalk interference should be minimized by shielding and other well-known printed-circuit board (PCB) layout techniques.
15-6
Analog Inputs and Multiplexer
15.3.2 Input Signal Considerations
During sampling, the analog input signal is applied to the internal capacitor array of the A/D core. Therefore, the charge of the capacitor array is supplied directly by the source. The capacitor array has to be charged completely during the sampling period. Therefore the external source resistances, dynamic impedances, and capacitance of the capacitor array must be matched with the sampling period so the analog signal can settle to within 12-bit accuracy. Additionally, source impedances also affect the accuracy of the converter. The source signal can drop at the input of the device due to leakage current or averaged dc-input currents (due to input switching currents). For a 12-bit converter, the error in LSBs due to leakage current is: Error(LSBs) = 4.096 x (A of leakage current) x (k of source resistance)/(VR+ - VR-) For example, a 50-nA leakage current with a 10-k source resistance and a 1.5-V VREF gives 1.4 LSBs of error. These errors due to source impedance also apply to the output impedance of any external-voltage reference source applied to VeREF+. The output impedance must be low enough to enable the transients to settle within 0.2/ADCLK and generate leakage current induced errors of <<1LSB. See the Sampling section for more details on sample timing and sampling considerations.
15.3.3 Using the Temperature Diode
To use the on-chip temperature diode, the user simply selects the analog input channel to 10. Any other configuration is done as if an external channel was selected, including reference selection, conversion-memory selection, etc. Selecting the diode channel automatically turns on the on-chip reference generator (see Figure 15-1) as a voltage source for the temperature diode. However, it does not enable the VREF+ output or affect the reference selections for the conversion; so, reference selections are the same as with any other channel. See the device data sheet for the temperature diode specifications.
ADC12
15-7
Conversion Memory
15.4 Conversion Memory
A typical approach in single-channel converters uses an interrupt request to signal the end of the conversion and requires the conversion data to be moved to another location before another conversion can be performed. However, the ADC12 incorporates 16 conversion-memory registers (ADC12MEMx, see Figure 15-1) allowing the A/D converter to run multiple conversions without software intervention. This increases the system performance by reducing software overhead. Additionally, each of the 16 conversion-memory registers has an associated control register (ADC12MCTLx) allowing total flexibility for each conversion. The memory-control registers allow the user to specify the channel and reference(s) used for each individual conversion. All other control bits that configure the other operating conditions of the ADC12, such as conversion modes, sample and conversion control signal, ADC clock, and sample timing, are located in control registers ADC12CTL0 and ADC12CTL1. Each conversion-memory register is individually accessible by software in the address range 0140h - 015Eh. Using the conversion memory involves control bits in two places. First, the CStartAdd bits located in ADC12CTL1 point to the conversion-memory register to be used for single-channel conversions or the first conversion-memory register to be used for a sequence. The conversion-start address (CStartAdd) can be any value from 0h - 0Fh and points to ADC12MEM0 - ADC12MEM15, respectively. Second, the end-of-sequence (EOS) bit in each conversion-memory control register marks the end of an automatic-conversion sequence. The EOS bit, when set, defines the end of a conversion sequence. When cleared, an internal conversion-memory pointer (not visible to software) is incremented after the current conversion is completed and the conversion result is stored in the conversion memory. The conversion-memory pointer is then prepared to use the next conversion-memory register to store the results of the next conversion. The internal conversion-memory pointer is incremented with each conversion until a set EOS bit is encountered. Note that defining the end of a sequence is independent from defining the mode of operation (see the Conversion Modes section), and that the EOS bits are ignored when using single-conversion mode or repeated conversion of a single-channel mode. Conversion sequences always use sequential conversion-memory registers, can start with any conversion-memory register, and do not necessarily require any EOS bit to be set. For example, if the CONSEQ bits define the mode of operation to be conversion of a sequence (single or repeated), the CStartAdd bits point to conversion-memory register 14, and no EOS bits are set for any of the conversion-memory registers, then the conversion-memory registers will be used in sequential order (14, 15, 0, 1, 2, ... , 14, 15, 0, 1, 2, ... etc.) for each consecutive conversion, and the sequence of conversions will continue until stopped by software. This is useful, for example, in an application that must take advantage of the buffering supplied by the conversion memory but requires more than 16 repeated conversions of a single channel. In this instance the user should set up each memory-control register identically, specifying the same channel and reference(s) for each conversion, and all EOS bits must be cleared. Once the converter is started, it will continue to run until stopped by software.
15-8
Conversion Modes
15.5 Conversion Modes
The ADC12 has four conversion modes:
-
Single-channel, single-conversion Single-channel, repeated-conversions Sequence-of-channels, single-sequence Sequence-of-channels, repeated-sequence
Each mode is summarized in Table 15-2 and described in detail in the following sections.
Table 15-2.Conversion-Modes Summary
CONVERSION MODE Single channel CONSEQ 00 OPERATION Single conversion from a selected channel X = CstartAdd, points to the conversion start address Result is in ADC12MEMx; interrupt flag is ADC12IFG.x Channel (INCH) and reference voltage (Sref) are selected in ADC12MCTLx Sequence-of-channels 01 A sequence-of-channels is converted x = CstartAdd; points to the conversion start address The last channel in a sequence (y) is marked with EOS=1 (ADC12MCTLx.7), all other EOS bits in ADC12MCTLx, ADC12MCTL(x+1)..., ADC12MCTL(y-1) are reset. Result is in ADC12MEMx, ADC12MEM(x+1),..., ADC12MEMy Interrupt flags are ADC12IFG.x, ADC12IFG.(x+1),..., ADC12IFG.y More than one sequence is possible Channel (INCH) and reference voltage (Sref) are selected in ADC12MCTLx Repeat single channel 10 The conversion of one single channel is permanently repeated until repeat is off or ENC is reset x = CstartAdd; points to the conversion start address Result is in ADC12MEMx; interrupt flag is ADC12IFG.x Channel (INCH) and reference voltage (Sref) are selected in ADC12MCTLx Repeat sequence-ofchannels 11 The conversion of a sequence-of-channels is permanently repeated until repeat is off or ENC is reset x = CstartAdd; points to the conversion start address The last channel in a sequence (y) is marked with EOS=1 (ADC12MCTL.7), all other EOS bits in ADC12MCTLx, ADC12MCTL(x+1),..., ADC12MCTL(y-1) are reset Result is in ADC12MEMx, ADC12MEMx+1,....; interrupt flag is ADC12IFG.x, ADC12IFG.x+1,.... More than one sequence is possible Channel (INCH) and reference voltage (Sref) are selected in ADC12MCTLx
15.5.1 Single-Channel, Single-Conversion Mode
The single-channel mode converts a single channel once. The channel to be converted is selected by the INCH bits in the conversion-memory control register (ADC12MCTLx) associated with the conversion-memory register pointed to by the CStartAdd bits (located in ADC12CTL1x. The conversion range (VR+,
ADC12
15-9
Conversion Modes
VR-) is configured in the same conversion-memory control register by the Sref bits. The conversion result is stored in conversion-memory register ADC12MEMx pointed to by the CStartAdd bits. The conversion may be stopped immediately by resetting the enableconversion bit (ENC, located in ADC12CTL0), but the conversion results will be unreliable, or the conversion may not be performed. This is illustrated in Figure 15-4.
Figure 15-4. Stopping Conversion With ENC Bit
ENC and ADC12SC may be set together ENC SAMPCON Operational Mode Sample Period Conversion Period Sample Period Conversion Period ENC and ADC12SC may be set together
ENC is reset before conversion period is completed: no conversion executed or unreliable conversion result. Sample-and-conversion (SAMPCOM) signal can be reset and conversion started when appropriate.
ENC is reset after conversion period is completed: conversion is executed regularly. Sample-and-conversion (SAMPCOM) signal can be reset and conversion started when appropriate.
ENC SAMPCON Operational Mode Sample Period Conversion Period Sample Period Conversion Period
ENC is reset before conversion period is completed: no conversion executed or unreliable conversion result. Sample-and-conversion (SAMPCOM) signal can be reset and conversion started when appropriate.
ENC is reset after conversion period is completed: conversion is executed regularly. Sample-and-conversion (SAMPCOM) signal can be reset and conversion started when appropriate.
When the conversion is complete and the results are written to the selected conversion-memory register, the corresponding interrupt flag ADC12IFG.x is set, and, if the appropriate interrupt enables are set, an interrupt request is generated (see the ADC12 Interrupt Vector Register ADC12IV section). Once the conversion is completed, the ENC bit must be reset and then set again to prepare for another conversion. All additional incoming sample-input signals will be ignored until the ENC bit is reset and set again. Also, the conversion mode may be changed after the conversion begins but before it has completed, and the new mode will take effect after the current conversion has completed. See also the Switching between Conversion Modes section. An illustration of single-channel, single-conversion mode is shown in Figure 15-5.
15-10
Conversion Modes
Figure 15-5. Single-Channel, Single-Conversion Mode
CONSEQ = 0
ADC12 off ENC =
ADC12ON = 1
x = CStartAdd Wait for Enable ENC = SHS = 0 and ENC = and ADC12SC = ENC =
Wait for Trigger SAMPCON = SAMPCON = 1
ENC = 0
ENC = 0
Sample, Input Channel Defined in ADC12MCTLx SAMPCON = < 12 x ADC12CLK Convert, use 12 x ADC12CLK
ENC = 0 1 x ADC12CLK Conversion Completed, Result Stored Into ADC12MEMx, ADC12IFG.x is Set
Conversion result is unpredictable
An example of the conversion-memory setup is shown in Figure 15-6 for single-channel conversion. The example uses the following conditions:
-
Single conversion of channel a4 Internal reference voltage with VR+ at AVCC and with VR- at AVSS Conversion result to be stored in conversion-memory register ADC12MEM1
This means that control bit CStartAdd in ADC12CTL0 is assigned a value of 1. The channel (INCH=4) and reference voltages (Sref=0) are selected via ADC12MCTL1.
ADC12
15-11
Conversion Modes
Figure 15-6. Example Conversion-Memory Setup
E Select O VR+/VR- S
Multiplexer
0
0140h 140h + 2 x CStartAdd 0142h
12-bit S A R
ADC12MEM0
ADC12MCTL0
080h 081h
0
conversion ADC12MEM2
16 x 12-bit
result
10000100
ADC12MCTL2 16 x 8-bit
80h + CStartAdd
ADC Memory
ADC Memory Controls
015Ch 015Eh
ADC12MEM14 ADC12MEM15
ADC12MCTL14 ADC12MCTL15
08Eh
08Fh
15.5.2 Sequence-of-Channels Mode
The sequence-of-channels mode converts a sequence of channels. The CStartAdd bits in ADC12CTL1 point to the first conversion-memory register used for the sequence. The results of the remaining conversions in the sequence are stored in sequential conversion-memory registers. For example, if a sequence is three-conversions long and the CStartAdd bits point to conversion-memory register 4, then when the sequence is started, the first conversion result isstored in ADC12MEM4, the second result is stored in ADC12MEM5, and the third result is stored in ADC12MEM6. When performing sequences of conversions, the channels and references for each conversion are individually configurable via the conversion-memory control register associated with the each conversion-memory register used in the sequence. For example, if a sequence of conversions uses ADC12MEM3 - ADC12MEM6, then the channel and reference(s) for each conversion are individually configurable with ADC12MCTL3 - ADC12MCTL6. The end of a sequence is marked by the end-of-sequence bit (EOS) in the last conversion-memory control register used in the sequence. Each conversionmemory control register contains an EOS bit. All EOS bits of the conversionmemory control registers used in a sequence must be reset, except for the last one in the sequence. For example, if a sequence starts with ADC12MEM7 and ends with ADC12MEM12, then the EOS bit of registers ADC12MCTL7 - ADC12MCTL11 must be reset and the EOS bit of ADC12MCTL12 must be set. Conversions stop when the end of a sequence is reached. To execute the same sequence, or a new sequence, the ENC bit must be reset and then set again. All additional sample-input signals are ignored until this happens. Note that the ENC bit may be reset any time after the sequence begins, and the sequence still completes normally (see Figure 15-7). If the conversion mode is changed after the sequence begins but before it has completed and the ENC bit is left high, the sequence completes normally, and the new mode takes effect after the sequence completes, unless the new mode is single-channel single-conversion. If the new mode is single-channel single-conversion, the current sequence-of-channels stops proceeding when
15-12
Conversion Modes
no sample-and-conversion is active, or after an active sample-and-conversion is completed. The original sequence may not be completed, but all completed conversion results are valid. See also the Switching Between Conversion Modes section. If the conversion mode is changed after the sequence begins, but before it has completed, and the ENC bit is toggled, then the original sequence completes normally and the new mode takes effect and is started after the original sequence completes - unless the new mode is single-channel single-conversion. If the new mode is single-channel single-conversion, then the original sequence stops when no sample-and-conversion is active, or after an active sample-and-conversion is completed, or when the ENC bit is reset, whichever comes first. Then, the single conversion begins when the ENC bit is set again. See also the Switching Between Conversion Modes section.
Figure 15-7. ENC Does Not Effect Active Sequence
ENC and ADC12SC ADC12SC reset ADC12SC set ADC12SC reset ADC12SC set ADC12SC reset may be set together starts conversion starts sampling starts conversion starts sampling starts conversion ENC
SAMPCON
Sample Conversion Single Conversion Time Single Period of Sequence
Sample Conversion
Sample Conversion
Sample Conversion
Sample Conversion
Single Conversion Single Conversion Time Time Single Period of Sequence Period of Sequences
Single Conversion Single Conversion Time Time Single Period Single Period of Sequence of Sequence Next Period of Sequences
First +SAMPCON with ADC12SC reset ENC set start S&C starts conversion
ADC12SC set ADC12SC reset ADC12SC set ADC12SC reset starts sampling starts conversion starts sampling starts conversion
ENC
SAMPCON
Sample Conversion Single Conversion Time Single Period of Sequence
Sample Conversion
Sample Conversion
Sample Conversion
Sample Conversion
Single Conversion Single Conversion Time Time Single Period of Sequence Period of Sequences
Single Conversion Single Conversion Time Time Single Period Single Period of Sequence of Sequence Next Period of Sequences
An active sequence may be stopped immediately by selecting single-channel single-conversion mode (reset CONSEQ.1 bit) and then resetting the enable-conversion bit ENC. The data in memory register ADC12MEMx is unpredictable and the interrupt flag ADC12IFG.x may or may not be set. This is generally not recommended but may be used as an emergency exit. Each time a conversion is completed, the results are loaded into the appropriate ADC12MEMx register and the corresponding interrupt flag ADC12IFG.x is set to indicate completion of the conversion. Additionally, If the appropriate interrupt-enable flags are set, an interrupt request is generated (see the ADC12 Interrupt Vector Register ADC12IV section).
ADC12
15-13
Conversion Modes
An illustration of sequence of channels mode is shown in Figure 15-8.
Figure 15-8. Sequence-of-Channels Mode
CONSEQ = 1 ADC12 off ADC12ON = 1 ENC =
x = CStartAdd Wait for Enable ENC = SHS = 0 and ENC = and ADC12SC = ENC =
Wait for Trigger SAMPCON = SAMPCON = 1 EOS.x = 1
If x < 15 then x = x + 1 else x = 0
Sample, Input Channel Defined in ADC12MCTLx
If x < 15 then x = x + 1 else x = 0 < 12 x ADC12CLK
SAMPCON = MSC = 1 and SHP = 1 and EOS.x = 0 Convert, Use 12 x ADC12CLK (MSC = 0 or SHP = 0) and EOS.x = 0
1 x ADC12CLK Conversion Completed, Result Stored Into ADC12MEMx, ADC12IFG.x is Set
15-14
Conversion Modes
An example showing a sequence of conversions is shown and flow-charted in Figures 15-9 and 15-10. The example shows the sequence a0, a5, a7, a0, a0, a3, and uses ADC12MEM6 for storing the first conversion results. The setup of each conversion in the sequence is:
-
a0, using reference voltages VR+ = AVCC and VR- = AVSS a5, using reference voltages VR+ at VREF+ and VR- = AVSS a7, using reference voltages VR+ at VREF+ and VR- = VeREF-/ VREF- a0, using reference voltages VR+ = AVCC and VR- = AVSS a0, using reference voltages VR+ = AVCC and VR- = AVSS a3, using reference voltages VR+ = AVCC and VR- = VeREF-/ VREF-
Figure 15-9. Sequence-of-Channels Mode Flow
SAMPCON
Define basic conversion conditions via control registers ADC12CTL0/1 x = 6 ( CStartAdd = 6 )
Sample Conversion
Sample and convert channel using ADC12MCTLx, and store conversion result in ADC12MEMx
Define reference and channel in control registers ADC12MCTL6x ADC12MCTL6 = 0h ADC12MCTL7 = 015h ADC12MCTL8 = 057h ADC12MCTL9 = 0h ADC12MCTL10 = 0h ADC12MCTL11 = 0C3h
Yes
EOS in ADC12MCTLx = 1
No x=x+1
No Yes ENC 0
1
Stop conversion sequence
ADC12
15-15
Conversion Modes
Figure 15-10. Sequence-of-Channels Mode Example
E select O VR+/VR- S
Multiplexer
0
0140h 0142h 0144h 0146h 0148h 140h + 2 x CStartAdd 014Ah 014Ch 014Eh 0150h 0152h Sequence 0154h 0156h 0158h 015Ah 015Ch 015Eh
12-bit S A R
ADC12MEM0 ADC12MEM1 ADC12MEM2 ADC12MEM3 ADC12MEM4 ADC12MEM5
ADC12MCTL0 ADC12MCTL1 ADC12MCTL2 ADC12MCTL3 ADC12MCTL4 ADC12MCTL5
080h 081h 082h 083h 084h 085h 80h + CStartAdd
0 0 0 0 0 0
Conversion result 1 Conversion result 1 Conversion result 1 16 x 12-bit Conversion result 1
ADC Memory 1 Conversion result
Conversion result 1
0 0 0 0 0 1
0 0 1 0 0 1
0 0 0 0 0 0
0 1 1 0 0 0
0 0 0 0 0 0
0 1 1 0 0 0
0 0 1 0 0 1
0 1 1 0 0 1
086h 087h 088h 089h
08Ah 08Bh 08Ch 08Dh 08Eh
08Fh
ADC12MEM12 ADC12MEM13 ADC12MEM14 ADC12MEM15
ADC12MCTL12 ADC12MCTL13 ADC12MCTL14 ADC12MCTL15
15.5.3 Repeat-Single-Channel Mode
The repeat-single-channel mode is identical to the single-channel mode, except that conversions are repeated on the chosen channel until stopped by software. Each time a conversion is completed, the results are loaded into the appropriate ADC12MEMx register and the corresponding interrupt flag ADC12IFG.x is set to indicate completion of the conversion. Additionally, If the appropriate interrupt-enable flags are set, an interrupt request is generated (see the ADC12 Interrupt Vector Register ADC12IV section). The conversion mode may be changed without first stopping the conversions. When this is done, the new mode takes effect after the current conversion completes (see also the Switching Between Conversion Modes section). There are three ways to stop repeated conversions on a single channel: 1) Select single-channel mode instead of repeat-single-channel mode with the CONSEQ bits. When this is done, the current conversion is completed normally, the result is loaded into ADC12MEMx, and the associated interrupt flag ADC12IFG.x is set. 2) Reset the ENC bit (ADC12CTL0.1) to stop conversions after the current conversion is completed. Again, the result is loaded into ADC12MEMx and the associated interrupt flag ADC12IFG.x is set. 3) Select single-channel mode instead of repeat-single-channel mode and then reset the enable-conversion bit (ENC). When this is done, the current conversion stops immediately. However, the data in memory register ADC12MEMx is unpredictable and the associated interrupt flag ADC12IFG.x may or may not be set. This method is generally not recommended.
15-16
Conversion Modes
An illustration of repeat-single-channel mode is shown in Figure 15-11.
Figure 15-11.Repeat-Single-Channel Mode
CONSEQ = 2 ADC12 off ADC12ON = 1 ENC =
x = CStartAdd Wait for Enable ENC = SHS = 0 and ENC = and ADC12SC = ENC =
Wait for Trigger SAMPCON = SAMPCON = 1 ENC = 0
Sample, Input Channel Defined in ADC12MCTLx SAMPCON = < 12 x ADC12CLK MSC = 1 and SHP = 1 and ENC = 1 Convert, Use 12 x ADC12CLK (MSC = 0 or SHP = 0) and ENC = 1
1 x ADC12CLK Conversion Completed, Result Stored Into ADC12MEMx, ADC12IFG.x is Set
15.5.4 Repeat-Sequence-of-Channels Mode
The repeat-sequence-of-channel mode is identical to the sequence-ofchannel mode, except the sequence is repeated continuously until stopped by software. Each time a conversion is completed, the results are loaded into the appropriate ADC12MEMx register and the corresponding interrupt flag ADC12IFG.x is set to indicate completion of the conversion. Additionally, If the appropriate interrupt-enable flags are set, an interrupt request is generated (see the ADC12 Interrupt Vector Register ADC12IV section). The conversion mode may be changed without first stopping the conversions. When this is done, the new mode takes effect after the current sequence com-
ADC12
15-17
Conversion Modes
pletes, except when the new mode is repeat-single-channel. In this case, the sequence does not complete and the new mode takes effect immediately (see also the Switching Between Conversion Modes section). There are four ways to stop repeat-sequence-of-channels conversions: 1) Select sequence-of-channels mode (CONSEQ = 1) instead of repeated sequence-of-channels mode (CONSEQ = 3). When this is done, the current sequence of conversions is completed normally and no further conversions take place. The conversion results are loaded into registers ADC12MEMx and the corresponding interrupt flags ADC12IFG.x are set. 2) Reset ENC bit (ADC12CTL0.1). This stops the conversions after the current sequence is completed. The conversion results of all conversions in the sequence are stored in their appropriate ADC12MEMx register and the associated interrupt flags ADC12IFG.x are set. 3) Select repeat-single-channel mode (CONSEQ = 2) instead of the repeatsequence-of-channel mode, and then select single-channel mode. The current conversion is completed normally. The current conversion result is loaded into register ADC12MEMx and the associated interrupt flags ADC12IFG.x are set. The data for x is somewhere between CStartAdd and the last register of the sequence. 4) Select single-channel mode (CONSEQ = 0) and reset enable-conversion bit ENC. The current conversion is stopped immediately. The data in memory register ADC12MEMx is unpredictable and the interrupt flag ADC12IFG.x may or may not be set. This method is generally not recommended.
15-18
Conversion Modes
An illustration Figure 15-12.
of
repeat-sequence-of-channels
mode
is
shown
in
Figure 15-12. Repeat-Sequence-of-Channels Mode
CONSEQ = 3 ADC12 off ADC12ON = 1 ENC =
x = CStartAdd Wait for Enable ENC = SHS = 0 and ENC = and ADC12SC = ENC =
Wait for Trigger SAMPCON = SAMPCON = 1 ENC = 0 and EOS.x = 1
Sample, Input Channel Defined in ADC12MCTLx SAMPCON = If EOS.x = 1 then x = CStartAdd else {if x < 15 then x = x + 1 else x = 0} MSC = 1 and SHP = 1 and (ENC = 1 or EOS.x = 0)
If EOS.x = 1 then x = CStartAdd else {if x < 15 then x = x + 1 else x = 0} < 12 x ADC12CLK
Convert, Use 12 x ADC12CLK
1 x ADC12CLK Conversion Completed, Result Stored Into ADC12MEMx, ADC12IFG.x is Set
(MSC = 0 or SHP = 0) and (ENC = 1 or EOS.x = 0)
15.5.5 Switching Between Conversion Modes
Changing the mode of operation of the ADC12 while the converter is not actively running is done simply by selecting the new mode of operation with the CONSEQ bits. However, if the conversion mode is changed while the converter is actively running, intermediate and undesirable modes can be accidentally selected if both CONSEQ bits are changed in a single instruction. Therefore, the following mode changes should be avoided while the converter is running: 0 3, 1 2, 2 1, and 3 0.
ADC12
15-19
Conversion Modes
The intermediate modes are caused by the asynchronous clocks for the CPU and the ADC12. These intermediate modes can be avoided simply by changing only one CONSEQ bit per instruction. For example, to change from mode 0 to mode 3 while the converter is actively running, the following instructions could be used: BIS #CONSEQ_0,&ADC12CTL1 ; Example: 0 3, first ................................ ; step is 0 1 BIS #CONSEQ_1,&ADC12CTL1 ... ; second step is 1 3 Acceptable sequence modifications are: 0 1, 0 2, 1 0, 1 3, 2 0, 2 3, 3 1, and 3 2.
15.5.6 Power Down
The ADC12 incorporates two bits (ADC12ON and REFON) for power savings. ADC12ON turns on the A/D core and REFON turns on the reference generator. Each bit is individually controllable by software. The ADC12 is turned off completely if both bits are reset. The ADC12 registers are not affected by either of these bits and can be accessed and modified at any time (see the ADC12 Control Registers section). Note, however, that ADC12ON and REFON may only be modified if ENC=0. Additionally, other ADC12 functions are automatically switched on and off as needed--if possible--to realize additional power savings - even while the ADC12 is running.
Caution! Do not power-down the converter or the reference generator while the converter is active. Conversion results will be false. It is possible to disable the reference generator and the ADC12 by resetting bits ADC12ON and REFON before an active conversion or sequence of conversions has completed. For example, if the conversion mode is set to sequence-of-channels, and software resets the ENC bit immediately after the sequence begins, the ADC12ON and REFON bits can then be reset before the sequence completes. If this occurs, the ADC12 will be powered down immediately and the conversion results will be false.
15-20
Conversion Clock and Conversion Speed
Caution! The following must be considered when turning the ADC12 and voltage reference on or off. ADC12 turnon time: when the ADC12 is turned on with the ADC12ON bit, the turnon time noted in the data sheet (tADC12ON) must be observed before a conversion is started. Otherwise, the results will be false. Reference-voltage settling Time: When the built-in reference is turned on with the VREFON bit, the settling timing noted in the data sheet must be observed before a conversion is started. Otherwise, the results will be false until the reference settles. Once all internal and external references have settled, no additional settling time is required when selecting or changing the conversion range for each channel. Settling time of external signals: external signals must be settled before performing the first conversion after turning on the ADC12. Otherwise, the conversion results will be false.
15.6 Conversion Clock and Conversion Speed
The conversion clock for the ADC12 (ADC12CLK shown in Figure 15-13) can be selected from several sources and can be divided by any factor from 1 - 8. The ADC12CLK is used for the A/D conversion and to generate the sampling period [if pulse-sampling mode is selected (SHP=1)]. Possible clock sources are the internal oscillator (ADC12OSC), ACLK, MCLK, and SMCLK. The internal oscillator generates the ADC12OSC signal and is in the 5-MHz range (see device data sheet for specifications). The internal-oscillator frequency will vary with individual devices, supply voltage, and temperature. A stable clock source should be used for the conversion clock when accurate conversion timing is required.
Figure 15-13. The Conversion Clock ADC12CLK
ADC12SSEL
ADC12ON ADC12DIV ADC12OSC
Internal Oscillator
VR-
VR+
ADC12CLK Divide by 1,2,3,4,5,6,7,8
ACLK MCLK SMCLK
12-bit A/D converter core
to Sample&Hold
ADC12
15-21
Sampling
The conversion starts with the falling edge of the sample signal SAMPCON (see the Sampling section and Figure 15-14). Thirteen conversion clocks (ADC12CLK) are required to complete a conversion. The conversion time is: tconversion = 13 x (ADC12DIV/fADC12CLK ) Where ADC12DIV is any integer from 1 to 8. The ADC12CLK frequency must not exceed the maximum and minimum frequencies specified in the data sheet. Either violation may result in inaccurate conversion results. Note: Availability of ADC12CLK During Conversion Users must ensure that the clock chosen for ADC12CLK remains active until the ADC12 can complete its operation. If the clock is removed while the ADC12 is active, the operation can not be completed and the end-of-conversion feedback to the program is not possible.
15.7 Sampling
The ADC12 sample-and-hold (S/H) circuitry (shown in Figure 15-14) is flexible and configurable. The configuration is done by software via control bits in the ADC12CTL0 and ADC12CTL1 registers. Configuration and operation of the S/H circuitry is discussed in this section.
Figure 15-14. The Sample-and-Hold Function
ADC12SSEL ADC12ON ADC12DIV ADC12OSC Internal Oscillator
VR-
analog input signal Sample and Hold
S/H
VR+
ADC12CLK
Divide by 1,2,3,4,5,6,7,8
ACLK MCLK SMCLK
12-bit A/D converter core SHP
SHT0 SHT1
ISSH
Sampling SAMPCON Timer SYNC MSC ENC SHS
ADC12SC Timer_A.OUT1 Timer_B.OUT0 Timer_B.OUT1
SHI
12-bit S A R
Conversion CTL
15.7.1 Sampling Operation
The sample-and-hold circuitry samples the analog signal when the sampling signal SAMPCON (see Figure 15-14) is high. Conversion starts immediately with the falling edge of SAMPCON. The sample-and-hold holds the signal value when SAMPCON is low. Conversion takes 13 ADC12CLK cycles (see Figure 15-15).
15-22
Sampling
Figure 15-15. Sample and Conversion, Basic Signal Timing
Start Sampling Stop Sampling Start Conversion Stop Conversion
SAMPCON Sample Conversion and Hold
The analog input signal must be valid and steady during the sampling period in order to obtain an accurate conversion. It is also desirable not to have any digital activity on any adjacent channels during the whole conversion period to ensure that errors due to supply glitching, ground bounce, or crosstalk do not corrupt the conversion results. In addition, gains and losses in internal charge limit the hold time. The user should ensure that the data sheet limits are not violated. Otherwise, the sampled analog voltage may increase or decrease, resulting in false conversion values.
15.7.2 Sample Signal Input Selection
The SAMPCON signal, which controls sample timing and the start of a conversion, may be sourced by one of several signals. SAMPCON may be sourced directly from one of the signals available at the input selection switch (see Figure 15-16), further called sample-signal input, or from the integrated sampling timer. When the sampling timer is used to source SAMPCON, the sample-signal input is used to trigger the sampling timer. The sample-signal input is selected by the SHS bits in ADC12CTL1. There are four choices for the sample-signal input: ADC12SC, Timer_A.OUT1, Timer_B.OUT0, and Timer_B.OUT1. The polarity of the sample-signal input may be selected by the ISSH bit (see Figure 15-16). Also, the sample-signal input is passed to the sampling timer or to the SAMPCON signal under control of the ENC bit. This is discussed in detail further ahead. ADC12SC is a control bit located in ADC12CTL0. Its value is set by software. Depending on the selected sampling mode, this bit allows the software to either start a sample-and-conversion (S/C) cycle (SHP=1), or to completely control the sampling period (SHP=0). The sample-signal input can be asynchronous to a conversion-enable, and is synchronized and enabled by the ENC bit. Without synchronization, the first sampling period after the ENC bit is set could be erroneous, depending on where the ENC bit is set within the cycle of the input signal. In Figure 15-18, for example, note that the ENC bit is set in the middle of a high pulse from the sample-signal input. If the sample-input signal were simply passed directly to the S/H, the first conversion of the example would be erroneous because the first sampling period is too short.
ADC12
15-23
Sampling
To prevent this problem, synchronization logic is implemented in the sample input selection switch. This ensures that the first sample-and-conversion cycle begins with the first rising edge of the sample-input signal applied after the ENC bit is set. Additionally, the last sample-and-conversion begins with the first rising edge of the sample-input signal after ENC has been reset.
Figure 15-16. Synchronized Sample and Conversion Signal With Enable Conversion
Enable Conversion ENC Sample-Signal Input t ssync t esync t ENC
SHI Sample and conversions Trigger signal enabled
15.7.3 Sampling Modes
The sampling circuitry has two modes of operation: pulse-sampling mode and extended-sampling mode. In pulse-sampling mode, the sample-signal input (selected by the SHS bits in ADC12CTL1) is used to trigger the internal sampling timer, and the actual sample timing signal (SAMPCON) is then generated by the sampling timer and is an integer multiple of the ADC12CLK signal. In extended-sampling mode, the sampling-signal input bypasses the sample timer and is used to source SAMPCON directly, therefore completely controlling the sample timing--asynchronously to ADC12CLK. Note that 13 ADC12CLK cycles are still required to complete one conversion.
15.7.3.1 Pulse-Sample Mode
In the pulse-sample mode, the sample-input signal, selected by the SHS bits, triggers the sampling timer with its rising edge. The sampling timer then generates the sample timing. The sampling time is programmable by the SHT0 or SHT1 bits located in ADC12CTL0. When conversion-memory registers ADC12MEM0 to ADC12MEM7 are selected to store the conversion result(s), the SHT0 bits are used to program the sampling time. When conversionmemory registers ADC12MEM8 to ADC12MEM15 are selected for the conversion data, the SHT1 bits are used to program the sampling timing. Therefore, it is possible to program two different sampling times for a sequence of conversions by using both upper and lower conversion-memory registers in the sequence. This feature is useful when different external-source impedance conditions exist and require different sample timings.
15-24
Sampling
In pulse-sampling mode, sampling time is a multiple of the ADC12CLK x 4, and is calculated by: tsample = 4 x tADC12CLK x SHTx SHTx is determined by bits SHT0 or SHT1 (see table in Control Registers ADC12CTL0 and ADC12CTL1 section). The sampling signal SAMPCON remains in the sampling state (high) for the synchronization time tsync and the selected sample time tsample, as shown in Figure 15-17. The conversion takes 13 x ADC12CLK cycles (tconvert). It is important to note that after a sample-and-conversion cycle has been triggered by the sample-input signal, additional triggers (via a rising edge on the sampleinput signal) will be missed/ignored until the prior sample-and-conversion cycle is completed.
Figure 15-17. Conversion Timing, Pulse-Sample Mode
SAMPCON
ADC12CLK t sample t sync t convert
An example of the pulse-sample mode configuration is shown in Figure 15-18. The selected input signal source is Timer_B.OUT0. The timing for the example is shown in Figure 15-19.
Figure 15-18. Pulse-Sample Mode Example Configuration
Internal ADC12SSEL ADC12ON ADC12DIV ADC12OSC Oscillator
VR-
analog input signal Sample and Hold
VR+
ADC12CLK
Divider by 1,2,3,4,5,6,7,8
ACLK MCLK SMCLK
12-bit A/D converter core
SHP
SHT0 SHT1
ISSH
S/H
Sampling SAMPCON Timer SYNC MSC ENC SHS
ADC12SC Timer_A.OUT1 Timer_B.OUT0 Timer_B.OUT1
SHI
12-bit S A R
Conversion CTL
ADC12
15-25
Sampling
Figure 15-19. Pulse-Sample Mode Example Timing
Timer_B.OUT0 SAMPCON Additional edges are ignored until after conversion completes
ADC12CLK tsample tsync tconvert Next sync and sample
15.7.3.2 Extended-Sample Mode
In extended-sample mode, the input signal selected by the SHS bits is used to control the sampling (SAMPCON signal) directly. The internal sampling timer is not used. As shown in Figure 15-20, the sampling period is active while SAMPCON is high. Hold mode is active when SAMPCON is low. The conversion starts with the falling edge of SAMPCON after a synchronization time tsync. The conversion takes 13 x ADC12CLK (tconvert).
Figure 15-20. Conversion Timing for Extended-Sample Mode
Sample-Input Signal SAMPCON
ADC12CLK t sample t sync t convert
The extended-sample mode allows total control of the sampling period and the start of a conversion. The extended-sample mode is useful in applications that require an extended sampling period to accommodate different input-source impedances, or in applications where the maximum sampling period supplied by the internal sampling timer is insufficient. An example of the extended-sample-mode configuration is shown in Figure 15-21. The selected input signal source is Timer_B.OUT0. The timing for the example is shown in Figure 15-22.
15-26
Sampling
Figure 15-21. Extended-Sample Mode Example Configuration
Internal ADC12SSEL ADC12ON ADC12DIV ADC12OSC Oscillator
VR-
analog input signal Sample and Hold
VR+
ADC12CLK
Divide by 1,2,3,4,5,6,7,8
ACLK MCLK SMCLK
12-bit A/D converter core
SHT0 SHT1 SHP Sampling
ISSH
S/H
ADC12SC SYNC Timer_A.OUT1 Timer_B.OUT0 Timer_B.OUT1
SAMPCON
Timer
SHI
MSC
12-bit S A R
Conversion CTL
ENC SHS
Figure 15-22. Extended-Sample Mode Example Timing
Timer_B.OUT0
ADC12CLK
t
sample
t convert t sync
15.7.4 Using the MSC Bit
The multiple-sample-and-conversion (MSC) control bit is not used if the sample signal SAMPCON is generated without the sampling timer. However, when the sampling timer is used to generate the SAMPCON signal and the operating mode is other than single-channel single-conversion (CONSEQ > 0), the MSC bit can be used to configure the converter to perform the successive conversions automatically and as quickly as possible. If MSC = 0, then a rising edge of the SHI signal is required to trigger each sample-and-conversion, regardless of what mode the converter is in. When MSC = 1 and CONSEQ > 0, the first rising edge of the SHI signal triggers the first conversion, but successive conversions are triggered automatically as soon as the prior conversion is completed. Additional rising edges on SHI are ignored until the sequence is completed or until the ENC bit is toggled (depending on mode). The function of the ENC bit is unchanged when using the MSC bit. See Figures 15-23 and 15-24.
ADC12
15-27
Sampling
Figure 15-23. Use of MSC Bit With Nonrepeated Modes
ADC12CLK SHT0 SHT1 SHP SAMPCON Sampling Timer SHI
ENC SHI SAMPCON Single channel MSC = 0
SAMPCON
Single channel
MSC = 1
SAMPCON
1
S/C
2
S/C
3
S/C
4
S/C S/C S/C
Sequence of Channel Sequence of Channel
MSC = 0
1 SAMPCON
S/C
2
S/C
3
S/C
4
S/C
1
S/C
2
S/C
3
S/C
4
S/C
MSC = 1
S/C
Conversion Period Sample Period
Figure 15-24. Use of MSC Bit With Repeated Modes
ADC12CLK
SHT0 SHT1 SHP 1
SAMPCON Sampling
Timer SHI
0
ENC
SHI
SAMPCON
S/C
Repeat Single
Channel
Repeat Single
MSC = 0
SAMPCON
S/C S/C S/C S/C S/C S/C S/C S/C S/C S/C S/C S/C S/C
Channel 1 2
S/C
MSC = 1
3
S/C
1
S/C
2
3
1
Repeat Sequence
SAMPCON
S/C
of Channel 1
S/C S/C
MSC = 0
2
S/C
3
S/C
1
S/C
2
S/C
3
S/C
1
S/C
2
S/C
3
S/C
1
S/C
2
S/C
3
S/C
1
S/C
2
S/C
3
S/C
1
S/C
Repeat Sequence of Channels
MSC = 1
Conversion Period Sample Period
15-28
Sampling
15.7.5 Sample Timing Considerations
The A/D converter uses the charge redistribution method. Thus, when the inputs are internally switched to sample the input analog signal, the switching action causes displacement currents to flow into and out of the analog inputs. These current spikes or transients occur at the leading and falling edges of the sample pulse, and usually decay and settle before causing any problems because typically the external time constant is less than that presented by the internal effective RC. Internally, the analog inputs see an effective maximum nominal RC of a 30 pF (C-array) capacitor in series with a 2-k resistor (Ron of switches). However, if the external dynamic-source impedance is large, then these transients may not settle within the allocated sampling time to ensure 12 bits of accuracy. It is imperative that the proper sample timing be used for accurate conversions. The next section discusses how to calculate the sample timing.
15.7.5.1 Simplified Sample-Timing Analysis
Using the equivalent circuit shown in Figure 15-25, the time required to charge the analog-input capacitance from 0 to VS within 1/2 LSB can be derived as follows.
Figure 15-25. Equivalent Circuit
MSP430 Rs VS VI ri VC Ci VI = Input voltage at pin Ax VS = External driving-source voltage Rs = Source resistance (must be real at input frequency) ri = Input resistance (MUX-on resistance) Ci = Input capacitance VC= Capacitance-charging voltage
The capacitance-charging voltage is given by: V
C
+ VS
1-EXP
-tc Rt C i
(1)
Where: Rt = Rs + Zi tc = Cycle time The input impedance Zi is ~1 k at 3.0 V, and is higher (~ 2 k) at 1.8 V. The final voltage to 1/2 LSB is given by: V (1 2LSB)
C
+ VS-
S 8192
V
(2)
Equating equation 1 to equation 2 and solving for cycle time tc gives: V S V- S 8192
+ VS
1-EXP
-tc Rt C i
(3)
ADC12
15-29
ADC12 Control Registers
and the time to charge to 1/2 LSB (minimum sampling time) is: tch(1/2 LSB) = Rt x Ci x In(8192) Where: In(8192) = 9.011 Therefore, with the values given, the time for the analog input signal to settle is: tch(1/2 LSB) = (Rs + 1 k) x Ci x 9.011 This time must be less than the sampling time. If the pulse-sampling mode is used, the maximum ADC12CLK frequency is: max[f(ADC12CLK)] (4)
+t
SHTx (1 2LSB) ch
(5)
This frequency must not exceed the maximum ADC12CLK frequency specified in the data sheet.
15.8 ADC12 Control Registers
Five control registers, sixteen conversion-memory registers, and sixteen conversion-memory control registers are used to configure the ADC12:
Register ADC control register 0 ADC control register 1 ADC interrupt flag register ADC interrupt enable register ADC interrupt vector word ADC memory 0 to ADC memory 15 ADC memory control 0 to ADC memory control 15
Note:
Short Form ADC12CTL0 ADC12CTL1 ADC12IFG ADC12IE ADC12IV ADC12MEM0
Register Type Read/write Read/write Read/write Read/write Read Read
Address 01A0h 01A2h 01A4h 01A6h 01A8h 0140h
Initial State Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Unchanged
ADC12MEM15 ADC12MCTL0 Read ADC12MCTL15
015Eh 080h Reset with POR 08Fh
All registers may be accessed by any instruction subject to register-access restrictions.
15-30
ADC12 Control Registers
15.8.1 Control Registers ADC12CTL0 and ADC12CTL1
All control bits of ADC12CTLx are reset during POR. Most of the control bits in registers ADC12CTL0, ADC12CTL1, and ADC12MCTLx can only be modified if ENC is reset. These bits are marked . All other bits can be modified at any time. The control bits of control register ADC12CTL0 and ADC12CTL1 are:
15
8
SHT1 SHT0 rw-(0) rw-(0) rw-(0)
7
MSC rw-(0) 2_5V rw-(0) REF ON ADC12 ADC12 ADC12 OVIE ON TOVIE rw-(0) rw-(0)
0
ADC12 ENC SC rw-(0) rw-(0)
ADC12CTL0 01A0h
rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)
rw-(0) rw-(0)
ADC12SC
bit0
Sample and convert. The ADC12SC bit can be used to control the conversion with software if ENC is set. It is recommended to have ISSH=0. If the sampling signal SAMPCON is generated by the sampling timer (SHP=1), changing the ADC12SC bit from 0 to 1 starts the sample-andconversion operation. When the A/D conversion is complete (BUSY=0) the ADC12SC bit is automatically reset. If the sample signal is directly controlled by ADC12SC (SHP=0), then the high level of the ADC12SC bit defines the sample time. The conversion starts once it is reset. All automatic-sequence functions (CONSEQ={1,2,3}) and multiple sampleand-conversion functions (MSC=1) are executed normally. Therefore, when using ADC12SC the software must ensure that the frequency of the timing of the ADC12SC bit meets the applicable timing requirements. NOTE: The start of a conversion by software (SHS=0, in ADC12CTL1) is possible by setting both ENC and ADC12SC control bits within one instruction.
ENC
bit1
Enable conversion. The software (via ADC12SC) or external signals can start a conversion only if the enable-conversion bit ENC is high. Most of the control bits in ADC12CTL0 and ADC12CTL 1, and all bits in ADCMCTL.x may be changed only if ENC is low. 0 : No conversion can be started. This is the initial state. 1 : The first sample and conversion starts with the first rising edge of the SAMPCON signal. The selected operation proceeds as long as ENC is set. CONSEQ=0, ADC12BUSY=1, ENC= 1 0: In this mode, if ENC is reset, the current conversion is immediately stopped. The conversion results are unpredictable. CONSEQ0, ADC12BUSY=x, ENC= 1 0: In these modes, if ENC is reset, the current conversion or sequence is completed and the conversion results are valid. The conversion activities are stopped after the current conversion or sequence is completed.
ADC12
15-31
ADC12 Control Registers
ADC12TOVIE
bit2
Conversion-time-overflow interrupt enable. The timing overflow happens if another sample-and-conversion is requested while the current conversion is not completed. This is independent of the conversion modes selected by CONSEQ. If the timing overflow vector is generated and the timing overflow interrupt enable flag ADC12TOVIE and the general interrupt enable bit GIE are set, an interrupt service is requested. There is no individual interrupt flag. See the ADC12 Interrupt Vector Register ADC12IV section for more information on ADC12 interrupts. Overflow-interrupt enable. Individual enable for the overflow-interrupt vector. The overflow happens if a conversion result is written into an ADC memory ADC12MEMx but the previous result was not read. An interrupt service is requested if the overflow vector is generated, the overflow-interrupt-enable flag ADC12OVIE is set, and the general-interrupt-enable bit GIE is set. There is no individual interrupt flag. See the ADC12 Interrupt Vector Register ADC12IV section for more information on ADC12 interrupts. Turn on the 12-bit ADC core. Settling-time constraints must be met when the ADC12 core is powered up. 0: Power consumption of the core is off. No conversion will be started. 1: ADC core is supplied with power. If no A/D conversion is needed, ADC12ON can be reset to conserve power.
ADC12OVIE
bit3
ADC12ON
bit4
REFON
bit5
Reference voltage ON. 0: The internal-reference voltage is switched off. No power is consumed from the reference-voltage generator. 1: The internal-reference voltage is switched on. The reference-voltage generator consumes power. When the reference generator is switched on, the settling time of the reference voltage must be completed before the first sampling and conversion is started.
2_5V
bit6
Reference-voltage level. 0: The internal reference voltage is 1.5V, if REFON = 1. 1: The internal reference voltage is 2.5V, if REFON = 1.
MSC
bit7
Multiple sample and conversion. Valid only when the sample timer is selected to generate the SAMPCON signal (SHP=1) and the A/D mode is chosen as repeat-single-channel, sequence-of-channel or repeatsequence-of-channels (CONSEQ0). 0: The sampling timer requires a rising edge of the SHI signal to trigger each sample-and-conversion. 1: The first rising edge of the SHI signal triggers the sampling timer, but further sample-and-conversion are performed automatically as soon as the prior conversion is completed--without additional rising edges of SHI. Additional rising edges of SHI are ignored until the sequence has completed or the ENC bit has been toggled (depending on mode).
15-32
ADC12 Control Registers
SHT0
bits 8-11
Sample-and-hold Time0. These bits define the sample timing for conversions whose results are stored in conversion-memory registers ADC12MEM0 to ADC12MEM7. The sample time is a multiple of the ADC12CLK x 4: tsample = 4 x ADC12CLK x n SHT0 n 0 1 1 2 2 4 3 8 4 16 5 24 6 32 7 48 8 64 9 96 10 11 12-15 256
128 192
SHT1
bits Sample-and-hold Time1. These bits define the sample timing for 12-15 conversions whose results are stored in conversion-memory registers ADC12MEM8 to ADC12MEM15. The sample time is a multiple of the ADC12CLK x 4: tsample = 4 x ADC12CLK x n SHT1 n 0 1 1 2 2 4 3 8 4 16 5 24 6 32 7 48 8 64 9 96 10 11 12-15 256
128 192
15
8
CSStartAdd
SHS SHP
ISSH
7
ADC12DIV ADC12SSEL CONSEQ
0
ADC12 BUSY
ADC12CTL1 01A2h
rw -(0) rw -(0) rw -(0) rw -(0) rw -(0) rw -(0) rw -(0) rw -(0) rw -(0) rw -(0) rw -(0) rw -(0) rw -(0) rw -(0) rw -(0)
r -(0)
ADC12BUSY
bit0
The ADC12BUSY bit indicates an active sample or conversion operation. It is used specifically when the conversion mode is single-channelsingle-conversion, because if the ENC bit is reset in this mode, the conversion stops immediately and the results are invalid. Therefore, the ADC12BUSY bit should be tested to verify that it is 0 before resetting the ENC bit when in single-channel-single-conversion mode. The busy bit is not useful in all other operating modes because resetting the ENC bit does not immediately affect any other mode. 0: No operation is active. 1: A sample period, conversion or conversion sequence is active.
CONSEQ
bits 1-2
The CONSEQ bits select the conversion mode. Repeat mode is on if the CONSEQ.1 is set. 0: Single-channel-single-conversion mode. One single channel is converted once. 1: Sequence-of-channels mode. A sequence of conversions is executed once. 2: Repeat-single-channel mode. Conversions on a single channel are repeated until CONSEQ is set to 0 or 1. 3: Repeat-sequence-of-channels. A sequence of conversions is repeated until CONSEQ is set to 0 or 1. NOTE: See also section Conversion Modes.
ADC12
15-33
ADC12 Control Registers
ADC12SSEL
bits 3-4
Select the clock source for the converter core 0: 1: 2: 3: ADC12 internal oscillator, ADC12OSC ACLK MCLK SMCLK
ADC12DIV
bits 5-7
Select the division rate for the clock source selected by ADC12SSEL bits. 0 to 7: Divide selected clock source by 1 to 8 The divider's output signal name is ADC12CLK. Thirteen of these clocks are required for a conversion. Invert sample-input signal. 0: The sample-input signal is not inverted. 1: The sample-input signal is inverted.
ISSH
bit8
SHP
bit9
The SHP bit selects the source of the sampling signal (SAMPCON) to be either the output of the sampling timer or the sample-input signal directly. 0: SAMPCOM signal is sourced directly from the sample-input signal. 1: SAMPCON signal is sourced from the sampling timer. The rising edge of the sample-input signal triggers the sampling timer.
SHS
bits Source select for the sample-input signal. 10-11 0: Control bit ADC12SC is selected. 1: Timer_A.OUT1 2: Timer_B.OUT0 3: Timer_B.OUT1 bits Conversion start address CStartAdd is used to define which ADC12 12-15 conversion-memory register (ADC12MEMx) is used for a single conversion or for the first conversion in a sequence of conversions. The value of CStartAdd is 0 to 0Fh, corresponding to ADC12MEM0 to ADC12MEM15. Since there is one corresponding conversion-memory control register (ADC12MCTLx) for each conversion-memory register (ADC12MEMx), CStartAdd also points to the corresponding ADC12MCTLx register.
CStartAdd
Warning : Modifying ADC control register during active conversion The enable conversion control bit (ENC) in the ADC12CTL0 register protects most bits from modification during an active conversion. However, some bits that are necessary for proper completion of active conversions and interrupt enable bits can be modified independently of ENC. The user must use caution when modifying theses bits to ensure an active conversion is not corrupted, or to not use corrupted data. To avoid corrupting any active conversions, stop the conversion, wait for the busy bit to be reset, reset the ENC bit, then modify the control bits.
15-34
ADC12 Control Registers
15.8.2 Conversion-Memory Registers ADC12MEMx
There are sixteen conversion-memory registers ADC12MEMx as follows:
15 12 11
0
LSB
ADC12MEM 0140h...015Eh r0
0
r0
0
r0
0
r0
0
MSB
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
ADC12MEM0, to ADC12MEM15
bits 0-15
Conversion results. The 12-bit conversion results are right-justified and the four MSBs are always read as 0. The ADC12OV interrupt flag will be set in time to indicate that a overflow situation occurred. Software can detect it if it reads the conversion result and then tests for overflow condition. The corresponding interrupt flag is reset if ADC12MEMx is accessed.
Warning : SOFTWARE WRITE TO REGISTER ADC12MEMx
TYPICALLY, SOFTWARE SHOULD NOT WRITE TO THE CONVERSION RESULT REGISTERS ADC12MEMX. IF SOFTWARE WRITES TO ONE OF THESE REGISTERS WHILE THE ADC12 IS ATTEMPTING TO WRITE TO THE SAME REGISTER, THE DATA IN THE REGISTER WILL BE UNPREDICTABLE. IF SOFTWARE ENSURES THAT IT IS WRITING TO A CONVERSION RESULT REGISTER THAT IS NOT BEING ACCESSED BY THE ADC12, THEN THE WRITE COMPLETES NORMALLY AND THE DATA IS WRITTEN CORRECTLY. THE ASSOCIATED INTERRUPT FLAG IS RESET.
15.8.3 Control Registers ADC12MCTLx
Each conversion-memory register ADC12MEMx has its own control register ADC12CTLx. The conversion-memory registers hold the conversion results, and the control register for each conversion-memory register selects basic conversion conditions such as selecting the analog channel, the reference voltage sources for VR+ and VR-, and indicating the end of a sequence. All control bits in ADC12CTLx are reset during POR (see Chapter 3 for POR details). The control registers ADC12MCTL.x can be modified only if the enable conversion control bit ENC is reset. Any instruction that writes to an ADC12MCTL register while the ENC bit is set will have no effect.
ADC12
15-35
ADC12 Control Registers
7
0
Sref, source of reference
rw-(0) rw-(0) rw-(0) rw-(0)
ADC12MCTLx
EOS
080h...08Fh
rw-(0)
INCH, input channel a0 to a11
rw-(0) rw-(0) rw-(0)
INCH,
bits 0-3
The INCH (input channel) bits select one of eight external, or one of four internal analog signals for conversion. 0-7: a0 to a7 8: VeREF+ 9: VREF- /VeREF- 10: Temperature diode 11-15: (AVCC - AVSS) / 2 Note: Selecting channel 10 automatically turns on the on-chip reference generator for a voltage source for the temperature diode. However, it does not enable the VREF+ output or effect the reference selections for the conversion. The Sref bits select one of six reference voltage combinations used for conversion. The conversion is done between the selected voltage range VR+ and VR-. 0: VR+ = AVCC and VR- = AVSS 1: VR+ = VREF+ and VR- = AVSS 2,3: VR+ = VeREF+ and VR- = AVSS 4: VR+ = AVCC and VR- = VREF-/ VeREF- 5: VR+ = VREF+ and VR- = VREF-/ VeREF- 6,7: VR+ = VeREF+ and VR- = VREF-/ VeREF- The end-of-sequence bit, when set, indicates the last conversion in a sequence of conversions. Note: A sequence will roll over from ADC12MEM15/ADC12MCTL15 to ADC12MEM0/ADC12MCTL0 if the EOS bit in ADC12MCTL15 is not set. Note: If none of the EOS bits is set and a sequence-of-channels (CONSEQ={1,3}) is selected, resetting the ENC bit will not stop the sequence. To stop the sequence, first select a single-channel mode (CONSEQ={0,2}) and then reset ENC. See also the ENC bit description.
Sref,
bits4-6
EOS,
bit7
15-36
ADC12 Control Registers
15.8.4 ADC12 Interrupt Flags ADC12IFG.x and Interrupt-Enable Registers ADC12IEN.x
There are 16 ADC12IFG.x interrupt flags, 16 ADC12IE.x interrupt enable bits, and one interrupt vector word. The interrupt flags and enable bits are associated with the 16 ADC12MEMx registers. All interrupt flags and interrupt-enable bits are reset during POR.
15
0
ADC IFG.14 ADC IFG.13 ADC IFG.12 ADC IFG.11 ADC IFG.10 ADC IFG.9 ADC IFG.8 ADC IFG.7 ADC IFG.6 ADC IFG.5 ADC IFG.4 ADC IFG.3 ADC IFG.2 ADC IFG.1 ADC IFG.0
ADC12IFG 0184h
ADC IFG.15
rw -(0) rw -(0) rw -(0) rw -(0)
rw -(0) rw -(0) rw -(0) rw -(0) rw -(0) rw -(0) rw -(0) rw -(0) rw -(0) rw -(0) rw -(0) rw -(0)
ADC12IFG.x,
bits 0-15 The ADC12IFG.x interrupt flag is set if a conversion-result register ADC12MEMx is loaded with the result of a conversion. The range for x is 0 to 15. The interrupt flags are reset if their corresponding ADC12MEMx conversion-result register is accessed. To enable correct handling of overflow conditions, they are not reset by accessing the interrupt vector word ADC12IV. The overflow condition exists if another conversion result is written to ADC12MEMx and the corresponding ADC12IFG.x is not reset.
0
ADC IE.14 ADC IE.13 ADC IE.12 ADC IE.11 ADC IE.10 ADC IE.9 ADC IE.8 ADC IE.7 ADC IE.6 ADC IE.5 ADC IE.4 ADC IE.3 ADC IE.2 ADC IE.1 ADC IE.0
15
ADC12IE 01A6h
ADC IE.15
rw -(0) rw -(0) rw -(0) rw -(0) rw -(0) rw -(0) rw -(0) rw -(0) rw -(0) rw -(0) rw -(0) rw -(0) rw -(0) rw -(0) rw -(0) rw -(0)
ADC12IE.x, bits 0-15
The ADC12IE.x interrupt-enable bit enables or disables the interruptrequest service generated if the corresponding interrupt flag ADC12IFG.x is set. The range for x is 0 to 15.
15.8.5 ADC12 Interrupt Vector Register ADC12IV
The 12-bit ADC has one interrupt vector to assist the handling of the 18 possible interrupt flags. Each of the 18 interrupt flags is prioritized and a unique vector word is generated according to the highest-pending interrupt. The priorities and corresponding vector-word values are shown in Table 15-3. Overflow flag ADC12OVIFG has the highest priority, followed by timingoverflow flag ADC12TOVIFG, and then by the interrupt flags for each conversion-memory register ADC12IFG.0 to ADC12IFG.15. The highest-pending interrupt flag generates a number from 0 (no interrupt is pending) to 36. This encoded number can be added to the program counter to automatically enter the software routine for handling each specific interrupt (see software example, section 15.8.5.1. An interrupt request is immediately generated if an interrupt flag is pending (ADC12IV0), if the corresponding interrupt enable bit (ADC12OVIE, ADC12TOVIE, or ADC12IE.x) is set, and if the general interrupt enable bit GIE is set. When an interrupt request is generated, the service is requested by the highest-priority interrupt that is enabled.
ADC12
15-37
ADC12 Control Registers
It is important to note that ADC12OVIFG and ADC12TOVIFG are reset automatically when either is the highest pending interrupt and the ADC12IV register is accessed. For example, if both are pending simultaneously, ADC12OVIFG will be reset automatically with the first access of ADC12IV, and ADC12TOVIFG will be reset automatically with the next access to the ADC12IV (assuming ADC12OVIFG was not set again). However, flags ADC12IFG.x must be reset by software or reset by accessing the corresponding conversion-memory register ADC12MEMx. Also note that the flags ADC12OVIFG and ADC12TOVIFG can not be accessed by software. They are visible only via the interrupt vector word ADC12IV data.
Table 15-3.ADC12IV Interrupt-Vector Values
ADC Interrupt Flags ADC12IFG ADC12TOV 15 0 x x x x : x 1 14 0 x x x x : 1 0 13 0 x x x x : 0 0 12 0 x x x x : 0 0 11 0 x x x x : 0 0 10 0 x x x x : 0 0 9 0 x x x x : 0 0 8 0 x x x x : 0 0 7 0 x x x x : 0 0 6 0 x x x x : 0 0 5 0 x x x x : 0 0 4 0 x x x x : 0 0 3 0 x x x x : 0 0 2 0 x x x x : 0 0 1 0 x x x 1 : 0 0 0 0 x x 1 0 : 0 0 0 x 1 0 0 : 0 0 0 1 0 0 0 : 0 0 0 2 4 6 8 : 34 36 ADC12OV ADC12IV
Note: Writing to Read Only Register ADC12IV When a write to vector word register ADC12IV occurs, the highest-pending interrupt flag is reset. Therefore, the interrupt event is missed.
15-38
ADC12 Control Registers
15.8.5.1 ADC Interrupt Vector Register, Software Example
The following software example shows the use of vector word ADC12IV and the associated software overhead. The numbers at the right margin show the cycles required for every instruction. The example shows a basic interrupt handler structure that can be adopted to individual application requirements. The software overhead for the different interrupt sources, including interrupt latency and return-from-interrupt cycles (but not the task handling itself), is:
-
ADC12IFG.0 to ADC12IFG.14, ADC12OV ADC12IFG.15
16 cycles 14 cycles
; Interrupt handler for the 12-bit ADC. ; The flag, which is enabled and has the highest priority, ; determines the interrupt vector word and is reset by ; hardware after accessing (instruction ; ADD &TADC12IV,PC). Flags ADC12OV, ADC12TOV, and ; ADC12IFG.x are reset by hardware. ADC_HND $ ; Interrupt latency 6 ADD &ADC12IV,PC ; Add offset to Jump table 3 RETI ; Vector 0: No interrupt 5 JMP ADC12OV ; Vector 2: ADC overflow 2 JMP ADC12TOV ; Vector 4: ADC timing overflow 2 JMP ADC12MOD0 ; Vector 6: ADC12MEM0 was loaded ...................... ; (ADC12IFG.0) 2 JMP ADC12MOD1 ; Vector 8: ADC12MEM1 was loaded ...................... ; (ADC12IFG.1) 2 : : JMP ADC12MOD13 ; Vector 34: ADC12MEM14 was loaded ; (ADC12IFG.14) 2 JMP ADC12MOD14 ; Vector 36: ADC12MEM15 was loaded ; (ADC12IFG.15) 2 ; ; Module 15. Handler for ADC12IFG.15 starts here. Note a JMP ; instruction is not needed to get here because the PC is ; already here after the ADD&ADC12IV,PC instruction. ; ADC12OV ... ; Vector 2: ADC12OV Flag ... ; First instruction to handle ADC12 ; overflow condition RETI 5 ; ADC12TOV ... ; Vector 4: ADC12OV Flag ... ; First instruction to handle ADC12 timing ; overflow condition RETI 5 ; ADC12MOD2 ; Vector 10: ADC12MEM2 was loaded ; (ADC12IFG.2) MOV &ADC12MEM2,R6 ; ADC12IFG2 is reset due to access ; of ADC memory ... ; Task starts here
ADC12
15-39
ADC12 Control Registers
RETI ; ADC12MOD1 ; Back to main program 5
; Vector 8: ADC12MEM1 was loaded ; (ADC12IFG.1) ADD &ADC12MEM1,R6 ; ADC12IFG1 is reset due to access ; of ADC memory ... ; Task starts here RETI ; Back to main program 5 ; The Module 3 handler shows a way to look if any other ;interrupt is pending: 5 cycles have to be spent, but 9 cycles ; may be saved if another interrupt is pending ; ADC12MOD0 ; Vector 6: ADC12MEM0 was loaded ; (ADC12IFG.0) ... ; First instruction to be executed x ... ; Task starts here JMP ADC12_HND ; With this instruction the software ; does not leave the handler; it looks ; for pending ADC12 interrupts 2 ; .SECT "VECTORS",0FFF4h ; Interrupt Vectors .WORD ADC12_HND ; Vector for 12-bit ADC interrupt ; flags and overflow
Note: Basic Clock System If the CPU clock MCLK is turned off (CPUOff=1), then two or three additional cycles need to be added for synchronous start of the CPU system. The delta of one clock cycle is caused when clocks are asynchronous to the restart of CPU clock MCLK.
15-40
A/D Grounding and Noise Considerations
15.9 A/D Grounding and Noise Considerations
As with any high-resolution converter, care and special attention must be paid to the printed-circuit-board layout and the grounding scheme to eliminate ground loops and any unwanted parasitic components/effects and noise. Industry-standard grounding and layout techniques should be followed to reduce these unwanted effects. Ground Loops are formed when return current from the A/D flows through paths that are common with other analog or digital circuitry. If care is not taken, this current can generate small, unwanted offset voltages that can add to or subtract from the reference or input voltages of the A/D converter. One way to avoid ground loops is to use a star connection scheme for AVSS (shown in Figure 15-26). This way the ground current or reference currents do not flow through any common input leads, eliminating any error voltages. The digital ground DVSS and analog ground AVSS can also be star-connected together. If separate supplies are used, two reverse biased diodes can be used to limit the voltage difference to less than 700mV. In addition to grounding, ripple and noise spikes on the power supply lines due to digital switching or switching power supplies can corrupt the conversion result. The ripple can become more dominant by reducing the value of the conversion voltage range (VR+ - VR-), therefore reducing the value of the LSB and the noise margin. Thus a clean, noise-free setup becomes even more important to achieve the desired accuracy. Adding carefully placed bypass capacitors returned to the respective ground planes can help in reducing ripple in the supply current and minimizing these effects.
Figure 15-26. A/D Grounding and Noise Considerations
A/D AVCC 22 F 0.1 F Ceramic Tantalum
VIN
+ -
CCCCCC CCCCCC EEEEEE CCCCCC EEEEEE CCCCCC EEEEEE CCCCCC CCCCCC CCCCCC CCCCCC CCCCCC
+ VREF -
VeREF+
VREF+ DVCC 22 F Tantalum 0.1 F Ceramic A0. . . 7
AVSS
DVSS
ADC12
15-41
15-42
Appendix A
Peripheral File Map
This appendix summarizes the peripheral file (PF) and control-bit information into a single location for reference. Each PF register is presented as a row of boxes containing the control or status bits belonging to the register. The register symbol (e.g. P0IN) and the PF hex address are to the left of each register.
Topic
A.1 A.2 A.3 A.4 A.5 A.6 A.7 A.8 A.9
Page
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 Special Function Register of MSP430x1xx Family, Byte Access . . . A-3 Digital I/O, Byte Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3 Basic Clock Registers, Byte Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5 EPROM Control Register Byte Access . . . . . . . . . . . . . . . . . . . . . . . . . . A-5 Comparator_A Registers, Byte Access . . . . . . . . . . . . . . . . . . . . . . . . . A-5 USART0, USART1, UART Mode (Sync=0), Byte Access . . . . . . . . . . . A-6 USART0, USART1 SPI Mode (Sync=1), Byte Access . . . . . . . . . . . . . A-7 ADC12 Registers, Byte and Word Access . . . . . . . . . . . . . . . . . . . . . . . A-8
A.10 Watchdog/Timer, Word Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-11 A.11 Flash Control Registers, Word Access . . . . . . . . . . . . . . . . . . . . . . . . . A-11 A.12 Hardware Multiplier, Word Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-12 A.13 Timer_A Registers, Word Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-13 A.14 Timer_B Registers, Word Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-15
Peripheral File Map
A-1
Overview
A.1 Overview
Bit accessibility and/or hardware definitions are indicated following each bit symbol:
-
rw: r: r0: r1: w: w0: w1: (w):
Read/write Read only Read as 0 Read as 1 Write only Write as 0 Write as 1 No register bit implemented; writing a 1 results in a pulse. The register bit is always read as 0. Cleared by hardware Set by hardware Condition after PUC signal active Condition after POR signal active
h0: h1: -0,-1: -(0),-(1):
The tables in the following sections describe byte access to each peripheral file according to the previously-described definitions.
A-2
Special Function Register of MSP430x1xx Family, Byte Access
A.2 Special Function Register of MSP430x1xx Family, Byte Access
000Fh
Module enable 2, ME2 0005h Module enable 1, ME1 0004h Interrupt flag 2, IFG2 0003h Interrupt flag 1, IFG1 0002h Interrupt enable 2, IE2 0001h Interrupt enable 1, IE1 0000h UTXIE0 rw-0 URXIE0 rw-0 UXIFG0 rw-1 URXIFG0 rw-0 UTXE0 rw-0 URXE0 USPIE0 rw-0
UTXE1 rw-0
URXE1 USPIE1 rw-0
UTXIFG1 rw-1
URXIFG1 rw-0 NMIIFG rw-0 OFIFG rw-1 WDTIFG rw-0
UTXIE1 rw-0 ACCVIE rw-0
URXIE1 rw-0 NMIIE rw-0 OFIE rw-0 WDTIE rw-0
Note:
SFR bits are not implemented on devices without the corresponding peripheral.
A.3 Digital I/O, Byte Access
Bit # Function select, P4SEL 001Fh Direction register, P4DIR 001Eh Output register, P4OUT 001Dh Input register, P4IN 001Ch Function select, P3SEL 001Bh Direction register, P3DIR 001Ah Output register, P3OUT 0019h Input register, P3IN 0018h 0017h 0016h 7 P4SEL.7 rw-0 P4DIR.7 rw-0 P4OUT.7 rw P4IN.7 r P3SEL.7 rw-0 P3DIR.7 rw-0 P3OUT.7 rw P3IN.7 r 6 P4SEL.6 rw-0 P4DIR.6 rw-0 P4OUT.6 rw P4IN.6 r P3SEL.6 rw-0 P3DIR.6 rw-0 P3OUT.6 rw P3IN.6 r 5 P4SEL.5 rw-0 P4DIR.5 rw-0 P4OUT.5 rw P4IN.5 r P3SEL.5 rw-0 P3DIR.5 rw-0 P3OUT.5 rw P3IN.5 r 4 P4SEL.4 rw-0 P4DIR.4 rw-0 P4OUT.4 rw P4IN.4 r P3SEL.4 rw-0 P3DIR.4 rw-0 P3OUT.4 rw P3IN.4 r 3 P4SEL.3 rw-0 P4DIR.3 rw-0 P4OUT.3 rw P4IN.3 r P3SEL.3 rw-0 P3DIR.3 rw-0 P3OUT.3 rw P3IN.3 r 2 P4SEL.2 rw-0 P4DIR.2 rw-0 P4OUT.2 rw P4IN.2 r P3SEL.2 rw-0 P3DIR.2 rw-0 P3OUT.2 rw P3IN.2 r 1 P4SEL.1 rw-0 P4DIR.1 rw-0 P4OUT.1 rw P4IN.1 r P3SEL.1 rw-0 P3DIR.1 rw-0 P3OUT.1 rw P3IN.1 r 0 P4SEL.0 rw-0 P4DIR.0 rw-0 P4OUT.0 rw P4IN.0 r P3SEL.0 rw-0 P3DIR.0 rw-0 P3OUT.0 rw P3IN.0 r
0010h
Peripheral File Map
A-3
Digital I/O, Byte Access (Continued)
A.3 Digital I/O, Byte Access (Continued)
Bit # Function select, P6SEL 0037h Direction register, P6DIR 0036h Output register, P6OUT 0035h Input register, P6IN 0034h Function select, P5SEL 0033h Direction register, P5DIR 0032h Output register, P5OUT 0031h Input register, P5IN 0030h 002Fh Function select, P2SEL 002Eh Interrupt enable, P2IE 002Dh Interrupt edge select, P2IES 002Ch Interrupt flags, P2IFG 002Bh Direction register, P2DIR 002Ah Output register, P2OUT 0029h Input register, P2IN 0028h 0027h Function select, P1SEL 0026h Interrupt enable, P1IE 0025h Int. edge select, P1IES 0024h Interrupt flags, P1IFG 0023h Direction register, P1DIR 0022h Output register, P1OUT 0021h Input register, P1IN 0020h P1SEL.7 rw-0 P1IE.7 rw-0 P1IES.7 rw P1IFG.7 rw-0 P1DIR.7 rw-0 P1OUT.7 rw P1IN.7 r P1SEL.6 rw-0 P1IE.6 rw-0 P1IES.6 rw P1IFG.6 rw-0 P1DIR.6 rw-0 P1OUT.6 rw P1IN.6 r P1SEL.5 rw-0 P1IE.5 rw-0 P1IES.5 rw P1IFG.5 rw-0 P1DIR.5 rw-0 P1OUT.5 rw P1IN.5 r P1SEL.4 rw-0 P1IE.4 rw-0 P1IES.4 rw P1IFG.4 rw-0 P1DIR.4 rw-0 P1OUT.4 rw P1IN.4 r P1SEL.3 rw-0 P1IE.3 rw-0 P1IES.3 rw P1IFG.3 rw-0 P1DIR.3 rw-0 P1OUT.3 rw P1IN.3 r P1SEL.2 rw-0 P1IE.2 rw-0 P1IES.2 rw P1IFG.2 rw-0 P1DIR.2 rw-0 P1OUT.2 rw P1IN.2 r P1SEL.1 rw-0 P1IE.1 rw-0 P1IES.1 rw P1IFG.1 rw-0 P1DIR.1 rw-0 P1OUT.1 rw P1IN.1 r P1SEL.0 rw-0 P1IE.0 rw-0 P1IES.0 rw P1IFG.0 rw-0 P1DIR.0 rw-0 P1OUT.0 rw P1IN.0 r P2SEL.7 rw-0 P2IE.7 rw-0 P2IES.7 rw P2IFG.7 rw-0 P2DIR.7 rw-0 P2OUT.7 rw P2IN.7 r P2SEL.6 rw-0 P2IE.6 rw-0 P2IES.6 rw P2IFG.6 rw-0 P2DIR.6 rw-0 P2OUT.6 rw P2IN.6 r P2SEL.5 rw-0 P2IE.5 rw-0 P2IES.5 rw P2IFG.5 rw-0 P2DIR.5 rw-0 P2OUT.5 rw P2IN.5 r P2SEL.4 rw-0 P2IE.4 rw-0 P2IES.4 rw P2IFG.4 rw-0 P2DIR.4 rw-0 P2OUT.4 rw P2IN.4 r P2SEL.3 rw-0 P2IE.3 rw-0 P2IES.3 rw P2IFG.3 rw-0 P2DIR.3 rw-0 P2OUT.3 rw P2IN.3 r P2SEL.2 rw-0 P2IE.2 rw-0 P2IES.2 rw P2IFG.2 rw-0 P2DIR.2 rw-0 P2OUT.2 rw P2IN.2 r P2SEL.1 rw-0 P2IE.1 rw-0 P2IES.1 rw P2IFG.1 rw-0 P2DIR.1 rw-0 P2OUT.1 rw P2IN.1 r P2SEL.0 rw-0 P2IE.0 rw-0 P2IES.0 rw P2IFG.0 rw-0 P2DIR.0 rw-0 P2OUT.0 rw P2IN.0 r 7 P6SEL.7 rw-0 P6DIR.7 rw-0 P6OUT.7 rw P6IN.7 r P5SEL.7 rw-0 P5DIR.7 rw-0 P5OUT.7 rw P5IN.7 r 6 P6SEL.6 rw-0 P6DIR.6 rw-0 P6OUT.6 rw P6IN.6 r P5SEL.6 rw-0 P5DIR.6 rw-0 P5OUT.6 rw P5IN.6 r 5 P6SEL.5 rw-0 P6DIR.5 rw-0 P6OUT.5 rw P6IN.5 r P6SEL.5 rw-0 P5DIR.5 rw-0 P5OUT.5 rw P5IN.5 r 4 P6SEL.4 rw-0 P6DIR.4 rw-0 P6OUT.4 rw P6IN.4 r P5SEL.4 rw-0 P5DIR.4 rw-0 P5OUT.4 rw P5IN.4 r 3 P6SEL.3 rw-0 P6DIR.3 rw-0 P6OUT.3 rw P6IN.3 r P5SEL.3 rw-0 P5DIR.3 rw-0 P5OUT.3 rw P5IN.3 r 2 P6SEL.2 rw-0 P6DIR.2 rw-0 P6OUT.2 rw P6IN.2 r P5SEL.2 rw-0 P5DIR.2 rw-0 P5OUT.2 rw P5IN.2 r 1 P6SEL.1 rw-0 P6DIR.1 rw-0 P6OUT.1 rw P6IN.1 r P5SEL.1 rw-0 P5DIR.1 rw-0 P5OUT.1 rw P5IN.1 r 0 P6SEL.0 rw-0 P6DIR.0 rw-0 P6OUT.0 rw P6IN.0 r P5SEL.0 rw-0 P5DIR.0 rw-0 P5OUT.0 rw P5IN.0 r
A-4
Basic Clock Registers, Byte Access
A.4
Basic Clock Registers, Byte Access
Bit # - BCSCTL2 0058h BCSCTL1 0057h DCOCTL 0056h 7 SELM.1 rw-0 XT2OFF rw-(1) DCO.2 rw-0 6 SELM.0 rw-0 XTS rw-(0) DCO.1 rw-1 5 DIVM.1 rw-0 DIVA.1 rw-(0) DCO.0 rw-1 4 DIVM.0 rw-0 DIVA.0 rw-(0) MOD.4 rw-0 3 SELS rw-0 XT5V rw-0 MOD.3 rw-0 2 DIVS.1 rw-0 Rsel.2 rw-1 MOD.2 rw-0 1 DIVS.0 rw-0 Rsel.1 rw-0 MOD.1 rw-0 0 DCOR rw-0 Rsel.0 rw-0 MOD.0 rw-0
A.5 EPROM Control Register Byte Access
Bit # - EPROM control register EPCTL 0054h 7 r-0 6 r-0 5 r-0 4 r-0 3 r-0 2 r-0 1 VPPS rw-0 0 EXE rw-0
Non-EPROM devices may use this register for other control purposes.
A.6
Comparator_A Registers, Byte Access
Bit # - 7 CAPD.7 rw-(0) CACTL2.7 rw-(0) CAEX rw-(0) 6 CAPD.6 rw-(0) CACTL2.6 rw-(0) CARSEL rw-(0) 5 CAPD.5 rw-(0) CACTL2.5 rw-(0) CAREF1 rw-(0) 4 CAPD.4 rw-(0) CACTL2.4 rw-(0) CAREF0 rw-(0) 3 CAPD.3 rw-(0) CA1 rw-(0) CAON rw-(0) 2 CAPD.2 rw-(0) CA0 rw-(0) CAIES rw-(0) 1 CAPD.1 rw-(0) CAF rw-(0) CAIE rw-(0) 0 CAPD.0 rw-(0) CAOUT r-(0) CAIFG rw-(0)
Comparator_A Port Disable, CAPD 005Bh Comparator_A control reg. 2, CACTL2 005Ah Comparator_A control reg. 1, CACTL1 0059h
Peripheral File Map
A-5
USART0, USART1, UART Mode (Sync=0), Byte Access
A.7 USART0, USART1, UART Mode (Sync=0), Byte Access
Bit # - USART1 Transmit buffer UTXBUF1 07Fh USART1 Receive buffer URXBUF1 07Eh USART1 Baud rate UBR11 07Dh USART1 Baud rate UBR01 07Ch USART1 Modulation control UMCTL1 07Bh USART1 Receive control URCTL1 07Ah USART1 Transmit control UTCTL1 079h USART1 USART control UCTL1 078h USART0 Transmit buffer UTXBUF0 077h USART0 Receive buffer URXBUF0 076h USART0 Baud rate UBR10 075h USART0 Baud rate UBR00 074h USART0 Modulation control UMCTL0 073h USART0 Receive control URCTL0 072h USART0 Transmit control UTCTL0 071h USART0 USART control UCTL0 070h 7 27 rw 27 r 215 rw 27 rw m7 rw FE rw-0 Unused rw-0 PENA rw-0 27 rw 27 r 215 rw 27 rw m7 rw FE rw-0 Unused rw-0 PENA rw-0 6 26 rw 26 r 214 rw 26 rw m6 rw PE rw-0 CKPL rw-0 PEV rw-0 26 rw 26 r 214 rw 26 rw m6 rw PE rw-0 CKPL rw-0 PEV rw-0 5 25 rw 25 r 213 rw 25 rw m5 rw OE rw-0 SSEL1 rw-0 SP rw-0 25 rw 25 r 213 rw 25 rw m5 rw OE rw-0 SSEL1 rw-0 SP rw-0 4 24 rw 24 r 212 rw 24 rw m4 rw BRK rw-0 SSEL0 rw-0 CHAR rw-0 24 rw 24 r 212 rw 24 rw m4 rw BRK rw-0 SSEL0 rw-0 CHAR rw-0 3 23 rw 23 r 211 rw 23 rw m3 rw URXEIE rw-0 URXSE rw-0 Listen rw-0 23 rw 23 r 211 rw 23 rw m3 rw URXEIE rw-0 URXSE rw-0 Listen rw-0 2 22 rw 22 r 210 rw 22 rw m2 rw URXWIE rw-0 TXWAKE rw-0 SYNC rw-0 22 rw 22 r 210 rw 22 rw m2 rw URXWIE rw-0 TXWAKE rw-0 SYNC rw-0 1 21 rw 21 r 29 rw 21 rw m1 rw RXWake rw-0 Unused rw-0 MM rw-0 21 rw 21 r 29 rw 21 rw m1 rw RXWake rw-0 Unused rw-0 MM rw-0 0 20 rw 20 r 28 rw 20 rw m0 rw RXERR rw-0 TXEPT rw-1 SWRST rw-1 20 rw 20 r 28 rw 20 rw m0 rw RXERR rw-0 TXEPT rw-1 SWRST rw-1
A-6
USART0, USART1, SPI Mode (Sync=1), Byte Access
A.8 USART0, USART1, SPI Mode (Sync=1), Byte Access
Bit # - USART1 Transmit buffer UTXBUF1 07Fh USART1 Receive buffer URXBUF1 07Eh USART1 Baud rate UBR11 07Dh USART1 Baud rate UBR01 07Ch USART1 Modulation control UMCTL1 07Bh USART1 Receive control URCTL1 07Ah USART1 Transmit control UTCTL1 079h USART1 USART control UCTL1 078h USART0 Transmit buffer UTXBUF0 077h USART0 Receive buffer URXBUF0 076h USART0 Baud rate UBR10 075h USART0 Baud rate UBR00 074h USART0 Modulation control UMCTL0 073h USART0 Receive control URCTL0 072h USART0 Transmit control UTCTL0 071h USART0 USART control UCTL0 070h 7 27 rw 27 r 215 rw 27 rw m7 rw FE rw-0 CKPH rw-0 Unused rw-0 27 rw 27 r 215 rw 27 rw m7 rw FE rw-0 CKPH rw-0 Unused rw-0 6 26 rw 26 r 214 rw 26 rw m6 rw Undef. rw-0 CKPL rw-0 Unused rw-0 26 rw 26 r 214 rw 26 rw m6 rw Undef. rw-0 CKPL rw-0 Unused rw-0 5 25 rw 25 r 213 rw 25 rw m5 rw OE rw-0 SSEL1 rw-0 Unused rw-0 25 rw 25 r 213 rw 25 rw m5 rw OE rw-0 SSEL1 rw-0 Unused rw-0 4 24 rw 24 r 212 rw 24 rw m4 rw Undef. rw-0 SSEL0 rw-0 CHAR rw-0 24 rw 24 r 212 rw 24 rw m4 rw Undef. rw-0 SSEL0 rw-0 CHAR rw-0 3 23 rw 23 r 211 rw 23 rw m3 rw Unused rw-0 Unused rw-0 Listen rw-0 23 rw 23 r 211 rw 23 rw m3 rw Unused rw-0 Unused rw-0 Listen rw-0 2 22 rw 22 r 210 rw 22 rw m2 rw Unused rw-0 Unused rw-0 SYNC rw-0 22 rw 22 r 210 rw 22 rw m2 rw Unused rw-0 Unused rw-0 SYNC rw-0 1 21 rw 21 r 29 rw 21 rw m1 rw Undef. rw-0 STC rw-0 MM rw-0 21 rw 21 r 29 rw 21 rw m1 rw Undef. rw-0 STC rw-0 MM rw-0 0 20 rw 20 r 28 rw 20 rw m0 rw Undef. rw-0 TXEPT rw-1 SWRST rw-1 20 rw 20 r 28 rw 20 rw m0 rw Undef. rw-0 TXEPT rw-1 SWRST rw-1
Peripheral File Map
A-7
ADC12 Registers, Byte and Word Access
A.9
ADC12 Registers, Byte and Word Access
Bit # - ADC12MCTL15 008Fh ADC12MCTL14 008Eh ADC12MCTL13 008Dh ADC12MCTL12 008Ch ADC12MCTL11 008Bh ADC12MCTL10 008Ah ADC12MCTL9 0089h ADC12MCTL8 0088h ADC12MCTL7 0087h ADC12MCTL6 0086h ADC12MCTL5 0085h ADC12MCTL4 0084h ADC12MCTL3 0083h ADC12MCTL2 0082h ADC12MCTL1 0081h ADC12MCTL0 0080h 7 EOS rw-(0) EOS rw-(0) EOS rw-(0) EOS rw-(0) EOS rw-(0) EOS rw-(0) EOS rw-(0) EOS rw-(0) EOS rw-(0) EOS rw-(0) EOS rw-(0) EOS rw-(0) EOS rw-(0) EOS rw-(0) EOS rw-(0) EOS rw-(0) 6 Sref.2 rw-(0) Sref.2 rw-(0) Sref.2 rw-(0) Sref.2 rw-(0) Sref.2 rw-(0) Sref.2 rw-(0) Sref.2 rw-(0) Sref.2 rw-(0) Sref.2 rw-(0) Sref.2 rw-(0) Sref.2 rw-(0) Sref.2 rw-(0) Sref.2 rw-(0) Sref.2 rw-(0) Sref.2 rw-(0) Sref.2 rw-(0) 5 Sref.1 rw-(0) Sref.1 rw-(0) Sref.1 rw-(0) Sref.1 rw-(0) Sref.1 rw-(0) Sref.1 rw-(0) Sref.1 rw-(0) Sref.1 rw-(0) Sref.1 rw-(0) Sref.1 rw-(0) Sref.1 rw-(0) Sref.1 rw-(0) Sref.1 rw-(0) Sref.1 rw-(0) Sref.1 rw-(0) Sref.1 rw-(0) 4 Sref.0 rw-(0) Sref.0 rw-(0) Sref.0 rw-(0) Sref.0 rw-(0) Sref.0 rw-(0) Sref.0 rw-(0) Sref.0 rw-(0) Sref.0 rw-(0) Sref.0 rw-(0) Sref.0 rw-(0) Sref.0 rw-(0) Sref.0 rw-(0) Sref.0 rw-(0) Sref.0 rw-(0) Sref.0 rw-(0) Sref.0 rw-(0) 3 INCH.3 rw-(0) INCH.3 rw-(0) INCH.3 rw-(0) INCH.3 rw-(0) INCH.3 rw-(0) INCH.3 rw-(0) INCH.3 rw-(0) INCH.3 rw-(0) INCH.3 rw-(0) INCH.3 rw-(0) INCH.3 rw-(0) INCH.3 rw-(0) INCH.3 rw-(0) INCH.3 rw-(0) INCH.3 rw-(0) INCH.3 rw-(0) 2 INCH.2 rw-(0) INCH.2 rw-(0) INCH.2 rw-(0) INCH.2 rw-(0) INCH.2 rw-(0) INCH.2 rw-(0) INCH.2 rw-(0) INCH.2 rw-(0) INCH.2 rw-(0) INCH.2 rw-(0) INCH.2 rw-(0) INCH.2 rw-(0) INCH.2 rw-(0) INCH.2 rw-(0) INCH.2 rw-(0) INCH.2 rw-(0) 1 INCH.1 rw-(0) INCH.1 rw-(0) INCH.1 rw-(0) INCH.1 rw-(0) INCH.1 rw-(0) INCH.1 rw-(0) INCH.1 rw-(0) INCH.1 rw-(0) INCH.1 rw-(0) INCH.1 rw-(0) INCH.1 rw-(0) INCH.1 rw-(0) INCH.1 rw-(0) INCH.1 rw-(0) INCH.1 rw-(0) INCH.1 rw-(0) 0 INCH.0 rw-(0) INCH.0 rw-(0) INCH.0 rw-(0) INCH.0 rw-(0) INCH.0 rw-(0) INCH.0 rw-(0) INCH.0 rw-(0) INCH.0 rw-(0) INCH.0 rw-(0) INCH.0 rw-(0) INCH.0 rw-(0) INCH.0 rw-(0) INCH.0 rw-(0) INCH.0 rw-(0) INCH.0 rw-(0) INCH.0 rw-(0)
All bits of ADC12MCTLx registers are only modifiable when ENC=0.
A-8
ADC12 Registers, Byte and Word Access (Continued)
A.9
ADC12 Registers, Byte and Word Access (Continued)
Bit # - 15 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 14 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 13 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 12 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 11 0 MSB <---------- Conversion Result ----------> LSB All conversion-result bits of type rw MSB <---------- Conversion Result ----------> LSB All conversion-result bits of type rw MSB <---------- Conversion Result ----------> LSB All conversion-result bits of type rw MSB <---------- Conversion Result ----------> LSB All conversion-result bits of type rw MSB <---------- Conversion Result ----------> LSB All conversion-result bits of type rw MSB <---------- Conversion Result ----------> LSB All conversion-result bits of type rw MSB <---------- Conversion Result ----------> LSB All conversion-result bits of type rw MSB <---------- Conversion Result ----------> LSB All conversion-result bits of type rw MSB <---------- Conversion Result ----------> LSB All conversion-result bits of type rw MSB <---------- Conversion Result ----------> LSB All conversion-result bits of type rw MSB <---------- Conversion Result ----------> LSB All conversion-result bits of type rw MSB <---------- Conversion Result ----------> LSB All conversion-result bits of type rw MSB <---------- Conversion Result ----------> LSB All conversion-result bits of type rw MSB <---------- Conversion Result ----------> LSB All conversion-result bits of type rw MSB <---------- Conversion Result ----------> LSB All conversion-result bits of type rw MSB <---------- Conversion Result ----------> LSB All conversion-result bits of type rw
ADC12MEM15 015Eh ADC12MEM14 015Ch ADC12MEM13 015Ah ADC12MEM12 0158h ADC12MEM11 0156h ADC12MEM10 0154h ADC12MEM9 0152h ADC12MEM8 0150h ADC12MEM7 014Eh ADC12MEM6 014Ch ADC12MEM5 014Ah ADC12MEM4 0148h ADC12MEM3 0146h ADC12MEM2 0144h ADC12MEM1 0142h ADC12MEM0 0140h
Peripheral File Map
A-9
ADC12 Registers, Byte and Word Access (Continued)
A.9
ADC12 Registers, Byte and Word Access (Continued)
Bit # - 15 ADC12IE.15 rw-(0) ADC12IFG.15 rw-(0) CStartAdd.3 rw-(0) SHT1.3 rw-(0) 14 ADC12IE.14 rw-(0) ADC12IFG.14 rw-(0) CStartAdd.2 rw-(0) SHT1.2 rw-(0) 13 ADC12IE.13 rw-(0) ADC12IFG.13 rw-(0) CStartadd.1 rw-(0) SHT1.1 rw-(0) 12 ADC12IE.12 rw-(0) ADC12IFG.12 rw-(0) CStartAdd.0 rw-(0) SHT1.0 rw-(0) 11 ADC12IE.11 rw-(0) ADC12IFG.11 rw-(0) SHS.1 rw-(0) SHT0.3 rw-(0) 10 ADC12IE.10 rw-(0) ADC12IFG.10 rw-(0) SHS.0 rw-(0) SHT0.2 rw-(0) 9 ADC12IE.9 rw-(0) ADC12IFG.9 rw-(0) SHP rw-(0) SHT0.1 rw-(0) 8 ADC12IE.8 rw-(0) ADC12IFG.8 rw-(0) ISSH rw-(0) SHT0.0 rw-(0)
ADC12IE 01A6h ADC12IFG 01A4h ADC12CTL1 01A2h ADC12CTL0 01A0h
Only modifiable when ENC=0.
Bit # -
ADC12IE 01A6h ADC12IFG
7 ADC12IE.7 rw-(0) ADC12IFG.7 rw-(0)
ADC12DIV.2
6
ADC12IE.6 rw-(0) ADC12IFG.6
5
ADC12IE.5 rw-(0) ADC12IFG.5 rw-(0) ADC12DIV.0 rw-(0) REFON rw-(0)
4
ADC12IE.4 rw-(0) ADC12IFG.4 rw-(0) ADC12SSEL.1
3
ADC12IE.3 rw-(0) ADC12IFG.3 rw-(0) ADC12SSEL.0
2
ADC12IE.2 rw-(0) ADC12IFG.2 rw-(0) CONSEQ.1 rw-(0) ADC12TOVIE rw-(0)
1
ADC12IE.1 rw-(0) ADC12IFG.1 rw-(0) CONSEQ.0 rw-(0) ENC rw-(0)
0
ADC12IE.0 rw-(0) ADC12IFG.0 rw-(0) ADC12BUSY r-(0) ADC12SC rw-(0)
01A4h
ADC12CTL1 01A2h
rw-(0)
ADC12DIV.1
rw-(0)
MSC rw-(0)
rw-(0)
2_5V rw-(0)
rw-(0)
ADC12ON rw-(0)
rw-(0)
ADC12OVIE rw-(0)
ADC12CTL0 01A0h
Only modifiable when ENC=0.
A-10
Watchdog/Timer, Word Access
A.10 Watchdog/Timer, Word Access
Bit # - Watchdog Timer, Control register WDTCTL 120h Bit # - Watchdog Timer, Control register WDTCTL 120h 15 <-------------------------- <-------------------------- Read as 069h Written as 05Ah 8 -----------------------> ------------------------>
7 HOLD rw-0
6 NMIES rw-0
5 NMI rw-0
4 TMSEL rw-0
3 CNTCL (w),r0
2 SSEL rw-0
1 IS1 rw-0
0 IS0 rw-0
A.11 Flash Control Registers, Word Access
Bit # - FCTL3 012Ch FCTL2 012Ah FCTL1 0128H 15 14 13 12 Read as 096h Written as 0A5h Read as 096h Written as 0A5h Read as 096h Written as 0A5h 11 10 9 8
<-------------------------- <-------------------------- <-------------------------- <-------------------------- <-------------------------- <--------------------------
----------------------------------> ----------------------------------> ----------------------------------> ----------------------------------> ----------------------------------> ---------------------------------->
Bit # - FCTL3 012Ch FCTL2 012Ah FCTL1 0128H
7 Reserved r0 SSEL1 rw-0 SEGWRT rw-0
6 Reserved r0 SSEL0 rw-1 WRT rw-0
5 EMEX rw-0 FN5 rw-0 Reserved r0
4 Lock rw-1 FN4 rw-0 Reserved r0
3 WAIT r-1 FN3 rw-0 Reserved r0
2 ACCVIFG rw-0 FN2 rw-0 MEras rw-0
1 KEYV rw-(0) FN1 rw-1 Erase rw-0
0 Busy r(w)-0 FN0 rw-0 Reserved r0
Peripheral File Map
A-11
Hardware Multiplier, Word Access
A.12 Hardware Multiplier, Word Access
Bit # - Sum extend, SumExt 013Eh Result-high word ResHI 013Ch Result-low word ResLO 013Ah Second operand OP2 0138h MPYS+ACC MACS 0136h MPY+ACC MAC 0134h Multiply signed MPYS 0132h Multiply unsigned MPY 0130h 15 r 215 rw 215 rw 215 rw 215 rw 215 rw 215 rw 215 rw 14 r 214 rw 214 rw 214 rw 214 rw 214 rw 214 rw 214 rw 13 r 213 rw 213 rw 213 rw 213 rw 213 rw 213 rw 213 rw 12 r 212 rw 212 rw 212 rw 212 rw 212 rw 212 rw 212 rw 11 r 211 rw 211 rw 211 rw 211 rw 211 rw 211 rw 211 rw 10 r 210 rw 210 rw 210 rw 210 rw 210 rw 210 rw 210 rw 9 r 29 rw 29 rw 29 rw 29 rw 29 rw 29 rw 29 rw 8 r 28 rw 28 rw 28 rw 28 rw 28 rw 28 rw 28 rw
Bit # - Sum extend, SumExt 013Eh Result-high word ResHI 013Ch Result-low word ResLO 013Ah Second operand OP2 0138h MPYS+ACC MACS 0136h MPY+ACC MAC 0134h Multiply signed MPYS 0132h Multiply unsigned MPY 0130h
7 r 27 rw 27 rw 27 rw 27 rw 27 rw 27 rw 27 rw
6 r 26 rw 26 rw 26 rw 26 rw 26 rw 26 rw 26 rw
5 r 25 rw 25 rw 25 rw 25 rw 25 rw 25 rw 25 rw
4 r 24 rw 24 rw 24 rw 24 rw 24 rw 24 rw 24 rw
3 r 23 rw 23 rw 23 rw 23 rw 23 rw 23 rw 23 rw
2 r 22 rw 22 rw 22 rw 22 rw 22 rw 22 rw 22 rw
1 r 21 rw 21 rw 21 rw 21 rw 21 rw 21 rw 21 rw
0 r 20 rw 20 rw 20 rw 20 rw 20 rw 20 rw 20 rw
The Sum Extend register SumExt holds a 16x16-bit multiplication (MPYS) sign result, or the overflow of the multiply and accumulate (MAC) operation, or the sign of the signed multiply and accumulate (MACS) operation. Overflow and underflow of the MACS operation must be handled by software.
A-12
Timer_A Registers, Word Access
A.13 Timer_A Registers, Word Access
Bit # - 017Eh 017Ch Cap/com register CCR4 017Ah Cap/com register CCR3 0178h Cap/com register CCR2 0176h Cap/com register CCR1 0174h Cap/com register CCR0 0172h Timer_A register TAR 0170h 016Eh 016Ch Cap/com control CCTL4, 016Ah Cap/com control CCTL3, 0168h Cap/com control CCTL2, 0166h Cap/com control CCTL1, 0164h Cap/com control CCTL0, 0162h Timer_A control TACTL 0160h CM41 rw-(0) CM31 rw-(0) CM21 rw-(0) CM11 rw-(0) CM01 rw-(0) Unused rw-(0) CM40 rw-(0) CM30 rw-(0) CM20 rw-(0) CM10 rw-(0) CM00 rw-(0) Unused rw-(0) CCIS41 rw-(0) CCIS31 rw-(0) CCIS21 rw-(0) CCIS11 rw-(0) CCIS01 rw-(0) Unused rw-(0) CCIS40 rw-(0) CCIS30 rw-(0) CCIS20 rw-(0) CCIS10 rw-(0) CCIS00 rw-(0) Unused rw-(0) SCS4 rw-(0) SCS3 rw-(0) SCS2 rw-(0) SCS1 rw-(0) SCS0 rw-(0) Unused rw-(0) SCCI4 rw-(0) SCCI3 rw-(0) SCCI2 rw-(0) SCCI1 rw-(0) SCCI0 rw-(0) SSEL2 rw-(0) Unused r0 Unused r0 Unused r0 Unused r0 Unused r0 SSEL1 rw-(0) CAP4 rw-(0) CAP3 rw-(0) CAP2 rw-(0) CAP1 rw-(0) CAP0 rw-(0) SSEL0 rw-(0) 215 rw-(0) 215 rw-(0) 215 rw-(0) 215 rw-(0) 215 rw-(0) 215 rw-(0) 214 rw-(0) 214 rw-(0) 214 rw-(0) 214 rw-(0) 214 rw-(0) 214 rw-(0) 213 rw-(0) 213 rw-(0) 213 rw-(0) 213 rw-(0) 213 rw-(0) 213 rw-(0) 212 rw-(0) 212 rw-(0) 212 rw-(0) 212 rw-(0) 212 rw-(0) 212 rw-(0) 211 rw-(0) 211 rw-(0) 211 rw-(0) 211 rw-(0) 211 rw-(0) 211 rw-(0) 210 rw-(0) 210 rw-(0) 210 rw-(0) 210 rw-(0) 210 rw-(0) 210 rw-(0) 29 rw-(0) 29 rw-(0) 29 rw-(0) 29 rw-(0) 29 rw-(0) 29 rw-(0) 28 rw-(0) 28 rw-(0) 28 rw-(0) 28 rw-(0) 28 rw-(0) 28 rw-(0) 15 14 13 12 11 10 9 8
Registers are reserved on devices with Timer_A3.
Peripheral File Map
A-13
Timer_A Registers, Word Access (Continued)
A.13 Timer_A Registers, Word Access (Continued)
Bit # - 017Eh 017Ch Cap/com register CCR4 017Ah Cap/com register CCR3 0178h Cap/com register CCR2 0176h Cap/com register CCR1 0174h Cap/com register CCR0 0172h Timer_A register TAR 0170h 016Eh 016Ch Cap/com control CCTL4, 016Ah Cap/com control CCTL3, 0168h Cap/com control CCTL2, 0166h Cap/com control CCTL1, 0164h Cap/com control CCTL0, 0162h Timer_A control TACTL 0160h
OutMod42 OutMod41 OutMod40
7
6
5
4
3
2
1
0
27 rw-(0) 27 rw-(0) 27 rw-(0) 27 rw-(0) 27 rw-(0) 27 rw-(0)
26 rw-(0) 26 rw-(0) 26 rw-(0) 26 rw-(0) 26 rw-(0) 26 rw-(0)
25 rw-(0) 25 rw-(0) 25 rw-(0) 25 rw-(0) 25 rw-(0) 25 rw-(0)
24 rw-(0) 24 rw-(0) 24 rw-(0) 24 rw-(0) 24 rw-(0) 24 rw-(0)
23 rw-(0) 23 rw-(0) 23 rw-(0) 23 rw-(0) 23 rw-(0) 23 rw-(0)
22 rw-(0) 22 rw-(0) 22 rw-(0) 22 rw-(0) 22 rw-(0) 22 rw-(0)
21 rw-(0) 21 rw-(0) 21 rw-(0) 21 rw-(0) 21 rw-(0) 21 rw-(0)
20 rw-(0) 20 rw-(0) 20 rw-(0) 20 rw-(0) 20 rw-(0) 20 rw-(0)
rw-(0)
OutMod32
rw-(0)
OutMod31
rw-(0)
OutMod30
CCIE4 rw-(0) CCIE3 rw-(0) CCIE2 rw-(0) CCIE1 rw-(0) CCIE0 rw-(0) MC0 rw-(0)
CCI4 r CCI3 r CCI2 r CCI1 r CCI0 r Unused rw-(0)
OUT4 rw-(0) OUT3 rw-(0) OUT2 rw-(0) OUT1 rw-(0) OUT0 rw-(0) CLR rw-(0)
COV4 rw-(0) COV3 rw-(0) COV2 rw-(0) COV1 rw-(0) COV0 rw-(0) TAIE rw-(0)
CCIFG4 rw-(0) CCIFG3 rw-(0) CCIFG2 rw-(0) CCIFG1 rw-(0) CCIFG0 rw-(0) TAIFG rw-(0)
rw-(0)
OutMod22
rw-(0)
OutMod21
rw-(0)
OutMod20
rw-(0)
OutMod12
rw-(0)
OutMod11
rw-(0)
OutMod10
rw-(0)
OutMod02
rw-(0)
OutMod01
rw-(0)
OutMod00
rw-(0) ID1 rw-(0)
rw-(0) ID0 rw-(0)
rw-(0) MC1 rw-(0)
Registers are reserved on devices with Timer_A3. Bit # - Timer_A interrupt vector TAIV 12Eh 15 0 r0 14 0 r0 13 0 r0 12 0 r0 11 0 r0 10 0 r0 9 0 r0 8 0 r0
Bit # - Timer_A interru t vector interrupt TAIV 12Eh
7 0 r0
6 0 r0
5 0 r0
4 0 r0
3 r-(0)
2 TAIV r-(0)
1 r-(0)
0 0 r0
TAIV Vector, Timer_A5 (five capture/compare blocks integrated) 0: No interrupt pending 2: CCIFG1 flag set, interrupt flag of capture/compare block 1 4: CCIFG2 flag set, interrupt flag of capture/compare block 2 (CCIFG1=0) 6: CCIFG3 flag set, interrupt flag of capture/compare block 3 (CCIFG1=CCIFG2=0) 8: CCIFG3 flag set, interrupt flag of capture/compare block 3 (CCIFG1=CCIFG2=CCIFG3=0) 10: TAIFG flag set, interrupt flag of Timer_A register/counter (CCIFG1=CCIFG2=CCIFG3=CCIFG4=0) TAIV Vector, Timer_A3 (three capture/compare blocks integrated) 0: No interrupt pending 2: CCIFG1 flag set, interrupt flag of capture/compare block 1 4: CCIFG2 flag set, interrupt flag of capture/compare block 2 (CCIFG1=0) 6: Reserved 8: Reserved 10: TAIFG flag set, interrupt flag of Timer_A register/counter (CCIFG1=CCIFG2=CCIFG3=CCIFG4=0)
A-14
Timer_B Registers, Word Access
A.14 Timer_B Registers, Word Access
Bit # - Cap/com register CCR6 019Eh Cap/com register CCR5 019Ch Cap/com register CCR4 019Ah Cap/com register CCR3 0198h Cap/com register CCR2 0196h Cap/com register CCR1 0194h Cap/com register CCR0 0192h Timer_B register TBR 0190h Cap/com control CCTL6, 018Eh Cap/com control CCTL5, 018Ch Cap/com control CCTL4, 018Ah Cap/com control CCTL3, 0188h Cap/com control CCTL2, 0186h Cap/com control CCTL1, 0184h Cap/com control CCTL0, 0182h Timer_B control TBCTL, 0180h 15 215 rw-(0) 215 rw-(0) 215 rw-(0) 215 rw-(0) 215 rw-(0) 215 rw-(0) 215 rw-(0) 215 rw-(0) CM61 rw-(0) CM51 rw-(0) CM41 rw-(0) CM31 rw-(0) CM21 rw-(0) CM11 rw-(0) CM01 rw-(0) Unused rw-(0) 14 214 rw-(0) 214 rw-(0) 214 rw-(0) 214 rw-(0) 214 rw-(0) 214 rw-(0) 214 rw-(0) 214 rw-(0) CM60 rw-(0) CM50 rw-(0) CM40 rw-(0) CM30 rw-(0) CM20 rw-(0) CM10 rw-(0) CM00 rw-(0) TBCLGRP1 rw-(0) 13 213 rw-(0) 213 rw-(0) 213 rw-(0) 213 rw-(0) 213 rw-(0) 213 rw-(0) 213 rw-(0) 213 rw-(0) CCIS61 rw-(0) CCIS51 rw-(0) CCIS41 rw-(0) CCIS31 rw-(0) CCIS21 rw-(0) CCIS11 rw-(0) CCIS01 rw-(0) TBCLGRP0 rw-(0) 12 212 rw-(0) 212 rw-(0) 212 rw-(0) 212 rw-(0) 212 rw-(0) 212 rw-(0) 212 rw-(0) 212 rw-(0) CCIS60 rw-(0) CCIS50 rw-(0) CCIS40 rw-(0) CCIS30 rw-(0) CCIS20 rw-(0) CCIS10 rw-(0) CCIS00 rw-(0) TBCNTL1 rw-(0) 11 211 rw-(0) 211 rw-(0) 211 rw-(0) 211 rw-(0) 211 rw-(0) 211 rw-(0) 211 rw-(0) 211 rw-(0) SCS6 rw-(0) SCS5 rw-(0) SCS4 rw-(0) SCS3 rw-(0) SCS2 rw-(0) SCS1 rw-(0) SCS0 rw-(0) TBCNTL0 rw-(0) 10 210 rw-(0) 210 rw-(0) 210 rw-(0) 210 rw-(0) 210 rw-(0) 210 rw-(0) 210 rw-(0) 210 rw-(0) CLLD6.1 rw-(0) CLLD5.1 rw-(0) CCLD4.1 rw-(0) CCLD3.1 rw-(0) CCLD2.1 rw-(0) CCLD1.1 rw-(0) CCLD0.1 rw-(0) Unused rw-(0) 9 29 rw-(0) 29 rw-(0) 29 rw-(0) 29 rw-(0) 29 rw-(0) 29 rw-(0) 29 rw-(0) 29 rw-(0) CLLD6.0 rw-(0) CLLD5.0 rw-(0) CCLD4.0 r0 CCLD3.0 r0 CCLD2.0 r0 CCLD1.0 r0 CCLD0.0 r0 TBSSEL1 rw-(0) 8 28 rw-(0) 28 rw-(0) 28 rw-(0) 28 rw-(0) 28 rw-(0) 28 rw-(0) 28 rw-(0) 28 rw-(0) CAP6 rw-(0) CAP5 rw-(0) CAP4 rw-(0) CAP3 rw-(0) CAP2 rw-(0) CAP1 rw-(0) CAP0 rw-(0) TBSSEL0 rw-(0)
Registers are reserved on devices with Timer_B3.
Peripheral File Map
A-15
Timer_B Registers, Word Access (Continued)
A.14 Timer_B Registers, Word Access (Continued)
Bit # - Cap/com register CCR6 019Eh Cap/com register CCR5 019Ch Cap/com register CCR4 019Ah Cap/com register CCR3 0198h Cap/com register CCR2 0196h Cap/com register CCR1 0194h Cap/com register CCR0 0192h Timer_B register TBR 0190h Cap/com control CCTL6, 018Eh Cap/com control CCTL5, 018Ch Cap/com control CCTL4, 018Ah Cap/com control CCTL3, 0188h Cap/com control CCTL2, 0186h Cap/com control CCTL1, 0184h Cap/com control CCTL0, 0182h Timer_B control TACTL 0180h 7 27 rw-(0) 27 rw-(0) 27 rw-(0) 27 rw-(0) 27 rw-(0) 27 rw-(0) 27 rw-(0) 27 rw-(0)
OutMod62
6 26 rw-(0) 26 rw-(0) 26 rw-(0) 26 rw-(0) 26 rw-(0) 26 rw-(0) 26 rw-(0) 26 rw-(0)
OutMod61
5 25 rw-(0) 25 rw-(0) 25 rw-(0) 25 rw-(0) 25 rw-(0) 25 rw-(0) 25 rw-(0) 25 rw-(0)
OutMod60
4 24 rw-(0) 24 rw-(0) 24 rw-(0) 24 rw-(0) 24 rw-(0) 24 rw-(0) 24 rw-(0) 24 rw-(0) CCIE6 rw-(0) CCIE5 rw-(0) CCIE4 rw-(0) CCIE3 rw-(0) CCIE2 rw-(0) CCIE1 rw-(0) CCIE0 rw-(0) TBMC0 rw-(0)
3 23 rw-(0) 23 rw-(0) 23 rw-(0) 23 rw-(0) 23 rw-(0) 23 rw-(0) 23 rw-(0) 23 rw-(0) CCI6 r CCI5 r CCI4 r CCI3 r CCI2 r CCI1 r CCI0 r Unused rw-(0)
2 22 rw-(0) 22 rw-(0) 22 rw-(0) 22 rw-(0) 22 rw-(0) 22 rw-(0) 22 rw-(0) 22 rw-(0) OUT6 rw-(0) OUT5 rw-(0) OUT4 rw-(0) OUT3 rw-(0) OUT2 rw-(0) OUT1 rw-(0) OUT0 rw-(0) TBCLR rw-(0)
1 21 rw-(0) 21 rw-(0) 21 rw-(0) 21 rw-(0) 21 rw-(0) 21 rw-(0) 21 rw-(0) 21 rw-(0) COV6 rw-(0) COV5 rw-(0) COV4 rw-(0) COV3 rw-(0) COV2 rw-(0) COV1 rw-(0) COV0 rw-(0) TBIE rw-(0)
0 20 rw-(0) 20 rw-(0) 20 rw-(0) 20 rw-(0) 20 rw-(0) 20 rw-(0) 20 rw-(0) 20 rw-(0) CCIFG6 rw-(0) CCIFG5 rw-(0) CCIFG4 rw-(0) CCIFG3 rw-(0) CCIFG2 rw-(0) CCIFG1 rw-(0) CCIFG0 rw-(0) TBIFG rw-(0)
rw-(0)
OutMod52
rw-(0)
OutMod51
rw-(0)
OutMod50
rw-(0)
OutMod42
rw-(0)
OutMod41
rw-(0)
OutMod40
rw-(0)
OutMod32
rw-(0)
OutMod31
rw-(0)
OutMod30
rw-(0)
OutMod22
rw-(0)
OutMod21
rw-(0)
OutMod20
rw-(0)
OutMod12
rw-(0)
OutMod11
rw-(0)
OutMod10
rw-(0)
OutMod02
rw-(0)
OutMod01
rw-(0)
OutMod00
rw-(0) TBID1 rw-(0)
rw-(0) TBID0 rw-(0)
rw-(0) TBMC1 rw-(0)
Registers are reserved on devices with Timer_B3.
A-16
Timer_B Registers, Word Access (Continued)
A.14 Timer_B Registers, Word Access (Continued)
Bit # - Timer_B interrupt vector TBIV 11Eh Bit # - Timer_B interrupt vector interru t TBIV 11Eh 15 0 r0 7 0 r0 14 0 r0 6 0 r0 13 0 r0 5 0 r0 12 0 r0 4 0 r0 11 0 r0 3 r-(0) 10 0 r0 2 TBIV r-(0) r-(0) 9 0 r0 1 8 0 r0 0 0 r0
TBIV Vector, Timer_B5 (five capture/compare blocks integrated) 0: No interrupt pending 2: CCIFG1 flag set, interrupt flag of capture/compare block 1 4: CCIFG2 flag set, interrupt flag of capture/compare block 2 (CCIFG1=0) 6: CCIFG3 flag set, interrupt flag of capture/compare block 3 (CCIFG1=CCIFG2=0) 8: CCIFG4 flag set, interrupt flag of capture/compare block 4 (CCIFG1=CCIFG2=CCIFG3=0) 10: CCIFG5 flag set, interrupt flag of capture/compare block 5 (CCIFG1=CCIFG2=CCIFG3=CCIFG4=0) 12: CCIFG6 flag set, interrupt flag of capture/compare block 6 (CCIFG1=CCIFG2=CCIFG3=CCIFG4=CCIFG5=0) 14: TBIFG flag set, interrupt flag of Timer_B register/counter (CCIFG1=CCIFG2=CCIFG3=CCIFG4=CCIFG5=CCIFG6=0) TBIV Vector, Timer_B3 (three capture/compare blocks integrated) 0: No interrupt pending 2: CCIFG1 flag set, interrupt flag of capture/compare block 1 4: CCIFG2 flag set, interrupt flag of capture/compare block 2 (CCIFG1=0) 6: Reserved 8: Reserved 10: Reserved 12: Reserved 14: TBIFG flag set, interrupt flag of Timer_B register/counter (CCIFG1=CCIFG2=0)
Peripheral File Map
A-17
A-18
Appendix B
Instruction Set Description
The MSP430 core CPU architecture evolved from a reduced instruction set with highly-transparent instruction formats. Using these formats, core instructions are implemented into the hardware. Emulated instructions are also supported by the assembler. Emulated instructions use the core instructions with the built-in constant generators CG1 and CG2 and/or the program counter (PC). The core and emulated instructions are described in detail in this section. The emulated instruction mnemonics are listed with examples. Program memory words used by an instruction vary from one to three words, depending on the combination of addressing modes.
Topic
B.1 B.2
Page
Instruction Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2 Instruction Set Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8
Instruction Set Description
B-1
Instruction Set Overview
B.1 Instruction Set Overview
The following list gives an overview of the instruction set. Status Bits V * * * 0 - - 0 - - - - - - * * * * * - - * * * N * * * * - - * - - - - 0 - * * * * * - - * * * Z * * * * - - * - - - - - 0 * * * * * - - * * * C * * * * - - * - - - 0 - - * * * * * - - * * *
* ADC[.W];ADC.B ADD[.W];ADD.B ADDC[.W];ADDC.B AND[.W];AND.B BIC[.W];BIC.B BIS[.W];BIS.B BIT[.W];BIT.B * BR CALL * CLR[.W];CLR.B * CLRC * CLRN * CLRZ CMP[.W];CMP.B * DADC[.W];DADC.B DADD[.W];DADD.B * DEC[.W];DEC.B * DECD[.W];DECD.B * DINT * EINT * INC[.W];INC.B * INCD[.W];INCD.B * INV[.W];INV.B JC/JHS JEQ/JZ JGE JL JMP JN JNC/JLO JNE/JNZ
dst dst + C -> dst src,dst src + dst -> dst src,dst src + dst + C -> dst src,dst src .and. dst -> dst src,dst .not.src .and. dst -> dst src,dst src .or. dst -> dst src,dst src .and. dst dst Branch to ....... dst PC+2 -> stack, dst -> PC dst Clear destination Clear carry bit Clear negative bit Clear zero bit src,dst dst - src dst dst + C -> dst (decimal) src,dst src + dst + C -> dst (decimal) dst dst - 1 -> dst dst dst - 2 -> dst Disable interrupt Enable interrupt dst Increment destination, dst +1 -> dst dst Double-Increment destination, dst+2->dst dst Invert destination Label Jump to Label if Carry-bit is set Label Jump to Label if Zero-bit is set Label Jump to Label if (N .XOR. V) = 0 Label Jump to Label if (N .XOR. V) = 1 Label Jump to Label unconditionally Label Jump to Label if Negative-bit is set Label Jump to Label if Carry-bit is reset Label Jump to Label if Zero-bit is reset
-- -- -- -- -- -- -- -- -- -- - ---
-- -- -- --
B-2
Instruction Set Overview
Status Bits V - - - - * N - - - - * Z - - - - * C - - - - *
MOV[.W];MOV.B * NOP * POP[.W];POP.B PUSH[.W];PUSH.B RETI
* RET * RLA[.W];RLA.B * RLC[.W];RLC.B RRA[.W];RRA.B RRC[.W];RRC.B * SBC[.W];SBC.B * SETC * SETN * SETZ SUB[.W];SUB.B SUBC[.W];SUBC.B SWPB SXT * TST[.W];TST.B XOR[.W];XOR.B
src,dst src -> dst No operation dst Item from stack, SP+2 SP src SP - 2 SP, src @SP Return from interrupt TOS SR, SP + 2 SP TOS PC, SP + 2 SZP Return from subroutine TOS PC, SP + 2 SP dst Rotate left arithmetically dst Rotate left through carry dst MSB MSB ....LSB C dst C MSB .........LSB C dst Subtract carry from destination Set carry bit Set negative bit Set zero bit src,dst dst + .not.src + 1 dst src,dst dst + .not.src + C dst dst swap bytes dst Bit7 Bit8 ........ Bit15 dst Test destination src,dst src .xor. dst dst
-- -- * * 0 * * - - - * * - 0 0 * * * * * * - 1 - * * - * * * * * * * * - - 1 * * - * * * * * * * * 1 - - * * - * 1 *
Note: Asterisked Instructions Asterisked (*) instructions are emulated. They are replaced with core instructions by the assembler.
Instruction Set Description
B-3
Instruction Set Overview
B.1.1 Instruction Formats
The following sections describe the instruction formats.
B.1.1.1 Double-Operand Instructions (Core Instructions)
The instruction format using double operands, as shown in Figure B-1, consists of four main fields to form a 16-bit code:
-
operational code field, four bits source field, six bits byte operation identifier, one bit destination field, five bits
[op-code] [source register + As] [BW] [dest. register + Ad]
The source field is composed of two addressing bits and a four-bit register number (0....15). The destination field is composed of one addressing bit and a four-bit register number (0....15). The byte identifier B/W indicates whether the instruction is executed as a byte (B/W = 1) or as a word instruction (B/W = 0).
Figure B-1.Double-Operand Instructions
15 OP-Code Operational Code Field 12 11 8 7 Ad 6 B/W 5 As 4 3 Destination Register 0
Source Register
Status Bits V * * 0 - - 0 * * - * * * N * * * - - * * * - * * * Z * * * - - * * * - * * * C * * * - - * * * - * * *
ADD[.W]; ADDC[.W]; AND[.W]; BIC[.W]; BIS[.W]; BIT[.W]; CMP[.W]; DADD[.W]; MOV[.W]; SUB[.W]; SUBC[.W]; XOR[.W];
ADD.B ADDC.B AND.B BIC.B BIS.B BIT.B CMP.B DADD.B MOV.B SUB.B SUBC.B XOR.B
src,dst src,dst src,dst src,dst src,dst src,dst src,dst src,dst src,dst src,dst src,dst src,dst
src + dst -> dst src + dst + C -> dst src .and. dst -> dst .not.src .and. dst -> dst src .or. dst -> dst src .and. dst dst - src src + dst + C -> dst (dec) src -> dst dst + .not.src + 1 -> dst dst + .not.src + C -> dst src .xor. dst -> dst
Note: Operations Using the Status Register (SR) for Destination All operations using status register SR for destination overwrite the SR contents with the operation result; as described in that operation, the status bits are not affected. Example: ADD #3,SR ; Operation: (SR) + 3 --> SR
B-4
Instruction Set Overview
B.1.1.2 Single Operand Instructions (Core Instructions)
The instruction format using a single operand, as shown in Figure B-2, consists of two main fields to form a 16-bit code:
-
operational code field, nine bits with four MSBs equal to 1h byte operation identifier, one bit [B/W] destination field, six bits [destination register + Ad]
The destination field is composed of two addressing bits and the four-bit register number (0....15). The destination field bit position is the same as that of the two operand instructions. The byte identifier (B/W) indicates whether the instruction is executed as a byte (B/W = 1) or as a word (B/W = 0).
Figure B-2.Single-Operand Instructions
15 0 0 0 12 1 11 X 10 X 9 X X 7 X 6 B/W 5 Ad 4 3 0 Destination Register
Operational Code Field
Destination Field
Status Bits RRA[.W]; RRA.B RRC[.W]; RRC.B PUSH[.W]; PUSH.B SWPB CALL RETI SXT dst dst dst dst dst dst dst MSB MSB ...LSB C C MSB ........LSB C SP - 2 SP, src @SP swap bytes PC2 + @SP, dst PC TOS SR, SP + 2 SP TOS PC, SP + 2 SP Bit 7 Bit 8 ........ Bit 15 V 0 * - - - * N * * - - - * Z * * - - - * * C * * - - - * *
0*
B.1.2 Conditional and Unconditional Jumps (Core Instructions)
The instruction format for conditional and unconditional jumps, as shown in Figure B-3, consists of two main fields to form a 16-bit code:
-
operational code (op-code) field, six bits jump offset field, ten bits
The operational-code field is composed of the op-code ( three bits), and three bits according to the following conditions.
Figure B-3.Conditional and Unconditional Jump Instructions
15 0 0 13 1 12 X X 10 X 9 X Sign X X X X X X X X 0 X
OP-Code Jump-On Code Operational Code Field
Offset Jump Offset Field
Conditional jumps jump to addresses in the range of -511 to +512 words relative to the current address. The assembler computes the signed offsets and inserts them into the op-code.
Instruction Set Description
B-5
Instruction Set Overview
JC/JHS JEQ/JZ JGE JL JMP JN JNC/JLO JNE/JNZ
Label Label Label Label Label Label Label Label
Jump to label if carry bit is set Jump to label if zero bit is set Jump to label if (N .XOR. V) = 0 Jump to label if (N .XOR. V) = 1 Jump to label unconditionally Jump to label if negative bit is set Jump to label if carry bit is reset Jump to label if zero bit is reset
Note: Conditional and Unconditional Jumps Conditional and unconditional jumps do not affect the status bits. A jump that is taken alters the PC with the offset: PCnew = PCold + 2 + 2*offset A jump that is not taken continues the program with the ascending instruction.
B.1.3 Emulated Instructions
The following instructions can be emulated with the reduced instruction set without additional code words. The assembler accepts the emulated instruction mnemonic, and inserts the applicable core instruction op-code.
B-6
Instruction Set Overview
The following list describes the emulated instruction short form. Mnemonic Description Status Bits VNZC * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Emulation
Arithmetical instructions ADC[.W] dst Add carry to destination ADC.B dst Add carry to destination DADC[.W] dst Add carry decimal to destination DADC.B dst Add carry decimal to destination DEC[.W] dst Decrement destination DEC.B dst Decrement destination DECD[.W] dst Double-decrement destination DECD.B dst Double-decrement destination INC[.W] dst Increment destination INC.B dst Increment destination INCD[.W] dst Increment destination INCD.B dst Increment destination SBC[.W] dst Subtract carry from destination SBC.B dst Subtract carry from destination Logical instructions INV[.W] dst INV.B dst RLA[.W] dst RLA.B dst RLC[.W] dst RLC.B dst
ADDC ADDC.B DADD DADD.B SUB SUB.B SUB SUB.B ADD ADD.B ADD ADD.B SUBC SUBC.B
#0,dst #0,dst #0,dst #0,dst #1,dst #1,dst #2,dst #2,dst #1,dst #1,dst #2,dst #2,dst #0,dst #0,dst
Invert destination Invert destination Rotate left arithmetically Rotate left arithmetically Rotate left through carry Rotate left through carry
* * * * * *
* * * * * *
* * * * * *
* * * * * *
XOR #0FFFFh,dst XOR.B #0FFFFh,dst ADD dst,dst ADD.B dst,dst ADDC dst,dst ADDC.B dst,dst
Data instructions (common use) CLR[.W] Clear destination CLR.B Clear destination CLRC Clear carry bit CLRN Clear negative bit CLRZ Clear zero bit POP dst Item from stack SETC Set carry bit SETN Set negative bit SETZ Set zero bit TST[.W] dst Test destination TST.B dst Test destination Program flow instructions BR dst Branch to ....... DINT Disable interrupt EINT Enable interrupt NOP No operation RET Return from subroutine
- - - - - - - - - 0 0
- - - 0 - - - 1 - * *
- - - - 0 - - - 1 * *
- - 0 - - - 1 - - 1 1
MOV MOV.B BIC BIC BIC MOV BIS BIS BIS CMP CMP.B
#0,dst #0,dst #1,SR #4,SR #2,SR @SP+,dst #1,SR #4,SR #2,SR #0,dst #0,dst
- - - - -
- - - - -
- - - - -
- - - - -
MOV BIC BIS MOV MOV
dst,PC #8,SR #8,SR #0h,#0h @SP+,PC
Instruction Set Description
B-7
Instruction Set Overview
B.2 Instruction Set Description
This section catalogues and describes all core and emulated instructions in alphabetical order. Some examples serve as explanations and others as application hints. The suffix .W or no suffix in the instruction mnemonic results in a word operation. The suffix .B at the instruction mnemonic results in a byte operation.
B-8
Instruction Set Overview
ADC[.W] ADC.B Syntax
Add carry to destination Add carry to destination ADC ADC.B dst dst or ADC.W dst
Operation Emulation
dst + C -> dst ADDC ADDC.B #0,dst #0,dst
Description
The carry bit (C) is added to the destination operand. The previous contents of the destination are lost. N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Set if dst was incremented from 0FFFFh to 0000, reset otherwise Set if dst was incremented from 0FFh to 00, reset otherwise V: Set if an arithmetic overflow occurs, otherwise reset OscOff, CPUOff, and GIE are not affected. The 16-bit counter pointed to by R13 is added to a 32-bit counter pointed to by R12. ADD @R13,0(R12) ; Add LSDs ADC 2(R12) ; Add carry to MSD The 8-bit counter pointed to by R13 is added to a 16-bit counter pointed to by R12. ADD.B @R13,0(R12) ; Add LSDs ADC.B 1(R12) ; Add carry to MSD
Status Bits
Mode Bits Example
Example
Instruction Set Description
B-9
Instruction Set Overview
ADD[.W] ADD.B Syntax
Add source to destination Add source to destination ADD ADD.B src,dst src,dst or ADD.W src,dst
Operation Description
src + dst -> dst The source operand is added to the destination operand. The source operand is not affected. The previous contents of the destination are lost. N: Z: C: V: Set if result is negative, reset if positive Set if result is zero, reset otherwise Set if there is a carry from the result, cleared if not Set if an arithmetic overflow occurs, otherwise reset
Status Bits
Mode Bits Example
OscOff, CPUOff, and GIE are not affected. R5 is increased by 10. The jump to TONI is performed on a carry. ADD JC ...... #10,R5 TONI
; Carry occurred ; No carry
Example
R5 is increased by 10. The jump to TONI is performed on a carry. ADD.B JC ...... #10,R5 TONI ; Add 10 to Lowbyte of R5 ; Carry occurred, if (R5) 246 [0Ah+0F6h] ; No carry
B-10
Instruction Set Overview
ADDC[.W] ADDC.B Syntax
Add source and carry to destination Add source and carry to destination ADDC ADDC.B src,dst src,dst or ADDC.W src,dst
Operation Description
src + dst + C -> dst The source operand and the carry bit (C) are added to the destination operand. The source operand is not affected. The previous contents of the destination are lost. N: Z: C: V: Set if result is negative, reset if positive Set if result is zero, reset otherwise Set if there is a carry from the MSB of the result, reset otherwise Set if an arithmetic overflow occurs, otherwise reset
Status Bits
Mode Bits Example
OscOff, CPUOff, and GIE are not affected. The 32-bit counter pointed to by R13 is added to a 32-bit counter, eleven words (20/2 + 2/2) above the pointer in R13. ADD ADDC ... @R13+,20(R13) @R13+,20(R13) ; ADD LSDs with no carry in ; ADD MSDs with carry ; resulting from the LSDs
Example
The 24-bit counter pointed to by R13 is added to a 24-bit counter, eleven words above the pointer in R13. ADD.B ADDC.B ADDC.B ... @R13+,10(R13) @R13+,10(R13) @R13+,10(R13) ; ADD LSDs with no carry in ; ADD medium Bits with carry ; ADD MSDs with carry ; resulting from the LSDs
Instruction Set Description
B-11
Instruction Set Overview
AND[.W] AND.B Syntax
Source AND destination Source AND destination AND AND.B src,dst src,dst or AND.W src,dst
Operation Description
src .AND. dst -> dst The source operand and the destination operand are logically ANDed. The result is placed into the destination. N: Z: C: V: Set if result MSB is set, reset if not set Set if result is zero, reset otherwise Set if result is not zero, reset otherwise ( = .NOT. Zero) Reset
Status Bits
Mode Bits Example
OscOff, CPUOff, and GIE are not affected. The bits set in R5 are used as a mask (#0AA55h) for the word addressed by TOM. If the result is zero, a branch is taken to label TONI. MOV AND JZ ...... ; ; ; ; ; AND JZ #0AA55h,R5 R5,TOM TONI ; Load mask into register R5 ; mask word addressed by TOM with R5 ; ; Result is not zero
or
#0AA55h,TOM TONI
Example
The bits of mask #0A5h are logically ANDed with the low byte TOM. If the result is zero, a branch is taken to label TONI. AND.B JZ ...... #0A5h,TOM TONI ; mask Lowbyte TOM with R5 ; ; Result is not zero
B-12
Instruction Set Overview
BIC[.W] BIC.B Syntax
Clear bits in destination Clear bits in destination BIC BIC.B src,dst src,dst or BIC.W src,dst
Operation Description
.NOT.src .AND. dst -> dst The inverted source operand and the destination operand are logically ANDed. The result is placed into the destination. The source operand is not affected. N: Z: C: V: Not affected Not affected Not affected Not affected
Status Bits
Mode Bits Example
OscOff, CPUOff, and GIE are not affected. The six MSBs of the RAM word LEO are cleared. BIC #0FC00h,LEO ; Clear 6 MSBs in MEM(LEO)
Example
The five MSBs of the RAM byte LEO are cleared. BIC.B #0F8h,LEO ; Clear 5 MSBs in Ram location LEO
Example
The port pins P0 and P1 are cleared. P0OUT P0_0 P0_1 BIC.B .equ .equ .equ 011h; Definition of port address 01h 02h ;Set P0.0 and P0.1 to low
#P0_0+P0_1,&P0OUT
Instruction Set Description
B-13
Instruction Set Overview
BIS[.W] BIS.B Syntax
Set bits in destination Set bits in destination BIS BIS.B src,dst src,dst or BIS.W src,dst
Operation Description
src .OR. dst -> dst The source operand and the destination operand are logically ORed. The result is placed into the destination. The source operand is not affected. N: Z: C: V: Not affected Not affected Not affected Not affected
Status Bits
Mode Bits Example
OscOff, CPUOff, and GIE are not affected. The six LSBs of the RAM word TOM are set. BIS #003Fh,TOM; set the six LSBs in RAM location TOM
Example
Start an A/D- conversion ASOC ACTL BIS .equ .equ 1 114h ; Start of conversion bit ; ADC control register ; Start A/D-conversion
#ASOC,&ACTL
Example
The three MSBs of RAM byte TOM are set. BIS.B #0E0h,TOM ; set the 3 MSBs in RAM location TOM
Example
Port pins P0 and P1 are set to high. P0OUT P0 P1 BIS.B .equ .equ .equ 011h 01h 02h
#P0+P1,&P0OUT
B-14
Instruction Set Overview
BIT[.W] BIT.B Syntax Operation Description Status Bits
Test bits in destination Test bits in destination BIT src .AND. dst The source and destination operands are logically ANDed. The result affects only the status bits. The source and destination operands are not affected. N: Z: C: V: Set if MSB of result is set, reset otherwise Set if result is zero, reset otherwise Set if result is not zero, reset otherwise (.NOT. Zero) Reset src,dst or BIT.W src,dst
Mode Bits Example
OscOff, CPUOff, and GIE are not affected. If bit 9 of R8 is set, a branch is taken to label TOM. BIT JNZ ... #0200h,R8 TOM ; bit 9 of R8 set? ; Yes, branch to TOM ; No, proceed
Example
Determine which A/D channel is configured by the MUX. ACTL BIT jnz .equ #4,&ACTL END 114h ; ADC control register ; Is channel 0 selected? ; Yes, branch to END
Example
If bit 3 of R8 is set, a branch is taken to label TOM. BIT.B JC #8,R8 TOM
Example
A serial communication receive bit (RCV) is tested. Because the carry bit is equal to the state of the tested bit while using the BIT instruction to test a single bit, the carry bit is used by the subsequent instruction; the read information is shifted into register RECBUF. ; ; Serial communication with LSB is shifted first: ; xxxx xxxx xxxx xxxx BIT.B #RCV,RCCTL ; Bit info into carry RRC RECBUF ; Carry -> MSB of RECBUF ; cxxx xxxx ...... ; repeat previous two instructions ...... ; 8 times ; cccc cccc ;^ ^ ; MSB LSB ; Serial communication with MSB is shifted first: BIT.B #RCV,RCCTL ; Bit info into carry RLC.B RECBUF ; Carry -> LSB of RECBUF ; xxxx xxxc ...... ; repeat previous two instructions ...... ; 8 times ; cccc cccc ;| LSB ; MSB
Instruction Set Description
B-15
Instruction Set Overview
* BR, BRANCH Syntax Operation Emulation Description
Branch to .......... destination BR dst -> PC MOV dst,PC dst
An unconditional branch is taken to an address anywhere in the 64K address space. All source addressing modes can be used. The branch instruction is a word instruction. Status bits are not affected. Examples for all addressing modes are given. BR #EXEC ;Branch to label EXEC or direct branch (e.g. #0A4h) ; Core instruction MOV @PC+,PC ; Branch to the address contained in EXEC ; Core instruction MOV X(PC),PC ; Indirect address ; Branch to the address contained in absolute ; address EXEC ; Core instruction MOV X(0),PC ; Indirect address ; Branch to the address contained in R5 ; Core instruction MOV R5,PC ; Indirect R5 ; Branch to the address contained in the word ; pointed to by R5. ; Core instruction MOV @R5,PC ; Indirect, indirect R5 ; Branch to the address contained in the word pointed ; to by R5 and increment pointer in R5 afterwards. ; The next time--S/W flow uses R5 pointer--it can ; alter program execution due to access to ; next address in a table pointed to by R5 ; Core instruction MOV @R5,PC ; Indirect, indirect R5 with autoincrement ; Branch to the address contained in the address ; pointed to by R5 + X (e.g. table with address ; starting at X). X can be an address or a label ; Core instruction MOV X(R5),PC ; Indirect, indirect R5 + X
Status Bits Example
BR
EXEC
BR
&EXEC
BR
R5
BR
@R5
BR
@R5+
BR
X(R5)
B-16
Instruction Set Overview
CALL Syntax Operation
Subroutine CALL dst SP - 2 PC tmp dst -> tmp -> SP -> @SP -> PC dst is evaluated and stored PC updated to TOS dst saved to PC
Description
A subroutine call is made to an address anywhere in the 64K address space. All addressing modes can be used. The return address (the address of the following instruction) is stored on the stack. The call instruction is a word instruction. Status bits are not affected. Examples for all addressing modes are given. CALL #EXEC ; Call on label EXEC or immediate address (e.g. #0A4h) ; SP-2 SP, PC+2 @SP, @PC+ PC ; Call on the address contained in EXEC ; SP-2 SP, PC+2 @SP, X(PC) PC ; Indirect address ; Call on the address contained in absolute address ; EXEC ; SP-2 SP, PC+2 @SP, X(PC) PC ; Indirect address ; Call on the address contained in R5 ; SP-2 SP, PC+2 @SP, R5 PC ; Indirect R5 ; Call on the address contained in the word ; pointed to by R5 ; SP-2 SP, PC+2 @SP, @R5 PC ; Indirect, indirect R5 ; Call on the address contained in the word ; pointed to by R5 and increment pointer in R5. ; The next time--S/W flow uses R5 pointer-- ; it can alter the program execution due to ; access to next address in a table pointed to by R5 ; SP-2 SP, PC+2 @SP, @R5 PC ; Indirect, indirect R5 with autoincrement ; Call on the address contained in the address pointed ; to by R5 + X (e.g. table with address starting at X) ; X can be an address or a label ; SP-2 SP, PC+2 @SP, X(R5) PC ; Indirect indirect R5 + X
Status Bits Example
CALL
EXEC
CALL
&EXEC
CALL
R5
CALL
@R5
CALL
@R5+
CALL
X(R5)
Instruction Set Description
B-17
Instruction Set Overview
* CLR[.W] * CLR.B Syntax
Clear destination Clear destination CLR CLR.B 0 -> dst MOV MOV.B #0,dst #0,dst dst dst or CLR.W dst
Operation Emulation
Description Status Bits Example
The destination operand is cleared. Status bits are not affected. RAM word TONI is cleared. CLR TONI ; 0 -> TONI
Example
Register R5 is cleared. CLR R5
Example
RAM byte TONI is cleared. CLR.B TONI ; 0 -> TONI
B-18
Instruction Set Overview
* CLRC Syntax Operation Emulation Description Status Bits
Clear carry bit CLRC 0 -> C BIC #1,SR
The carry bit (C) is cleared. The clear carry instruction is a word instruction. N: Z: C: V: Not affected Not affected Cleared Not affected
Mode Bits Example
OscOff, CPUOff, and GIE are not affected. The 16-bit decimal counter pointed to by R13 is added to a 32-bit counter pointed to by R12. CLRC DADD DADC ; C=0: defines start @R13,0(R12) ; add 16-bit counter to low word of 32-bit counter 2(R12) ; add carry to high word of 32-bit counter
Instruction Set Description
B-19
Instruction Set Overview
* CLRN Syntax Operation
Clear negative bit CLRN 0N or (.NOT.src .AND. dst -> dst) BIC #4,SR
Emulation Description
The constant 04h is inverted (0FFFBh) and is logically ANDed with the destination operand. The result is placed into the destination. The clear negative bit instruction is a word instruction. N: Z: C: V: Reset to 0 Not affected Not affected Not affected
Status Bits
Mode Bits Example
OscOff, CPUOff, and GIE are not affected. The Negative bit in the status register is cleared. This avoids special treatment with negative numbers of the subroutine called. CLRN CALL ...... ...... JN ...... ...... ...... RET
SUBR
SUBR
SUBRET
; If input is negative: do nothing and return
SUBRET
B-20
Instruction Set Overview
* CLRZ Syntax Operation
Clear zero bit CLRZ 0Z or (.NOT.src .AND. dst -> dst) BIC #2,SR
Emulation Description
The constant 02h is inverted (0FFFDh) and logically ANDed with the destination operand. The result is placed into the destination. The clear zero bit instruction is a word instruction. N: Z: C: V: Not affected Reset to 0 Not affected Not affected
Status Bits
Mode Bits Example
OscOff, CPUOff, and GIE are not affected. The zero bit in the status register is cleared. CLRZ
Instruction Set Description
B-21
Instruction Set Overview
CMP[.W] CMP.B Syntax
Compare source and destination Compare source and destination CMP CMP.B src,dst src,dst or CMP.W src,dst
Operation
dst + .NOT.src + 1 or (dst - src) The source operand is subtracted from the destination operand. This is accomplished by adding the 1s complement of the source operand plus 1. The two operands are not affected and the result is not stored; only the status bits are affected. N: Z: C: V: Set if result is negative, reset if positive (src >= dst) Set if result is zero, reset otherwise (src = dst) Set if there is a carry from the MSB of the result, reset otherwise Set if an arithmetic overflow occurs, otherwise reset
Description
Status Bits
Mode Bits Example
OscOff, CPUOff, and GIE are not affected. R5 and R6 are compared. If they are equal, the program continues at the label EQUAL. CMP JEQ R5,R6 EQUAL ; R5 = R6? ; YES, JUMP
Example
Two RAM blocks are compared. If they are not equal, the program branches to the label ERROR. MOV CMP JNZ DEC JNZ #NUM,R5 &BLOCK1,&BLOCK2 ERROR R5 L$1 ; number of words to be compared ; Are Words equal? ; No, branch to ERROR ; Are all words compared? ; No, another compare
L$1
Example
The RAM bytes addressed by EDE and TONI are compared. If they are equal, the program continues at the label EQUAL. CMP.B EDE,TONI JEQ EQUAL ; MEM(EDE) = MEM(TONI)? ; YES, JUMP
Example
Check two keys connected to port pins P0 and P1. If key1 is pressed, the program branches to label MENU1; if key2 is pressed, the program branches to MENU2. P0IN KEY1 KEY2 .EQU .EQU .EQU CMP.B JEQ CMP.B JEQ 010h 01h 02h #KEY1,&P0IN MENU1 #KEY2,&P0IN MENU2
B-22
Instruction Set Overview
* DADC[.W] * DADC.B Syntax
Add carry decimally to destination Add carry decimally to destination DADC DADC.B dst dst or DADC.W src,dst
Operation Emulation
dst + C -> dst (decimally) DADD DADD.B #0,dst #0,dst
Description Status Bits
The carry bit (C) is added decimally to the destination. N: Set if MSB is 1 Z: Set if dst is 0, reset otherwise C: Set if destination increments from 9999 to 0000, reset otherwise Set if destination increments from 99 to 00, reset otherwise V: Undefined OscOff, CPUOff, and GIE are not affected. The four-digit decimal number contained in R5 is added to an eight-digit decimal number pointed to by R8. CLRC DADD DADC R5,0(R8) 2(R8) ; Reset carry ; next instruction's start condition is defined ; Add LSDs + C ; Add carry to MSD
Mode Bits Example
Example
The two-digit decimal number contained in R5 is added to a four-digit decimal number pointed to by R8. CLRC DADD.B DADC R5,0(R8) 1(R8) ; Reset carry ; next instruction's start condition is defined ; Add LSDs + C ; Add carry to MSDs
Instruction Set Description
B-23
Instruction Set Overview
DADD[.W] DADD.B Syntax
Source and carry added decimally to destination Source and carry added decimally to destination DADD DADD.B src,dst src,dst or DADD.W src,dst
Operation Description
src + dst + C -> dst (decimally) The source operand and the destination operand are treated as four binary coded decimals (BCD) with positive signs. The source operand and the carry bit (C) are added decimally to the destination operand. The source operand is not affected. The previous contents of the destination are lost. The result is not defined for non-BCD numbers. N: Set if the MSB is 1, reset otherwise Z: Set if result is zero, reset otherwise C: Set if the result is greater than 9999 Set if the result is greater than 99 V: Undefined OscOff, CPUOff, and GIE are not affected. The eight-digit BCD number contained in R5 and R6 is added decimally to an eight-digit BCD number contained in R3 and R4 (R6 and R4 contain the MSDs). CLRC DADD DADD JC ; CLEAR CARRY R5,R3 ; add LSDs R6,R4 ; add MSDs with carry OVERFLOW ; If carry occurs go to error handling routine
Status Bits
Mode Bits Example
Example
The two-digit decimal counter in the RAM byte CNT is incremented by one. CLRC DADD.B or SETC DADD.B ; DADC.B ; clear Carry ; increment decimal counter
#1,CNT
#0,CNT
CNT
B-24
Instruction Set Overview
* DEC[.W] * DEC.B Syntax
Decrement destination Decrement destination DEC DEC.B dst dst or DEC.W dst
Operation Emulation Emulation Description
dst - 1 -> dst SUB SUB.B #1,dst #1,dst
The destination operand is decremented by one. The original contents are lost. N: Z: C: V: Set if result is negative, reset if positive Set if dst contained 1, reset otherwise Reset if dst contained 0, set otherwise Set if an arithmetic overflow occurs, otherwise reset. Set if initial value of destination was 08000h, otherwise reset. Set if initial value of destination was 080h, otherwise reset.
Status Bits
Mode Bits
OscOff, CPUOff, and GIE are not affected.
Instruction Set Description
B-25
Instruction Set Overview
Example
R10 is decremented by 1 DEC R10 ; Decrement R10
; Move a block of 255 bytes from memory location starting with EDE to memory location starting with ;TONI. Tables should not overlap: start of destination address TONI must not be within the range EDE ; to EDE+0FEh ; MOV #EDE,R6 MOV #255,R10 L$1 MOV.B @R6+,TONI-EDE-1(R6) DEC R10 JNZ L$1 ; Do not transfer tables using the routine above with the overlap shown in Figure B-4.
Figure B-4.Decrement Overlap
EDE
TONI EDE+254
TONI+254
Example
Memory byte at address LEO is decremented by one. DEC.B LEO ; Decrement MEM(LEO)
; Move a block of 255 bytes from memory location starting with EDE to memory location starting with ; TONI. Tables should not overlap: start of destination address TONI must not be within the range EDE ; to EDE+0FEh ; MOV #EDE,R6 MOV.B #255,LEO L$1 MOV.B @R6+,TONI-EDE-1(R6) DEC.B LEO JNZ L$1
B-26
Instruction Set Overview
* DECD[.W] * DECD.B Syntax
Double-decrement destination Double-decrement destination DECD DECD.B dst dst or DECD.W dst
Operation Emulation Emulation Description Status Bits
dst - 2 -> dst SUB SUB.B #2,dst #2,dst
The destination operand is decremented by two. The original contents are lost. N: Z: C: V: Set if result is negative, reset if positive Set if dst contained 2, reset otherwise Reset if dst contained 0 or 1, set otherwise Set if an arithmetic overflow occurs, otherwise reset. Set if initial value of destination was 08001 or 08000h, otherwise reset. Set if initial value of destination was 081 or 080h, otherwise reset.
Mode Bits Example
OscOff, CPUOff, and GIE are not affected. R10 is decremented by 2. DECD R10 ; Decrement R10 by two
; Move a block of 255 words from memory location starting with EDE to memory location ; starting with TONI ; Tables should not overlap: start of destination address TONI must not be within the ; range EDE to EDE+0FEh ; MOV #EDE,R6 MOV #510,R10 L$1 MOV @R6+,TONI-EDE-2(R6) DECD R10 JNZ L$1 Example Memory at location LEO is decremented by two. DECD.B LEO ; Decrement MEM(LEO)
Decrement status byte STATUS by two. DECD.B STATUS
Instruction Set Description
B-27
Instruction Set Overview
* DINT Syntax Operation
Disable (general) interrupts DINT 0 GIE or (0FFF7h .AND. SR SR BIC #8,SR
/
.NOT.src .AND. dst -> dst)
Emulation Description
All interrupts are disabled. The constant 08h is inverted and logically ANDed with the status register (SR). The result is placed into the SR. N: Z: C: V: Not affected Not affected Not affected Not affected
Status Bits
Mode Bits Example
GIE is reset. OscOff and CPUOff are not affected. The general interrupt enable (GIE) bit in the status register is cleared to allow a nondisrupted move of a 32-bit counter. This ensures that the counter is not modified during the move by any interrupt. DINT NOP MOV MOV EINT ; All interrupt events using the GIE bit are disabled COUNTHI,R5 ; Copy counter COUNTLO,R6 ; All interrupt events using the GIE bit are enabled
Note: Disable Interrupt If any code sequence needs to be protected from interruption, the DINT should be executed at least one instruction before the beginning of the uninterruptible sequence, or should be followed by an NOP.
B-28
Instruction Set Overview
* EINT Syntax Operation
Enable (general) interrupts EINT 1 GIE or (0008h .OR. SR -> SR / .NOT.src .OR. dst -> dst) BIS #8,SR
Emulation Description
All interrupts are enabled. The constant #08h and the status register SR are logically ORed. The result is placed into the SR. N: Z: C: V: Not affected Not affected Not affected Not affected
Status Bits
Mode Bits Example
GIE is set. OscOff and CPUOff are not affected. The general interrupt enable (GIE) bit in the status register is set.
; Interrupt routine of port P0.2 to P0.7 ; The interrupt level is the lowest in the system ; P0IN is the address of the register where all port bits are read. P0IFG is the address of ; the register where all interrupt events are latched. ; PUSH.B &P0IN BIC.B @SP,&P0IFG ; Reset only accepted flags EINT ; Preset port 0 interrupt flags stored on stack ; other interrupts are allowed BIT #Mask,@SP JEQ MaskOK ; Flags are present identically to mask: jump ...... MaskOK BIC #Mask,@SP ...... INCD SP ; Housekeeping: inverse to PUSH instruction ; at the start of interrupt subroutine. Corrects ; the stack pointer. RETI Note: Enable Interrupt The instruction following the enable interrupt instruction (EINT) is always executed, even if an interrupt service request is pending when the interrupts are enable.
Instruction Set Description
B-29
Instruction Set Overview
* INC[.W] * INC.B Syntax
Increment destination Increment destination INC INC.B dst dst or INC.W dst
Operation Emulation Description Status Bits
dst + 1 -> dst ADD #1,dst
The destination operand is incremented by one. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFFh, reset otherwise Set if dst contained 0FFh, reset otherwise C: Set if dst contained 0FFFFh, reset otherwise Set if dst contained 0FFh, reset otherwise V: Set if dst contained 07FFFh, reset otherwise Set if dst contained 07Fh, reset otherwise OscOff, CPUOff, and GIE are not affected. The item on the top of a software stack (not the system stack) for byte data is removed. SSP ; .EQU INC R4 SSP ; Remove TOSS (top of SW stack) by increment ; Do not use INC.B since SSP is a word register
Mode Bits Example
Example
The status byte of a process STATUS is incremented. When it is equal to 11, a branch to OVFL is taken. INC.B CMP.B JEQ STATUS #11,STATUS OVFL
B-30
Instruction Set Overview
* INCD[.W] * INCD.B Syntax
Double-increment destination Double-increment destination INCD INCD.B dst dst or INCD.W dst
Operation Emulation Emulation Example Status Bits
dst + 2 -> dst ADD ADD.B #2,dst #2,dst
The destination operand is incremented by two. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFEh, reset otherwise Set if dst contained 0FEh, reset otherwise C: Set if dst contained 0FFFEh or 0FFFFh, reset otherwise Set if dst contained 0FEh or 0FFh, reset otherwise V: Set if dst contained 07FFEh or 07FFFh, reset otherwise Set if dst contained 07Eh or 07Fh, reset otherwise OscOff, CPUOff, and GIE are not affected. The item on the top of the stack (TOS) is removed without using a register. ....... PUSH INCD
Mode Bits Example
R5 SP
; R5 is the result of a calculation, which is stored ; in the system stack ; Remove TOS by double-increment from stack ; Do not use INCD.B, SP is a word-aligned ; register
RET Example The byte on the top of the stack is incremented by two. INCD.B 0(SP) ; Byte on TOS is increment by two
Instruction Set Description
B-31
Instruction Set Overview
* INV[.W] * INV.B Syntax
Invert destination Invert destination INV INV.B dst dst
Operation Emulation Emulation Description Status Bits
.NOT.dst -> dst XOR XOR.B #0FFFFh,dst #0FFh,dst
The destination operand is inverted. The original contents are lost. N: Set if result is negative, reset if positive Z: Set if dst contained 0FFFFh, reset otherwise Set if dst contained 0FFh, reset otherwise C: Set if result is not zero, reset otherwise ( = .NOT. Zero) Set if result is not zero, reset otherwise ( = .NOT. Zero) V: Set if initial destination operand was negative, otherwise reset OscOff, CPUOff, and GIE are not affected. Content of R5 is negated (twos complement). MOV #00Aeh,R5 ; INV R5 ; Invert R5, INC R5 ; R5 is now negated, Content of memory byte LEO is negated. MOV.B INV.B INC.B #0AEh,LEO ; MEM(LEO) = 0AEh LEO ; Invert LEO, MEM(LEO) = 051h LEO ; MEM(LEO) is negated,MEM(LEO) = 052h
Mode Bits Example
R5 = 000AEh R5 = 0FF51h R5 = 0FF52h
Example
B-32
Instruction Set Overview
JC JHS Syntax
Jump if carry set Jump if higher or same JC JHS label label
Operation
If C = 1: PC + 2 x offset -> PC If C = 0: execute following instruction The status register carry bit (C) is tested. If it is set, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If C is reset, the next instruction following the jump is executed. JC (jump if carry/higher or same) is used for the comparison of unsigned numbers (0 to 65536). Status bits are not affected. The P0IN.1 signal is used to define or control the program flow. BIT JC ...... #10h,&P0IN PROGA ; State of signal -> Carry ; If carry=1 then execute program routine A ; Carry=0, execute program here
Description
Status Bits Example
Example
R5 is compared to 15. If the content is higher or the same, branch to LABEL. CMP JHS ...... #15,R5 LABEL ; Jump is taken if R5 15 ; Continue here if R5 < 15
Instruction Set Description
B-33
Instruction Set Overview
JEQ, JZ Syntax Operation
Jump if equal, jump if zero JEQ label, JZ label
If Z = 1: PC + 2 x offset -> PC If Z = 0: execute following instruction The status register zero bit (Z) is tested. If it is set, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If Z is not set, the instruction following the jump is executed. Status bits are not affected. Jump to address TONI if R7 contains zero. TST JZ R7 TONI ; Test R7 ; if zero: JUMP
Description
Status Bits Example
Example
Jump to address LEO if R6 is equal to the table contents. CMP JEQ ...... R6,Table(R5) LEO ; Compare content of R6 with content of ; MEM (table address + content of R5) ; Jump if both data are equal ; No, data are not equal, continue here
Example
Branch to LABEL if R5 is 0. TST JZ ...... R5 LABEL
B-34
Instruction Set Overview
JGE Syntax Operation
Jump if greater or equal JGE label
If (N .XOR. V) = 0 then jump to label: PC + 2 x offset -> PC If (N .XOR. V) = 1 then execute the following instruction The status register negative bit (N) and overflow bit (V) are tested. If both N and V are set or reset, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If only one is set, the instruction following the jump is executed. This allows comparison of signed integers.
Description
Status Bits Example
Status bits are not affected. When the content of R6 is greater or equal to the memory pointed to by R7, the program continues at label EDE. CMP JGE ...... ...... ...... @R7,R6 EDE ; R6 (R7)?, compare on signed numbers ; Yes, R6 (R7) ; No, proceed
Instruction Set Description
B-35
Instruction Set Overview
JL Syntax Operation
Jump if less JL label
If (N .XOR. V) = 1 then jump to label: PC + 2 x offset -> PC If (N .XOR. V) = 0 then execute following instruction The status register negative bit (N) and overflow bit (V) are tested. If only one is set, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If both N and V are set or reset, the instruction following the jump is executed. This allows comparison of signed integers.
Description
Status Bits Example
Status bits are not affected. When the content of R6 is less than the memory pointed to by R7, the program continues at label EDE. CMP JL ...... ...... ...... @R7,R6 EDE ; R6 < (R7)?, compare on signed numbers ; Yes, R6 < (R7) ; No, proceed
B-36
Instruction Set Overview
JMP Syntax Operation Description
Jump unconditionally MP label
PC + 2 x offset -> PC The 10-bit signed offset contained in the instruction LSBs is added to the program counter. Status bits are not affected. This one-word instruction replaces the BRANCH instruction in the range of - 511 to +512 words relative to the current program counter.
Status Bits Hint:
Instruction Set Description
B-37
Instruction Set Overview
JN Syntax Operation
Jump if negative JN label
if N = 1: PC + 2 x offset -> PC if N = 0: execute following instruction The negative bit (N) of the status register is tested. If it is set, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If N is reset, the next instruction following the jump is executed. Status bits are not affected. The result of a computation in R5 is to be subtracted from COUNT. If the result is negative, COUNT is to be cleared and the program continues execution in another path. SUB JN ...... ...... ...... ...... CLR ...... ...... ...... R5,COUNT L$1 ; COUNT - R5 -> COUNT ; If negative continue with COUNT=0 at PC=L$1 ; Continue with COUNT0
Description
Status Bits Example
L$1
COUNT
B-38
Instruction Set Overview
JNC JLO Syntax
Jump if carry not set Jump if lower JNC JNC label label
Operation
if C = 0: PC + 2 x offset -> PC if C = 1: execute following instruction The status register carry bit (C) is tested. If it is reset, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If C is set, the next instruction following the jump is executed. JNC (jump if no carry/lower) is used for the comparison of unsigned numbers (0 to 65536). Status bits are not affected. The result in R6 is added in BUFFER. If an overflow occurs, an error handling routine at address ERROR is used. ADD JNC ...... ...... ...... ...... ...... ...... ...... R6,BUFFER CONT ; BUFFER + R6 -> BUFFER ; No carry, jump to CONT ; Error handler start
Description
Status Bits Example
ERROR
CONT
; Continue with normal program flow
Example
Branch to STL 2 if byte STATUS contains 1 or 0. CMP.B JLO ...... #2,STATUS STL2
; STATUS < 2 ; STATUS 2, continue here
Instruction Set Description
B-39
Instruction Set Overview
JNE, JNZ Syntax Operation
Jump if not equal, jump if not zero JNE label, JNZ label
If Z = 0: PC + 2 x offset -> PC If Z = 1: execute following instruction The status register zero bit (Z) is tested. If it is reset, the 10-bit signed offset contained in the instruction LSBs is added to the program counter. If Z is set, the next instruction following the jump is executed. Status bits are not affected. Jump to address TONI if R7 and R8 have different contents. CMP JNE ...... R7,R8 TONI ; COMPARE R7 WITH R8 ; if different: jump ; if equal, continue
Description
Status Bits Example
B-40
Instruction Set Overview
MOV[.W] MOV.B Syntax
Move source to destination Move source to destination MOV MOV.B src -> dst The source operand is moved to the destination. The source operand is not affected. The previous contents of the destination are lost. Status bits are not affected. OscOff, CPUOff, and GIE are not affected. The contents of table EDE (word data) are copied to table TOM. The length of the tables must be 020h locations. MOV MOV MOV DEC JNZ ...... ...... ...... #EDE,R10 #020h,R9 @R10+,TOM-EDE-2(R10) R9 Loop ; Prepare pointer ; Prepare counter ; Use pointer in R10 for both tables ; Decrement counter ; Counter 0, continue copying ; Copying completed src,dst src,dst or MOV.W src,dst
Operation Description
Status Bits Mode Bits Example
Loop
Example
The contents of table EDE (byte data) are copied to table TOM. The length of the tables should be 020h locations MOV #EDE,R10 MOV #020h,R9 MOV.B @R10+,TOM-EDE-1(R10) DEC JNZ ...... ...... ...... R9 Loop ; Prepare pointer ; Prepare counter ; Use pointer in R10 for ; both tables ; Decrement counter ; Counter 0, continue ; copying ; Copying completed
Loop
Instruction Set Description
B-41
Instruction Set Overview
* NOP Syntax Operation Emulation Description
No operation NOP None MOV #0,#0
No operation is performed. The instruction may be used for the elimination of instructions during the software check or for defined waiting times. Status bits are not affected. The NOP instruction is mainly used for two purposes:
Status Bits
-
To hold one, two or three memory words To adjust software timing
Note: Emulating No-Operation Instruction Other instructions can emulate no-operation instruction using different numbers of cycles and code words. Examples: MOV MOV BIC JMP BIC 0(R4),0(R4) @R4,0(R4) #0,EDE(R4) $+2 #0,R5 ; 6 cycles, 3 words ; 5 cycles, 2 words ; 4 cycles, 2 words ; 2 cycles, 1 word ; 1 cycle, 1 word
B-42
Instruction Set Overview
* POP[.W] * POP.B Syntax
Pop word from stack to destination Pop byte from stack to destination POP POP.B dst dst
Operation
@SP -> dst SP + 2 -> SP MOV MOV.B @SP+,dst @SP+,dst or MOV.W @SP+,dst
Emulation Emulation Description
The stack location pointed to by the stack pointer (TOS) is moved to the destination. The stack pointer is incremented by two afterwards. Status bits are not affected. The contents of R7 and the status register are restored from the stack. POP POP R7 SR ; Restore R7 ; Restore status register
Status Bits Example
Example
The contents of RAM byte LEO is restored from the stack. POP.B LEO ; The low byte of the stack is moved to LEO.
Example
The contents of R7 is restored from the stack. POP.B R7 ; The low byte of the stack is moved to R7, ; the high byte of R7 is 00h
Example
The contents of the memory pointed to by R7 and the status register are restored from the stack. POP.B 0(R7) ; The low byte of the stack is moved to the ; the byte which is pointed to by R7 : Example: R7 = 203h ; Mem(R7) = low byte of system stack : Example: R7 = 20Ah ; Mem(R7) = low byte of system stack
POP
SR
Note: The System Stack Pointer The system stack pointer (SP) is always incremented by two, independent of the byte suffix.
Instruction Set Description
B-43
Instruction Set Overview
PUSH[.W] PUSH.B Syntax
Push word onto stack Push byte onto stack PUSH PUSH.B SP - 2 SP src @SP The stack pointer is decremented by two, then the source operand is moved to the RAM word addressed by the stack pointer (TOS). N: Z: C: V: Not affected Not affected Not affected Not affected src src or PUSH.W src
Operation
Description
Status Bits
Mode Bits Example
OscOff, CPUOff, and GIE are not affected. The contents of the status register and R8 are saved on the stack. PUSH PUSH SR R8 ; save status register ; save R8
Example
The contents of the peripheral TCDAT is saved on the stack. PUSH.B &TCDAT ; save data from 8-bit peripheral module, ; address TCDAT, onto stack
Note: The System Stack Pointer The system stack pointer (SP) is always decremented by two, independent of the byte suffix.
B-44
Instruction Set Overview
* RET Syntax Operation
Return from subroutine RET @SP PC SP + 2 SP MOV @SP+,PC
Emulation Description
The return address pushed onto the stack by a CALL instruction is moved to the program counter. The program continues at the code address following the subroutine call. Status bits are not affected.
Status Bits
Instruction Set Description
B-45
Instruction Set Overview
RETI Syntax Operation
Return from interrupt RETI TOS SP + 2 TOS SP + 2 SR SP PC SP
Description
The status register is restored to the value at the beginning of the interrupt service routine by replacing the present SR contents with the TOS contents. The stack pointer (SP) is incremented by two. The program counter is restored to the value at the beginning of interrupt service. This is the consecutive step after the interrupted program flow. Restoration is performed by replacing the present PC contents with the TOS memory contents. The stack pointer (SP) is incremented.
Status Bits
N: Z: C: V:
restored from system stack restored from system stack restored from system stack restored from system stack
Mode Bits Example
OscOff, CPUOff, and GIE are restored from system stack. Figure B-5 illustrates the main program interrupt.
Figure B-5.Main Program Interrupt
PC -6 PC -4 PC -2 PC PC +2 PC +4 PC +6 PC +8 Interrupt Accepted PC+2 is Stored Onto Stack PC = PCi PCi +2 PCi +4 Interrupt Request
PCi +n-4 PCi +n-2 PCi +n RETI
B-46
Instruction Set Overview
* RLA[.W] * RLA.B Syntax Operation Emulation Description
Rotate left arithmetically Rotate left arithmetically RLA RLA.B dst dst or RLA.W dst
C <- MSB <- MSB-1 .... LSB+1 <- LSB <- 0 ADD ADD.B dst,dst dst,dst
The destination operand is shifted left one position as shown in Figure B-6. The MSB is shifted into the carry bit (C) and the LSB is filled with 0. The RLA instruction acts as a signed multiplication by 2. An overflow occurs if dst 04000h and dst < 0C000h before operation is performed: the result has changed sign.
Figure B-6.Destination Operand--Arithmetic Shift Left
Word C Byte 7 0 15 0 0
An overflow occurs if dst 040h and dst < 0C0h before the operation is performed: the result has changed sign. Status Bits N: Z: C: V: Set if result is negative, reset if positive Set if result is zero, reset otherwise Loaded from the MSB Set if an arithmetic overflow occurs: the initial value is 04000h dst < 0C000h; otherwise it is reset Set if an arithmetic overflow occurs: the initial value is 040h dst < 0C0h; otherwise it is reset
Mode Bits Example
OscOff, CPUOff, and GIE are not affected. R7 is multiplied by 4. RLA RLA R7 R7 ; Shift left R7 (x 2) - emulated by ADD R7,R7 ; Shift left R7 (x 4) - emulated by ADD R7,R7
Example
The low byte of R7 is multiplied by 4. RLA.B RLA.B R7 R7 ; Shift left low byte of R7 (x 2) - emulated by ; ADD.B R7,R7 ; Shift left low byte of R7 (x 4) - emulated by ; ADD.B R7,R7
Note: RLA Substitution The assembler does not recognize the instruction: RLA @R5+ nor RLA.B @R5+.
It must be substituted by: ADD @R5+,-2(R5) or ADD.B @R5+,-1(R5).
Instruction Set Description
B-47
Instruction Set Overview
* RLC[.W] * RLC.B Syntax Operation Emulation Description
Rotate left through carry Rotate left through carry RLC RLC.B dst dst or RLC.W dst
C <- MSB <- MSB-1 .... LSB+1 <- LSB <- C ADDC dst,dst
The destination operand is shifted left one position as shown in Figure B-7. The carry bit (C) is shifted into the LSB and the MSB is shifted into the carry bit (C).
Figure B-7.Destination Operand--Carry Left Shift
Word C Byte 7 0 15 0
Status Bits
N: Z: C: V:
Set if result is negative, reset if positive Set if result is zero, reset otherwise Loaded from the MSB Set if arithmetic overflow occurs, reset otherwise Set if 03FFFh < dstinitial < 0C000h, reset otherwise Set if 03Fh < dstinitial < 0C0h, reset otherwise
Mode Bits Example
OscOff, CPUOff, and GIE are not affected. R5 is shifted left one position. RLC R5 ; (R5 x 2) + C -> R5
Example
The input P0IN.1 information is shifted into the LSB of R5. BIT.B RLC #2,&P0IN R5 ; Information -> Carry ; Carry=P0in.1 -> LSB of R5
Example
The MEM(LEO) content is shifted left one position. RLC.B LEO ; Mem(LEO) x 2 + C -> Mem(LEO)
Example
The input P0IN.1 information is to be shifted into the LSB of R5. BIT.B RLC.B #2,&P0IN R5 ; Information -> Carry ; Carry = P0in.1 -> LSB of R5 ; High byte of R5 is reset
Note: RLC and RLC.B Emulation The assembler does not recognize the instruction: RLC @R5+.
It must be substituted by: ADDC @R5+,-2(R5).
B-48
Instruction Set Overview
RRA[.W] RRA.B Syntax
Rotate right arithmetically Rotate right arithmetically RRA RRA.B dst dst or RRA.W dst
Operation Description
MSB -> MSB, MSB -> MSB-1, ... LSB+1 -> LSB,
LSB -> C
The destination operand is shifted right one position as shown in Figure B-8. The MSB is shifted into the MSB, the MSB is shifted into the MSB-1, and the LSB+1 is shifted into the LSB.
Figure B-8.Destination Operand--Arithmetic Right Shift
Word C Byte 15 0 15 0
Status Bits
N: Z: C: V:
Set if result is negative, reset if positive Set if result is zero, reset otherwise Loaded from the LSB Reset
Mode Bits
OscOff, CPUOff, and GIE are not affected.
Instruction Set Description
B-49
Running Title--Attribute Reference
Example
R5 is shifted right one position. The MSB retains the old value. It operates equal to an arithmetic division by 2. RRA R5 ; R5/2 -> R5
; ;
The value in R5 is multiplied by 0.75 (0.5 + 0.25). PUSH RRA ADD RRA ...... ...... R5 R5 @SP+,R5 R5 ; hold R5 temporarily using stack ; R5 x 0.5 -> R5 ; R5 x 0.5 + R5 = 1.5 x R5 -> R5 ; (1.5 x R5) x 0.5 = 0.75 x R5 -> R5
; OR ; RRA PUSH RRA ADD ...... Example R5 R5 @SP @SP+,R5 ; R5 x 0.5 -> R5 ; R5 x 0.5 -> TOS ; TOS x 0.5 = 0.5 x R5 x 0.5 = 0.25 x R5 -> TOS ; R5 x 0.5 + R5 x 0.25 = 0.75 x R5 -> R5
The low byte of R5 is shifted right one position. The MSB retains the old value. It operates equal to an arithmetic division by 2. RRA.B R5 ; R5/2 -> R5: operation is on low byte only ; High byte of R5 is reset
; ;
The value in R5 (low byte only) is multiplied by 0.75 (0.5 + 0.25). PUSH.B RRA.B ADD.B RRA.B ...... R5 R5 @SP+,R5 R5 ; hold low byte of R5 temporarily using stack ; R5 x 0.5 -> R5 ; R5 x 0.5 + R5 = 1.5 x R5 -> R5 ; (1.5 x R5) x 0.5 = 0.75 x R5 -> R5
; OR ; RRA.B PUSH.B RRA.B ADD.B ...... R5 R5 @SP @SP+,R5 ; R5 x 0.5 -> R5 ; R5 x 0.5 -> TOS ;TOS x 0.5 = 0.5 x R5 x 0.5 = 0.25 x R5 -> TOS ; R5 x 0.5 + R5 x 0.25 = 0.75 x R5 -> R5
B-50
Instruction Set Overview
RRC[.W] RRC.B Syntax
Rotate right through carry Rotate right through carry RRC RRC dst dst or RRC.W dst
Operation Description
C -> MSB -> MSB-1 .... LSB+1 -> LSB -> C The destination operand is shifted right one position as shown in Figure B-6. The carry bit (C) is shifted into the MSB, the LSB is shifted into the carry bit (C).
Figure B-9.Destination Operand--Carry Right Shift
Word C Byte 7 0 15 0
Status Bits
N: Z: C: V:
Set if result is negative, reset if positive Set if result is zero, reset otherwise Loaded from the LSB Set if initial destination is positive and initial carry is set, otherwise reset
Mode Bits Example
OscOff, CPUOff, and GIE are not affected. R5 is shifted right one position. The MSB is loaded with 1. SETC RRC ; Prepare carry for MSB ; R5/2 + 8000h -> R5
R5
Example
R5 is shifted right one position. The MSB is loaded with 1. SETC RRC.B ; Prepare carry for MSB ; R5/2 + 80h -> R5; low byte of R5 is used
R5
Instruction Set Description
B-51
Instruction Set Overview
* SBC[.W] * SBC.B Syntax
Subtract (borrow*) from destination Subtract (borrow*) from destination SBC SBC.B dst dst or SBC.W dst
Operation
dst + 0FFFFh + C -> dst dst + 0FFh + C -> dst SUBC SUBC.B #0,dst #0,dst
Emulation
Description
The carry bit (C) is added to the destination operand minus one. The previous contents of the destination are lost. N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Reset if dst was decremented from 0000 to 0FFFFh, set otherwise Reset if dst was decremented from 00 to 0FFh, set otherwise V: Set if initially C = 0 and dst = 08000h Set if initially C = 0 and dst = 080h OscOff, CPUOff, and GIE are not affected. The 16-bit counter pointed to by R13 is subtracted from a 32-bit counter pointed to by R12. SUB SBC @R13,0(R12) 2(R12) ; Subtract LSDs ; Subtract carry from MSD
Status Bits
Mode Bits Example
Example
The 8-bit counter pointed to by R13 is subtracted from a 16-bit counter pointed to by R12. SUB.B SBC.B @R13,0(R12) 1(R12) ; Subtract LSDs ; Subtract carry from MSD
Note: Borrow Is Treated as a .NOT. The borrow is treated as a .NOT. carry : Borrow Yes No Carry bit 0 1
B-52
Instruction Set Overview
* SETC Syntax Operation Emulation Description Status Bits
Set carry bit SETC 1 -> C BIS #1,SR
The carry bit (C) is set. N: Z: C: V: Not affected Not affected Set Not affected
Mode Bits Example
OscOff, CPUOff, and GIE are not affected. Emulation of the decimal subtraction: Subtract R5 from R6 decimally Assume that R5 = 3987 and R6 = 4137 ADD INV SETC DADD #6666h,R5 R5 ; Move content R5 from 0-9 to 6-0Fh ; R5 = 03987 + 6666 = 09FEDh ; Invert this (result back to 0-9) ; R5 = .NOT. R5 = 06012h ; Prepare carry = 1 ; Emulate subtraction by addition of: ; (10000 - R5 - 1) ; R6 = R6 + R5 + 1 ; R6 = 4137 + 06012 + 1 = 1 0150 = 0150
DSUB
R5,R6
Instruction Set Description
B-53
Instruction Set Overview
* SETN Syntax Operation Emulation Description Status Bits
Set negative bit SETN 1 -> N BIS #4,SR
The negative bit (N) is set. N: Z: C: V: Set Not affected Not affected Not affected
Mode Bits
OscOff, CPUOff, and GIE are not affected.
B-54
Instruction Set Overview
* SETZ Syntax Operation Emulation Description Status Bits
Set zero bit SETZ 1 -> Z BIS #2,SR
The zero bit (Z) is set. N: Z: C: V: Not affected Set Not affected Not affected
Mode Bits
OscOff, CPUOff, and GIE are not affected.
Instruction Set Description
B-55
Instruction Set Overview
SUB[.W] SUB.B Syntax
Subtract source from destination Subtract source from destination SUB SUB.B src,dst src,dst or SUB.W src,dst
Operation
dst + .NOT.src + 1 -> dst or [(dst - src -> dst)] The source operand is subtracted from the destination operand by adding the source operand's 1s complement and the constant 1. The source operand is not affected. The previous contents of the destination are lost. N: Set if result is negative, reset if positive Z: Set if result is zero, reset otherwise C: Set if there is a carry from the MSB of the result, reset otherwise. Set to 1 if no borrow, reset if borrow. V: Set if an arithmetic overflow occurs, otherwise reset OscOff, CPUOff, and GIE are not affected. See example at the SBC instruction. See example at the SBC.B instruction. Note: Borrow Is Treated as a .NOT. The borrow is treated as a .NOT. carry : Borrow Yes No Carry bit 0 1
Description
Status Bits
Mode Bits Example Example
B-56
Instruction Set Overview
SUBC[.W]SBB[.W] SUBC.B,SBB.B Syntax
Subtract source and borrow/.NOT. carry from destination Subtract source and borrow/.NOT. carry from destination SUBC SBB SUBC.B src,dst src,dst src,dst or or or SUBC.W SBB.W SBB.B src,dst src,dst src,dst or
Operation
dst + .NOT.src + C -> dst or (dst - src - 1 + C -> dst) The source operand is subtracted from the destination operand by adding the source operand's 1s complement and the carry bit (C). The source operand is not affected. The previous contents of the destination are lost. N: Set if result is negative, reset if positive. Z: Set if result is zero, reset otherwise. C: Set if there is a carry from the MSB of the result, reset otherwise. Set to 1 if no borrow, reset if borrow. V: Set if an arithmetic overflow occurs, reset otherwise. OscOff, CPUOff, and GIE are not affected. Two floating point mantissas (24 bits) are subtracted. LSBs are in R13 and R10, MSBs are in R12 and R9. SUB.W SUBC.B R13,R10 ; 16-bit part, LSBs R12,R9 ; 8-bit part, MSBs
Description
Status Bits
Mode Bits Example
Example
The 16-bit counter pointed to by R13 is subtracted from a 16-bit counter in R10 and R11(MSD). SUB.B SUBC.B ... @R13+,R10 @R13,R11 ; Subtract LSDs without carry ; Subtract MSDs with carry ; resulting from the LSDs
Note: Borrow Is Treated as a .NOT. Carry The borrow is treated as a .NOT. carry : Borrow Yes No Carry bit 0 1
Instruction Set Description
B-57
Instruction Set Overview
SWPB Syntax Operation Description
Swap bytes SWPB dst
Bits 15 to 8 <-> bits 7 to 0 The destination operand high and low bytes are exchanged as shown in Figure B-10. N: Z: C: V: Not affected Not affected Not affected Not affected
Status Bits
Mode Bits
OscOff, CPUOff, and GIE are not affected.
Figure B-10. Destination Operand Byte Swap
15 8 7 0
Example MOV SWPB Example #040BFh,R7 R7 ; 0100000010111111 -> R7 ; 1011111101000000 in R7
The value in R5 is multiplied by 256. The result is stored in R5,R4. SWPB MOV BIC BIC R5 R5,R4 #0FF00h,R5 #00FFh,R4 ; ;Copy the swapped value to R4 ;Correct the result ;Correct the result
B-58
Instruction Set Overview
SXT Syntax Operation Description Status Bits
Extend Sign SXT dst
Bit 7 -> Bit 8 ......... Bit 15 The sign of the low byte is extended into the high byte as shown in Figure B-11. N: Z: C: V: Set if result is negative, reset if positive Set if result is zero, reset otherwise Set if result is not zero, reset otherwise (.NOT. Zero) Reset
Mode Bits
OscOff, CPUOff, and GIE are not affected.
Figure B-11. Destination Operand Sign Extension
15 8 7 0
Example
R7 is loaded with the Timer/Counter value. The operation of the sign-extend instruction expands bit 8 to bit 15 with the value of bit 7. R7 is then added to R6. MOV.B SXT ADD &TCDAT,R7 R7 R7,R6 ; TCDAT = 080h: . . . . . . . . 1000 0000 ; R7 = 0FF80h: 1111 1111 1000 0000 ; add value of EDE to 16-bit ACCU
Instruction Set Description
B-59
Instruction Set Overview
* TST[.W] * TST.B Syntax
Test destination Test destination TST TST.B dst dst or TST.W dst
Operation
dst + 0FFFFh + 1 dst + 0FFh + 1 CMP CMP.B #0,dst #0,dst
Emulation
Description
The destination operand is compared with zero. The status bits are set according to the result. The destination is not affected. N: Z: C: V: Set if destination is negative, reset if positive Set if destination contains zero, reset otherwise Set Reset
Status Bits
Mode Bits Example
OscOff, CPUOff, and GIE are not affected. R7 is tested. If it is negative, continue at R7NEG; if it is positive but not zero, continue at R7POS. TST JN JZ ...... ...... ...... R7 R7NEG R7ZERO ; Test R7 ; R7 is negative ; R7 is zero ; R7 is positive but not zero ; R7 is negative ; R7 is zero
R7POS R7NEG R7ZERO Example
The low byte of R7 is tested. If it is negative, continue at R7NEG; if it is positive but not zero, continue at R7POS. TST.B JN JZ ...... ..... ...... R7 R7NEG R7ZERO ; Test low byte of R7 ; Low byte of R7 is negative ; Low byte of R7 is zero ; Low byte of R7 is positive but not zero ; Low byte of R7 is negative ; Low byte of R7 is zero
R7POS R7NEG R7ZERO
B-60
Instruction Set Overview
XOR[.W] XOR.B Syntax
Exclusive OR of source with destination Exclusive OR of source with destination XOR XOR.B src,dst src,dst or XOR.W src,dst
Operation Description
src .XOR. dst -> dst The source and destination operands are exclusive ORed. The result is placed into the destination. The source operand is not affected. N: Z: C: V: Set if result MSB is set, reset if not set Set if result is zero, reset otherwise Set if result is not zero, reset otherwise ( = .NOT. Zero) Set if both operands are negative
Status Bits
Mode Bits Example
OscOff, CPUOff, and GIE are not affected. The bits set in R6 toggle the bits in the RAM word TONI. XOR R6,TONI ; Toggle bits of word TONI on the bits set in R6
Example
The bits set in R6 toggle the bits in the RAM byte TONI. XOR.B R6,TONI ; Toggle bits in word TONI on bits ; set in low byte of R6,
Example
Reset to 0 those bits in low byte of R7 that are different from bits in RAM byte EDE. XOR.B INV.B EDE,R7 R7 ; Set different bit to 1s ; Invert Lowbyte, Highbyte is 0h
Instruction Set Description
B-61
B-62
Appendix C
Flash Memory
This chapter describes the MSP430 flash memory module. The flash memory module is electrically erasable and programmable. Devices with a flash memory module are multiple-time programmable devices (MTP). They can be erased and programmed off-board, or in a system via the MSP430's JTAG peripheral module or via the processor's resources. Software running on an MSP430 device can erase and program the flash memory module. This active software may run in RAM, in ROM, or in the flash memory. The flash memory may be a different memory module or the same memory module. The active software may not be in a memory location which is actively erased.
Topic
C.1 C.2 C.3 C.4 C.5
Page
Flash Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2 Flash Memory Data Structure and Operation . . . . . . . . . . . . . . . . . . . . C-5 Flash Memory Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-13 Flash Memory, Interrupt and Security Key Violation . . . . . . . . . . . . . C-18 Flash Memory Access via JTAG and Software . . . . . . . . . . . . . . . . . . C-22
Flash Memory
C-1
Flash Memory Organization
C.1 Flash Memory Organization
The flash memory may have one or more modules of different sizes as shown in Figure C-1. A module is a physical memory unit that operates independent from other modules. In an MSP430 configuration with more than one flash memory module, all modules are located in one linear-address range.
Figure C-1.Interconnection of Flash Memory Module(s)
ROM RAM
TDI TDO/TDI MAB, 16 Bit CPU Incl. 16 Reg. Test JTAG To Other Peripheral Modules
TMS TCK Test/VPP Optional
MDB, 16 Bit
Flash Memory Module 1
Flash Memory Module 2
Independent modules, such as Module1 and Module2, are intended to execute software code from one module while simultaneously programming or erasing another module. Note: Flash Memory Module(s) in MSP430 Devices Different devices may have one or more flash memory modules. If the active software and the target programming location are in the same flash memory module, the program execution is halted (flag BUSY=1) until the programming cycle is completed (flag BUSY=0). Then it proceeds with the next instruction. The active software may also erase segments of the flash memory module. The user should be careful not to erase memory locations that are necessary to execute the software correctly. A flash memory module, being programmed or erased, can not be accessed. Figure C-2 shows the flash memory Module1 in program or erase operation. During this operation the module is disconnected from the memory address
C-2
Flash Memory Organization
bus and memory data bus. When a second module (here Module2) is implemented, program code in this module can be executed while Module1 is disconnected.
Figure C-2.Flash Memory Module1 Disabled, Module2 Can Execute Code Simultaneously
ROM RAM
TDI TDO/TDI MAB, 16 Bit CPU Incl. 16 Reg. Test JTAG To Other Peripheral Modules
TMS TCK Test/VPP Optional
MDB, 16 Bit
Flash Memory Module 1
Flash Memory Module 2
One MSP430 flash memory module will have, in addition to its code segments, extra flash memory called information memory.
Flash Memory
C-3
Flash Memory Organization
Figure C-3.Flash Memory Module Example
ONE module Flash Memory 4Kbyte + 256Byte FFFFh 4-kbyte Flash Memory F000h
010FFh 01000h
256-Byte Flash Memory
A module has several segments. The information memory has two segments of 128 bytes each. In the example in Figure C-4, the 4-kB module has eight segments of 512 bytes (Segment0 to Segment7), and two 128-byte segments (SegmentA and SegmentB). Segment0 to Segment7 can be erased individually or as a group. SegmentA and SegmentB can be erased individually or as a group with segments 0 to 7. The segment structure is described in the device's data sheet. The information memory can be located directly below the main memory's address, or at a different address but will be in the same module. Note: Flash memory modules may have different numbers of segments. Segment are numbered from 0 up to n, e.g., segment 0 to segment n.
C-4
Flash Memory Data Structure and Operation
Figure C-4.Segments in Flash Memory Module, 4K-Byte Example
Flash Memory One Module 4Kbyte + 256Byte FFFFh 4-kbyte Flash Main Memory F000h 010FFh 01000h 256-Byte Flash Information Memory FFFFh FE00h FDFFh FC00h Flash Memory One Module Several Segments Segment0 Segment1 Segment2 Segment3 Segment4 Segment5 Segment6 F000h 010FFh Segment7 SegmentA SegmentB
01000h
C.1.1 Why Is a Flash Memory Module Divided Into Several Segments?
Once a bit in flash memory has been programmed, it cannot be erased without erasing a whole segment. For this reason, the MSP430 flash memory modules have been heavily segmented to allow erasing and reprogramming of smaller memory segments.
C.2 Flash Memory Data Structure and Operation
The flash memory can be read and written (programmed) in bytes or words. Bits can be written as 0s once between erase cycles. The read access does not differ from access to masked ROM or RAM. Flash memory has restrictions in write operation:
-
The default (erased) level for all bits is 1. Bits that are not programmed to 0s can be programmed to 0s at any time. The smallest memory portion to be erased is a segment. No single byte or word erase is possible. Access to a flash memory module is only possible when the module is not in a write or erase operation. For example, program code can not be executed in a module while it is processing a write or erase operation. The access limitation has no critical impact on program execution, but an access violation can be flagged in some situations (see flash memory register section in this chapter).
Flash Memory
C-5
Flash Memory Data Structure and Operation
C.2.1 Flash Memory Basic Functions
The basic functions of flash memory are to:
-
Supply program code and data during program execution Erase, under software or JTAG control, parts of a module (one segment), multiple segments, or an entire module. Write data to a memory location under software or JTAG control. A doublespeed programming sequence is implemented within a 64-byte section of the address range xx00h to xx3fh.
C.2.2 Flash Memory Block Diagram
The flash memory module has a minimum of three control registers, a timing generator, a voltage generator to supply program and erase voltages, and the flash memory itself. Data and address are latched when execution of a write (program) or erase operation is in progress.
Figure C-5.Flash Memory Module Block Diagram
MAB
MDB Address Latch Data Latch
FCTL1
FCTL2
Enable Address Latch Flash Memory Array Enable Data Latch
FCTL3
Timing Generator
Programming Voltage Generator
C.2.3 Flash Memory, Basic Operation
The flash memory module works in read mode most of the time, the address and data latch are transparent, and the timing generator and programming voltage generator are off. The flash memory module changes its mode of operation when data is written (programmed) to the module, or when the flash memory, or parts of it, are erased. In these situations, flash control registers FCTL1, FCTL2, and FCTL3 need to be set up properly to ensure correct write
C-6
Flash Memory Data Structure and Operation
or erase operation. Once these registers are set up and write or erase is started, the timing generator controls the entire operation and applies all signals internally. If the BUSY control signal is set, it indicates that the timing generator is active and a write or erase cycle is active. The segment write mode also uses a second control bit WAIT. There are three basic parts to a write or erase cycle: preparation of program/erase voltage, control timing for the program or erase operation, and the switch-off sequence of the program/erase voltage. Once a write or erase function is started, the software should not access the flash memory until the BUSY signal indicates, with 0, that it can be accessed again. In critical situations where flash programming or erase should be immediately stopped, the emergency exit bit EMEX can be set. The current operation may be incomplete or the result may be incorrect. Two different clock sources (ACLK, MCLK, or SMCLK) can be selected to clock the timing generator. The connected clock sources applied to the timing generator may vary with the device, see data sheet for details. The clock source selected should be active from the beginning of write or erase until the operation is fully completed.
Figure C-6.Block Diagram of the Timing Generator in the Flash Memory Module
SSEL1 SSEL0 ACLK MCLK SMCLK SMCLK 0 1 2 3 FN5 ........... FN0 fx Divider, 1-64 PUC Write `1' to EMEX
Reset Flash Timing Generator
Busy
Wait
The selected clock source should be divided to meet the frequency requirement fx of the flash timing generator. If the clock signals are not available throughout the duration of the write or erase operation, or their frequencies change drastically, the result of the write or erase may be marginal, or the flash memory module may be stressed above the limits of reliable operation. Table C-1 shows all useful combinations of control bits for proper write and erase operation:
Flash Memory
C-7
Flash Memory Data Structure and Operation
Table C-1. Control Bits for Write or Erase Operation
FUNCTION PERFORMED
SEGWRT 0 1
WRT 1 1
Meras 0 0
Erase 0 0
BUSY 0 0
WAIT 0 1
Lock 0 0
Write word or byte Write word or byte in same segment, segment write mode Erase one segment by writing to any address in the target segment (0 to n or A or B) Erase all segments (0 to n) but not the information memory (SegmentA and SegmentB) Erase all segments (0 to n and A and B) by writing to any address in the flash memory module
Note:
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
A write to flash memory performed with any other combination of bits SEGWRT, WRT, Meras, Eras, BUSY, WAIT, and Lock will result in an access violation. ACCVIFG is set and an NMI is requested if ACCVIE=1.
C.2.4 Flash Memory Status During Code Execution
The flash memory module delivers data for code execution in the same manner as any masked ROM or RAM. The flash memory module should be in read mode, with no write (programming) or erase operation active. By default, power-on reset (POR) puts the flash memory into read mode. No control bits need to be defined in the flash memory control registers after POR for code execution.
C.2.5 Flash Memory Status During Erase
The default bit level of the flash memory is 1. Any successful erase sets all bits of a segment or a block to this default level. Once a bit is programmed to the 0-level, only the erase function can reset it back to 1. Erase can be performed for one segment, a group of segments, or for an entire module. This can vary for each device configuration, and the exact implementation should be noted in the data sheet. The erase operation starts with the following sequence: 1) Set the correct input-clock frequency of the timing generator by selecting the clock source and predivider. 2) Reset the LOCK control bit, if set. 3) Watch the BUSY bit. Continue to the next steps only if the BUSY bit is reset. 4) Set the erase control bit Erase to erase a segment, or 5) Set the mass-erase control bit MEras to erase a group of segments or 6) Set the mass-erase (MEras) and erase (Erase) control bits to erase the entire flash memory 7) Execute a dummy write to any address in the range to be erased.
C-8
Flash Memory Data Structure and Operation
The dummy write starts the erase cycle. An example of dummy write is CLR &0F012h. Note that a dummy write is ignored in a segment where the selected operation can not be executed successfully. An example of such a situation can take place when Segment 1 is to be erased: the control bits are set properly, but the dummy write is sent to the information memory. No flag indicates this unsuccessful erase situation.
Figure C-7.Basic Flash EEPROM Module Timing During the Erase Cycle
Generate Erase Voltage
Erase Operation Active Entire Erase Cycle Timing
Remove Erase Voltage
Time of Increased Current Consumption From Supply, VCC BUSY
Mass Erase: t(erase) = 5296/fx; Page Erase: t(erase) = 4817/fx
The erase cycle completes successfully when none of the following restrictions is violated:
-
The selected clock source is available until the cycle is completed. The predivider should not be modified during the operation. No further access to the flash memory module is performed while BUSY is set.
J J J -
No read of data from this block No write into this block No further erase of this block
An access will result in setting the KEYV bit and requesting an NMI interrupt. The NMI interrupt routine should handle such violations. The supply voltage should be within the devices' electrical specifications defined in the respective data sheet; however, slight variations can be tolerated.
Control bit BUSY indicates an active erase cycle. It is set immediately after a dummy write starts the timing generator. It remains set until the entire erase cycle is completed and the erased segment or block is ready to be accessed again. The BUSY bit can not be set by software. But it can be reset. In case of emergency, set the emergency exit (EMEX) bit and the erase operation will be stopped immediately; BUSY bit is reset. One example of stop erase by software is when the supply voltage drops drastically and the operating conditions of the controller are exceeded. Another example is when the timing of the erase cycle gets out of control, for example, when the clock-source signal is lost.
Flash Memory
C-9
Flash Memory Data Structure and Operation
Note: When the erase cycle is stopped before its normal completion by the hardware, the timing generator is stopped and erasure of the flash memory can be marginal. An incomplete erasure can be verified. But an erase level of 1 can be inconsistently read as valid when supply voltage, temperature, access time (instruction execution, data read), and frequency vary.
C.2.6 Flash Memory Status During Write (Programming)
The flash memory erase bit level is 1. Bits can only be written (programmed) to a 0-level. Once a bit is programmed, only the erase function can reset it back to the 1-level. The byte or word 0-level can not be written (programmed) in one cycle. Any bit can be programmed from 1 to 0 at any time, but not from 0 to 1. Two slightly different write operations can be performed: write a single byte or word of data, or write a sequence of bytes or words. A write sequence of bytes or words can be performed as multiple sequential, or as a segment write. The segment write is approximately twice as fast as a multiple sequential write algorithm. The write (program) operation starts with the following sequence:
-
Set the correct input clock frequency of the timing generator by selecting the clock source and predivider. Reset the LOCK control bit, if set. Watch the BUSY bit. Continue with the next steps only if the BUSY bit is reset. Set the write-control bit WRT when a single byte of word data is to be written. Set the write WRT and SEGWRT control bits when segment write is chosen to write multiple bytes or words to the flash memory module. Writing the data to the selected address starts the timing generator. The data is written (programmed) while the timing generator proceeds.
Note: Whenever the write cycle is stopped before its normal ending by the hardware, the timing generator is stopped and the data written to the flash memory can be marginal. The data may be incorrect, which can be verified, or the data are verified to be correct but the programming is marginal. Reading of the data may be inconsistently valid when varying the supply voltage, the temperature, the access time (instruction execution, data read), or the time.
C-10
Flash Memory Data Structure and Operation
Figure C-8.Basic Flash Memory Module Timing During Write (Single Byte or Word) Cycle
Generate Programming Voltage
Programming Operation Active Entire Programming Cycle Timing
Remove Programming Voltage
Time of Increased Current Consumption From Supply, VCC BUSY
t(prog) = 33/fx
Figure C-9.Basic Flash Memory Module Timing During a Segment-Write Cycle
SEGWRT bit Write to Flash e.g., MOV #123h, &Flash
Generate Programming Voltage
Programming Operation Active Entire Programming Cycle Timing
Remove Programming Voltage
Time of Increased Current Consumption From Supply, VCC BUSY t(prog_all) =< 25ms WAIT t(prog1) = 30/fx t(prog2) = 20/fx t(prog2) = 20/fx t(prog3) = 5/fx
The segment write can be used on sequential addresses of the memory module. One segment is 64 bytes long, starting at 0xx00h, 0xx40h, 0xx80h, or 0xxC0h, and ending at 0xx3Fh, 0xx7Fh, 0xxBFh, or 0xxFFh. Examples of sequential segment addresses are: 0F000h to 0F03Fh, 0F040h to 0F07Fh,0F080h to 0F0BFh, 0F0C0h to 0F0FFh, 0F100 to 0F13Fh, The segment-write (program) operation at the 64-byte boundaries needs special software support (test of address 0xx3Fh, 0xx7Fh, 0xxBFh, or 0xxFFh was successful):
-
Wait until the WAIT bit is set, indicating that the write of the last byte or word was completed. Reset control bit SEGWRT. The BUSY bit remains set until the programming voltage is removed from the flash memory module and overstress is avoided. Wait the recovery time t(rcv) before another segment write is started.
Flash Memory
II II
I I
C-11
Flash Memory Data Structure and Operation
The write cycle is successfully completed if none of the following restrictions is violated:
-
The selected clock source is available until the cycle is completed. The predivider is not modified. The access to the flash memory module is restricted as long as BUSY is set.
The conditions to read data from the flash memory with and without access violation are listed in Table C-2.
Table C-2. Conditions to Read Data From Flash Memory
Flash Operation Instruction Fetch (see Note 1) No Yes Flash read mode Page erase cycle (see Note 3) No Yes Mass-erase cycle (see Note 3) No Yes All erase (mass and information memory) No Yes Segment write (see Note 4) N.A. No Yes
Notes:
BUSY
WAIT
Data on Memory Data Bus (MDB) 3FFF 3FFF JMP $ Memory contents from applied address 3FFF 3FFF JMP $ 3FFF 3FFF JMP $ 3FFF 3FFF JMP $ 3FFF 3FFF 3FFF
Action
Byte/word program cycle (see Note 2)
1 1 0 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 1 1
Access violation Nothing PC = PC + 2 Access violation Nothing Access violation Nothing Access violation Nothing Access violation and LOCK (see Note 5) Nothing Access violation and LOCK (see Note 5)
1) Instruction fetch refers to the fetch part of an instruction, and reads one word. The instruction fetch reads the first word of instructions with more than one word. The JMP instruction has one word. The data fetched (3FFFh) is used by the CPU as an instruction. 2) Ensure that the programmed data does not result in unpredictable program execution, such as destruction of executable code sequences. 3) If the PC points to the memory location being erased, no access violation indicates this situation. After erase, no executable code is available and an unpredictable situation occurs. 4) Any software located in a flash memory module can not use the SEGWRT mode to program the same flash memory module. Using the byte or word programming mode allows programming data in the flash memory module holding the software code currently executing. 5) The access violation sets the LOCK bit to 1. Setting the LOCK bit allows completion of the active segment write operation in the normal manner.
C-12
Flash Memory Control Registers
-
The supply voltage should be within the devices' electrical conditions and can only vary slightly, as specified in the applicable data sheet
The control bit BUSY indicates that the write or segment-write cycle is active. It is set by the instruction that writes data to the flash memory module and starts the timing generator. It remains set until the write cycle is completed and the programming voltage is removed. In the write mode the BUSY bit indicates if the flash memory is ready for another write operation. In segment write mode the WAIT bit indicates if the flash memory is ready for another write operation and the BUSY bit indicates the segment write operation is completed. In case of emergency, the emergency exit bit EMEX is set and stops the write cycle immediately. The programming voltage is switched off. One situation where the write cycle should be stopped by software is when the supply voltage drops drastically and the controller's operating conditions may be exceeded. Another case is when the flash memory timing gets out of control, as when the clocksource signal is lost. Note: Whenever the write cycle is stopped before its normal ending by the hardware, the timing generator is stopped and the data written in flash memory may be marginal. Data reading may be inconsistently valid when varying the supply voltage, the temperature, the access time (instruction execution, data read), or the time.
C.3 Flash Memory Control Registers
Defining the correct control bits of three control registers enables write (program), erase, or mass-erase. All three registers should be accessed using word instructions only. The control registers are protected against false write or erase cycles via a key word. Any violation of this keyword sets the KEYV bit and requests a nonmaskable interrupt (NMI). The keyword is different to the keyword used with the Watchdog Timer. All control bits are reset during PUC. PUC is activated after VCC is applied, a reset condition is applied to the RST/NMI pin or watchdog, or a flash operation was not performed normally.
C.3.1 Flash Memory Control Register FCTL1
Any write to control register FCTL1 during erase, mass-erase, or write (programming) will end in an access violation with ACCVIFG=1. In an active segment-write mode, the control register can be written if wait mode is active (WAIT=1). In an active segment write mode and while WAIT=0, writing to control register FCTL1 will also end in an access violation with ACCVIFG=1. Read access is possible at any time without restrictions. Any write to control register FCTL1 during erase, mass-erase, or write (programming) will end in an access violation with ACCVIFG=1. In an active seg-
Flash Memory
C-13
Flash Memory Control Registers
ment write mode, the control register can be written if wait mode is active (WAIT=1). In an active segment write mode and while WAIT=0, writing to control register FCTL1 will also end in an access violation with ACCVIFG=1. Read access is possible at any time without restrictions. The control bits of control register FCTL1 are:
15 FCTL1 0128h FCTL1 read: FCTL1 write: 096h 0A5h 8 7 0 SEG WRT res. res. res. MEras Erase res. WRT rw-0 rw-0 r0 r0 r0 rw-0 rw-0 r0
Erase
0128h, bit1,
Erase a segment 0: No segment erase is started. 1: Erase of one segment is enabled. The segment n to be erased is defined by a dummy write into any address within the segment. The Erase bit is automatically reset when the erase operation is completed. Note: Instruction fetch access during erase is allowed. Any other access to the flash memory during erase results in setting the ACCVIFG bit, and an NMI interrupt is requested. The NMI interrupt routine should handle such violations.
MEras
0128h, bit2,
Mass-erase, Segment0 to Segmentn are erased together. 0: No erase is started 1: Erase of Segment0 to Segmentn is enabled. When a dummy write into any address in Segment0 to Segmentn is executed, masserase is started. The MEras bit is automatically reset when the erase operation is completed. Note: Instruction fetch access during mass-erase is allowed. Any other access to the flash memory during erase results in setting the ACCVIFG bit, and an NMI interrupt is requested. The NMI interrupt routine should handle such violations.
WRT
0128h, bit6,
The bit WRT should be set to get a successful write execution. If bit WRT is reset and write access to the flash memory is performed, an access violation occurs and ACCVIFG is set. Note: Instruction fetch access during erase is allowed. Any other access to the flash memory during erase results in setting the ACCVIFG bit, and an NMI interrupt is requested. The NMI interrupt routine should handle such violations.
SEGWRT
0128h, bit7,
Bit SEGWRT can be used to reduce total programming time. The segment-write bit SEGWRT is useful if larger sequences of data have to be programmed. If programming of one segment is completed, a reset and set sequence should be performed to enable access to the next segment. The WAIT bit should be high before the next write instruction is executed. See also paragraph C.1.1 and Figure C-9. 0: No segment write accelerate is selected. 1: Segment write is used. This bit needs to be reset and set between segment borders.
C-14
Flash Memory Control Registers
C.3.2 Flash Memory Control Register FCTL2
A PUC resets the flash timing generator. The generator is also reset if the emergency exit bit EMEX is set. The timing generator generates the timing necessary to write, erase, and mass-erase from a selected clock source. Two control bits SSEL0 and SSEL1 in control register FCTL2 can select one of three clock sources. The clock source selected should be divided to meet the frequency requirements for fx, as specified in the device's data sheet. Writing to control register FCTL2 should not be attempted if the BUSY bit is set; otherwise an access violation will occur (ACCVIFG=1). Read access to FCTL2 is possible at any time without restrictions.
15 FCTL2 012Ah FCTL2 read: FCTL2 write: 096h 0A5h 8 7
SSEL1 SSEL0 FN5 FN4 FN3 FN2 FN1
0
FN0
rw-0 rw-1 rw-0 rw-0 rw-0 rw-0 rw-1 rw-0
The control bits are: FN0 to FN5 SSEL0 SSEL1 012Ah, bit0, 012Ah, bit5, 012Ah, bit0, These six bits define the division rate of the clock signal. The division rate can be 1 to 64, depending on the digital value of FN5 to FN0 plus one Determine the clock source. 0: ACLK 1: MCLK 2,3 SMCLK
Flash Memory
C-15
Flash Memory Control Registers
C.3.3 Flash Memory Control Register FCTL3
There are no restrictions on modifying this control register. The control bits are reset or set (WAIT) by a PUC, but key violation bit KEYV is reset by POR.
15 FCTL3 012Ch FCTL3 read: FCTL3 write: 8 7
res. res.
0
ACCV EMEX Lock WAIT KEYV BUSY IFG
096h 0A5h
r0
r0
rw-0 rw-1 r-1
rw-0 rw-(0) r(w)-0
BUSY
0128h, bit0,
The bit BUSY shows if an access to the flash memory is possible (BUSY=0), or if an access violation can occur. The BUSY bit is read only, but a write operation is allowed. The BUSY bit should be tested before each write and erase cycle. The flash-timing generator hardware immediately sets the BUSY bit after the start of a write operation, a segment-write operation, a segment erase, or a masserase. Once the timing generator has completed its function, the BUSY bit is reset by hardware. The program and erase timing are shown in Figures C-7, C-8, and C-9. 0: Flash memory is not busy. Read, write, erase and mass-erase are possible without any violation of the internal flash timing. The BUSY bit is reset by POR and by the flash timing generator. 1: Flash memory is busy. Remains in busy state if segment write function is in wait mode. The conditions for access to the flash memory during BUSY=1 are described in paragraph C.2.6.
KEYV,
012Ch, bit1,
Key Violated. 0: Key 0A5h (high byte) was not violated. 1: Key 0A5h (high byte) was violated. Violation occurs when a write access to register FCTL1, FCTL2 or FCTL3 is executed and the high byte is not equal to 0A5h. If the security key is violated, bit KEYV is set and a PUC is performed. The KEYV bit can be used to determine the source that forced a start of the program at the reset vector's address. The KEYV bit is not automatically reset and should reset by software. Note: Any key violation results in a PUC, independent of the state of the KEYV bit. To avoid endless software loops, the flash memory control registers should not be written during a key violation service routine. Note: The software can set the KEYV bit. A PUC is also performed if it is set by software.
C-16
Flash Memory Control Registers
ACCVIFG
bit2,
Access violation interrupt flag The access-violation interrupt flag is set when the flash memory module is improperly accessed while a write or erase operation is active. The violation situations are described in section C.2. When the access-violation interrupt-enable bit is set, the interrupt-service request is accepted and the program continues at the NMI interrupt-vector address. Reading the control registers will not set the ACCVIFG bit. Note: The proper interrupt-enable bit ACCVIE is located in interruptenable register IE1 of the special-function register. Software can set the ACCVIFG bit; in this case, an NMI is also executed.
WAIT
012Ch, bit3,
Wait. In the segment write mode the WAIT bit indicates that the flash memory is ready to receive the (next) data for programming. The WAIT bit is read only, but a write to the WAIT bit is allowed. The WAIT bit is automatically reset if the SEGWRT bit is reset or the LOCK bit is set. Segment-write operation is completed, and then the WAIT bit returns to 1. Condition, SEGWRT=1 (see Figure C-9): After each successful write operation, the BUSY bit is reset to indicate that another byte or word can be written (programmed). The BUSY bit does not indicate the condition when the timing generator has completed the entire programming. The high-voltage portion and voltage generator remain active. The maximum time t(CPT) should not be violated. 0: Segment-write operation has started and programming is in progress. 1: Segment-write operation is active and programming of data is completed. Waiting for the next data to be programmed.
Lock
012Ch, bit4,
The Lock bit can be set during any write, erase of a segment, or mass-erase request. The active sequence is completed normally. In segment-write mode, if the Lock bit is set and SEGWRT and WAIT are set, the SEGWRT and WAIT bits are reset and the mode ends normally. The WAIT bit is 1 after segment-write mode has ended. Software or hardware can control the Lock bit. If an access violation occurs (see conditions described in paragraph C.1.1), the ACCVIFG and the Lock bit are set. 0: Flash memory can be read, programmed, erased, and masserased. 0: Flash memory can be read but not programmed, erased, or mass-erased. A current program, erase, or mass-erase operation is completed normally. The access-violation interrupt flag ACCVIFG is set when the flash memory module is accessed while the Lock bit is set.
Flash Memory
C-17
Flash Memory, Interrupt and Security Key Violation
EMEX
012Ch, bit5,
Emergency exit. The emergency exit should only be used when a flash memory write or erase operation is out-of-control. 0: No function. 0: Stops the active operation immediately and shuts down all internal parts of the flash memory controller. Current consumption immediately drops back to the active mode. All bits in control register FCTL1 are reset. Since the EMEX bit is automatically reset by hardware, the software always reads EMEX as 0.
C.4 Flash Memory, Interrupt and Security Key Violation
One NMI vector is used for three non-maskable interrupt (NMI) events, RST/ NMI, oscillator fault (OFIFG), and flash-access violation (ACCVIFG). The software can determine the source of the interrupt request by testing interrupt flags NMIIFG, OFIFG, and ACCVIFG. They remain set until reset by software.
C-18
Flash Memory, Interrupt and Security Key Violation
Figure C-10. Basic Flash Memory Module Timing During Segment Write Cycle
ACCV ACCVIFG
S FCTL1.1
Flash Module Flash Module Flash Module ACCVIE
IE1.5
Clear KEYV VCC POR PUC System Reset Generator POR
RST/NMI
PO R
S
NMIIFG
IFG1.4
Clear TMSEL NMIES NMI WDTQn EQU
NMIRS
PUC POR
PUC NMIIE WDTIFG IE1.4 Clear IFG1.0 Counter S IFG1.4 OFIE IE1.0 Clear IE1.4 Clear PUC NMI_IRQA PUC IRQA: Interrupt Request Accepted Watchdog Timer Module OFIFG WDT POR IRQA TIMSEL WDTIE S IRQ
OSCFault
Clear
Flash Memory
C-19
Flash Memory, Interrupt and Security Key Violation
C.4.1 Example of an NMI Interrupt Handler
Start of NMI Interrupt Handler Reset by HW: OFIE, NMIE, NMIIFG no ACCVIFG=1 yes Reset ACCVIFG no NMIIFG=1 yes Reset NMIIFG no
OFIFG=1 yes Reset OFIFG
User's Software, Oscillator Fault Handler Optional Set NMIIE, OFIE, ACCVIE Within One Instruction RETI End of NMI Interrupt Handler
User's Software, Flash Access Violation Handler
User's Software, External NMI Handler
Example1: BIS #(NMIIE+OFIE+ACCVIE), &IE1 Example2: BIS Mask,&IE1 ; Mask enables only ; interrupt sources
The NMI handler takes care of all sources requesting a nonmaskable interrupt. The NMI interrupt is a multiple-source interrupt per MSP430 definition. The hardware resets the interrupt-enable flags: the external nonmaskable interrupt enable NMIIE, the oscillator fault interrupt enable OFIE, and the flash memory access-violation interrupt enable. The individual software handlers reset the interrupt flags and reenables the interrupt enable bits according to the application needs. After all software is processed, the interrupt enable bits have to be set if another NMI event is to be accepted. Setting the interrupt enable bits should be the last instruction before the return-from-interrupt instruction RETI. If this rule is violated, the stack can grow out of control while other NMI requests are already pending. Setting the interrupt enable bits can be accomplished by using a bit-set-instruction BIS using immediate data or a mask. The mask data can be modified anywhere via software (for example in RAM); this constitutes the nonmaskable interrupt processing.
C.4.2 Protecting One-Flash Memory-Module Systems From Corruption
MSP430 configurations having one flash memory module use this module for program code and interrupt vectors. When the flash memory module is in a write, erase, or mass-erase operation and the program accesses it, an access violation occurs. This violation will request an interrupt service - but when the interrupt vector is read from the flash memory, 03FFFh will be read independent of the data in the flash memory at the vector's memory location.
C-20
Flash Memory, Interrupt and Security Key Violation
To protect the software from this error situation, all interrupt sources have to be disabled since all interrupt requests will fail. The flash memory returns the vector 03FFFh. Before the interrupt enable bits are modified, they can be stored in RAM to be restored when the flash memory is ready for access again. The following interrupt enable bits should be reset to stop all interrupt service requests:
-
GIE = 0 NMIIE = ACCVIE = OFIE = 0
Additionally the watchdog should be halted to prevent its expiration when flash memory is busy: WDTHOLD = 1
When the flash memory is ready, the interrupt sources can be enabled again. Before they are enabled, critical interrupt flags should be checked and, if necessary, served or reset by software. GIE = 1 or left disabled, or be restored to the previous level NMIIE = ACCVIE = OFIE = 1 or left disabled, or be restored to the previous level WDTHOLD = 0 or left disabled, or be restored to the previous level
Flash Memory
C-21
Flash Memory Access via JTAG and Software
C.5 Flash Memory Access via JTAG and Software
C.5.1 Flash Memory Protection
Flash memory access via the serial test and programming interface JTAG can be inhibited when the security fuse is activated. The security fuse is activated via serial instructions shifted into the JTAG. Activating the fuse is not reversible, and any access to the internal system is disrupted. The bypass function described in the IEEE1149.1 standard is active.
C.5.2 Program Flash Memory Module via Serial Data Link Using JTAG Feature
The hardware interconnection to the JTAG pins is done via four separate pins, plus the ground or VSS reference level. The JTAG pins are TMS, TCK, TDI (/VPP), and TDO (/TDI).
Figure C-11. Signal Connections to MSP430 JTAG Pins
VCC TMS TCK EN1 TDI TDO TDI TDO/TDI VCC SN74AHC244 TCLK EN2 Test/VPP TEST VCC/DVCC AVCC VSS/DVSS AVSS 68 k MSP430Fxxx XOUT/TCLK Level Shifter TMS TCK
C.5.3 Programming a Flash Memory Module via Controller Software
No special external hardware is required to program a flash memory module. The power supply at pin VCC should supply the higher current during write (program) and erase modes. The software algorithm is simple. The embedded timing generator in the flash memory module controls the program and erase cycles. Software can not run in the same flash memory module where data is to be written. Such background software needs to run on other memory device, such as a ROM module, a RAM module, or another flash memory module.
C-22
Flash Memory Access via JTAG and Software
C.5.3.1 Example: Programming One Word Into a Flash Memory Module via Software Execution Outside this Module
This example assumes that the code to program the flash location is not executed from the target flash memory module.
Disable all Interrupt Sources and Watchdog yes Fxkey .set 03300h Fwkey .set 0A500h ; No interrupt request may happen while the flash is programmed Test_Busy1 BIT JNZ MOV MOV MOV Test_Busy2 BIT JNZ MOV XOR #BUSY,&FCTL3 Test_Busy1 #Fwkey,&FCTL3 : Clear lock bit #(Fwkey+WRT),&FCTL1: : Enable write to flash #123h,&0FF1Eh : Write a word to flash #BUSY,&FCTL3 Test_Busy2 #Fwkey,&FCTL1 #(Fxkey+Lock),&FCTL3 ; still busy? ; yes, repeat busy test : Reset write bit : Change lock bit to 1
BUSY = 1 no
Lock = 0, WRT = 1 Write Data to Flash Address yes
BUSY = 1 no Lock = 1
Restore or Enable Required Interrupt Sources and Watchdog
; Enable those interrupt sources that should be accepted
The BUSY bit can be tested before the write to the flash memory module is done, or after a write (program) starts:
-
For flash memory locations that hold data, it is a good practice to test the BUSY bit before the write is executed. This has some time benefits, since the write process is executed via the flash memory timing generator without further CPU intervention. It is important that the clock source remains active until BUSY is reset by the flash memory hardware. The power or clock management, responsible for entering low-power modes, has to make sure that it does not switch off the clock source used by the flash controller.
-
For flash memory blocks that hold program code, it is a good practice to test the BUSY bit after the write is executed. The program can only proceed if the module can be accessed again. No special attention is needed during execution of software code. Every write to the flash memory module has to leave the programming cycle with the BUSY bit reset. Testing the BUSY bit before writing to a flash memory block that holds program code ensures that the active program will not access the flash memory module. Two types of access are visible: execute program code, or read and write data on this flash memory module.
Flash Memory
C-23
Flash Memory Access via JTAG and Software
C.5.3.2 Example: Programming One Word Into the Same Flash Memory Module via Software
The program execution waits after the write-to-flash instruction (MOV #123h,&0FF1Eh) until the busy bit is reset again. If no other write-to-flash instruction method is used the BUSY bit test may not be needed to ensure correct flash-write handling.
Disable all interrupt sources and Watchdog Lock = 0, WRT = 1 Write Data to Flash Address Fxkey Fwkey .set .set 03300h 0A500h
; No interrupt request may happen while the flash is programmed MOV MOV MOV XOR #(Fwkey+WRT),&FCTL1: : Enable Write to flash #123h,&0FF1Eh : Write a word to flash #Fwkey,&FCTL1 #(Fxkey+Lock),&FCTL3 : Reset Write bit : Change Lock bit to 1
WRT = 0, Lock = 1
Restore or Enable Required Interrupt Sources and Watchdog
; Enable those interrupt sources that should be accepted
C-24
Flash Memory Access via JTAG and Software
C.5.3.3 Example, Programming Byte Sequences Into a Flash Memory Module via Software
Sequences of data, bytes, or words can use the segment-write feature. This reduces the programming time by about one half.
Fxkey .set 03300h Fwkey .set 0A500h Frkey .set 09600h ; Ensure that neither Watchdog Timer, nor ; interrupts nor Low-Power Modes may corrupt ; proper execution RAM2FLASH
Set Pointer for Start and End Clear Lock Bit yes
MOV MOV MOV Test_Busy1
#Start_Ptr,Rx #End_Ptr,Ry #Fkey,&FCTL3
; Clear lock bit
Busy ? no SEG WRT = WRT =1
BIT JNZ
#BUSY,&FCTL3 Test_Busy1
; Flash busy? SEGWRT ended?
MOV Test_WAIT1
#(Fwkey+WRT+SEGWRT),&FCTL1 ; Segment write
yes WAIT = 1 no All data Programmed? no Write Byte to Flash no Segment border? yes yes
BIT JNE
#WAIT,&FCTL3 Test_WAIT1
CMP JZ
Rx,Ry End_Seg_Write
; All data programmed?
; Program data: in this example one byte MOV.B @Rx+,(Flash_Start_Ptr-Start_ptr-1) (Rx) BIT JNZ Test_Wait2 #03Fh,Rx Test_Wait1 ; Segment border?
yes
WAIT = 1 no SEG WRT = WRT =0
BIT JZ MOV JMP
#WAIT,&FCTL3 Test_Wait2 #Fwkey,&FCTL1 Test_busy1
; Test if data written
; Stop segment write ; Segment write ends if busy=0
End_Seg_Write
SEG WRT = WRT =0
; All data are programmed MOV Test_Busy2 #Fwkey,&FCTL1 ; Stop segment write
yes
Busy ? no End of Segment Write
BIT JNZ XOR
#BUSY,&FCTL3 Test_Busy2 #(Fxkey+Lock),&FCTL3
; Segment write ended? ; Change Lock bit to '1
Flash Memory
C-25
Flash Memory Access via JTAG and Software
C.5.3.4 Example, Erase Flash Memory Segment or Module via Software Execution Outside This Flash Module
The following sequence can be used to erase a segment, or mass-erase a block of segments.
Erase or `Mass' Erase yes BUSY = 1 Segment Erase: Erase = 1 or Mass Erase: MEras = 1 BIC #( Fwkey+Lock),&FCTL3 ;Reset Lock bit
Test_Busy1 BIT JNZ MOV #BUSY,&FCTL3 Test_Busy1 #(Fwkey+Erase),&FCTL1 ; select segment erase
CLR Dummy Write
&0F000h
yes BUSY = 1
Test_Busy2 BIT #BUSY,&FCTL3 JNZ Test_Busy2
End of Erase or `Mass' Erase
XOR
#(Fxkey+Lock),&FCTL3
C.5.3.5 Example, Erase Flash Memory Segment Module in the Same Flash Memory Module via Software
Disable all interrupt sources and Watchdog Lock = 0,Eras=1 (or MEras=1) Dummy Write to Flash Address in the Target Segment ; Disable all possible interrupt sources and watchdog
MOV #(Fwkey+Eras),&FCTL1 CLR &0FA00h
;Enable Erase of Flash ;Dummy Write to Flash ;Erase Segment 2
; Program execution in information memory if MEras=1 (Eras=0) XOR #(Fwkey+Lock),&FCTL3 Lock = 1 ; The erase bit Eras is automatically reset Restore or Enable Required Interrupt Sources and Watchdog ; Enable those interrupt sources that should be accepted : Change Lock bit to 1
C.5.3.6 Code for Write (Program), Erase, and Mass-Erase
Software that is active during write, erase, or mass-erase may not run in the flash memory module where it is written or erased. Software that controls write, erase, or mass-erase can be located in the flash memory module and copied during execution into RAM. In this case the code should be written position-independent, and should be loaded (for instance, to RAM) before it is used. The algorithm runs in RAM during the programming sequence to avoid conflict when the flash memory is written or erased.
C-26
Flash Memory Access via JTAG and Software
The target flash memory module can not execute the programming code sequence while data is being written to it. In the following example, a subroutine moves the programming-code sequence to another memory such as RAM.
Start-of-Subroutine: Load_Flash_Routine Source Start Address of The Code Sequence >> R7 Destination Start Address of The Code Sequence >> R10
Move One Word: (R7) >> (R10) Increment Source and Destination Pointer in R7 and R10
End-of-Source Code ?
End-of-Subroutine: RET
;-----------------------------------------------------------; Definitions used in Subroutine: ; Move programming code sequence into RAM (load_flash_routine) ;-----------------------------------------------------------Flash_ram .set 0222h ; Start address of flash ; program in the RAM ; program in the RAM Prg_source_start .set 0xxxxh ; Start address of code ; in the flash to be prg'ed Prg_source_end .set 0yyyyh ; End address of code ; in the flash to be prg'ed Prg_dest_start .set Flash_ram load_flash_routine ; The code of the program which moves ; Flash access code (write, erase,..) ; starts at label load_flash_routine push r9 push r10 mov #Prg_source_start,R9 ; load pointer source mov #Prg_dest_start,R10 ; load pointer destination load_flash_prg mov @R9,0(R10) ; move a word incd R10 ; destination pointer + 2 incd R9 ; source pointer + 2 cmp # Prg_source_end,R9 ; compare to end_of_code jne load_ flash_prg pop r9 pop r10 ret
Flash Memory
C-27
C-28


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