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MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
SLAS272A - JULY 2000 - REVISED JULY 2000
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description
The Texas Instruments MSP430 series is an ultralow-power microcontroller family consisting of several devices featuring different sets of modules targeted to various applications. The microcontroller is designed to be battery operated for use in extended-time applications. The MSP430 achieves maximum code efficiency with its 16-bit RISC architecture, 16-bit CPU-integrated registers, and a constant generator. The digitally-controlled oscillator provides wake-up from low-power mode to active mode in less than 6 s. The MSP430x13x and the MSP430x14x series are microcontroller configurations with two built-in 16-bit timers, a fast 12-bit A/D converter, one or two universal serial synchronous/asynchronous communication interfaces (USART), and 48 I/O pins. Typical applications include sensor systems that capture analog signals, convert them to digital values, and process and transmit the data to a host system. The timers make the configurations ideal for industrial control applications such as ripple counters, digital motor control, EE-meters, hand-held meters, etc. The hardware multiplier enhances the performance and offers a broad code and hardware-compatible family solution.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright (c) 2000, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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PRODUCT PREVIEW
Low Supply-Voltage Range, 1.8 V . . . 3.6 V Ultralow-Power Consumption: - Standby mode: 1.3 A - RAM Retention Off Mode: 0.1 A Low Operating Current: - 7 A at 32 kHz, 2.2 V - 250 A at 1 MHz, 2.2 V Five Power-Saving Modes Wake-Up From Standby Mode in 6 s 16-Bit RISC Architecture, 125-ns Instruction Cycle Time 12-Bit A/D Converter With Internal Reference, Sample-And-Hold and Autoscan Feature 16-Bit Timer With Seven Capture/Compare-With-Shadow Registers, Timer_B 16-Bit Timer With Three Capture/Compare Registers, Timer_A
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On-Chip Comparator Serial Onboard Programming, No External Programming Voltage Needed Programmable Code Protection by Security Fuse Family Members Include: - MSP430F133: 8KB Flash Memory, 256B RAM - MSP430F135: 16KB Flash Memory, 512B RAM - MSP430F147: 32KB Flash Memory, 1KB RAM - MSP430F148: 48KB Flash Memory, 2KB RAM - MSP430F149: 60KB Flash Memory, 2KB RAM Available in 64-Pin Quad Flat Pack (QFP)
Advanced Information
MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
SLAS272A - JULY 2000 - REVISED JULY 2000
AVAILABLE OPTIONS PACKAGED DEVICES TA PLASTIC 64-PIN QFP (PM) MSP430F133IPM MSP430F135IPM MSP430F147IPM MSP430F148IPM MSP430F149IPM
-40C to 85C
pin designation, MSP430F133, MSP430F135
PM PACKAGE (TOP VIEW)
PRODUCT PREVIEW
DVCC P6.3/A3 P6.4/A4 P6.5/A5 P6.6/A6 P6.7/A7 VREF+ XIN XOUT/TCLK VeREF+ VREF-/VeREF- P1.0/TACLK P1.1/TA0 P1.2/TA1 P1.3/TA2 P1.4/SMCLK
1 2 3 4 5 6 7 8 9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
P5.6/ACLK P5.5/SMCLK P5.4/MCLK P5.3 P5.2 P5.1 P5.0 P4.7/TBCLK P4.6 P4.5 P4.4 P4.3 P4.2/TB2 P4.1/TB1 P4.0/TB0 P3.7 P3.6 P3.5/URXD0
10 11 12 13 14 15
33 16 1718 19 20 21 22 23 24 25 26 27 28 29 30 31 32
2
P1.5/TA0 P1.6/TA1 P1.7/TA2 P2.0/ACLK P2.1/TAINCLK P2.2/CAOUT/TA0 P2.3/CA0/TA1 P2.4/CA1/TA2 P2.5/Rosc P2.6/ADC12CLK P2.7/TA0 P3.0/STE0 P3.1/SIMO0 P3.2/SOMI0 P3.3/UCLK0 P3.4/UTXD0
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AVCC DVSS AV SS P6.2/A2 P6.1/A1 P6.0/A0 RST/NMI TCK TMS TDI TDO/TDI XT2IN XT2OUT P5.7/TBoutH
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MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
SLAS272A - JULY 2000 - REVISED JULY 2000
pin designation, MSP430F147, MSP430F148, MSP430F149
PM PACKAGE (TOP VIEW)
10 11 12 13 14 15
39 38 37 36 35 34
33 16 1718 19 20 21 22 23 24 25 26 27 28 29 30 31 32
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PRODUCT PREVIEW
DVCC P6.3/A3 P6.4/A4 P6.5/A5 P6.6/A6 P6.7/A7 VREF+ XIN XOUT/TCLK VeREF+ VREF-/VeREF- P1.0/TACLK P1.1/TA0 P1.2/TA1 P1.3/TA2 P1.4/SMCLK
1 2 3 4 5 6 7 8 9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40
P5.6/ACLK P5.5/SMCLK P5.4/MCLK P5.3/UCLK1 P5.2/SOMI1 P5.1/SIMO1 P5.0/STE1 P4.7/TBCLK P4.6/TB6 P4.5/TB5 P4.4/TB4 P4.3/TB3 P4.2/TB2 P4.1/TB1 P4.0/TB0 P3.7/URXD1 P3.6/UTXD1 P3.5/URXD0
P1.5/TA0 P1.6/TA1 P1.7/TA2 P2.0/ACLK P2.1/TAINCLK P2.2/CAOUT/TA0 P2.3/CA0/TA1 P2.4/CA1/TA2 P2.5/Rosc P2.6/ADC12CLK P2.7/TA0 P3.0/STE0 P3.1/SIMO0 P3.2/SOMI0 P3.3/UCLK0 P3.4/UTXD0
AVCC DVSS AVSS P6.2/A2 P6.1/A1 P6.0/A0 RST/NMI TCK TMS TDI TDO/TDI XT2IN XT2OUT P5.7/TBoutH
MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
SLAS272A - JULY 2000 - REVISED JULY 2000
functional block diagrams
MSP430x14x
XIN XOUT/TCLK DVCC DVSS AVCC AVSS RST/NMI P1 P2 P3 P4 P5 P6
Rosc XT2IN XT2OUT
Oscillator System Clock
ACLK SMCLK
60 kB Flash 48 kB Flash 32 kB Flash
2 kB RAM 2 kB RAM 1 kB RAM
12 Bit ADC 8 Channels <10 s Conv.
I/O Port 1/2 16 I/Os, With Interrupt Capability
I/O Port 3/4 16 I/Os
I/O Port 5 8 I/Os
I/O Port 6 8 I/Os
MCLK
Test JTAG CPU Imulatiom Module Incl. 16 Reg.
MAB, 16 Bit
MAB, 4 Bit MCB
MDB, 16 Bit
Bus Conv MDB, 8 Bit
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PRODUCT PREVIEW
TMS TCK TDI TDO/TDI
Multipy MPY, MPYS MAC,MACS 8x8 Bit 8x16 Bit 16x8 Bit 16x16 Bit Watchdog timer ACLK SMCLK 15 / 16 Bit Timer_B7 7 CC-Reg. Shadow Reg. Timer_A3 3 CC-Reg. Power on Reset Comparator A USART0 UART Mode SPI Mode USART1 UART Mode SPI Mode
MSP430x13x
XIN XOUT/TCLK DVCC DVSS AVCC AVSS RST/NMI P1 P2 P3 P4 P5 P6
Rosc XT2IN XT2OUT
Oscillator System Clock
ACLK SMCLK 16 kB Flash 8 kB Flash 512B RAM 256B RAM
12 Bit ADC 8 Channels <10 s Conv.
I/O Port 1/2 16 I/Os, With Interrupt Capability
I/O Port 3/4 16 I/Os
I/O Port 5 8 I/Os
I/O Port 6 8 I/Os
MCLK
Test JTAG CPU Imulatiom Module Incl. 16 Reg.
MAB, 16 Bit
MAB, 4 Bit MCB
MDB, 16 Bit
Bus Conv MDB, 8 Bit
4 TMS TCK TDI TDO/TDI ACLK SMCLK Watchdog timer 15 / 16 Bit Timer_B3 3 CC-Reg. Shadow Reg. Timer_A3 3 CC-Reg. Power on Reset Comparator A USART0 UART Mode SPI Mode
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MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
SLAS272A - JULY 2000 - REVISED JULY 2000
Terminal Functions
TERMINAL NAME AVCC AVSS DVCC DVSS P1.0/TACLK P1.1/TA0 P1.2/TA1 P1.3/TA2 P1.4/SMCLK P1.5/TA0 P1.6/TA1 P1.7/TA2 P2.0/ACLK P2.1/TAINCLK P2.2/CAOUT/TA0 P2.3/CA0/TA1 P2.4/CA1/TA2 P2.5/Rosc P2.6/ADC12CLK P2.7/TA0 P3.0/STE0 P3.1/SIMO0 P3.2/SOMI0 P3.3/UCLK0 P3.4/UTXD0 P3.5/URXD0 P3.6/UTXD1 P3.7/URXD1 P4.0/TB0 P4.1/TB1 P4.2/TB2 P4.3/TB3 P4.4/TB4 P4.5/TB5 P4.6/TB6 P4.7/TBCLK P5.0/STE1 P5.1/SIMO1 P5.2/SOMI1 P5.3/UCLK1 P5.4/MCLK P5.5/SMCLK 14x devices only NO. 64 62 1 63 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O DESCRIPTION Analog supply voltage, positive terminal. Supplies only the analog portion of the analog-to-digital converter. Analog supply voltage, negative terminal. Supplies only the analog portion of the analog-to-digital converter. Digital supply voltage, positive terminal. Supplies all digital parts. Digital supply voltage, negative terminal. Supplies all digital parts. General digital I/O pin/Timer_A, clock signal TACLK input General digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output General digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output General digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output General digital I/O pin/SMCLK signal output General digital I/O pin/Timer_A, compare: Out0 output General digital I/O pin/Timer_A, compare: Out1 output General digital I/O pin/Timer_A, compare: Out2 output/ General digital I/O pin/ACLK output General digital I/O pin/Timer_A, clock signal at INCLK General digital I/O pin/Timer_A, capture: CCI0B input/Comparator_A output General digital I/O pin/Timer_A, compare: Out1 output/Comparator_A input General digital I/O pin/Timer_A, compare: Out2 output/Comparator_A input General-purpose digital I/O pin, input for external resistor defining the DCO nominal frequency General digital I/O pin, conversion clock - 12-bit ADC General digital I/O pin/Timer_A, compare: Out0 output General digital I/O, slave transmit enable - USART0/SPI mode General digital I/O, slave in/master out of USART0/SPI mode General digital I/O, slave out/master in of USART0/SPI mode General digital I/O, external clock input - USART0/UART or SPI mode, clock output - USART0/SPI mode General digital I/O, transmit data out - USART0/UART mode General digital I/O, receive data in - USART0/UART mode General digital I/O, transmit data out - USART1/UART mode General digital I/O, receive data in - USART1/UART mode General-purpose digital I/O, capture I/P or PWM output port - Timer_B7 CCR0 General-purpose digital I/O, capture I/P or PWM output port - Timer_B7 CCR1 General-purpose digital I/O, capture I/P or PWM output port - Timer_B7 CCR2 General-purpose digital I/O, capture I/P or PWM output port - Timer_B7 CCR3 General-purpose digital I/O, capture I/P or PWM output port - Timer_B7 CCR4 General-purpose digital I/O, capture I/P or PWM output port - Timer_B7 CCR5 General-purpose digital I/O, capture I/P or PWM output port - Timer_B7 CCR6 General-purpose digital I/O, input clock TBCLK - Timer_B7 General-purpose digital I/O, slave transmit enable - USART1/SPI mode General-purpose digital I/O slave in/master out of USART1/SPI mode General-purpose digital I/O, slave out/master in of USART1/SPI mode General-purpose digital I/O, external clock input - USART1/UART or SPI mode, clock output - USART1/SPI mode General-purpose digital I/O, main system clock MCLK output General-purpose digital I/O, submain system clock SMCLK output
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PRODUCT PREVIEW
MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
SLAS272A - JULY 2000 - REVISED JULY 2000
Terminal Functions (Continued)
TERMINAL NAME P5.6/ACLK P5.7/TboutH P6.0/A0 P6.1/A1 P6.2/A2 P6.3/A3 P6.4/A4 P6.5/A5 P6.6/A6 P6.7/A7 RST/NMI TCK TDI NO. 50 51 59 60 61 2 3 4 5 6 58 57 55 54 56 10 7 11 8 9 53 52 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I/O I I/P O O I I/O I O DESCRIPTION General-purpose digital I/O, auxiliary clock ACLK output General-purpose digital I/O, switch all PWM digital output ports to high impedance - Timer_B7 TB0 to TB6 General digital I/O, analog input a0 - 12-bit ADC General digital I/O, analog input a1 - 12-bit ADC General digital I/O, analog input a2 - 12-bit ADC General digital I/O, analog input a3 - 12-bit ADC General digital I/O, analog input a4 - 12-bit ADC General digital I/O, analog input a5 - 12-bit ADC General digital I/O, analog input a6 - 12-bit ADC General digital I/O, analog input a7 - 12-bit ADC Reset input, nonmaskable interrupt input port, or bootstrap loader start (in Flash devices). Test clock. TCK is the clock input port for device programming test and bootstrap loader start (in Flash devices). Test data input. TDI is used as a data input port. The device protection fuse is connected to TDI. Test data output port. TDO/TDI data output or programming data input terminal Test mode select. TMS is used as an input port for device programming and test. Input for an external reference voltage to the ADC Output of positive terminal of the reference voltage in the ADC Negative Terminal for the ADC's reference voltage for both sources, the internal reference voltage, or an external applied reference voltage Input port for crystal oscillator XT1. Standard or watch crystals can be connected. Output terminal of crystal oscillator XT1 or test clock input Input port for crystal oscillator XT2. Only standard crystals can be connected. Output terminal of crystal oscillator XT2
PRODUCT PREVIEW
TDO/TDI TMS VeREF+ VREF+ VREF-/VeREF- XIN XOUT/TCLK XT2IN XT2OUT
short-form description
processing unit The processing unit is based on a consistent and orthogonal CPU and instruction set. This design structure results in a RISC-like architecture, highly transparent to the application development and notable for its ease of programming. All operations other than program-flow instructions are consequently performed as register operations in conjunction with seven addressing modes for source and four modes for destination operand. CPU The CPU has sixteen registers that provide reduced instruction execution time. This reduces the register-to-register operation execution time to one cycle of the processor frequency. Four of the registers are reserved for special use as program counter, stack pointer, status register, and constant generator. The remaining registers are available as general-purpose registers. Peripherals are connected to the CPU using a data address and control bus, and can be easily handled with all memory manipulation instructions.
Program Counter Stack Pointer Status Register Constant Generator General-Purpose Register General-Purpose Register PC/R0 SP/R1 SR/CG1/R2 CG2/R3 R4 R5
General-Purpose Register General-Purpose Register
R14 R15
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MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
SLAS272A - JULY 2000 - REVISED JULY 2000
short-form description (continued)
instruction set The instruction set for this register-to-register architecture constitutes a powerful and easy-to-use assembler language. The instruction set consists of 51 instructions with three formats and seven address modes. Table 1 provides a summary and example of the three types of instruction formats; the address modes are listed in Table 2. Table 1. Instruction Word Formats
Dual operands, source-destination Single operands, destination only Relative jump, un/conditional e.g. ADD R4,R5 e.g. CALL e.g. JNE R8 R4 + R5 ---> R5 PC -->(TOS), R8--> PC Jump-on-equal bit = 0
Each instruction operating on word and byte data is identified by the suffix B. Examples: WORD INSTRUCTIONS MOV ADD PUSH SWPB EDE, TONI #235h,&MEM R5 R5 BYTE INSTRUCTIONS MOV.B ADD.B PUSH.B -- EDE,TONI #35h,&MEM R5
Table 2. Address Mode Descriptions
ADDRESS MODE Register SD SYNTAX MOV Rs,Rd MOV X(Rn),Y(Rm) MOV EDE,TONI MOV &MEM,&TCDAT MOV at Rn,Y(Rm) MOV at Rn+,Rm MOV #X,TONI MOV at R10,Tab(R6) MOV at R10+,R11 MOV #45,TONI EXAMPLE MOV R10,R11 MOV 2(R5),6(R6) OPERATION R10 --> R11 M(2+R5)--> M(6+R6) M(EDE) --> M(TONI) M(MEM) --> M(TCDAT) M(R10) --> M(Tab+R6) M(R10) --> R11 R10 + 2--> R10 #45 --> M(TONI)
n Indexed n Symbolic (PC relative) n Absolute n Indirect n
Indirect autoincrement Immediate NOTE: S = source
n n n n
n n
D = destination
Computed branches (BR) and subroutine call (CALL) instructions use the same address modes as other instructions. These address modes provide indirect addressing, which is ideally suited for computed branches and calls. The full use of this programming capability results in a program structure which is different from structures used with conventional 8- and 16-bit controllers. For example, numerous routines can be easily designed to deal with pointers and stacks instead of using flag-type programs for flow control. operating modes and interrupts The MSP430 operating modes provide advanced support of the requirements for ultralow-power and ultralowenergy consumption. This goal is achieved by intelligent management during the different operating modes of modules and CPU states and is fully supported during interrupt event handling. An interrupt event awakes the system from each of the various operating modes and returns, using the RETI instruction, to the mode that was selected before the interrupt event occurred. The different requirements on CPU and modules--driven by system cost and current consumption objectives--require the use of different clock signals:
D D D
Auxiliary clock ACLK, sourced by LFXT1CLK (crystal frequency) and used by the peripheral modules Main system clock MCLK, used by the CPU and system Subsystem clock SMCLK, used by the peripheral modules
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MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
SLAS272A - JULY 2000 - REVISED JULY 2000
operating modes and interrupts (continued)
DIVA 2 LFXT1CLK OscOff XIN XTS LFXT1 Oscillator /1, /2, /4, /8 ACLKGEN ACLK Auxiliary Clock
High Frequency XT1 Oscillator, XTS = 1 XOUT
SELM 2 0.1 XT2CLK 2 3
DIVM 2
CPUOff
Low Power LF Oscillator, XTS = 0
/1, /2, /4, /8, Off MCLKGEN
MCLK Main System Clock
XT2Off XT2IN
PRODUCT PREVIEW
XT2OUT VCC
XT2 Oscillator VCC Rsel SCG0 DCO 3 0 1 DC Generator DCGEN DCOR MOD 5 DCOCLK 0 1 SMCLKGEN SELS DIVS 2 /1, /2, /4, /8, Off SMCLK SUB-System Clock SCG1
P2.5/Rosc
Digital Controlled Oscillator DCO + Modulator MOD DCOMOD
The DCO generator is connected to pin P2.5/Rosc if DCOR control bit is set. The port pin P2.5/Rosc is selected if DCOR control bit is reset (initial state). P2.5
Any of these clock sources--LFXT1CLK, XT2CLK, or DCOCLK--can be used to drive the MSP430 system. LFXT1CLK is defined by connecting a low-power, low-frequency crystal to the oscillator, by connecting a high-frequency crystal to the oscillator, or by applying an external clock source. The high-frequency crystal oscillator is used if control bit XTS is set. The crystal oscillator may be switched off if LFXT1CLK is not required for the current operating mode. XT2CLK is defined by connecting a high-frequency crystal to the oscillator or by applying an external clock source. Crystal oscillator XT2 may be switched off using the XT2Off control bit if not required by the current operating mode. When DCOCLK is active, its frequency is selected or adjusted by software. DCOCLK is inactive or stopped when it is not being used by the CPU or peripheral modules. The dc generator can be stopped when SCG0 is reset and DCOCLK is not required. The dc generator determines the basic DCO frequency, and can be set by one external resistor or adjusted in eight steps by selection of integrated resistors.
NOTE:
The system clock generator always starts with DCOCLK selected as MCLK (CPU clock) to ensure proper start of program execution. The software determines the final system clock through control bit manipulation. The system clock MCLK is also selected by hardware to be the DCOCLK (DCO and DCGEN are on) if the crystal oscillator (XT1 or XT2) fails while being selected as MCLK. Without this forced clock mode the NMI, requested by the oscillator fault flag, can not be handled and control may be lost. Without forced-clock mode the processor could not execute any code until the failed oscillator restarts.
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SLAS272A - JULY 2000 - REVISED JULY 2000
low-power consumption capabilities The various operating modes are handled by software by controlling the operation of the internal clock system. This clock system provides a large combination of hardware and software capabilities to run the application while maintaining the lowest power consumption and optimizing system costs. This is accomplished by:
D D D D
Use of the internal clock (DCO) generator without any external components Selection of an external crystal or ceramic resonator for lowest frequency and cost Selection and activation of the proper clock signals (LFXT1CLK, XT2Off, and/or DCOCLK) and clock predivider function. Control bit XT2Off is embedded in control register BCSCTL1. Application of an external clock source
The control bits that most influence the operation of the clock system and support fast turnon from low power operating modes are located in the status register SR. Four bits control the CPU and the system clock generator: SCG1, SCG0, OscOff, and CPUOff.
15 Reserved For Future Enhancements 9 8 V 7 SCG1 SCG0 OscOff CPUOff GIE N Z 0 C
rw-0
CPUOff, SCG1, SCG0, and OscOff are the most important bits in low-power control when the basic function of the system clock generator is established. They are pushed to the stack whenever an interrupt is accepted and saved for returning to the operation before an interrupt request. They can be manipulated via indirect access to the data on the stack during execution of an interrupt handler so that program execution can be resume in another power operating mode after return-from-interrupt. CPUOff: SCG1: OscOff: Clock signal MCLK, used with the CPU, is active when the CPUOff bit is reset or stopped when set. Clock signal SMCLK, used with peripherals, is enabled when the SCG1 bit is reset or stopped when set. Crystal oscillator LFXT1 is active when the OscOff bit is reset. The LFXT1 oscillator can be inactive only when the OscOff bit is set and not used for MCLK. The setup time to start a crystal oscillation requires special consideration when the off option is used. Mask-programmable devices can disable this feature and the oscillator can never be switched off by software. The dc generator is active when the SCG0 bit is reset. The DCO can be inactive only if the SCG0 bit is set and the DCOCLK signal is not used as MCLK or SMCLK. The dc current consumed by the dc generator defines the basic frequency of the DCOCLK. When the current is switched off (SCG0=1) the start of the DCOCLK is slightly delayed. This delay is in the microsecond range. Clock signal DCOCLK is stopped if not used as MCLK or SMCLK. There are two situations when the SCG0 bit can not switch the DCOCLK signal off: The DCOCLK frequency is used as MCLK (CPUOff=0 and SELM.1=0), or the DCOCLK frequency is used as SMCLK (SCG1=0 and SELS=0). If DCOCLK is required for operation, the SCG0 bit can not switch the dc generator off.
SCG0:
DCOCLK:
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PRODUCT PREVIEW
MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
SLAS272A - JULY 2000 - REVISED JULY 2000
interrupt vector addresses The interrupt vectors and the power-up starting address are located in the address range 0FFFFh - 0FFE0h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
INTERRUPT SOURCE Power-up External Reset Watchdog Flash memory NMI Oscillator Fault Flash memory access violation Timer_B7 (see Note 5) Timer_B7 (see Note 5) Comparator_A Watchdog timer USART0 receive USART0 transmit INTERRUPT FLAG WDTIFG KEYV (see Note 1) NMIIFG (see Notes 1 & 4) OFIFG (see Notes 1 & 4) ACCVIFG (see Notes 1 & 4) BCCIFG0 (see Note 2) BCCIFG1 to BCCIFG6 TBIFG (see Notes 1 & 2) CMPAIFG WDTIFG URXIFG.0 UTXIFG.0 ADCIFG (see Notes 1 & 2) CCIFG0 (see Note 2) CCIFG1, CCIFG2, TAIFG (see Notes 1 & 2) P1IFG.0 (see Notes 1 & 2) To P1IFG.7 (see Notes 1 & 2) URXIFG.1 UTXIFG.1 P2IFG.0 (see Notes 1 & 2) To P2IFG.7 (see Notes 1 & 2) Maskable SYSTEM INTERRUPT Reset WORD ADDRESS 0FFFEh PRIORITY 15, highest
(Non)maskable (Non)maskable (Non)maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable
0FFFCh 0FFFAh 0FFF8h 0FFF6h 0FFF4h 0FFF2h 0FFF0h 0FFEEh 0FFECh 0FFEAh
14 13 12 11 10 9 8 7 6 5
PRODUCT PREVIEW
ADC Timer_A3 Timer_A3
I/O port P1 (eight flags) USART1 receive USART1 transmit I/O port P2 (eight flags)
Maskable Maskable
0FFE8h 0FFE6h 0FFE4h 0FFE2h 0FFE0h
4 3 2 1 0, lowest
NOTES: 1. 2. 3. 4.
Multiple source flags Interrupt flags are located in the module. Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable can not disable it. 5. Timer_B7 in MSP430x14x family has 7 CCRs; Timer_B3 in MSP430x13x family has 3 CCRs; in Timer_B3 there are only interrupt flags CCIFG0, 1, and 2, and the interrupt-enable bits CCIE0, 1, and 2 integrated.
special function registers
Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits not allocated to a functional purpose are not physically present in the device. This arrangement provides simple software access.
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SLAS272A - JULY 2000 - REVISED JULY 2000
interrupt enable 1 and 2
Address 0h 7 UTXIE0 rw-0 6 URXIE0 rw-0 5 ACCVIE rw-0 4 NMIE rw-0 3 2 1 OFIE rw-0 0 WDTIE rw-0
WDTIE: OFIE: NMIIE: ACCVIE: URXIE0: UTXIE0:
Address 01h 7
Watchdog-timer-interrupt enable signal Oscillator-fault-interrupt enable signal Nonmaskable-interrupt enable signal (Non)maskable-interrupt enable signal, access violation if FLASH memory/module is busy USART0, UART, and SPI receive-interrupt enable signal USART0, UART, and SPI transmit-interrupt enable signal
6 5 UTXIE1 rw-0 4 URXIE1 rw-0 3 2 1 0
UTXIE1:
USART1, UART, and SPI transmit-interrupt enable signal
interrupt flag register 1 and 2
Address 02h 7 UTXIFG0 rw-1 6 URXIFG0 rw-0 5 4 NMIIFG rw-0 3 2 1 OFIFG rw-1 0 WDTIFG rw-0
WDTIFG: OFIFG: NMIIFG: URXIFG0: UTXIFG0:
Address 03h 7
Set on overflow or security key violation or reset on VCC power-on or reset condition at RST/NMI Flag set on oscillator fault Set via RST/NMI pin USART0, UART, and SPI receive flag USART0, UART, and SPI transmit flag
6 5 UTXIFG1 rw-1 4 URXIFG1 rw-0 3 2 1 0
URXIFG1: UTXIFG1:
USART1, UART, and SPI receive flag USART1, UART, and SPI transmit flag
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URXIE1:
USART1, UART, and SPI receive-interrupt enable signal
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module enable registers 1 and 2
Address 04h 7 UTXE0 rw-0 6 URXE0 USPIIE0 rw-0 5 4 3 2 1 0
URXE0: UTXE0: USPIIE0:
Address 05h 7
USART0, UART receive enable USART0, UART transmit enable USART0, SPI (synchronous peripheral interface) transmit and receive enable
6 5 UTXE1 rw-0 4 URXE1 USPIIE1 rw-0 3 2 1 0
URXE1: UTXE1: USPIIE1:
USART1, UART receive enable USART1, UART transmit enable USART1, SPI (synchronous peripheral interface) transmit and receive enable
Bit Can Be Read and Written Bit Can Be Read and Written. It is Reset by PUC. SFR Bit Not Present in Device
PRODUCT PREVIEW
Legend: rw: rw-0:
memory organization
MSP430F133 Memory Main: interrupt vector Main: code memory Information memory Boot memory RAM Peripherals Size Flash Flash Size Flash Size ROM Size 16-bit 8-bit 8-bit SFR 8kB 0FFFFh - 0FFE0h 0FFFFh - 0E000h 256 Byte 010FFh - 01000h 1kB 0FFFh - 0C00h 256 Byte 02FFh - 0200h 01FFh - 0100h 0FFh - 010h 0Fh - 00h MSP430F135 16kB 0FFFFh - 0FFE0h 0FFFFh - 0C000h 256 Byte 010FFh - 01000h 1kB 0FFFh - 0C00h 512 Byte 03FFh - 0200h 01FFh - 0100h 0FFh - 010h 0Fh - 00h MSP430F147 32kB 0FFFFh - 0FFE0h 0FFFFh - 08000h 256 Byte 010FFh - 01000h 1kB 0FFFh - 0C00h 1kB 05FFh - 0200h 01FFh - 0100h 0FFh - 010h 0Fh - 00h MSP430F148 48kB 0FFFFh - 0FFE0h 0FFFFh - 04000h 256 Byte 010FFh - 01000h 1kB 0FFFh - 0C00h 2kB 09FFh - 0200h 01FFh - 0100h 0FFh - 010h 0Fh - 00h MSP430F149 60kB 0FFFFh - 0FFE0h 0FFFFh - 01100h 256 Byte 010FFh - 01000h 1kB 0FFFh - 0C00h 2kB 09FFh - 0200h 01FFh - 0100h 0FFh - 010h 0Fh - 00h
boot ROM containing bootstrap loader
The intention of the bootstrap loader is to download data into the flash memory module. Various write, read, and erase operations are needed for a proper download environment. The bootstrap loader is only available on F devices. functions of the bootstrap loader: Definition of read: write: Apply and transmit data of peripheral registers or memory to pin P1.1 (BSLTX) Read data from pin P2.2 (BSLRX) and write them into flash memory
unprotected functions
Mass erase, erase of the main memory (segment 0 to segment n) and information memory (segment A and segment B) Access to the MSP430 via the bootstrap loader is protected. It must be enabled before any protected function can be performed. The 256 bits in 0FFE0h to 0FFFFh provide the access key.
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boot ROM containing bootstrap loader (continued)
protected functions
All protected functions can be executed only if the access is enabled.
D D D D D
Write/program byte into flash memory; Parameters passed are start address and number of bytes (the segment-write feature of the flash memory is not supported and not useful with the UART protocol). Segment erase of segment 0 to segment n in main memory, and segment erase of segments A and B in the information memory. Read all data in main memory and information memory. Read and write to all byte peripheral modules and RAM. Modify PC and start program execution immediately.
NOTE: Unauthorized readout of code and data is prevented by the user's definition of the data in the interrupt memory locations.
features of the bootstrap loader are:
hardware resources used for serial input/output:
D D D D D D D
Pins P1.1 and P2.2 for serial data transmission Test and RST/NMI to start program execution at the reset or bootstrap loader vector Basic clock module: Rsel=5, DCO=4, MOD=0, DCOCLK for MCLK and SMCLK, clock divider for MCLK and SMCLK at default: dividing by 1 Timer_A: Timer_A operates in continuous mode with MCLK source selected, input divider set to 1, using CCR0, and polling of CCIFG0. WDT: Watchdog timer is halted Interrupt: GIE=0, NMIIE=0, OFIFG=0, ACCVIFG=0 Memory allocation and stack pointer: If the stack pointer points to RAM addresses above 0220h, 6 bytes of the stack are allocated, plus RAM addresses 0200h to 0219h. Otherwise the stack pointer is set to 0220h and allocates RAM from 0200h to 021Fh.
NOTE:
When writing RAM data via the bootstrap loader, make sure that the stack is outside the range of the data to be written.
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D D D D D
UART communication protocol, fixed to 9600 baud Port pin P1.1 for transmit, P2.2 for receive TI standard serial protocol definition Implemented in flash memory version only Program execution starts with the user vector at 0FFFEh or with the bootstrap loader (start vector is at address 0C00h)
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boot ROM containing bootstrap loader (continued)
Program execution begins with the user's reset vector at FFFEh (standard method) if TCK is held high while RST/NMI goes from low to high:
RST/NMI TCK User Program Starts
Program execution begins with the bootstrap vector at 0C00h (boot ROM) if a minimum of two negative edges have been applied to TCK while RST/NMI is low, and TCK is low when RST/NMI goes from low to high.
RST/NMI TCK Bootloader Starts
PRODUCT PREVIEW
TMS
The bootstrap loader will not start (via the vector in address 0C00h) if:
D D D D
There are less than two negative edges at TCK while RST/NMI is low TCK is high when RST/NMI goes from low to high JTAG has control over the MSP430 resources The supply voltage VCC drops and a POR is executed
NOTES: 6. The default level of TCK is high. An active low has to be applied to enter the bootstrap loader. Other MSP430s which have a pin function used with a low default level can use an inverted signal. 7. The TMS signal must be high while TCK clocks are applied. This ensures that the JTAG controller function remains in its default mode.
WARNING: The bootstrap loader starts correctly only if the RST/NMI pin is in reset mode. Unpredictable program execution may result if it is switched to the NMI function. However, a bootstrap load may be started using software and the bootstrap vector, for example using the instruction BR &0C00h.
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flash memory
D D D D D D D D
Flash memory has n segments of main memory and two segments of information memory (A and B) of 128 bytes each. Each segment in main memory is 512 bytes in size. Segments 0 to n may be erased in one step, or each segment may be individually erased. Segments A and B can be erased individually, or as a group with segments 0-n. Segments A and B are also called information memory. A security fuse burning is irreversible; no further access to JTAG is possible afterwards Internal generation of the programming/erase voltage: no external VPP has to be applied, but VCC increases the supply current requirements. Program and erase timing is controlled by hardware in the flash memory - no software intervention is needed. The control hardware is called the flash-timing generator. The input frequency of the flash-timing generator should be in the proper range and should be maintained until the write/program or erase operation is completed.
D
Unprogrammed, new devices may have some bytes programmed in the information memory (needed for test during manufacturing). The user should perform an erase of the information memory prior to first use.
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PRODUCT PREVIEW
During program or erase, no code can be executed from flash memory and all interrupts must be disabled by setting the GIE, NMIIE, ACCVIE, and OFIE bits to zero. If a user program requires execution concurrent with a flash program or erase operation, the program must be executed from memory other than the flash memory (e.g., boot ROM, RAM). In the event a flash program or erase operation is initiated while the program counter is pointing to the flash memory, the CPU will execute JMP $ instructions until the flash program or erase operation is completed. Normal execution of the previously running software then resumes.
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flash memory (continued)
8 kB 0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh 16 kB 0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh 32 kB 0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh 48 kB 0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh 60 kB 0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh Segment 0 w/ Interrupt Vectors Segment 1
Segment 2
Main Memory
0E400h 0E3FFh
0C400h 0C3FFh 0C200h 0C1FFh 0C000h 010FFh 01080h 0107Fh 01000h
08400h 083FFh 08200h 081FFh 08000h 010FFh 01080h 0107Fh 01000h
04400h 043FFh 04200h 041FFh 04000h 010FFh 01080h 0107Fh 01000h
01400h 013FFh Segment n-1 01200h 011FFh Segment n 01100h 010FFh Segment A 01080h 0107Fh Segment B 01000h Information Memory
PRODUCT PREVIEW
0E200h 0E1FFh 0E000h 010FFh 01080h 0107Fh 01000h
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flash memory, control register FCTL1
All control bits are reset during PUC. PUC is active after application of VCC, application of a reset condition to the RST/NMI pin, expiration of the Watchdog Timer, occurrence of a watchdog access violation, or execution of an improper flash operation. A more detailed description of the control-bit functions is found in the flash-memory module description (in the MSP430x1xx user's guide, literature number SLAU049). Any write to control register FCTL1 during erase, mass erase, or write (programming) will end in an access violation with ACCVIFG=1. In an active segment-write mode the control register can be written if the wait mode is active (WAIT=1). Special conditions apply during segment-write mode. See the MSP430x1xx user's guide for details. Read access is possible at any time without restrictions. The bits of control register FCTL1 are:
15 FCTL1 0128h FCTL1 Read: FCTL1 Write: 096h 0A5h 8 7 SEG WRT WRT rw-0 res. res. r0 res. r0 0 MEras Erase res. rw-0 rw-0 r0
rw-0 r0
MEras
0128h, bit2
Mass erase, Segment0 to Segmentn are erased together. 0: No erase will be started 1: Erase of Segment0 to Segmentn is enabled. A dummy write to any address in Segment0 to Segmentn starts mass erase. The MEras bit is automatically reset when the erase operation is completed. See Note 7 below. Bit WRT should be set for a successful write operation. An access violation occurs and ACCVIFG is set if bit WRT is reset and write access to the flash memory is performed. See Note 7 below. Bit SEGWRT may be used to reduce total programming time. Segment-write bit SEGWRT is useful when larger sequences of data have to be programmed. After completion of programming of one segment, a reset and set sequence has to be performed to enable access to the next segment. The WAIT bit must be high before executing the next write instruction. 0: No segment write accelerate is selected. 1: Segment write is used. This bit needs to be reset and set between segment borders.
WRT
0128h, bit6
SEGWRT
0128h, bit7
NOTE 8: Only instruction-fetch access is allowed during program, erase, or mass-erase cycles. Any other access to the flash memory during these cycles will result in setting the ACCVIFG bit. An NMI interrupt should handle such violations.
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Erase
0128, bit1
Erase a segment 0: No segment erase will be started. 1: Erase of one segment is enabled. The segment to be erased is defined by a dummy write into any address within the segment. The erase bit is automatically reset when the erase operation is completed. See Note 7 below.
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flash memory, control register FCTL1 (continued)
Table 3. Valid Combinations of Control Bits for Flash Memory Access (see Note 9)
FUNCTION PERFORMED Write word or byte Write word or byte in same segment, segment write mode Erase one segment by writing to any address in the target segment Erase all segments (0 to n) but not the information memory (segments A and B) Erase all segments (0 to n, and A and B) by writing to any address in the flash memory module SEGWRT 0 1 0 0 0 WRT 1 1 0 0 0 MERAS 0 0 0 1 1 ERASE 0 0 1 0 1 BUSY 0 0 0 0 0 WAIT 0 1 0 0 0 LOCK 0 0 0 0 0
NOTE 9: The table shows all possible combinations of control bits SEGWRT, WRT, MEras, Erase, and BUSY. All other combinations will result in an access violation.
flash memory, the timing generator, control register FCTL2
The timing generator (Figure 1) produces all the timing signals necessary for write, erase, and mass erase from the selected clock source. One of three different clock sources may be selected by control bits SSEL0 and SSEL1 in control register FCTL2. The selected clock source should be divided to meet the frequency requirements specified in the recommended operating conditions. The flash-timing generator is reset with PUC. It is also reset if the emergency exit bit EMEX is set. Control register FCTL2 may not be written to if the BUSY bit is set; otherwise, an access violation will occur (ACCVIFG=1). Read access is possible at any time without restrictions.
15 FCTL2 012Ah FCTL2 Read: FCTL2 Write: 096h 0A5h
SSEL1 SSEL0 FN5 FN4 FN3 FN2 FN1 FN0
PRODUCT PREVIEW
8
7
0
rw-0
rw-1
rw-0
rw-0
rw-0
rw-0
rw-1
rw-0
The control bits are: FN0 to FN5 SSEL0 SSEL1 012Ah, bit0 These six bits determine the division rate of the clock signal. The division rate is 1 012Ah, bit5 to 64, depending on the value of FN5 to FN0 plus one. 012Ah, bit0 Determine the clock source 0: ACLK 1: MCLK 2: SMCLK 3: SMCLK
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flash memory control register FCTL3
There are no restrictions on modifying this control register. The control bits are reset or set (WAIT) by a PUC, but key violation bit KEYV is reset with a POR.
15 FCTL3 012Ch FCTL3 Read: FCTL3 Write: 096h 0A5h
res. res. EMEX Lock WAIT
8
7
0
ACCV KEYV BUSY IFG
r0
r0
rw-0
rw-1
r-1
rw-0
rw-(0) r(w)-0
BUSY
012Ch, bit0
The BUSY bit shows if an access to the flash memory is correct (BUSY=0), or if an access violation has taken place. The BUSY bit should be tested before each write and erase cycle. 0: Flash memory is not busy. 1: Flash memory is busy. It remains in busy state if segment-write function is in wait mode. Key violated 0: Key 0A5h (high byte) was not violated. 1: Key 0A5h (high byte) was violated. Violation occurs when a write access to register FCTL1, FCTL2, or FCTL3 is executed and the high byte is not equal to 0A5h. If the security key is violated, bit KEYV is set and a PUC is performed. Access-violation interrupt flag The access-violation interrupt flag is set only when a write or erase operation is active. Access violation can only happen if the flash-memory module is written or read while it is busy. An instruction can be fetched during write, erase, and mass erase, but not during segment write. When the access-violation interrupt-enable bit is set, the interrupt-service request is accepted and the program continues at the NMI interrupt-vector address. Reading the control registers will not set the ACCVIFG bit. In the segment-write mode, the WAIT bit indicates that the flash memory is prepared to receive the (next) data for programming. The WAIT bit is read only, but a write to WAIT bit is allowed. 0: Segment-write operation is started and programming is in progress 1: Segment write operation is active and programming of data has been completed The lock bit may be set during any write, erase of a segment, or mass erase request. The active sequence is completed normally. In segment-write mode, the SEGWRT and WAIT bits are reset and the mode ends in the regular manner. The software or hardware controls the lock bit. If an access violation occurs during segment-write mode, the ACCVIFG and LOCK bits may be set. 0: Flash memory may be read, programmed, erased, and mass erased. 1: Flash memory may be read but not programmed, erased, and mass-erased. A current program, erase, or mass-erase operation will complete normally. The access-violation interrupt flag ACCVIFG is set when the flash-memory module is accessed while the lock bit is set. Emergency exit. The emergency exit should only be used if a flash memory write or erase operation is out of control. 0: No function 1: Stops the active operation immediately and shuts down all internal parts in the flash memory controller. Current consumption immediately drops back to the active mode level. All bits in control register FCTL1 are reset. Since the EMEX bit is automatically reset by hardware, the software always reads EMEX as 0.
KEYV,
012Ch, bit1
ACCVIFG,
012Ch, bit2
WAIT,
012Ch, bit3
Lock
012Ch, bit4
EMEX,
012Ch, bit5
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flash memory, interrupt and security key violation
ACCV ACCVIFG S FCTL1.1 Flash Module Flash Module Flash Module
ACCVIE IE1.5 PUC PUC RST/NMI System Reset Generator TMSEL POR Clear KEYV VCC POR PUC
NMIES
NMI
PRODUCT PREVIEW
NMIIFG S IFG1.4 PUC WDTQn Counter PUC OSCFault OFIFG S IFG1.1 POR IRQA TIMSEL OFIE IE1.1 PUC NMI_IRQA IRQA: Interrupt Request Accepted Watchdog Timer Module PUC Clear IE1.0 S Clear WDTIE IFG1.0 Clear WDTIFG S IRQ Clear NMIRS EQU PUC POR
NMIIE IE1.1 Clear
Figure 1. Block Diagram of NMI Interrupt Sources One NMI vector is used for three NMI events: RST/NMI (NMIIFG), oscillator fault (OFIFG), and flash memory access violation (ACCVIFG). The software can determine the source of the interrupt request, since all flags remain set until reset by software. The enable flag(s) should be set only within one instruction directly before the return-from-interrupt (RETI) instruction. This ensures that the stack remains under control. A pending NMI interrupt request will not increase stack demand unnecessarily.
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peripherals
Peripherals are connected to the CPU through data, address, and control busses, and can be easily handled using all memory-manipulation instructions.
oscillator and system clock
Three clocks are used in the system--the main system (master) clock (MCLK) used by the CPU and the system, the subsystem (master) clock (SMCLK) used by the peripheral modules, and the auxiliary clock (ACLK) originated by LFXT1CLK (crystal frequency) and used by the peripheral modules. Following a POR the DCOCLK is used by default, the DCOR bit is reset, and the DCO is set to the nominal initial frequency. Additionally, if either LFXT1CLK or XT2CLK fails as the source for MCLK, DCOCLK is automatically selected to ensure fail-safe operation. SMCLK can be generated from XT2CLK or DCOCLK. ACLK is always generated from LFXT1CLK. Crystal oscillator LFXT1 can be defined to operate with watch crystals (32,768 Hz) or with higher-frequency ceramic resonators or crystals. The crystal or ceramic resonator is connected across two terminals. No external components are required for watch-crystal operation. If the high-frequency XT1 mode is selected, external capacitors from XIN to VSS and XOUT to VSS are required, as specified by the crystal manufacturer. The LFXT1 oscillator starts after application of VCC. If the OscOff bit is set to 1, the oscillator stops when it is not used for MCLK. Crystal oscillator XT2 is identical to oscillator LFXT1, but only operates with higher-frequency ceramic resonators or crystals. The crystal or ceramic resonator is connected across two terminals. External capacitors from XT2IN to VSS and XT2OUT to VSS are required as specified by the crystal manufacturer. The XT2 oscillator is off after application of VCC, since the XT2 oscillator control bit XT2Off is set. If bit XT2Off is set to 1, the XT2 oscillator stops when it is not used for MCLK. Clock signals ACLK , MCLK, and SMCLK may be used externally via port pins. Different application requirements and system conditions dictate different system-clock requirements, including:
D D D D
High frequency for quick reaction to system hardware requests or events Low frequency to minimize current consumption, EMI, etc. Stable peripheral clock for timer applications, such as real-time clock (RTC) Start-stop operation that can be enabled with minimum delay
multiplication
The multiplication operation is supported by a dedicated peripheral module. The module performs 16x16, 16x8, 8x16, and 8x8 bit operations. The module is capable of supporting signed and unsigned multiplication as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are required.
digital I/O
There are six 8-bit I/O ports implemented--ports P1 through P6. Ports P1 and P2 use seven control registers, while ports P3, P4, P5, and P6 use only four of the control registers to provide maximum digital input/output flexibility to the application:
D D D D
All individual I/O bits are independently programmable. Any combination of input, output, and interrupt conditions is possible. Interrupt processing of external events is fully implemented for all eight bits of ports P1 and P2. Read/write access to all registers using all instructions is possible.
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MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
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digital I/O (continued)
The seven control registers are:
D D D D D D D
Input register Output register Direction register Interrupt edge select Interrupt flags Interrupt enable Selection (port or module)
8 bits at ports P1 through P6 8 bits at ports P1 through P6 8 bits at ports P1 through P6 8 bits at ports P1 and P2 8 bits at ports P1 and P2 8 bits at ports P1 and P2 8 bits at ports P1 through P6
Each one of these registers contains eight bits. Two interrupt vectors are implemented: one commonly used for any interrupt event on ports P1.0 to P1.7, and another commonly used for any interrupt event on ports P2.0 to P2.7. Ports P3, P4, P5, and P6 have no interrupt capability.
Watchdog Timer
PRODUCT PREVIEW
The primary function of the Watchdog Timer (WDT) module is to perform a controlled system restart after a software upset has occurred. A system reset is generated if the selected time interval expires. If an application does not require this watchdog function, the module can work as an interval timer, which generates an interrupt after a selected time interval. The Watchdog Timer counter (WDTCNT) is a 15/16-bit up-counter not directly accessible by software. The WDTCNT is controlled using the Watchdog Timer control register (WDTCTL), which is an 8-bit read/write register. Writing to WDTCTL in either operating mode (watchdog or timer) is only possible when using the correct password (05Ah) in the high-byte. If any value other than 05Ah is written to the high-byte of the WDTCTL, a system reset PUC is generated. The password is read as 069h to minimize accidental write operations to the WDTCTL register. The low-byte stores data written to the WDTCTL. In addition to the Watchdog Timer control bits, there are two bits included in the WDTCTL that configure the NMI pin.
USART0 and USART1
There are two USART peripherals implemented in the MSP430x14x: USART0 and USART1; but only one in the MSP430x13x configuration: USART0. Both have an identical function as described in the applicable chapters of the MSP430x1xx User's Guide. They use different pins to communicate, and different registers for module control. Registers with identical functions have different addresses. The universal synchronous/asynchronous interface is a dedicated peripheral module used in serial communications. The USART supports synchronous SPI (3- or 4-pin), and asynchronous UART communication protocols, using double-buffered transmit and receive channels. Data streams of 7 or 8 bits in length can be transferred at a rate determined by the program, or by an external clock. Low-power applications are optimized by UART mode options which allow for the reception of only the first byte of a complete frame. The application software should then decide if the succeeding data is to be processed. This option reduces power consumption. Two dedicated interrupt vectors are assigned to each USART module--one for the receive and one for the transmit channels.
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timer_A (three capture/compare registers)
The timer module offers one sixteen-bit counter and three capture/compare registers. The timer clock source can be selected from an external source TACLK (SSEL=0 or 3), or from two internal sources--ACLK (SSEL=1) or SMCLK (SSEL=2). The clock source can be divided by one, two, four, or eight. The timer can be fully controlled (in word mode)--it can be halted, read, and written; it can be stopped, run continuously, or made to count up or up/down using one compare block to determine the period. The three capture/compare blocks are configured by the application to run in capture or compare mode. The capture mode is mostly used to individually measure internal or external events from any combination of positive, negative, or positive and negative edges. It can also be stopped by software. Three different external events can be selected: TA0, TA1, and TA2. In the capture/compare register CCR2, ACLK is the capture signal if CCI2B is selected. Software capture is chosen if CCISx=2 or CCISx=3. The compare mode is mostly used to generate timing for the software or application hardware, or to generate pulse-width modulated output signals for various purposes like D/A conversion functions or motor control. An individual output module is assigned to each of the three capture/compare registers. This module can run independently of the compare function or can be triggered in several ways.
SSEL1 SSEL0 P1.0/TACLK TACLK ACLK P2.1/TAINCLK SMCLK INCLK 0 1 2 3 32kHz to 8MHz Timer Clock 15 Input Divider Clk 16-bit Timer RC Carry/Zero POR/CLR Timer Bus Capture Data 0 Mode Control 16-bit Timer
Equ0 Set_TAIFG
ID1 ID0 CCIS01CCIS00 P1.1/TA0 P2.2/CAOUT/TA0 CCI0A CCI0B GND VCC 0 1 2 3
MC1 MC0
Capture Mode
15 0 Capture/Compare Capture/Compare Register CCR0
OM02 OM01OM00 P1.1/TA0 Out0 Output Unit0 P1.5/TA0 P2.7/TA0 EQU0
Comparator 0 CCI0 CCM01CCM00 Capture/Compare Reg. CCR1 15 Capture Mode Comparator 1 CCI1 CCM11 CCM10 EQU1 Capture Capture/Compare Register CCR1 0 OM12 OM11 OM10
CCIS11 CCIS10 P1.2/TA1 CAOUT from Comparator_A CCI1A CCI1B GND VCC 0 1 2 3
P1.2/TA1 Out1 Output Unit1 P1.6/TA1 P2.3/CA0/TA1 ADC12I1 (i/p at ADC12)
CCIS21CCIS20 P1.3/TA2 ACLK CCI2A CCI2B GND VCC 0 1 2 3 Capture
15 Capture Mode Comparator 2 Capture/Compare Capture/Compare Register CCR2
0
OM22 OM21OM20 Out2 Output Unit2 EQU2 P1.3/TA2 P1.7/TA2 P2.4/CA1/TA2
CCI2 CCM21CCM20
Figure 2. Timer_A, MSP430x13x/14x Configuration Two interrupt vectors are used by the module. One vector is assigned to capture/compare block CCR0, and one common-interrupt vector is implemented for the timer and the other two capture/compare blocks. The three interrupt events using the same vector are identified by an individual interrupt vector word. The interrupt vector word is used to add an offset to the program counter so that the interrupt handler software continues at the corresponding program location. This simplifies the interrupt handler and assigns each interrupt event the same five-cycle overhead.
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PRODUCT PREVIEW
MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
SLAS272A - JULY 2000 - REVISED JULY 2000
timer_B (7 capture/compare registers in 'x14x and 3 capture/compare rregisters in 'x13x)
Timer_B7 is identical to Timer_A3, except for the following:
D D D D D
The timer counter can be configured to operate in 8-, 10-, 12-, or 16-bit mode. The function of the capture/compare registers is slightly different when in compare mode. In Timer_B, the compare data is written to the capture/compare register, but is then transferred to the associated compare latch for the comparison. All output level Outx can be set to Hi-Z from the TboutH external signal. The SCCI bit is not implemented in Timer_B Timer_B7 has seven capture compare registers
The timer module has one sixteen-bit counter and seven capture/compare registers. The timer clock source can be selected from an external source TBCLK (SSEL=0 or 3), or from two internal sources: ACLK (SSEL=1) and SMCLK (SSEL=2)). The clock source can be divided by one, two, four, or eight. The timer can be fully controlled (in word mode): it can be halted, read, and written; it can be stopped, run continuously, or made to count up or up/down using one compare block to determine the period. The seven capture/compare blocks are configured by the application to run in capture or in compare mode.
PRODUCT PREVIEW
The capture mode is mostly used to measure external or internal events from any combination of positive, negative, or positive and negative edges. It can also be stopped by software. Any of seven different external events TB0 to TB6 can be selected. In the capture/compare register CCR6, ACLK is the capture signal if CCI6B is selected. Software capture is chosen if CCISx=2 or CCISx=3. The compare mode is mostly used to generate timing for the software or application hardware, or to generate pulse-width modulated output signals for various purposes such as D/A conversion functions or motor control. An individual output module is assigned to each of the seven capture/compare registers. This module can run independently of the compare function, or can be triggered in several ways. The comparison is made from the data in the compare latches (TBCLx) and not from the compare register. Two interrupt vectors are used by the module. One vector is assigned to capture/compare block CCR0, and one common interrupt vector is implemented for the timer and the other six capture/compare blocks. The seven interrupt events using the same vector are identified by an individual interrupt vector word. The interrupt vector word is used to add an offset to the program counter so that the interrupt handler software continues at the corresponding program location. This simplifies the interrupt handler and assigns each interrupt event the same five-cycle overhead.
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compare latches (TBCLx) The compare latches can be loaded directly by software or via selected conditions triggered by the PWM function. They are reset by the POR signal.
Load TBCLx immediate, CLLD=0: Load TBCLx at Zero, CLLD=1: Load TBCLx at Zero + Period, CLLD=2: Capture/compare register CCRx and the corresponding compare latch are loaded simultaneously. The data in capture/compare register CCRx is loaded to the corresponding compare latch when the 16-bit timer TBR counts to zero. The data in capture/compare register CCRx is loaded to the corresponding compare latch when the 16-bit timer TBR counts to zero or when the next period starts (in UP/DOWN mode). The data in capture/compare register CCRx is loaded when CCRx is equal to TBR.
Load TBCLx at EQUx, CLLD=3:
Loading the compare latches can be done individually or in groups. Individually means that whenever the selected load condition (see above) is true, the CCRx data is loaded into TBCLx.
Load TBCLx individually, TBCLGRP=0: Dual load TBCLx mode, TBCLGRP=1: Compare latch TBCLx is loaded when the selected load condition (CLLD) is true. Two compare latches TBCLx are loaded when data are written to both CCRx registers of the same group and the load condition (CLLD) is true. Three groups are defined: CCR1+CCR2, CCR3+CCR4, and CCR5+CCR6.
Triple load TBCLx mode, Three compare latches TBCLx are loaded when data are written to all CCRx registers of the TBCLGRP=2: same group and then the selected load condition (CLLD) is true. Two groups are defined: CCR1+CCR2+CCR3 and CR4+CCR5+CCR6. Full load TBCLx mode, TBCLGRP=3: All seven compare latches TBCLx are loaded when data are written to all seven CCRx registers and then the selected load condition (CLLD) is true. All CCRx data, CCR0+CCR1+CCR2+CCR3+CCR4+CCR5+CCR6, are simultaneously loaded to the corresponding SHRx compare latches.
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PRODUCT PREVIEW
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compare latches (TBCLx) (continued)
Data SSEL1 P4.7/ TBCLK P4.7/ TBINCLK TBCLK ACLK SMCLK INCLK SSEL0 0 1 2 3 Input Clk Divider Timer Clock 15 16-bit Timer RC Carry/Zero POR/CLR Timer Bus 15 Capture Capture Mode CCI0 CCM01 CCM00 15 Compare Latch TBCL0 Out0 Output Unit0 Comparator 0 EQU0 EQU0 P4.0/TB0 ADC12I2 ip at ADC12 Capture/Compare Register CCR0 0 OM02 OM01 OM00 MDB 0 0 Mode Control Equ0 Set_TAIFG 16-bit Timer
ID1 ID0
MC1 MC0
CCIS01 CCIS00 P4.0/TB0 P4.0/TB0 CCI0A CCI0B GND VCC 0 1 2 3
PRODUCT PREVIEW
CCIS11 CCIS10 P4.1/TB1 P4.1/TB1 CCI1A CCI1B GND VCC 0 1 2 3 Capture Mode CCI1 CCM11 CCM10 Capture
MDB 15 Capture/Compare Register CCR1 15 Compare Latch TBCL1 Out1 Output Unit1 Comparator 1 EQU1 EQU0 P4.1/TB1 ADC12I3 i/p at ADC12 P4.2/TB2 P4.3/TB3 P4.4/TB4 P4.5/TB5 0 OM12 OM11 OM10 0
P4.2/TB2 P4.3/TB3 P4.4/TB4 P4.5/TB5 CCIS61 CCIS60 P4.6/TB6 ACLK CCI6A CCI6B GND VCC 0 1 2 3 Capture Capture Mode CCI6 CCM61 CCM60 15 Compare Latch TBCL6 MDB 15 Capture/Compare Register CCR6
Capture/Compare Reg. CCR2 Capture/Compare Reg. CCR3 Capture/Compare Reg. CCR4 Capture/Compare Reg. CCR5 0
0
OM62 OM61 OM60 Out6 Output Unit6
P4.6/TB6
Comparator 6 EQU6 EQU0
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comparator_A
The primary functions of the comparator module are support of precision slope conversion in A/D applications, battery voltage supervision, and external analog signal monitoring. The comparator is connected to port pins P2.3 (+ terminal) and to P2.4 (-terminal). It is controlled via eight control bits in the CACTL register.
0 V VCC P2CA0 0 P2.3/ CA0/ TA1 1 1 0 P2.4/ CA1/ TA2 1 1 0V 0 V VCC P2CA1 0 1 CAON 0V 2.0 s P2.2/ CAOUT/TA0 Set CAIFG Flag CA1 + _ 0 0 1 CAEX 0 1 CAON CAF
CA0
0
Low Pass Filter 0 1
CCI1B
CAOUT
3
2
1
0 CAREF
CARSEL 1 0 VCAREF
0 2 1 3
0.5 x VCC
0.25 x VCC
0V
0V
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PRODUCT PREVIEW
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comparator_A
The control bits are: CAOUT, CAF, P2CA0, P2CA1, CACTL2.4 to CATCTL2.7 CAIFG, CAIE, CAIES, 05Ah, bit0 05Ah, bit1 05Ah, bit2 05Ah, bit3 05Ah, bit4 05Ah, bit7 059h, bit0 059h, bit1 059h, bit2 Comparator_A interrupt flag Comparator_A interrupt enable Comparator_A interrupt edge select bit 0: The rising edge sets the Comparator_A interrupt flag CAIFG 1: The falling edge set the Comparator_A interrupt flag CAIFG The comparator is switched on. Comparator_A reference 0: Internal reference is switched off, an external reference can be applied. 1: 0.25 x VCC reference selected. 2: 0.50 x VCC reference selected. 3: A diode reference selected. An internal reference VCAREF, selected by CAREF bits, can be applied to signal path CA0 or CA1. The signal VCAREF is only driven by a voltage source if the value of CAREF control bits is 1, 2, or 3. The comparator inputs are exchanged, used to measure and compensate the offset of the comparator. Comparator output The comparator output is transparent or fed through a small filter 0: Pin P2.3/CA0/TA1 is not connected to Comparator_A. 1: Pin P2.3/CA0/TA1 is connected to Comparator_A. 0: Pin P2.4/CA1/TA2 is not connected to Comparator_A. 1: Pin P2.4/CA1/TA2 is connected to Comparator_A. Bits are implemented but do not control any hardware in this device.
PRODUCT PREVIEW
CAON, CAREF,
059h, bit3 059h, bit4,5
CARSEL,
059h, bit6
CAEX,
059h, bit7
Eight additional bits are implemented into the Comparator_A module. They enable the software to switch off the input buffer of Port P2. A CMOS input buffer can dissipate supply current when the input is not near VSS or VCC. Control bits CAPI0 to CAIP7 are initially reset and the port input buffer is active. The port input buffer is inactive if the corresponding control bit is set.
A/D converter
The 12-bit analog-to-digital converter (ADC) uses a 10-bit weighted capacitor array plus a 2-bit resistor string. The CMOS threshold detector in the successive-approximation conversion technique determines each bit by examining the charge on a series of binary-weighted capacitors. The features of the ADC are:
D D D D D D
12-bit converter with 1 LSB differential (DNL) and 1 LSB integral nonlinearity (INL) Built-in sample-and-hold Eight external and four internal analog channels. The external ADC input terminals are shared with digital port I/O pins. Internal reference voltage VREF+ of 1.5 V or 2.5 V, software-selectable by control bit 2_5V Internal-temperature diode for temperature measurement Battery-voltage measurement: N = 0.5 x (AVCC - AVSS) x 4096/1.5V; VREF+ is selected for 1.5 V.
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A/D converter (continued)
D D D D D D D
VeREF+
2_5V
REFON
INCH= 0Ah
VREF+ VREF- / Ve REF-
ADC12CTLx.0..3
VREF+
1.5V or 2.5V AVSS AVCC Ref_X AVSS ADC12SSEL ADC12DIV on on AVCC Reference
Internal
Oscillator ADC12OSC ACLK MCLK SMCLK P2.6/ADC12CLK
P6.0/A0 P6.1/A1 P6.2/A2 P6.3/A3 P6.4/A4 P6.5/A5 P6.6/A6 P6.7/A7 a8 a9 a10 a11 SAMPCON 12 : 1
S/H
ADC12CTLx.4..6
ADC12ON
Analog Multi- plexer Sample
VR- &
Hold
VR+
ADC12CLK
Divide by 1,2,3,4,5,6,7,8
12-bit A/D converter core SHP
SHT0 SHT1
Sampling ISSH SYNC MSC ENC 080h 081h 082h 083h 084h 085h 086h 087h 088h 089h 08Ah 08Bh 08Ch 08Dh 08Eh 08Fh
ADC12SC Timer_A3.Out1 Timer_Bx.Out0 Timer_Bx.Out1
Timer
SHI
12-bit S A R
Conversion CTL
AVCC Ref_X 0140h 0142h 0144h 0146h 0148h 014Ah ADC12MEM0 ADC12MEM1 ADC12MEM2 ADC12MEM3 ADC12MEM4 ADC12MEM5 ADC12MEM6 ADC12MEM7 ADC12MEM8 ADC12MEM9 ADC12MEM10 ADC12MEM11 ADC12MEM12 ADC12MEM13 ADC12MEM14 ADC12MEM15 16 x 12-bit ADC Memory (leading bits 15 to 12 are 0) ADC12CTL0 ADC12CTL1 ADC12CTL2 ADC12CTL3 ADC12CTL4 ADC12CTL5 ADC12CTL6 ADC12CTL7 ADC12CTL8 ADC12CTL9 ADC12CTL10 ADC12CTL11 ADC12CTL12 ADC12CTL13 ADC12CTL14 ADC12CTL15 16 x 8-bit ADC Memory Control SHS
T
AVSS
014Ch 014Eh 0150h 0152h 0154h 0156h 0158h 015Ah 015Ch 015Eh
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PRODUCT PREVIEW
Source of positive reference voltage level VR+ can be selected as internal (1.5 V or 2.5 V), external, or AVCC. The source is selected individually for each channel. Source of negative reference voltage level VR- can be selected as external or AVSS. The source is selected individually for each channel. Conversion time can be selected from various clock sources: ACLK, MCLK, SMCLK, or the internal ADC12CLK oscillator. The clock source is divided by an integer from 1 to 8, as selected by software. Channel conversion: individual channels, a group of channels, or repeated conversion of a group of channels. If conversion of a group of channels is selected, the sequence, the channels, and the number of channels in the group can be defined by software. For example, a1-a2-a5-a2-a2-.... The conversion is enabled by the ENC bit, and can be triggered by software via sample and conversion control bit ADC12SC, Timer_A3, or Timer_Bx. Most of the control bits can be modified only if ENC control bit is low. This prevents unpredictable results caused by unintended modification. Sampling time can be 4 x n0 x ADC12CLK or 4 x n1 x ADC12CLK. It can be selected to sample as long as the sample signal is high (ISSH=0) or low (ISSH=1). SHT0 defines n0 and SHT1 defines n1. The conversion result is stored in one of sixteen registers. The sixteen registers have individual addresses and can be accessed via software. Each of the sixteen registers is linked to an 8-bit register that defines the positive and negative reference source and the channel assigned.
MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
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A/D converter (continued)
Table 4. Reference Voltage Configurations
SREF 0 1 2, 3 4 5 6, 7 VOLTAGE AT VR+ AVCC VREF+ (internal) VeREF+ (external) AVCC VREF+ (internal) VeREF+ (external) VOLTAGE AT VR- AVSS AVSS AVSS VREF-/VeREF- (internal or external) VREF-/VeREF- (internal or external) VREF-/VeREF- (internal or external)
control registers ADC12CTL0 and ADC12CTL1
All control bits are reset during POR. POR is active after VCC or a reset condition is applied to pin RST/NMI. A more detailed description of the control bit functions is found in the ADC12 module description (in the user's guide). Most of the control bits in registers ADC12CTL0, ADC12CTL1, and ADC12MCTLx can only be modified if ENC is low.
PRODUCT PREVIEW
The following illustration highlights these bits. Six bits are excluded and can be unrestrictedly modified: ADC12SC, ENC, ADC12TOVIE, ADC12OVIE, and CONSEQ. The control bits of control registers ADC12CTL0 and ADC12CTL1 are:
15 ADC12CTL0
SHT1 SHT0 MSC 2_5 V
8
7
REF ON ADC12 ADC12 ADC12 ON OVIE TOVIE
0
ADC12 ENC SC
01A0h
rw-(0) rw-(0)
rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)
ADC12SC 01A0h, bit0
Sample and convert. The ADC12SC bit is used to control the conversion by software. It is recommended that ISSH=0. SHP=1: Changing the ADC12SC bit from 0 to 1 starts the sample and conversion operation. Bit ADC12SC is automatically reset when the conversion is complete (BUSY=0). SHP=0: A high level of bit ADC12SC determines the sample time. Conversion starts once it is reset (by software). The conversion takes 13 ADC12CLK cycles. Enable conversion. A conversion can be started by software (via ADC12SC) or by external signals, only if the enable conversion bit ENC is high. Most of the control bits in ADC12CTL0 and ADC12CTL1, and all the bits in ADCMCTL.x can only be changed if ENC is low. 0 :No conversion can be started. This is the initial state. 1: The first sample and conversion starts with the first rising edge of the sampling signal. The operation selected proceeds as long as ENC is set.
ENC 01A0h, bit1
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control registers ADC12CTL0 and ADC12CTL1
ADC12TOVIE 01A0h, bit2 Conversion time overflow interrupt enable. The timing overflow takes place and a timing overflow vector is generated if another start of sample and conversion is requested while the current conversion or sequence of conversions is still active. The timing overflow enable, if set, may request an interrupt. Overflow interrupt enables the individual enable for the overflow-interrupt vector. The overflow takes place if the next conversion result is written into ADC memory ADC12MEMx but the previous result was not read. If an overflow vector is generated, the overflow-interrupt enable flag ADC12OVIE and the general-interrupt enable GIE are set and an interrupt service is requested. Switch on the 12-bit ADC core. Make sure that the settling timing constraints are met if ADC core is powered up. 0: Power consumption of the core is off. No conversion is started. 1: ADC core is supplied with power. If no A/D conversion is required, ADC12ON can be reset to conserve power.
ADC12OVIE 01A0h, bit3
ADC12ON 01A0h, bit4
2_5V 01A0h, bit6 MSC 01A0h, bit7
Reference voltage level 0: The internal-reference voltage is 1.5 V if REFON = 1. 1: The internal-reference voltage is 2.5 V if REFON = 1. Multiple sample and conversion. Works only when the sample timer is selected to generate the sample signal and to repeat single channel, sequence of channel, or when repeat sequence of channel (CONSEQ0) is selected. 0 :Only one sample is taken. 1 :If SHP is set and CONSEQ = {1, 2, or 3}, then the rising edge of the sample timer's input signal starts the repeat and/or the sequence of channel mode. Then the second and all further conversions are immediately started after the current conversion is completed. Sample-and-hold Time0 Sample-and-hold Time1 The sample time is a multiple of the ADC12CLK x 4: tsample = 4 x ADC12CLK x n SHT0/1 n 0 1 1 2 2 4 3 8 4 16 5 24 6 32 7 48 8 64 9 96 10 128 11 192 12-15 256
SHT0 01A0h, bit8-11 SHT1 01A0h, bit12-15
The sampling time defined by SHT0 is used when ADC12MEM0 through ADC12MEM7 are used during conversion. The sampling time defined by SHT1 is used when ADC12MEM8 through ADC12MEM15 are used during conversion.
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PRODUCT PREVIEW
REFON 01A0h, bit5
Reference voltage on 0: The internal reference voltage is switched off. No power is consumed by the reference voltage generator. 1: The internal reference voltage is switched on and consumes additional power. The settling time of the reference voltage should be over before the first sample and conversion is started.
MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
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control registers ADC12CTL0 and ADC12CTL1 (continued)
15 ADC12CTL1 01A2h
CSStartAdd SHS SHP
8
ISSH
7
ADC12DIV ADC12SSEL CONSEQ
0
ADC12 BUSY
rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) r -(0)
ADC12BUSY 01A2h, bit0 CONSEQ 01A2h, bit1/2
The BUSY signal indicates an active sample and conversion operation. 0: No conversion is active. The enable conversion bit ENC can be reset normally. 1: A sample period. Conversion or conversion sequence is active. Select the conversion mode. Repeat mode is on if CONSEQ.1 (bit 1) is set. 0: One single channel is converted 1: One single sequence of channels is converted 2: Repeating conversion of one single channel 3: Repeating conversion of a sequence of channels Selects the clock source for the converter core 0: Internal oscillator embedded in the ADC12 module 1: ACLK 2: MCLK 3: SMCLK Selects the division rate for the clock source selected by ADC12SSEL. The clock-operation signal ADC12CLK is used in the converter core. The conversion, without sampling time, requires 13 ADC12CLK clocks. 0 to 7: Divide selected clock source by integer from 1 to 8 Invert source for the sample signal 0: The source for the sample signal is not inverted. 1: The source for the sample signal is inverted. Sample-and-hold pulse, programmable length of sample pulse 0: The sample operation lasts as long as the sample-and-hold signal is 1. The conversion operation starts if the sample-and-hold signal goes from 1 to 0. 1: The sample time (sample signal is high) is defined by nx4x(1/fADC12CLK). SHTx holds the data for n. The conversion starts when the sample signal goes from 1 to 0. Source for sample-and-hold 0: Control bit ADC12SC triggers sample-and-hold followed by the A/D conversion. 1: The trigger signal for sample-and-hold and conversion comes from Timer_A3.EQU1. 2: The trigger signal for sample-and-hold and conversion comes from Timer_B.EQU0. 3: The trigger signal for sample-and-hold and conversion comes from Timer_B.EQU1. Conversion start address CstartAdd is used to define which ADC12 control memory is used to start a (first) conversion. The value of CstartAdd ranges from 0 to 0Fh, corresponding to ADC12MEM0 to ADC12MEM15 and the associated control registers ADC12MCTL0 to ADC12MCTL15.
ADC12SSEL 01A2h, bit3/4
PRODUCT PREVIEW
ADC12DIV 01A2h, bit5,6,7
ISSH 01A2h, bit8 SHP 01A2h, bit9
SHS 01A2h, bit10/11
CStartAdd 01A2h, bit12 to bit15
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control register ADC12MCTLx and conversion memory ADC12MEMx
All control bits are reset during POR. POR is active after application of VCC, or after a reset condition is applied to pin RST/NMI. Control registers ADC12MCTL.x can be modified only if enable conversion control bit ENC is reset. Any instruction that writes to an ADC12MCTLx register while the ENC bit is reset has no effect. A more detailed description of the control bit functions is found in the ADC12 module description (in the MSP430x1xx User's Guide). There are sixteen ADC12MCTLx 8-bit memory control registers and sixteen ADC12MEMx 16-bit registers. Each of the memory control registers is associated with one ADC12MEMx register; for example, ADC12MEM0 is associated with ADC12MCTL0, ADC12MEM1, is associated with ADC12MCTL1, etc.
7 ADC12MCTLx
EOS Sref, Source of Reference INCH, Input Channel a0 to a11
0
080h....08Fh rw-(0) rw-(0) rw-(0)
The following illustration shows the conversion-result registers ADC12MEM0 to ADC12MEM15:
ADC12MEM 0140h...015Eh r0 15 0 r0 0 r0 0 r0 12 0 11 MSB 0 LSB
rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0)
ADC12MEM0 to ADC12MEM15
0140h, bit0, 015Eh, bit15
The 12 bits of the conversion result are stored in 16 control registers ADC12MEM0 to ADC12MEM15. The 12 bits are right-justified and the upper four bits are always read as 0.
ADC12 interrupt flags ADC12IFG.x and enable registers ADC12IEN.x
There are 16 ADC12IFG.x interrupt flags, 16 ADC12IE.x interrupt-enable bits, and one interrupt-vector word. The 16 interrupt flags and enable bits are associated with the 16 ADC12MEMx registers. For example, register ADC12MEM0, interrupt flag ADC12IFG.0, and interrupt-enable bit ADC12IE.0 form one conversion-result block. ADC12IFG.0 has the highest priority and ADC12IFG.15 has the lowest priority. All interrupt flags and interrupt-enable bits are reset during POR. POR is active after application of VCC or after a reset condition is applied to the RST/NMI pin.
ADC12 interrupt vector register
The 12-bit ADC has one interrupt vector for the overflow flag, the timing overflow flag, and sixteen interrupt flags. This vector indicates that a conversion result is stored into registers ADC12MEMx. Handling of the 18 flags is assisted by the interrupt-vector word. The 16-bit vector word ADC12IV indicates the highest pending interrupt. The interrupt-vector word is used to add an offset to the program counter so that the interrupt-handler software continues at the corresponding program location according to the interrupt event. This simplifies the interrupthandler operation and assigns each interrupt event the same five-cycle overhead.
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PRODUCT PREVIEW
The control register bits are used to select the analog channel, the reference voltage sources for VR+ and VR-, and a control signal which marks the last channel in a group of channels. The sixteen 16-bit registers ADC12MEMx are used to hold the conversion results.
MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
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peripheral file map
PERIPHERALS WITH WORD ACCESS Watchdog Timer_B7 Timer_B3 (see Note 9) Watchdog Timer control Timer_B interrupt vector Timer_B control Capture/compare control 0 Capture/compare control 1 Capture/compare control 2 Capture/compare control 3 Capture/compare control 4 Capture/compare control 5 Capture/compare control 6 Timer_B register Capture/compare register 0 Capture/compare register 1 Capture/compare register 2 Capture/compare register 3 Capture/compare register 4 Capture/compare register 5 Capture/compare register 6 Timer_A3 Timer_A interrupt vector Timer_A control Capture/compare control 0 Capture/compare control 1 Capture/compare control 2 Reserved Reserved Reserved Reserved Timer_A register Capture/compare register 0 Capture/compare register 1 Capture/compare register 2 Reserved Reserved Reserved Reserved Multiply In MSP430x14x only Sum extend Result high word Result low word Second operand Multiply signed +accumulate/operand1 Multiply+accumulate/operand1 Multiply signed/operand1 Multiply unsigned/operand1 SumExt ResHi ResLo OP_2 MACS MAC MPYS MPY TAR CCR0 CCR1 CCR2 WDTCTL TBIV TBCTL CCTL0 CCTL1 CCTL2 CCTL3 CCTL4 CCTL5 CCTL6 TBR CCR0 CCR1 CCR2 CCR3 CCR4 CCR5 CCR6 TAIV TACTL CCTL0 CCTL1 CCTL2 0120h 011Eh 0180h 0182h 0184h 0186h 0188h 018Ah 018Ch 018Eh 0190h 0192h 0194h 0196h 0198h 019Ah 019Ch 019Eh 012Eh 0160h 0162h 0164h 0166h 0168h 016Ah 016Ch 016Eh 0170h 0172h 0174h 0176h 0178h 017Ah 017Ch 017Eh 013Eh 013Ch 013Ah 0138h 0136h 0134h 0132h 0130h
PRODUCT PREVIEW
NOTE 10: Timer_B7 in MSP430x14x family has 7 CCR, Timer_B3 in MSP430x13x family has 3 CCR.
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SLAS272A - JULY 2000 - REVISED JULY 2000
peripheral file map (continued)
PERIPHERALS WITH WORD ACCESS (CONTINUED) Flash Flash control 3 Flash control 2 Flash control 1 ADC12 See also Peripherals with Byte Access Conversion memory 15 Conversion memory 14 Conversion memory 13 Conversion memory 12 Conversion memory 11 Conversion memory 10 Conversion memory 9 Conversion memory 8 Conversion memory 7 Conversion memory 6 Conversion memory 5 Conversion memory 4 Conversion memory 3 Conversion memory 2 Conversion memory 1 Conversion memory 0 Interrupt-vector-word register Inerrupt-enable register Inerrupt-flag register Control register 1 Control register 0 ADC12 ADC memory-control register15 ADC memory-control register14 ADC memory-control register13 ADC memory-control register12 ADC memory-control register11 ADC memory-control register10 ADC memory-control register9 ADC memory-control register8 ADC memory-control register7 ADC memory-control register6 ADC memory-control register5 ADC memory-control register4 ADC memory-control register3 ADC memory-control register2 ADC memory-control register1 ADC memory-control register0 FCTL3 FCTL2 FCTL1 ADC12MEM15 ADC12MEM14 ADC12MEM13 ADC12MEM12 ADC12MEM11 ADC12MEM10 ADC12MEM9 ADC12MEM8 ADC12MEM7 ADC12MEM6 ADC12MEM5 ADC12MEM4 ADC12MEM3 ADC12MEM2 ADC12MEM1 ADC12MEM0 ADC12IV ADC12IE ADC12IFG ADC12CTL1 ADC12CTL0 ADC12MCTL15 ADC12MCTL14 ADC12MCTL13 ADC12MCTL12 ADC12MCTL11 ADC12MCTL10 ADC12MCTL9 ADC12MCTL8 ADC12MCTL7 ADC12MCTL6 ADC12MCTL5 ADC12MCTL4 ADC12MCTL3 ADC12MCTL2 ADC12MCTL1 ADC12MCTL0 012Ch 012Ah 0128h 015Eh 015Ch 015Ah 0158h 0156h 0154h 0152h 0150h 014Eh 014Ch 014Ah 0146h 0144h 0142h 0140h 01A8h 01A6h 01A4h 01A2h 01A0h 08Fh 08Eh 08Dh 08Ch 08Bh 08Ah 089h 088h 087h 086h 085h 084h 083h 082h 081h 080h 0148h
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MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
SLAS272A - JULY 2000 - REVISED JULY 2000
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS UART1 (Only in `x14x) Transmit buffer Receive buffer Baud rate Baud rate Modulation control Receive control Transmit control UART control UART0 Transmit buffer Receive buffer Baud rate Baud rate Modulation control Receive control Transmit control UART control UTXBUF.1 URXBUF.1 UBR1.1 UBR0.1 UMCTL.1 URCTL.1 UTCTL.1 UCTL.1 UTXBUF.0 URXBUF.0 UBR1.0 UBR0.0 UMCTL.0 URCTL.0 UTCTL.0 UCTL.0 CAPD CACTL2 CACTL1 BCSCTL2 BCSCTL1 DCOCTL P6SEL P6DIR P6OUT P6IN P5SEL P5DIR P5OUT P5IN P4SEL P4DIR P4OUT P4IN P3SEL P3DIR P3OUT P3IN P2SEL P2IE P2IES P2IFG P2DIR P2OUT P2IN 07Fh 07Eh 07Dh 07Ch 07Bh 07Ah 079h 078h 077h 076h 075h 074h 073h 072h 071h 070h 05Bh 05Ah 059h 058h 057h 056h 037h 036h 035h 034h 033h 032h 031h 030h 01Fh 01Eh 01Dh 01Ch 01Bh 01Ah 019h 018h 02Eh 02Dh 02Ch 02Bh 02Ah 029h 028h
PRODUCT PREVIEW
Comparator_A
Comp._A port disable Comp._A control2 Comp._A control1
System Clock
Basic clock system control2 Basic clock system control1 DCO clock frequency control
Port P6
Port P6 selection Port P6 direction Port P6 output Port P6 input
Port P5
Port P5 selection Port P5 direction Port P5 output Port P5 input
Port P4
Port P4 selection Port P4 direction Port P4 output Port P4 input
Port P3
Port P3 selection Port P3 direction Port P3 output Port P3 input
Port P2
Port P2 selection Port P2 interrupt enable Port P2 interrupt-edge select Port P2 interrupt flag Port P2 direction Port P2 output Port P2 input
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MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
SLAS272A - JULY 2000 - REVISED JULY 2000
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS Port P1 Port P1 selection Port P1 interrupt enable Port P1 interrupt-edge select Port P1 interrupt flag Port P1 direction Port P1 output Port P1 input Special Functions SFR module enable 2 SFR module enable 1 SFR interrupt flag2 SFR interrupt flag1 SFR interrupt enable2 SFR interrupt enable1 P1SEL P1IE P1IES P1IFG P1DIR P1OUT P1IN ME2 ME1 IFG2 IFG1 IE2 IE1 026h 025h 024h 023h 022h 021h 020h 005h 004h 003h 002h 001h 000h
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE: All voltages referenced to VSS.
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PRODUCT PREVIEW
Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to + 4.1 V Voltage applied to any pin (referenced to VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VCC+0.3 V Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 mA Storage temperature (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 150C Storage Temperature (programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 85C
MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
SLAS272A - JULY 2000 - REVISED JULY 2000
recommended operating conditions
PARAMETER Supply voltage during program execution, VCC (AVCC = DVCC = VCC) Supply voltage during flash memory programming, VCC (AVCC = DVCC = VCC) Supply voltage, VSS Operating free-air temperature range, TA LF selected, XTS=0 LFXT1 crystal frequency, f(LFXT1) frequency (see Notes 10, 11) 10 XT2 crystal frequency f(XT2) frequency, Processor frequency (signal MCLK), f(S t ) MCLK) (System) Flash-timing-generator frequency, f(FTG) XT1 selected, XTS=1 XT1 selected, XTS=1 MSP430F13x, MSP430F14x MSP430F13x, MSP430F14x MSP430x13x MSP430x14x Watch crystal Ceramic resonator Crystal Ceramic resonator Crystal VCC = 2.2 V VCC = 3.6 V MSP430F13x, MSP430F14x VCC = 2.7 V/3.6 V MSP430F13x MSP430F14x VSS 0.8VCC 450 1000 450 1000 DC DC 257 MIN 1.8 2.7 0.0 -40 32768 8000 8000 8000 8000 5 8 476 NOM MAX 3.6 3.6 0.0 85 UNITS V V V C Hz kHz kHz kHz MHz kHz
PRODUCT PREVIEW
Cumulative program time, t(CPT) (see Note 12)
3 VSS +0.6 VCC
ms V V
Low-level input voltage (TCK, TMS, TDI, RST/NMI), VIL (excluding Xin, Xout) VCC = 2.2 V/3 V High-level input voltage (TCK, TMS, TDI, RST/NMI), VIH VCC = 2.2 V/3 V (excluding Xin, Xout) Input levels at Xin and Xout VIL(Xin, Xout) VIH(Xin, Xout) VCC = 2.2 V/3 V
VSS 0.2xVSS V 0.8xVCC VCC NOTES: 11. In LF mode, the LFXT1 oscillator requires a watch crystal and the LFXT1 oscillator requires a 5.1-M resistor from XOUT to VSS when VCC < 2.5 V. In XT1-mode, the LFXT1. and XT2 oscillators accept a ceramic resonator or a crystal frequency of 4 MHz at VCC 2.2 V. In XT1-mode, the LFXT1 and XT2 oscillators accept a ceramic resonator or an 8-MHz crystal frequency at VCC 2.8 V. 12. In LF mode, the LFXT1 oscillator requires a watch crystal. LFXT1 accepts a ceramic resonator or a crystal in XT1 mode. 13. The cumulative program time must not be exceeded during a segment-write operation. f (MHz) Supply voltage range, 'F13x/14x during programming of the flash memory
8.0 MHz
Supply voltage range, 'F13x/14x during program execution
4.0 MHz
1.8 V
2.7 V 3 V
Supply Voltage - V
Figure 3. Frequency vs Supply Voltage, MSP430F13x or MSP430F14x
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MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
SLAS272A - JULY 2000 - REVISED JULY 2000
electrical characteristics over recommended operating free-air temperature (unless otherwise noted)
supply current into AVCC + DVCC excluding external current, f(System) = 1 MHz
PARAMETER Active mode, f(MCLK) = f(SMCLK) = 1 MHz, , f(ACLK) = 32,768 Hz XTS=0, SELM=(0,1) Active mode, f(MCLK) = f(SMCLK) = 4 096 Hz, f(ACLK) = 4 096 Hz 4,096 XTS=0, SELM=(0,1) XTS=0, SELM=3 Low power mode (LPM0) Low-power mode, Low-power mode, Low power mode (LPM2) F135, , F149 TEST CONDITIONS VCC = 2.2 V TA = -40C to 85C 40C VCC = 3 V VCC = 2.2 V TA = -40C to 85C 40C VCC = 3 V F135, , F149 TA = -40C to 85C 40C TA = -40C to 85C 40C TA = -40C TA = 25C I(LPM3) Low-power mode, (LPM3) MHz, f(MCLK) = f(SMCLK) = 0 MHz f(ACLK) = 32,768 Hz, SCG0 = 1 TA = 85C TA = -40C TA = 25C TA = 85C TA = -40C TA = 25C I(LPM4) Low-power mode, (LPM4) MHz, MHz, f(MCLK) = 0 MHz f(SMCLK) = 0 MHz F(ACLK) = 0 Hz, SCG0 = 1 TA = 85C TA = -40C TA = 25C TA = 85C VCC = 3 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V TBD 65 70 11 17 1 0.9 2.7 2 1.9 3.9 0.1 VCC = 2.2 V 0.1 1.6 0.1 0.1 1.9 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD A A A A A A 340 TBD TBD TBD A MIN NOM 225 MAX TBD A UNIT
I(AM)
I(AM)
F135, , F149
I(LPM0) I(LPM2)
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MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
SLAS272A - JULY 2000 - REVISED JULY 2000
electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
Current consumption of active mode versus system frequency, F-version I(AM) = I(AM) [1 MHz] x f(System) [MHz] Current consumption of active mode versus supply voltage, F-version I(AM) = I(AM) [3 V] + 120 A/V x (VCC - 3 V) SCHMITT-trigger inputs - Ports P1, P2, P3, P4, P5, and P6
PARAMETER VIT IT+ VIT IT- VI - VO Positive-going Positive going input threshold voltage Negative-going Negative going input threshold voltage Input/output voltage differential, (hysteresis) differential TEST CONDITIONS VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V MIN 1.1 1.5 0.4 0.90 0.3 0.5 TYP MAX 1.3 1.8 0.9 1.2 1 1.4 UNIT V V V
PRODUCT PREVIEW
standard inputs - RST/NMI; JTAG: TCK, TMS, TDI, TDO/TDI
PARAMETER VIL VIH Low-level input voltage High-level input voltage TEST CONDITIONS VCC = 2.2 V / 3 V 22 MIN VSS 0.8xVCC TYP MAX VSS+0.6 VCC UNIT V V
outputs - Port 1: P1.0 to P1.7; Port 2: P2.0 to P2.5 (see Note 13)
PARAMETER TEST CONDITIONS IOH(max) = -1.5 mA, IOH(max) = -6 mA, IOH(max) = -1.5 mA, IOH(max) = -6 mA, IOL(max) = 1.5 mA, IOL(max) = 6 mA, IOL(max) = 1.5 mA, IOL(max) = 6 mA, VCC = 2.2 V, VCC = 2.2 V, VCC = 3 V, VCC = 3 V, VCC = 2.2 V, VCC = 2.2 V, VCC = 3 V, VCC = 3 V, See Note 14 See Note 15 See Note 14 See Note 15 See Note 14 See Note 15 See Note 14 See Note 15 MIN VCC-0.25 VCC-0.6 VCC-0.25 VCC-0.6 VSS VSS VSS VSS TYP MAX VCC VCC VCC VCC VSS+0.25 VSS+0.6 VSS+0.25 VSS+0.6 UNIT
VOH
High-level High level output voltage
V
VOL
Low level output voltage Low-level
V
NOTES: 14. In LF mode, the LFXT1 oscillator requires a 5.1-M resistor connected from XOUT to VSS when VCC 2.5V. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The current consumptions in LPM2, LPM3, and LPM4 are measured with active ACLK selected. 15. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed 12 mA to satisfy the maximum specified voltage drop. 16. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed 48 mA to satisfy the maximum specified voltage drop.
input frequency - Ports P1 to P6
PARAMETER f(IN) t(h) = t(L) TEST CONDITIONS VCC = 2.2 V VCC = 3 V MIN TYP MAX 8 10 UNIT MHz
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SLAS272A - JULY 2000 - REVISED JULY 2000
electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
capture timing _ Timer_A3: TA0, TA1, TA2; Timer_B7: Tb0 to TB6
PARAMETER t( ) (int) Ports P2, P4: P t P2 P4 interru t External trigger signal for the interrupt flag (see Notes 16 and 17) TEST CONDITIONS VCC = 2.2 V/3 V VCC = 2.2 V MIN 1.5 62 TYP MAX UNIT Cycle ns
VCC = 3 V 50 NOTES: 17. The external signal sets the interrupt flag every time t(int) is met. It may be set even with trigger signals shorter than t(int). The conditions to set the flag must be met independently of this timing constraint. t(int). is defined in MCLK cycles. 18. The external signal needs additional timing because of the maximum input-frequency constraint.
output frequency
PARAMETER fTAx fACLK, fMCLK, fSMC TA0..2, TB0-TB6, Internal clock source, SMCLK signal applied (see Note 18) P5.6/ACLK, P5.4/MCLK, P5.5/SMCLK CL = 20 pF TEST CONDITIONS MIN DC TYP MAX fSystem MHz CL = 20 pF P2.0/ACLK CL = 20 pF, VCC = 2.2 V / 3 V tXdc Duty cycle of output frequency, P1 4/SMCLK P1.4/SMCLK, CL = 20 pF, VCC = 2.2 V / 3 V fACLK = fLFXT1 = fXT1 fACLK = fLFXT1 = fLF fACLK = fLFXT1/n fSMCLK = fLFXT1 = fXT1 fSMCLK = fLFXT1 = fLF fSMCLK = fLFXT1/n fSMCLK = fDCOCLK 40% 30% 50% 40% 35% 50%- 15 ns 50%- 15 ns 50% 50% 60% 65% 50%- 15 ns 50%- 15 ns fSystem 60% 70% UNIT
NOTE 19: The limits of the system clock MCLK has to be met; the system (MCLK) frequency should not exceed the limits. MCLK and SMCLK frequencies can be different.
external interrupt timing
PARAMETER t( ) (int) Ports P1, P2: External trigger signal for the interrupt flag ( d 17) (see N Notes 16 and 1 ) TEST CONDITIONS VCC = 2.2 V/3 V VCC = 2.2 V MIN 1.5 62 TYP MAX UNIT Cycle ns
VCC = 3 V 50 NOTES: 16 The external signal sets the interrupt flag every time t(int) is met. It may be set even with trigger signals shorter than t(int). The conditions to set the flag must be met independently of this timing constraint. t(int) is defined in MCLK cycles. 17 The external signal needs additional timing because of the maximum input-frequency constraint.
wake-up LPM3
PARAMETER t( (LPM3) ) Delay time TEST CONDITIONS f = 1 MHz f = 2 MHz f = 3 MHz VCC = 2.2 V/3 V MIN TYP MAX 6 6 6 s UNIT
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MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
SLAS272A - JULY 2000 - REVISED JULY 2000
electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
leakage current (see Note 19)
PARAMETER Ilkg(P1.x) Ilkg(P2.x) Port P1 Leakage Lk current Port P2 TEST CONDITIONS Port 1: V(P1.x) (see Note 20) Port 2: V(P2.3) V(P2.4) (see Note 20) VCC = 2.2 V/3 V MIN TYP MAX 50 50 nA UNIT
Ilkg(P6.x) Port P6 Port 6: V(P6.x) (see Note 20) 50 NOTES: 20. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. 21. The port pin must be selected as input and there must be no optional pullup or pulldown resistor.
RAM
PARAMETER VRAMh TEST CONDITIONS CPU HALTED (see Note 21) MIN 1.6 TYP MAX UNIT V
NOTE 22: This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution should take place during this supply voltage condition.
Comparator_A (see Note 23)
PARAMETER TEST CONDITIONS CAON=1, CARSEL=0 CAON=1 CARSEL=0, CAREF=0 CAON=1, CARSEL=0, CAREF=1/2/3, CAREF=1/2/3 No load at P2.3/CA0/TA1 and P2.4/CA1/TA2 Common-mode input voltage Voltage @ 0.25 V V CC CC node CC node CAON =1 PCA0=1, CARSEL=1, CAREF=1, No load at P2.3/CA0/TA1 and P2.4/CA1/TA2, See Figure 4 PCA0=1, CARSEL=1, CAREF=2, No load at P2.3/CA0/TA1 and P2.4/CA1/TA2, See Figure 4 PCA0=1, CARSEL=1, CAREF=3, No load at P2.3/CA0/TA1 and P2 3/CA0/TA1 P2.4/CA1/TA2 Offset voltage Input hysteresis See Note 18 CAON=1 TA = 25C, Overdrive 10 mV, Without filter: CAF=0 t(response LH) ( TA = 25C, Overdrive 10 mV, With filter: CAF=1 TA = 25C, Overdrive 10 mV, without filter: mV CAF=0 TA = 25C, Overdrive 10 mV, with filter: CAF=1 VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V/3 V VCC = 2.2 V/3 V 0 MIN TYP 25 45 30 45 MAX 40 60 50 71 VCC-1 0.24 0.25 V UNIT A
PRODUCT PREVIEW
I(DD) I(Refladder/ RefDiode) V(IC) V(Ref025) See Figure 4 V(Ref050) See Figure 4
A
0.23
Voltage @ 0.5 V V CC
VCC = 2.2 V/3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V/3 V VCC = 2.2 V/3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V
0.47 430 450 -30 0 160 90 1.6 1.1 160 90 1.6 1.1
0.48 550 565
0.5 645 mV 660 30 mV mV ns s
V(R fVT) (RefVT) V(offset) Vhys
0.7 210 150 1.9 1.5 210 150 1.9 1.5
1.4 300 200 3.4 2.6 300
ns 200 3.4 2.6 s
t(response HL) (res onse
NOTES: 23. The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification. 24. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements. The two successive measurements are then summed together.
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MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
SLAS272A - JULY 2000 - REVISED JULY 2000
electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
VCC = 3 V 650 Mean - 6 Sigma Mean - 4 Sigma Mean Mean + 4 Sigma Mean + 6 Sigma 650 VCC = 2.2 V Mean - 6 Sigma Mean - 4 Sigma Mean Mean + 4 Sigma Mean + 6 Sigma
600
600
550
550
500
500
-25
-5
15
35
55
75
450 -45
-25
-5
15
35
55
75
Figure 4. V(RefVT) vs Temperature, VCC = 3 V
0 V VCC 0 1 CAON
Figure 5. V(RefVT) vs Temperature, VCC = 2.2 V
CAF
Low Pass Filter + _ 0 1 0 1
To Internal Modules
V+ V-
CAOUT Set CAIFG Flag 2.0 s
Figure 6. Block Diagram of Comparator_A Module
Overdrive V-
VCAOUT
400 mV V+ t(response)
Figure 7. Overdrive Definition
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450 -45
MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
SLAS272A - JULY 2000 - REVISED JULY 2000
electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
POR
PARAMETER t(POR) Delay V(POR) V(POR) V(POR) V(min) t(Reset) V VCC POR CONDITIONS TA = -40C TA = +25C TA = +85C PUC/POR Reset is accepted internally 2.2 V/3 V VCC 2.2 V/3 V MIN 1.4 1.1 0.8 0 2 NOM 150 MAX 250 1.8 1.5 1.2 0.4 UNIT s V V V V s
V (POR)
PRODUCT PREVIEW
V (min)
POR
No POR
POR
t
Figure 8. Power-On Reset (POR) vs Supply Voltage
2 1.8 1.6 V(POR) - V 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -40 -20 0 20 40 60 80 TA - Temperature - C 25C 0.8 1.2 1.4 1.8 1.5 1.2
Figure 9. V(POR) vs Temperature
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electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
DCO (see Note 25)
PARAMETER f(DCO03) f(DCO13) f(DCO23) f(DCO33) f(DCO43) f(DCO53) f(DCO63) f(DCO73) f(DCO47) S(Rsel) S(DCO) Dt DV TEST CONDITIONS Rsel = 0, DCO = 3, MOD = 0, DCOR = 0, TA = 25C Rsel = 1, DCO = 3, MOD = 0, DCOR = 0, TA = 25C Rsel = 2, DCO = 3, MOD = 0, DCOR = 0, TA = 25C Rsel = 3, DCO = 3, MOD = 0, DCOR = 0, TA = 25C Rsel = 4, DCO = 3, MOD = 0, DCOR = 0, TA = 25C Rsel = 5, DCO = 3, MOD = 0, DCOR = 0, TA = 25C Rsel = 6, DCO = 3, MOD = 0, DCOR = 0, TA = 25C Rsel = 7, DCO = 3, MOD = 0, DCOR = 0, TA = 25C VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V/3 V VCC = 2.2 V/3 V VCC = 2.2 V/3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V/3 V MIN 0.08 0.08 0.14 0.14 0.22 0.22 0.37 0.37 0.61 0.61 1 1 1.6 1.69 2.4 2.7 fDCO40 x 1.7 1.35 1.07 -0.31 -0.33 0 NOM 0.12 0.13 0.19 0.18 0.30 0.28 0.49 0.47 0.77 0.75 1.2 1.3 1.9 2.0 2.9 3.2 fDCO40 x 2.1 1.65 1.12 -0.36 -0.38 5 MAX 0.15 0.16 0.23 0.22 0.36 0.34 0.59 0.56 0.93 0.90 1.5 1.5 2.2 2.29 3.4 3.65 fDCO40 x 2.5 2 1.16 -0.40 -0.43 10 %/C %/V UNIT MHz MHz MHz MHz MHz MHz MHz MHz MHz
Rsel = 4, DCO = 7, MOD = 0, DCOR = 0, TA = 25C SR = fRsel+1 / fRsel SDCO = fDCO+1 / fDCO Temperature drift, Rsel = 4, DCO = 3, MOD = 0 , , , (see Note 26) Drift with VCC variation, Rsel = 4, DCO = 3, MOD = 0 (see Note 26)
NOTES: 25. The DCO frequency may not exceed the maximum system frequency defined by parameter Processor frequency, f(System). 26. This parameter is not production tested. 1 f DCOCLK
max. f DCO_7 min.
IIIIIII IIIIIII
max. f DCO_0 min.
3
5
VCC - V
0
1
2
3
4
5
6
7
DCO
Figure 10. DCO Characteristics
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MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
SLAS272A - JULY 2000 - REVISED JULY 2000
electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
main DCO characteristics
D D D D
Individual devices have a minimum and maximum operation frequency. The specified parameters for fDCOx0 to fDCOx7 are valid for all devices. All ranges selected by Rsel(n) overlap with Rsel(n+1): Rsel0 overlaps with Rsel1, ... Rsel6 overlaps with Rsel7. DCO control bits DCO0, DCO1, and DCO2 have a step size as defined by parameter SDCO. Modulation control bits MOD0 to MOD4 select how often fDCO+1 is used within the period of 32 DCOCLK cycles. The frequency f(DCO) is used for the remaining cycles. The frequency is an average equal to f(DCO) x (2MOD/32 ).
PARAMETER TEST CONDITIONS XTS=0; LF oscillator selected VCC = 2.2 V/3 V XTS=1; XT1 oscillator selected VCC = 2.2 V/3 V XTS=0; LF oscillator selected VCC = 2.2 V/3 V XTS=1; XT1 oscillator selected VCC = 2.2 V/3 V VCC = 2.2 V/3 V VCC = 2.2 V/3 V VSS 0.8 x VCC MIN NOM 12 pF 2 12 pF 2 0.2 x VCC VCC V V MAX UNIT
crystal oscillator, LFXT1 oscillator (see Note 27)
XCIN
Integrated input capacitance
PRODUCT PREVIEW
XCOUT
Integrated output capacitance
XINL XINH
Input levels at XIN, XOUT
NOTE 27: The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer.
crystal oscillator, XT2 oscillator (see Note 27)
PARAMETER XCIN XCOUT XINL XINH Integrated input capacitance Integrated output capacitance Input levels at XIN, XOUT TEST CONDITIONS VCC = 2.2 V/3 V VCC = 2.2 V/3 V VCC = 2.2 V/3 V VCC = 2.2 V/3 V VSS 0.8 x VCC MIN NOM 2 2 0.2 x VCC VCC MAX UNIT pF pF V V
NOTE 26: The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer.
USART (see Note 28
PARAMETER t( ) () USART: deglitch time VCC = 2.2 V VCC = 2.2 V TEST CONDITIONS MIN 0.6 0.3 NOM MAX 2.6 1.4 UNIT s
NOTE 28: The signal applied to the USART receive signal/terminal (URXD) should meet the timing requirements of t(t) to ensure that the URXS flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t(t). The operating conditions to set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on the URXD line.
46
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MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
SLAS272A - JULY 2000 - REVISED JULY 2000
electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
12-bit ADC, power supply and input range conditions (see Note 29)
PARAMETER AVCC Analog supply voltage TEST CONDITIONS AVCC and DVCC are connected together AVSS and DVSS are connected together V(AVSS) = V(DVSS) = 0 V 2_5 V = 1 for 2.5 V built-in reference 2_5 2 5 V = 0 for 1.5 V built-in reference 1 5 built in IV(REF)+ < 1 mA 3V 2.2 V/3 V 2.2 V 3V IV(REF)+ = 500 A +/- 100 A Analog input voltage ~0.75 V; 0 75 2_5 V = 0 IV(REF)+ = 500 A 100 A Analog i/p voltage ~1.25 V; 2_5 V = 1 IV(REF)+ =100 A 900 A, VCC=3 V, VCC 3 V ax ~0.5 x VREF 05 REF+ Error of conversion result 1 LSB 2.2 V 3V 3V CVREF+=0 pF CVREF+=5 F 1.4 0 1.4 MIN 1.8 2.4 1.44 0.01 2.5 1.5 NOM MAX 3.6 2.6 V 1.56 -0.5 -1 1 1 1 600 ns 20 VAVCC VAVCC - 1.4 VAVCC VAVCC 0.65 0.8 0.5 0.5 0.5 1.3 mA 3V 3V 2.2 V 3V 1.6 0.8 0.8 mA 0.8 mA V V V LSB mA LSB UNIT V
VREF REF+
Positive built-in reference voltage output Load current out of VREF+ terminal
IVREF+ VREF
IL(VREF)+ L(VREF)
Load-current regulation g VREF+ terminal
IDL(VREF)+ DL(VREF)
Load current regulation g VREF+ terminal Positive external reference voltage input Negative external reference voltage input Differential external reference voltage input Analog input voltage range (see Note 33) Operating supply current into AVCC terminal (see Note 34) Operating supply current into AVCC terminal (see Note 35) Operating supply current g y (see Note 35)
VeREF+ VREF- /VeREF- (VeREF+ - VREF-/VeREF-) V(P6.x/Ax)
VeREF+ > VeREF-/VeREF- (see Note 30) VeREF+ > VeREF-/VeREF- (see Note 31) VeREF+ > VeREF-/VeREF- (see Note 32) All P6.0/A0 to P6.7/A7 terminals. Analog inputs selected in ADC12MCTLx register and P6Sel.x=1 0 x 7; V(AVSS) VP6.x/Ax V(AVCC) fADC12CLK = 5.0 MHz ADC12ON = 1, REFON = 0 fADC12CLK = 5.0 MHz ADC12ON = 0, REFON = 1, 2_5V = 1 fADC12CLK = 5.0 MHz ADC12ON = 0, 0 REFON = 1, 2_5V = 0 2.2 V
0
V
IADC12
IREF+
IREF+ REF
NOTES: 29. The leakage current is defined in the leakage current table with P6.x/Ax parameter. 30. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced accuracy requirements. 31. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced accuracy requirements. 32. The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with reduced accuracy requirements. 33. The analog input voltage range must be within the selected reference voltage range VR+ to VR- for valid conversion results. 34. The internal reference supply current is not included in current consumption parameter IADC12. 35. The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
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47
PRODUCT PREVIEW
MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
SLAS272A - JULY 2000 - REVISED JULY 2000
electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
12-bit ADC, built-in reference (see Note 39)
PARAMETER IVeREF+ IVREF-/VeREF- CVREF+ Ci Static input current (see Note 36) Static input current (see Note 36) Capacitance at pin VREF+ (see Note 37) Input capacitance (see Note 38) Input MUX ON resistance(see Note 38) Temperature coefficient of built-in reference TEST CONDITIONS 0V VeREF+ VAVCC 0V VeREF- VAVCC REFON =1, 0 mA IVREF+ IV(REF)+(max) REFON =1, 0 mA IV(REF)+ IV(REF)+(max) Only one terminal can be selected at one time, P6.x/Ax 0V VAx VAVCC IV(REF)+ is a constant in the range of 0 mA IV(REF)+ 1 mA 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V 3V 2.2 V/3 V 20 5 18 30 2000 1000 ppm/C MIN NOM MAX 1 1 200 UNIT A A pF F
Zi
TREF+
PRODUCT PREVIEW
NOTES: 36. The external reference is used during conversion to charge and discharge the capacitance array. The dynamic impedance should follow the recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy. 37. The internal buffer operational amplifier and the accuracy specifications require an external capacitor. The external capacitance has two limits: the first is a capacitance of 0 to the maximum data (pF-range), and the second is an external capacitor of greater than the minimum data (F-range). The output amplifier operates in the safe area in both ranges. 38. The input capacitance is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy. 39. The voltage source on VeREF+ and VREF-/VeREF-) needs to have low dynamic impedance for 12-bit accuracy. A minimum of 470 nF of the reference supply allows the charge to settle for the 12-bit accuracy.
48
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MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
SLAS272A - JULY 2000 - REVISED JULY 2000
electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
12-bit ADC, timing parameters
PARAMETER Settle time of internal reference voltage (see Figure 11 and Note 40) Conversion time (see Figure 12 tCONVERT Conversion time tADC12ON tSample S l Settle time of the ADC Sampling time TEST CONDITIONS IV(REF)+ = 0.5 mA, CV(REF)+ = 10 F, VREF+ = 1.5 V, VAVCC = 2.2 V IV(REF)+ = 0.5 mA, 0 CV(REF)+ 200pF, VREF+ = 1.5 V, VAVCC = 2.2 V AVCC(min) VAVCC AVCC(max), CVREF+ 5 F, Internal oscillator, fOSC = 4 MHz to 6 MHz AVCC(min) VAVCC AVCC(max), External fADC12(CLK) from ACLK or MCLK or SMCLK: ADC12SSEL 0 AVCC(min) VAVCC AVCC(max) (see Note 41) VAVCC(min) < VAVCC < VAVCC(max) 3V Ri( F i(source) = 400 , Zi = 1000 , Ci = 30 pF ) 2.2 V = [Ri(source) x+ Zi] x Ci;(see Note 42) 2.17 MIN NOM MAX 17 20 UNIT ms s s
tREF(ON)
2.17
3.6
13xADC12DIVx 1/fADC12(CLK) 100 1220
s ns ns
1400
CVREF+ 100 F 10 F 1 F 100 nF 10 nF 1 nF 100 pF 0 1 s 10 s 100 s 1 ms 10 ms 100 ms tREF(ON) VCC = 3 V VREf+ = 2.5 V VCC = 2.2 V VREf+ = 1.5 V
Figure 11. Maximum Settling Time of Internal Reference tREF(ON) vs External Capacitor on VREF+
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PRODUCT PREVIEW
NOTES: 40. The condition is that the error in a conversion started after tREF(ON) is less than 0.5 LSB. The settling time depends on the external capacitive load. The feedback of the binary-weighted capacitor array to the reference voltage requires a large external capacitor. Small external capacitors need greater conversion time (decreased fADC12CLK). 41. The condition is that the error in a conversion started after tADC12ON is less than 0.5 LSB. The reference used is already settled. 42. Ten Tau () are needed to get an error of less than 0.5 LSB. tSample = 10 x (Ri + Zi) + 800 ns
MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
SLAS272A - JULY 2000 - REVISED JULY 2000
electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
f(ADC12CLK(max)) 5 MHz
2.5 MHz
0.625 MHz Use Serial R of 500 on VREF+
100 pF
200 pF
5 F
Capacitor at VREF+
PRODUCT PREVIEW
Figure 12. Maximum Frequency fADC12(CLK) vs External Capacitor on VREF+ 12-bit ADC, linearity parameters
PARAMETER EI ED EO EG ET Integral linearity error Differential linearity error Offset error Gain error Total unadjusted error TEST CONDITIONS (VeREF+ - VREF-/VeREF-)min (VeREF+ - VREF-/VeREF-) (VeREF+ - VREF-/VeREF-)min (VeREF+ - VREF-/VeREF-) (VeREF+ - VREF-/VeREF-)min (VeREF+ - VREF-/VeREF-), Internal impedance of source Ri < 100 (VeREF+ - VREF-/VeREF-)min (VeREF+ - VREF-/VeREF-) (VeREF+ - VREF-/VeREF-)min (VeREF+ - VREF-/VeREF-) 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V MIN NOM 1 1 2 1.1 2 MAX TBD TBD TBD TBD TBD UNIT LSB LSB LSB LSB LSB
50
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MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
SLAS272A - JULY 2000 - REVISED JULY 2000
electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
12-bit ADC, temperature sensor and built-in Vmid
PARAMETER ISENSOR VSENSOR TCSENSOR tSENSOR(ON) IVMID VMID tON(VMID) On-time if channel 10 is selected (see Note 44) Current into divider at channel 11 AVCC divider at channel 11 On-time if channel 11 is selected (see Note 46) Operating supply current into g y AVCC terminal (see Note 43) TEST CONDITIONS VREFON = 0, INCH = 0Ah, , , ADC12ON=NA., TA = 25_C ADC12ON = 1, INCH = 0Ah, TA = 0C 1 0Ah ADC12ON = 1 INCH = 0Ah 1, ADC12ON = 1, INCH = 0Ah, , , Error of conversion result 1 LSB ADC12ON = 1, INCH = 0Bh, ( , , (see Note 45) ADC12ON = 1, INCH = 0Bh, , , VMID is ~0.5 x VAVCC ADC12ON = 1, INCH = 0Bh, Error of conversion result 1 LSB 2.2 V 3V 2.2 V 3V 2.2 V 3V 2.2 V 3V 2.2 V 3V 2.2 V 3V 2.2 V 3V 0.9 1.5 MIN NOM 135 135 986 986 3.55 3.55 MAX TBD TBD 9865% 9865% 3.553% 3.553% 25 21 NA NA 0.900.04 1.500.04 NA NA UNIT A mV mV/C s A V ns
NOTES: 43. The sensor current ISENSOR is consumed if (ADC12ON = 1 and VREFON=1), or (ADC12ON=1 AND INCH=0Ah and sample signal is high). 44. The typical equivalent impedance of the sensor is 51 k. The sample time needed is the sensor-on time tSENSOR(ON) 45. No additional current is needed. The VMID is anyway used during conversion. 46. The on-time tON(VMID) is identical to sampling time tSample; no additional on time is needed.
JTAG, program memory and fuse
PARAMETER f(TCK) JTAG/Test TCK frequency Pullup resistors on TMS, TCK, TDI (see Note 47) VFB IFB I(DD-PGM) I(DD-Erase) t(retention) ( t ti ) Fuse-blow voltage, F versions (see Note 49) JTAG/fuse JTAG/f (see Note 48) F-versions only F-versions only F-versions F versions only Supply current on TDI with fuse blown Time to blow the fuse Current from DVCC when programming is active Programming time, single pulse Write/erase cycles Data retention TJ = 25C 2.7 V/3.6 V 2.7 V/3.6 V 104 100 3 3 105 TEST CONDITIONS VCC 2.2 V 3V 2.2 V/ 3V 2.2 V/3 V MIN DC DC 25 6.0 60 NOM MAX 5 10 90 7.0 100 1 5 5 UNIT MHz k V mA ms mA mA cycles years
NOTES: 47. TMS, TDI, and TCK pull-up resistors are implemented in all F versions. 48. Once the fuse is blown, no further access to the MSP430 JTAG/test feature is possible. The JTAG block is switched to bypass mode. 49. The supply voltage to blow the fuse is applied to the TDI pin. 50. f(TCK) may be restricted to meet the timing requirements of the module selected. Duration of the program/erase cycle is determined by f(FTG) applied to the flash timing controller. It can be calculated as follows: t(word write) = 33 x 1/f(FTG) t(segment write, byte 0) = 30 x 1/f(FTG) t(segment write, byte 1 - 63) = 20 x 1/f(FTG) t(mass erase) = 5296 x 1/f(FTG) t(page erase) = 4817 x 1/f(FTG)
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51
PRODUCT PREVIEW
MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
SLAS272A - JULY 2000 - REVISED JULY 2000
input/output schematic
port P1, P1.0 to P1.7, input/output with Schmitt-trigger
P1SEL.x P1DIR.x Direction Control From Module 0 1 Pad Logic P1OUT.x Module X OUT 0 1 P1.7/TA2 P1.0/TACLK ..
P1IN.x EN
PRODUCT PREVIEW
Module X IN P1IRQ.x
D P1IE.x Q P1IFG.x EN Set Interrupt Edge Select
Interrupt Flag
P1IES.x P1SEL.x
PnSel.x P1Sel.0 P1Sel.1 P1Sel.2 P1Sel.3 P1Sel.4 P1Sel.5 P1Sel.6 P1Sel.7
PnDIR.x P1DIR.0 P1DIR.1 P1DIR.2 P1DIR.3 P1DIR.4 P1DIR.5 P1DIR.6 P1DIR.7
Dir. CONTROL FROM MODULE P1DIR.0 P1DIR.1 P1DIR.2 P1DIR.3 P1DIR.4 P1DIR.5 P1DIR.6 P1DIR.7
PnOUT.x P1OUT.0 P1OUT.1 P1OUT.2 P1OUT.3 P1OUT.4 P1OUT.5 P1OUT.6 P1OUT.7
MODULE X OUT DVSS Out0 signal Out1 signal Out2 signal SMCLK Out0 signal Out1 signal Out2 signal
PnIN.x P1IN.0 P1IN.1 P1IN.2 P1IN.3 P1IN.4 P1IN.5 P1IN.6 P1IN.7
MODULE X IN TACLK CCI0A CCI1A CCI2A unused unused unused unused
PnIE.x P1IE.0 P1IE.1 P1IE.2 P1IE.3 P1IE.4 P1IE.5 P1IE.6 P1IE.7
PnIFG.x P1IFG.0 P1IFG.1 P1IFG.2 P1IFG.3 P1IFG.4 P1IFG.5 P1IFG.6 P1IFG.7
PnIES.x P1IES.0 P1IES.1 P1IES.2 P1IES.3 P1IES.4 P1IES.5 P1IES.6 P1IES.7
Signal from or to Timer_A
52
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MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
SLAS272A - JULY 2000 - REVISED JULY 2000
input/output schematic (continued)
port P2, P2.0 to P2.2, P2.6, and P2.7 input/output with Schmitt-trigger
P2SEL.x P2DIR.x Direction Control From Module P2OUT.x Module X OUT 0 1 0 1 P2.0/ACLK P2.1/TAINCLK P2.2/CAOUT/TA0 P2.6/ADC12CLK P2.7/TA0 Bus Keeper 0: Input 1: Output
Pad Logic P2IN.x EN Module X IN P2IRQ.x D P2IE.x P2IFG.x Q EN Set Interrupt Edge Select P2IES.x P2SEL.x CAPD.X
Interrupt Flag
x: Bit Identifier 0 to 2, 6, and 7 for Port P2 Dir. CONTROL FROM MODULE P2DIR.0 P2DIR.1 P2DIR.2 P2DIR.6 P2DIR.7
PnSel.x P2Sel.0 P2Sel.1 P2Sel.2 P2Sel.6 P2Sel.7
PnDIR.x P2DIR.0 P2DIR.1 P2DIR.2 P2DIR.6 P2DIR.7
PnOUT.x P2OUT.0 P2OUT.1 P2OUT.2 P2OUT.6 P2OUT.7
MODULE X OUT ACLK DVSS CAOUT ADC12CLK Out0 signal
PnIN.x P2IN.0 P2IN.1 P2IN.2 P2IN.6 P2IN.7
MODULE X IN unused INCLK CCI0B unused unused
PnIE.x P2IE.0 P2IE.1 P2IE.2 P2IE.6 P2IE.7
PnIFG.x P2IFG.0 P2IFG.1 P2IFG.2 P2IFG.6 P2IFG.7
PnIES.x P2IES.0 P2IES.1 P2IES.2 P2IES.6 P2IES.7
Signal from Comparator_A Signal to Timer_A Signal from Timer_A ADC12CLK signal is output of the 12-bit ADC module
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PRODUCT PREVIEW
MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
SLAS272A - JULY 2000 - REVISED JULY 2000
input/output schematic (continued)
port P2, P2.3 to P2.4, input/output with Schmitt-trigger
P2SEL.3 P2DIR.3 Direction Control From Module P2OUT.3 Module X OUT 0 1 0 1 0: Input 1: Output Pad Logic P2.3/CA0/TA1
P2IN.3 EN Module X IN P2IRQ.3 D P2IE.3 P2IFG.3 Q EN Set
Interrupt Edge Select
Bus Keeper
CAPD.3 Comparator_A CAEX P2CA CAREF CAF +
PRODUCT PREVIEW
Interrupt Flag
P2IES.3 P2SEL.3
CCI1B To Timer_A3
- CAREF Reference Block
P2SEL.4 Interrupt P2IES.4 Flag P2IFG.4 P2IRQ.4 Module X IN P2IE.4 D EN P2IN.4 Q Set EN
Edge Select Interrupt
CAPD.4
Bus Keeper
Module X OUT P2OUT.4 From Module Direction Control P2DIR.4 P2SEL.4 DIRECTION CONTROL FROM MODULE P2DIR.3 P2DIR.4
1 0 1 0 Pad Logic 1: Output 0: Input P2.4/CA1/TA2
PnSel.x P2Sel.3
PnDIR.x P2DIR.3
PnOUT.x P2OUT.3 P2OUT.4
MODULE X OUT Out1 signal Out2 signal
PnIN.x P2IN.3 P2IN.4
MODULE X IN unused unused
PnIE.x P2IE.3 P2IE.4
PnIFG.x P2IFG.3 P2IFG.4
PnIES.x P2IES.3 P2IES.4
P2Sel.4 P2DIR.4 Signal from Timer_A
54
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MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
SLAS272A - JULY 2000 - REVISED JULY 2000
input/output schematic (continued)
port P2, P2.5, input/output with Schmitt-trigger and Rosc function for the basic clock module
P2SEL.5 P2DIR.5 Direction Control From Module P2OUT.5 Module X OUT 0 1 0 1 P2.5/Rosc 0: Input 1: Output Pad Logic
Bus Keeper P2IN.5 EN Module X IN P2IRQ.5 D P2IE.5 Q P2IFG.5 EN Set Edge Select Interrupt VCC Internal to Basic Clock Module 0
1
Interrupt Flag
P2IES.5 P2SEL.5
to DCOR CAPD.5 DC Generator
DCOR: Control Bit From Basic Clock Module If it Is Set, P2.5 Is Disconnected From P2.5 Pad DIRECTION CONTROL FROM MODULE P2DIR.5
PnSel.x P2Sel.5
PnDIR.x P2DIR.5
PnOUT.x P2OUT.5
MODULE X OUT DVSS
PnIN.x P2IN.5
MODULE X IN unused
PnIE.x P2IE.5
PnIFG.x P2IFG.5
PnIES.x P2IES.5
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55
PRODUCT PREVIEW
MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
SLAS272A - JULY 2000 - REVISED JULY 2000
input/output schematic (continued)
port P3, P3.0 and P3.4 to P3.7, input/output with Schmitt-trigger
P3SEL.x P3DIR.x Direction Control From Module 0 1 Pad Logic P3OUT.x Module X OUT 0 1 P3.0/STE0 0: Input 1: Output
P3.4/UTXD0 P3.5/URXD0 P3.6/UTXD1 P3.7/URXD1
P3IN.x EN
PRODUCT PREVIEW
Module X IN
D
x: Bit Identifier, 0 and 4 to 7 for Port P3 DIRECTION CONTROL FROM MODULE DVSS DVSS DVCC DVSS DVCC
PnSel.x P3Sel.0 P3Sel.4 P3Sel.5 P3Sel.6 P3Sel.7
PnDIR.x P3DIR.0 P3DIR.4 P3DIR.5 P3DIR.6 P3DIR.7
PnOUT.x P3OUT.0 P3OUT.4 P3OUT.5 P3OUT.6 P3OUT.7
MODULE X OUT DVSS UTXD0 DVSS UTXD1 DVSS
PnIN.x P3IN.0 P3IN.4 P3IN.5 P3IN.6 P3IN.7
MODULE X IN STE0 Unused URXD0 Unused URXD1
Output from USART0 module Output from USART1 module Input to USART0 module Input to USART1 module
port P3, P3.1, input/output with Schmitt-trigger
P3SEL.1 SYNC MM STC STE P3DIR.1 DCM_SIMO P3OUT1 (SI)MO0 From USART0 0 1 Pad Logic 0 1 P3.1/SIMO0 0: Input 1: Output
P3IN.1 EN SI(MO)0 To USART0 D
56
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MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
SLAS272A - JULY 2000 - REVISED JULY 2000
input/output schematic (continued)
port P3, P3.2, input/output with Schmitt-trigger
P3SEL.2 SYNC MM STC STE P3DIR.2 DCM_SOMI P3OUT.2 SO(MI)0 From USART0 0 1 Pad Logic 0 1 P3.2/SOMI0 0: Input 1: Output
P3IN.2 EN (SO)MI0 To USART0 D
port P3, P3.3, input/output with Schmitt-trigger
P3SEL.3 SYNC MM STC STE P3DIR.3 DCM_UCLK P3OUT.3 UCLK.0 From USART0 0 1 Pad Logic 0 1 P3.3/UCLK0 0: Input 1: Output
P3IN.3 EN UCLK0 D To USART0 NOTE: UART mode: The UART clock can only be an input. If UART mode and UART function are selected, the P3.3/UCLK0 is always an input. SPI, slave mode: The clock applied to UCLK0 is used to shift data in and out. SPI, master mode: The clock to shift data in and out is supplied to connected devices on pin P3.3/UCLK0 (in slave mode).
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57
PRODUCT PREVIEW
MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
SLAS272A - JULY 2000 - REVISED JULY 2000
input/output schematic (continued)
port P4, P4.0 to P4.6, input/output with Schmitt-trigger
P4SEL.x P4DIR.x Direction Control From Module TBoutHiZ P4OUT.x Module X OUT 0 1 Pad Logic 0 1 P4.0/TB0 .. 0: Input 1: Output
P4.6/TB6
Bus Keeper P4IN.x EN
PRODUCT PREVIEW
Module X IN
D
x: bit identifier, 0 to 6 for Port P4 DIRECTION CONTROL FROM MODULE P4DIR.0 P4DIR.1 P4DIR.2 P4DIR.3 P4DIR.4 P4DIR.5 P4DIR.6
PnSel.x P4Sel.0 P4Sel.1 P4Sel.2 P4Sel.3 P4Sel.4 P4Sel.5 P4Sel.6 Signal from Timer_B Signal to Timer_B
PnDIR.x P4DIR.0 P4DIR.1 P4DIR.2 P4DIR.3 P4DIR.4 P4DIR.5 P4DIR.6
PnOUT.x P4OUT.0 P4OUT.1 P4OUT.2 P4OUT.3 P4OUT.4 P4OUT.5 P4OUT.6
MODULE X OUT Out0 signal Out1 signal Out2 signal Out3 signal Out4 signal Out5 signal Out6 signal
PnIN.x P4IN.0 P4IN.1 P4IN.2 P4IN.3 P4IN.4 P4IN.5 P4IN.6
MODULE X IN CCI0A / CCI0B CCI1A / CCI1B CCI2A / CCI2B CCI3A / CCI3B CCI4A / CCI4B CCI5A / CCI5B CCI6A / CCI6B
58
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MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
SLAS272A - JULY 2000 - REVISED JULY 2000
input/output schematic (continued)
port P4, P4.7, input/output with Schmitt-trigger
P4SEL.7 P4DIR.7 0 1 Pad Logic P4OUT.7 DVSS 0 1 P4.7/TBCLK 0: Input 1: Output
P4IN.7 EN Timer_B, TBCLK D
port P5, P5.0 and P5.4 to P5.7, input/output with Schmitt-trigger
P5SEL.x P5DIR.x Direction Control From Module 0 1 Pad Logic P5OUT.x Module X OUT 0 1 P5.0/STE1 0: Input 1: Output
P5.4/MCLK P5.5/SMCLK P5.6/ACLK P5.7/TBOutH
P5IN.x EN Module X IN D
x: Bit Identifier, 0 and 4 to 7 for Port P5 Dir. CONTROL FROM MODULE DVSS DVCC DVCC DVCC DVSS
PnSel.x P5Sel.0 P5Sel.4 P5Sel.5 P5Sel.6 P5Sel.7
PnDIR.x P5DIR.0 P5DIR.4 P5DIR.5 P5DIR.6 P5DIR.7
PnOUT.x P5OUT.0 P5OUT.4 P5OUT.5 P5OUT.6 P5OUT.7
MODULE X OUT DVSS MCLK SMCLK ACLK DVSS
PnIN.x P5IN.0 P5IN.4 P5IN.5 P5IN.6 P5IN.7
MODULE X IN STE.1 unused unused unused TBoutHiZ
PnIE.x P5IE.0 P5IE.4 P5IE.5 P5IE.6 P5IE.7
PnIFG.x P5IFG.0 P5IFG.4 P5IFG.5 P5IFG.6 P5IFG.7
PnIES.x P5IES.0 P5IES.4 P5IES.5 P5IES.6 P5IES.7
NOTE: TBoutHiZ signal is used by port module P4, pins P4.0 to P4.6. The function of TboutHiZ is mainly useful when used with Timer_B7.
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PRODUCT PREVIEW
MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
SLAS272A - JULY 2000 - REVISED JULY 2000
input/output schematic (continued)
port P5, P5.1, input/output with Schmitt-trigger
P5SEL.1 SYNC MM STC STE P5DIR.1 DCM_SIMO P5OUT.1 (SI)MO1 From USART1 0 1 Pad Logic 0 1 P5.1/SIMO1 0: Input 1: Output
P5IN.1 EN SI(MO)1 To USART1 D
PRODUCT PREVIEW
port P5, P5.2, input/output with Schmitt-trigger
P5SEL.2 SYNC MM STC STE P5DIR.2 DCM_SOMI P5OUT.2 SO(MI)1 From USART1 0 1 Pad Logic 0 1 P5.2/SOMI1 0: Input 1: Output
P5IN.2 EN (SO)MI1 To USART1 D
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MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
SLAS272A - JULY 2000 - REVISED JULY 2000
input/output schematic (continued)
port P5, P5.3, input/output with Schmitt-trigger
P5SEL.3 SYNC MM STC STE P5DIR.3 DCM_SIMO P5OUT.3 UCLK1 From USART1 0 1 Pad Logic 0 1 P5.3/UCLK1 0: Input 1: Output
P5IN.3 EN D UCLK1 To USART1 NOTE: UART mode: The UART clock can only be an input. If UART mode and UART function are selected, the P5.3/UCLK1 direction is always input. SPI, slave mode: The clock applied to UCLK1 is used to shift data in and out. SPI, master mode: The clock to shift data in and out is supplied to connected devices on pin P5.3/UCLK1 (in slave mode).
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61
PRODUCT PREVIEW
MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
SLAS272A - JULY 2000 - REVISED JULY 2000
input/output schematic (continued)
port P6, P6.0 to P6.7, input/output with Schmitt-trigger
P6SEL.x P6DIR.x Direction Control From Module 0 1 0 1 0: Input 1: Output Pad Logic P6.0 .. P6.7 P6OUT.x Module X OUT
Bus Keeper P6IN.x EN
PRODUCT PREVIEW
Module X IN
D
From ADC To ADC
x: Bit Identifier, 0 to 7 for Port P6 NOTE: Analog signals applied to digital gates can cause current flow from the positive to the negative terminal. The throughput current flows if the analog signal is in the range of transitions 01 or 10. The value of the throughput current depends on the driving capability of the gate. For MSP430, it is approximately 100 A. Use P6SEL.x=1 to prevent throughput current. P6SEL.x should be set, even if the signal at the pin is not being used by the ADC12. PnSel.x P6Sel.0 P6Sel.1 P6Sel.2 P6Sel.3 P6Sel.4 P6Sel.5 P6Sel.6 P6Sel.7 PnDIR.x P6DIR.0 P6DIR.1 P6DIR.2 P6DIR.3 P6DIR.4 P6DIR.5 P6DIR.6 P6DIR.7 DIR. CONTROL FROM MODULE P6DIR.0 P6DIR.1 P6DIR.2 P6DIR.3 P6DIR.4 P6DIR.5 P6DIR.6 P6DIR.7 PnOUT.x P6OUT.0 P6OUT.1 P6OUT.2 P6OUT.3 P6OUT.4 P6OUT.5 P6OUT.6 P6OUT.7 MODULE X OUT DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS PnIN.x P6IN.0 P6IN.1 P6IN.2 P6IN.3 P6IN.4 P6IN.5 P6IN.6 P6IN.7 MODULE X IN unused unused unused unused unused unused unused unused
NOTE: The signal at pins P6.x/Ax is used by the 12-bit ADC module.
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MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
SLAS272A - JULY 2000 - REVISED JULY 2000
input/output schematic (continued)
JTAG pins TMS, TCK, TDI, TDO/TDI, input/output with Schmitt-trigger
TDO Controlled by JTAG Controlled by JTAG JTAG Controlled by JTAG TDI DVCC DVCC TDO/TDI
Fuse Burn & Test Fuse Test & Emulation Module TMS DVCC see Note 1 TDI
TMS DVCC TCK TCK During Programming Activity and During Blowing of the Fuse, Pin TDO/TDI Is Used to Apply the Test Input Data for JTAG Circuitry
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63
PRODUCT PREVIEW
MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
SLAS272A - JULY 2000 - REVISED JULY 2000
MECHANICAL DATA
PM (S-PQFP-G64)
0,27 0,17 48 33
PLASTIC QUAD FLATPACK
0,50
0,08 M
49
32
PRODUCT PREVIEW
64
17 0,13 NOM
1 7,50 TYP 10,20 SQ 9,80 12,20 SQ 11,80 1,45 1,35
16 Gage Plane
0,25 0,05 MIN 0- 7
0,75 0,45
Seating Plane 1,60 MAX 0,08 4040152 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Falls within JEDEC MS-026 May also be thermally enhanced plastic with leads connected to the die pads.
64
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Copyright (c) 2000, Texas Instruments Incorporated

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