 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| TSB21LV03BI IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER SGLS108 - FEBRUARY 1999 D D D D D D D D D D Supports Provisions of IEEE 1394-1995 Standard for High Performance Serial Bus Fully Interoperable with FireWireTM Implementation of IEEE 1394-1995 Provides Three Fully-Compliant Cable Ports at 100/200 Megabits per Second (Mbits/s) Cable Ports Monitor Line Conditions for Active Connection to Remote Node Device Power-Down Feature to Conserve Energy in Battery-Powered Applications Inactive Ports Disabled to Save Power Logic Performs System Initialization and Arbitration Functions Encode and Decode Functions Included for Data-Strobe Bit-Level Encoding Incoming Data Resynchronized to Local Clock Single 3.3-V Supply Operation D D D D D D D D D Interface to Link-Layer Controller Supports TITM Bus-Holder Isolation Data Interface to Link-Layer Controller Provided Through 2/4 Parallel Lines at 50 MHz 25-MHz Crystal Oscillator and PLL Provide Transmit/Receive Data at 100/200 Mbits/s, and Link-Layer Controller Clock at 50 MHz Interoperable with 1394 Link-Layer Controllers Using 5-V Supplies Interoperable Across 1394 Cable with 1394 Physical Layers (Phy) Using 5-V Supplies Node Power-Class Information Signaling for System Power Management Cable Power Presence Monitoring Separate Cable Bias and Driver Termination Voltage Supply for Each Port High Performance 64-Pin TQFP (PM) Package description The TSB21LV03B provides the analog and digital physical layer functions needed to implement a three-port node in a cable-based IEEE 1394-1995 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB21LV03B is designed to interface with a link-layer controller (LLC), such as the TSB12LV21A, TSB12LV31, or TSB12C01A. The TSB21LV03B requires either an external 24.576-MHz crystal or crystal oscillator. The internal oscillator drives an internal phase-locked loop (PLL), which generates the required 196.608-MHz reference signal. The 196.608-MHz reference signal is internally divided to provide the 49.152/98.304-MHz clock signals that control transmission of the outbound encoded strobe and data information. The 49.152-MHz clock signal is also supplied to the associated LLC for synchronization of the two chips and is used for resynchronization of the received data. For the TSB21LV03B, the 49.152 MHz clock output is active when RESET is asserted low. The power-down function, when enabled by taking the PD terminal high, stops operation of the PLL and disables all circuitry except the cable-not-active signal circuitry. The TSB21LV03B supports an optional isolation barrier between itself and its LLC. When ISO is tied high, the link interface outputs behave normally. Also, when ISO is tied high, the internal bus hold function is enabled for use with the TI Bus Holder (patent pending) isolation. TI bus holder isolation is implemented when ISO is tied high. This serial bus implements technology covered by one or more patents of Apple Computer, Incorporated and INMOS, Limited. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. FireWire is a trademark of Apple Computer, Incorporated. TI is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1999, Texas Instruments Incorporated POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 TSB21LV03BI IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER SGLS108 - FEBRUARY 1999 description (continued) Data bits to be transmitted through the cable ports are received from the LLC on two or four data lines (D0 - D3), and are latched internally in the TSB21LV03B in synchronization with the 49.152-MHz system clock. These bits are combined serially, encoded, and transmitted at 98.304 or 196.608 Mbits/s as the outbound data-strobe information stream. During transmission, the encoded data information is transmitted differentially on the TPB cable pair(s), and the encoded strobe information is transmitted differentially on the TPA cable pair(s). During packet reception the TPA and TPB transmitters of the receiving cable port are disabled, and the receivers for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded Strobe information is received on the TPB cable pair. The received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The serial data bits are split into two or four parallel streams, resynchronized to the local system clock, and sent to the associated LLC. The received data is also transmitted (repeated) out of the other active (connected) cable ports. Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this common mode voltage is used during arbitration to set the speed of the next packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage for the presence of the remotely supplied twisted-pair bias voltage. The presence or absence of this common-mode voltage is used as an indication of cable connection status. The cable connection status signal is internally debounced in the TSB21LV03B on a cable disconnect-to-connect. The debounced cable connection status signal initiates a bus reset. After a cable disconnect-to-connect, a debounce delay is initiated. There is no delay on a cable disconnect. The TSB21LV03B provides a 1.86-V nominal bias voltage for driver load termination. This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. The value of this bias voltage has been chosen to allow interoperability between transceiver chips operating from either 5-V or 3-V nominal supplies. This bias voltage source should be stabilized by using an external filter capacitor of approximately 1.0 F. The transmitter circuitry is disabled under the following conditions: power down, cable not active, reset, or transmitter disable. The receiver circuitry is disabled under the following conditions: power down, cable not active, or receiver disable. The twisted-pair bias voltage circuitry is disabled under the following conditions: power down or reset. The power-down condition occurs when the PD input is high. The cable-not-active (CNA) condition occurs when the cable connection status indicates that no cable is connected. The reset condition occurs when the RESET input terminal is low. The transmitter disable and receiver disable conditions are determined from the internal logic. The line drivers in the TSB21LV03B operate in a high-impedance current mode and are designed to work with external 110- line-termination resistor networks. One network is provided at each end of each twisted-pair cable. Each network is composed of a pair of series-connected 55- resistors. The midpoint of the pair of resistors that is directly connected to the twisted-pair A (TPA) package terminals is connected to the TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly connected to the twisted-pair B (TPB) package terminals is coupled to ground through a parallel RC network with recommended resistor and capacitor values of 5 K and 250 pF respectively. The values of the external resistors are designed to meet the draft standard specifications when connected in parallel with the internal receiver circuits and are shown in Figure 3. The driver output current, along with other internal operating currents, is set by an external resistor. This resistor is connected between the R0 and R1 terminals and has a value of 6.3 k, 0.5%. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB21LV03BI IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER SGLS108 - FEBRUARY 1999 description (continued) Four package terminals are used as inputs to set four configuration status bits in the self-identification (Self-ID) packet. These terminals are hardwired high or low as a function of the equipment design. PC0 - PC2 are the three terminals that indicate either the need for power from the cable or the ability to supply power to the cable. The fourth terminal, C/LKON, indicates whether a node is a contender for bus manager. When the C/LKON terminal is asserted, it means the node can be a contender for bus manager. When the terminal is not asserted, it means that the node is not a contender. The C bit corresponds to bit 20 in the Self-ID packet, PC0 corresponds to bit 21, PC1 corresponds to bit 22, and PC2 corresponds to bit 23 (see Table 4-29 of the IEEE 1394-1995 standard for additional details). A power-down terminal, PD, is provided to allow a power-down mode where most of the TSB21LV03B circuits are powered down to conserve energy in battery-powered applications. A cable status terminal, CNA, provides a high output when all twisted-pair cable ports are disconnected. This output is not debounced. The CNA output can be used to determine when to power the TSB21LV03B down or up. In the power-down mode all circuitry is disabled except the CNA circuitry. It should be noted that when the device is powered-down it does not act in a repeater mode. When the TSB21LV03B is powered down using the PD terminal, the twisted-pair transmitter and receiver circuitry has been designed to present a high impedance to the cable to prevent loading the TPBias terminal voltage on the other end of the cable. If the TSB21LV03B is being used with one or more of the ports not being brought out to a connector, the TPB terminals must be terminated for reliable operation. For each unused port, the TPB+ and TPB- terminals must be connected to GND. This is done in the normal termination network. When a port does not have a cable connected, the normal termination network pulls TPB+ and TPB- to ground through a 5-k resistor, thus disabling the port. NOTE: All gap counts on all nodes of a 1394 bus must be identical. This may only be accomplished by using phy configuration packets (see section 4.3.4.3 of IEEE 1394-1995 Standard) or by using two bus resets, which resets the gap counts to the maximum level (3Fh). The link power status (LPS) terminal works with the C/LKON terminal to manage the LLC power usage of the node. The LPS terminal indicates that the LLC of the node is powered down and powers down the phy-LLC interface to save power. If the phy then receives a link-on packet, the C/LKON terminal is activated to output a 6.114 MHz signal, which can be used by the LLC to power itself up. Once the LLC is powered up, the LPS signal communicates this to the TSB21LV03B, the C/LKON signal is turned off, and the phy-link interface is enabled. Two of the package terminals are used to set up various test conditions used in manufacturing. These terminals, TESTM1 and TESTM2, should be connected to VDD for normal operation. The TSB21LV03BI is characterized for operation over the full industrial temperature range of - 40_C to 85_C. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 TSB21LV03BI IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER SGLS108 - FEBRUARY 1999 functional block diagram CPS LPS ISO CNA SYSCLK LREQ CTL0 CTL1 D0 D1 D2 D3 Arbitration and Control State Machine Logic Link Interface I/O Received Data Decoder/ Retimer Bias Voltage and Current Generator R0 R1 TPBIAS1 TPBIAS2 TPBIAS3 TPA 1+ TPA1 - PC0 PC1 PC2 C/LKON TESTM1 TESTM2 Cable Port 1 TPB1 + TPB1 - TPA2 + PD Transmit Data Encoder Cable Port 2 TPA2 - TPB2 + TPB2 - RESET TPA3 + Cable Port 3 TPA3 - TPB3 + TPB3 - Crystal Oscillator, PLL System, and Clock Generator XI XO FILTER 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB21LV03BI IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER SGLS108 - FEBRUARY 1999 package outline DGND DGND ISO AGND R1 R0 PLLV DD XO XI AV DD FILTER PLLGND PLLGND AV DD RESET LPS LREQ VDD-5V DVDD DVDD PD DGND SYSCLK DGND CTL0 CTL1 D0 D1 D2 D3 AGND AGND 47 46 45 44 43 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 TSB21LV03BI 10 11 12 13 14 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 TPBIAS3 TPBIAS2 TPBIAS1 TPA1+ TPA1- TPB1+ TPB1- AGND TPA2+ TPA2- TPB2+ TPB2- TPA3+ TPA3- TPB3+ TPB3- DGND DGND DVDD DVDD TESTM2 TESTM1 CPS AV DD AV DD AGND C/LKON PC2 PC1 PC0 CNA AGND AVAILABLE OPTIONS PACKAGE TA PLASTIC QUAD FLAT PACK (PM) TSB21LV03BIPM - 40C to 85C POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 TSB21LV03BI IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER SGLS108 - FEBRUARY 1999 Terminal Functions TERMINAL NAME AGND NO. 26, 32, 41, 49, 50, 61 24, 25, 51, 55 TYPE Supply I/O -- DESCRIPTION Analog circuit ground. All AGND terminals should be tied together to the low-impedance circuit-board ground plane. External to the device, AGND should be tied to DGND and PLLGND. Analog circuit power. A combination of high frequency decoupling capacitors near each AVDD terminal is suggested, such as 0.1-F and 0.001-F capacitors. Lower frequency 10-F filtering capacitors are also recommended. AVDD terminals are separated from DVDD terminals internally from the other supply terminals to provide noise isolation. They should be tied together to a power plane on the circuit board. Each supply source should be individually filtered. Bus manager capable (input). When set as an input, C/LKON specifies in the Self-ID packet that the node is bus manager capable. The bit value programming is done by tying the terminal through a 10-k resistor to VDD (high, bus manager capable) or to GND (low, not bus manager capable). Using either the pullup or pulldown resistor allows the link-on output to override the input bit value when necessary. Link-on (output). When set as an output, C/LKON indicates the reception of a link-on message by asserting a 6.114-MHz signal. CNA CPS 31 23 CMOS CMOS O I Cable-not-active output. CNA is asserted high when none of the TSB21LV03B ports are connected to another active port. This circuit remains active during the power-down mode. Cable power status. CPS is normally connected to the cable power through a 400-k resistor. This circuit drives an internal comparator that detects the presence of cable power. This information is maintained in two internal registers and is available to the LLC by way of a register read (see the Phy-Link Interface Annex in the IEEE 1394-1995 standard). Control I/O. The CTLn terminals are bidirectional communications control signals between the TSB21LV03B and the LLC. These signals control the passage of information between the two devices. Control I/O terminals are 5-V tolerant. The CTLn terminals have an internal bushold function built-in. Data I/O. The D terminals are bidirectional and pass data between the TSB21LV03B and the LLC. Data I/O terminals are 5-V tolerant. The D terminals have an internal bushold function built-in. Digital circuit ground. The DGND terminals should be tied to the low-impedance circuit-board ground plane. External to the device, AGND should be tied to DGND and PLLGND. Digital circuit power. DVDD supplies power to the digital portion of the device. It is recommended that a combination of high-frequency decoupling capacitors be connected to DVDD (i.e., paralleled 0.1 F and 0.001 F). Lower frequency 10-F filtering capacitors can also be used. These supply terminals are separated from AVDD internally to provide noise isolation. These terminals should also be tied together to a power plane on the circuit board. Individual filtering networks for each is desired. PLL filter. FILTER is connected to a 0.1-F capacitor and then to PLLGND to complete the internal lag-lead filter. This filter is required for stable operation of the frequency multiplier PLL running off of the crystal oscillator. Link interface isolation input. ISO is normally tied high both to implement TI bus-holder isolation and for normal isolation. The TSB21LV03B does not support Annex J isolation. Link power status. LPS is connected to either the VDD supplying the LLC through a 1-k resistor or directly to a pulsed output that is active when the LLC is powered for the purpose of monitoring the LLC power status. The pulsed signal must be between 220 kHz and 5.5 MHz to be sensed as active. If LPS is inactive, the phy-LLC interface is disabled, and the TSB21LV03B performs only the basic repeater functions required for network initialization and operation. LPS is 5-V tolerant and has an internal bushold function built-in. If this terminal is tied through a resistor to a fixed state, the resistor must be 1 k or less. AVDD Supply -- C/LKON 27 CMOS I/O CTL0 CTL1 11 12 CMOS I/O D0 - D3 13, 14, 15, 16 8, 10, 17, 18, 63, 64 5, 6, 19, 20 CMOS I/O DGND Supply -- DVDD Supply -- FILTER 54 CMOS I/O ISO LPS 62 2 CMOS CMOS I I 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB21LV03BI IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER SGLS108 - FEBRUARY 1999 Terminal Functions (Continued) TERMINAL NAME LREQ NO. 3 TYPE CMOS I/O I DESCRIPTION Link request. LREQ is an input from the LLC that requests the TSB21LV03B to perform some service. LREQ is 5-V tolerant and has an internal bushold function built-in. If this terminal is tied through a resistor to a fixed state, the resistor must be 1 k or less. Power class indicators. The PC signals set the bit values of the three power-class bits in the Self-ID packet (bits 21, 22, and 23). These bits can be programmed by tying the terminals to VDD (high) or to GND (low). Power down. When asserted high, PD turns off all internal circuitry except the CNA monitor circuits that drive the CNA terminal. PD is 5-V tolerant. The PD terminal may be tied directly to VDD or to DGND. If this terminal is tied through a resistor to a fixed state, the resistor must be 1 k or less. The PD terminal has an internal bushold function built into it. PLL circuit ground. The PLLGND terminals should be tied to the low-impedance circuit-board ground plane. External to the device, AGND should be tied to DGND and PLLGND. PLL circuit power. PLLVDD supplies power to the PLL portion of the device. It is recommended that a combination of high-frequency decoupling capacitors be connected to PLLVDD (i.e., paralleled 0.1 F and 0.001 F). Lower frequency 10-F filtering capacitors can also be used. The PLLVDD supply terminals are separated from AVDD and DVDD internally in the device to provide noise isolation. The PLLVDD, AVDD, and DVDD terminals should also be tied together to a power plane on the circuit board. Individual filtering networks for each are recommended. Current setting resistor. An internal reference voltage is applied to a resistor connected between R0 and R1 to set the operating current and the cable driver output current. A low temperature-coefficient resistor (TCR) 6.3 k 0.5% resistor should be used to meet the IEEE 1394-1995 standard requirements for output voltage limits. Reset. When RESET is asserted low (active), a bus reset condition is set on the active cable ports and the the internal logic is reset to the reset start state. An internal pullup resistor, which is connected to VDD, is provided so only an external delay capacitor is required. This input is a standard logic buffer and can also be driven by an open-drain logic output buffer. The minimum hold time for RESET is listed in the recommended operating characteristics table. System clock. SYSCLK provides a 49.152-MHz clock signal, which is synchronized with the data transfers to the LLC. Test mode control. TESTM1 and TESTM2 are used during the manufacturing test and should be tied to VDD. PC2 - PC0 28, 29, 30 CMOS I PD 7 CMOS I PLLGND 52, 53 Supply -- PLLVDD 58 Supply -- R0 R1 59 60 -- -- RESET 1 CMOS I SYSCLK TESTM1 TESTM2 TPA1+ TPA2+ TPA3+ TPA1- TPA2- TPA3- TPB1+ TPB2+ TPB3+ TPB1- TPB2- TPB3- TPBIAS1 TPBIAS2 TPBIAS3 VDD-5V 9 22 21 45 40 36 44 39 35 43 38 34 42 37 33 46 47 48 4 CMOS CMOS O I Cable O Portn, port cable pair A. TPAn is the port A connection to the twisted-pair cable. Board traces from these terminals should be kept matched and as short as possible to the external load resistors and to the cable connector. Cable O Portn, port cable pair B. TPBn is the port B connection to the twisted-pair cable. Board traces from these terminals should be kept matched and as short as possible to the external load resistors and to the cable connector. Cable O Portn, twisted-pair bias. TPBIASn provides the 1.86-V nominal bias voltage needed for proper operation of the twisted-pair cable drivers and receivers and for sending a valid cable connection signal to the remote nodes. 5-V VDD supply. VDD-5V should be connected to the LLC VDD supply when a 5-V LLC is connected to the phy, and it should be connected to the phy DVDD when a 3-V LLC is used. Crystal oscillator. XO and XI connect to a 24.576-MHz parallel resonant fundamental mode crystal. Although, when a 24.576-MHz crystal oscillator is used, it can be connected to XI with XO left unconnected. The optimum values for the external shunt capacitors are dependent on the specifications of the crystal used. The suggested values of 12 pF are appropriate for a crystal with 15-pF specified loads. Supply -- XI XO 56 57 -- -- POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 TSB21LV03BI IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER SGLS108 - FEBRUARY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 4 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VDD+0.5 V Output voltage range at any output, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VDD+0.5V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40_C to 85_C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65_C to 150_C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300_C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATING TABLE PACKAGE TA 25_C POWER RATING DERATING FACTOR ABOVE TA = 25_C 14.9 mW/_C TA = 70_C POWER RATING TA = 85_C POWER RATING 972 mW PM 1866 mW 1194 mW This is the inverse of the traditional junction-to-ambient thermal resistance (RJA) and uses a board-mounted 67_C/W. recommended operating conditions MIN Supply voltage VDD voltage, High-level input voltage, VIH Low-level input voltage, VIL Differential input voltage, VID Source power node Nonsource power node CMOS inputs CMOS inputs Cable inputs, 100-Mbit operation Cable inputs, 200-Mbit operation Cable inputs, during arbitration TPB cable inputs, 100-Mbit or speed signaling off, Source power node TPB cable inputs, 100-Mbit or speed signaling off, Nonsource power node TPB cable inputs, 200-Mbit speed signaling, Source power node TPB cable inputs, 200-Mbit speed signaling, Nonsource power node Receive input jitter Receive input slew Output current, IOL/IOH current Output current, IO Hold time, power-up reset (RESET) For a node that does not source power (see Section 4.2.2.2 in IEEE 1394-1995 Standard). TPA, TPB cable inputs, 100-Mbit operation TPA, TPB cable inputs, 200-Mbit operation Between TPA and TPB cable inputs, 100-Mbit operation Between TPA and TPB cable inputs, 200-Mbit operation SYSCLK Control, Data, CNA and C/LKON outputs TPBIAS outputs - 16 - 12 -3 2 142 132 171 1.165 1.165 0.935 0.935 3.0 2.7 0.85 VDD 0.2 VDD 260 260 262 2.515 2.015 V 2.515 2.015 1.08 0.5 0.8 0.55 16 12 1.3 ns ns mA mA ms mV NOM 3.3 3 MAX 3.6 3.6 UNIT V V V Common mode input voltage VIC Common-mode voltage, 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB21LV03BI IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER SGLS108 - FEBRUARY 1999 electrical characteristics over recommended operating conditions (unless otherwise noted) driver PARAMETER VOD V(OFF) IO(diff) I(SP) Differential output voltage Off-state differential output voltage Differential current (TPA+, TPA-, TPB+, TPB-) Common-mode speed signaling current (TPB+, TPB-) TEST CONDITION 55- load Drivers disabled Driver enabled, Speed signaling off -1.05 - 2.53 MIN 172 TYP MAX 265 20 1.05 - 4.84 UNIT mV mV mA mA 200-Mbit speed signaling enabled Limits are defined as the algebraic sum of TPA+ and TPA- driver currents. Limits also apply to TPB+ and TPB- as the algebraic sum of driver currents. Limits are defined as the absolute limit of each of TPB+ and TPB- driver currents. receiver PARAMETER VIT VIT IIC ZID ZIC Input threshold voltage Cable bias-detect input threshold voltage, TPBn cable inputs Common-mode input current Differential input impedance Driver disabled Driver disabled Driver disabled 20 Common-mode Common mode impedance Driver disabled 24 pF TEST CONDITION MIN -30 0.6 -40 15 6 TYP MAX 30 1.0 40 UNIT mV V A k pF k POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 TSB21LV03BI IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER SGLS108 - FEBRUARY 1999 device PARAMETER TEST CONDITIONS VDD = 3.3 V IDD Supply current y Node transmitting or repeating Node receiving VDD = 3.6 V VDD = 3.6 V, Power-down mode VIT VOH VOL II Ioff Power status input threshold voltage (CPS) High-level output voltage Low-level output voltage Input current (TESTM1, TESTM2, PC0, PC1, PC2) Off-state output current (CTL0, CTL1, D0, D1, D2, D3, C/LKON) Pullup current (RESET) VTH+ VTH- VIT VO Positive arbitration comparator-input threshold voltage Negative arbitration comparator-input threshold voltage Speed-signal input threshold voltage Output voltage (TPBIAS1, TPBIAS2, TPBIAS3) Bus holding current (LPS, LREQ, CTLn, Dn, PD) TPBIAS -TPA common-mode voltage At rated IO current VI = 1/2 (VDD) RL = 400 k VDD = min, VDD = max, VI = VDD or 0 VO = VDD or 0 VI = 0 or 1.5 V - 110 89 - 168 49 1.665 725 - 45 IOH max IOL min 4.7 VDD- 0.55 0.5 1 5 - 10 168 - 89 131 2.015 MIN TYP 114 140 175 20 7.5 MAX UNIT mA mA mA V V V A A A mV mV mV V A thermal characteristics PARAMETER RJA Junction-to-free-air thermal resistance TEST CONDITIONS EIA/JESD51-3, No air flow MIN TYP 67 MAX UNIT _C/W RJC Junction-to-case thermal resistance 10.4 _C/W Thermal characteristics vary depending on packaging and system environment. These values represent typical die and pad sizes for this package. The RJA value was calculated using simulation models based on the Electronics Industries Association Standard EIA/JESD51-3, titled Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages. switching characteristics PARAMETER Jitter, transmit Skew rate, transmit tr tf tsu th td Rise time, transmit Fall time, transmit Setup time, Dn, CTLn, LREQ to SYSCLK Hold time, Dn, CTLn, LREQ before SYSCLK Delay time, SYSCLK to Dn, CTLn MEASURED TPA, TPB Between TPA and TPB 10% to 90% 90% to 10% 50% to 50% 50% to 50% 50% to 50% RL=55 , RL=55 , See Figure 1 See Figure 1 See Figure 2 CL=10 pF CL=10 pF 5 2 2 11 TEST CONDITIONS MIN TYP MAX 0.25 0.15 2.2 2.2 UNIT ns ns ns ns ns ns ns 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB21LV03BI IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER SGLS108 - FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION SYSCLK tsu th Dn, CTLn, LREQ 50% 50% 50% Figure 1. Dn, CTLn, LREQ Input Setup and Hold Timing Waveforms SYSCLK 50% td Dn, CTLn 50% Figure 2. Dn and CTLn Output-Delay Timing Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 TSB21LV03BI IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER SGLS108 - FEBRUARY 1999 APPLICATION INFORMATION internal register configuration The accessible internal registers of this device are listed in Table 1. Table 1. Internal Register Configuration Address 0000 0001 0010 0011 0100 0101 0110 0111 1000 LoopInt RHB SPD AStat1 AStat2 AStat3 CPSInt CPS IBR Rev BStat1 BStat2 BStat3 IR Reserved Reserved Ch1 Ch2 Ch3 Con1 Con2 Con3 Reserved 0 1 2 Physical ID GC NP Reserved Reserved Reserved C 3 4 5 6 R 7 CPS Table 2. Internal Register Field Descriptions AAA A A AAAAAAA AAA AA A AAAAAAAA AA A AAAAAAAA AA A AAAAAAAA AA AA AAAAAAAAA AAAAAAAAA AAA A AA AA AAAAAAAAA AAAAAAA AAAAAAAAA AAAAAAAA AAAAAAAAA AAAAAAAA AA AA AAA AA A AAAAAAAAA AA AAAAAAAAA AAAAAAAA AAA A A AA A AAAAAAAA AAAAAAA AAAAAAAAA AA A AA AA A AAAAAAAA AA AA AAAAAAAAA AA AAAAAAAAA AAAAAAAAA AAAAAA AStat(n) 2 Read only BStat(n) 2 Read only C 1 R Ch(n) 1 Read only Con(n) 1 Read only 12 FIELD SIZE TYPE DESCRIPTION AStat contains the line state of TPAn. The status is indicated by the following: 11 = high-impedance state 01 = 1 10 = 0 00 = Invalid data state. Power-up reset initializes to this line state. This line state is also output during transmit and receive operations, including date-end signaling. The line state outputs are generally valid during arbitration and idle conditions on the bus. BStat contains the line state of TPBn. The status is indicated by the following: 11 = high-impedance state 01 = 1 10 = 0 00 = Invalid data state. Power-up reset initializes to this line state. This line state is also output during transmit and receive operations. The line state outputs are generally valid during arbitration and idle conditions on the bus. Bus manager capable. C indicates the state of the Bus Manager Capable input. When set, this bit is used by the TSB21LV03B to specify in the Self-ID packet that the node is Bus Manager Capable. When Ch = 1, the port is a child, otherwise it is a parent. This bit is invalid after a hardware reset or a bus reset until tree-ID processing is completed. Con indicates the connection status of the port. When Con = 1, the port is connected, otherwise it is disconnected. This bit is set to 1 by a hardware reset and is updated to reflect the actual cable connection status of the port during bus reset. The TSB21LV03B contains connection debounce circuitry that prevents a new cable connection on a port from initiating a bus reset until the connection status has been stable for at least 335 ms. A cable disconnect initiates a bus reset immediately. After a hardware reset, the TSB21LV03B sets the connection status of all ports to 0. The TSB21LV03B proceeds with the bus reset, tree-ID, and Self-ID, but with all ports considered to be disconnected child ports. The TSB21LV03B can not transmit any signals on the serial bus ports during this time. The TSB21LV03B does report itself as root with a physical address of 00h at the completion of Self-ID. If any port is actually connected, after the debounce delay, the TSB21LV03B initiates another bus reset, which proceeds normally with interaction between the TSB21LV03B and its peer nodes. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB21LV03BI IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER SGLS108 - FEBRUARY 1999 APPLICATION INFORMATION Table 2. Internal Register Field Descriptions (continued) AAAAAAAA AA AA AAA A A AA AA AAAAAAA AAAAAA AAAAAAAA A AAAAAAAA AAA AAAAAAAA AAAAAAA AA AA A AAAAAAAA AAAAAAAA AA AAAAAAAA AA AA A AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AA AA AAAAAAAA AAA A AAAAAAAA AA AA AAAAAAAA AAAAAAAA AA A AA AAAAAAAA AA A AAAAAAA AA AAAAAAAA AAAAAA A AAA A A AAAAAA AAA A AA A A AAAAAAAA AAAAAAAA AA AAAAAAAA AAAAA AAAAAAAA AA AAA A A AA AAAAAAAA AAAAA CPS 1 Read only CPSInt 1 Read/ Write GC 6 Read/ Write IBR IR 1 1 Read/ Write Read/ Write Read/ Write Read only Read only Read only Read only LoopInt 1 NP 4 Physical ID 6 R 1 2 1 2 Rev RHB SPD Read/ Write Read only FIELD SIZE TYPE DESCRIPTION Cable power status (CPS) contains the status of the CPS input terminal. When cable power voltage has dropped too low for reliable operation, CPS is reset (0). CPS is included twice in the internal registers to expedite handling of the CPSInt. CPSint indicates that a cable power status interrupt has occurred. This interrupt occurs whenever the CPS input goes low. The interrupt indicates that the cable power voltage has dropped too low to ensure reliable operation. This bit is cleared (0) by a hardware reset or by writing a 0 to this register. However, if the CPS input is still low, another cable-power status interrupt immediately occurs. The gap count (GC) register sets the fair and arb-reset gap times. The gap count may be set to a particular value to optimize bus performance. Typically, the gap count should be set to 2 times the maximum number of hops on the bus and must be set to the same value for all nodes on the bus. The gap count can be set by either a write to this register or by reception or transmission of a PHY_CONFIG packet. The gap count is reset to 3Fh after a hardware reset or after two consecutive bus resets without an intervening write to the gap count register (either a write to the gap count register by the LLC or a PHY_CONFIG packet). When set, initiate bus reset (IBR) causes the current node to immediately initiate a bus reset. IBR is cleared (0) after a hardware reset or a bus reset. IR indicates that the last bus reset was initiated in this TSB21LV03B phy. This bit is also included in the Self-ID packet. LoopInt indicates that a configuration loop timeout has occurred. This interrupt occurs when the arbitration controller waits for too long a period of time during tree-ID. This interrupt can indicate that the bus is configured in a loop. This bit is cleared (0) by a hardware reset or by writing a 0 to this register bit. NP contains the number of ports implemented in the core logic (not the number of ports actually on the device). For the TSB21LV03B, NP is set to 0011b. Physical ID contains the physical address of the local node. The physical ID in valid after a hardware reset or a bus reset until the Self-ID process has been completed. A complete Self-ID is indicated by an unsolicited status transfer of the register 0 contents to the LLC. R indicates whether the current node is the root node or not. This bit is cleared (0) on a hardware reset or a bus reset. This bit is set during tree-ID when the current node is root. The revision (Rev) bits indicate the design revision of the core logic. For the TSB21LV03B, Rev is set to 00. When set, the root hold-off bit (RHB) instructs the local node to try to become the root node during the next bus reset. RHB is reset (0) during a hardware reset and is not affected by a bus reset. The speed (SPD) bits indicates the top signaling speed of the local port and for the TSB21LV03B is set to 01b. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 13 TSB21LV03BI IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER SGLS108 - FEBRUARY 1999 APPLICATION INFORMATION TSB21LV03B CPS AGND DGND PLLGND 1 F TYP + 55 TPAn+ TPAn- Cable Twisted Pair 55 - 400 k Cable Power Pair TPBIASn Cable Port TPBn+ TPBn- 55 55 Cable Twisted Pair 250 pF 5 k Figure 3. Twisted-Pair Cable Interface Connections 1 k Link Power LPS Square Wave Input (See LPS in Terminal Function Table) LPS Figure 4. Non-Isolated Connection Variations for LPS 14 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB21LV03BI IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER SGLS108 - FEBRUARY 1999 APPLICATION INFORMATION 12 pF 12 pF 6.3 k 0.5% VDD VDD 24.576 MHz 0.1 F VDD VDD 53 52 51 50 49 PLLGND PLLGND FILTER AVDD AGND AGND 64 63 62 61 60 59 DGND DGND AGND R1 ISO 58 57 PLLV DD R0 56 55 54 XO AVDD XI 1 0.1 F Link Pulse or VDD LLC Interface Link VDD VDD Power Down 2 3 4 5 6 7 8 9 10 11 12 LLC Interface 13 14 15 16 LPS LREQ VDD-5V DVDD DVDD PD DGND TSB21LV03BI SYSCLK DGND CTL0 CTL1 D0 D1 D2 TESTM2 TESTM1 C/LKON D3 DGND DGND DVDD DVDD AVDD AVDD AGND TPBIAS2 TPBIAS1 TPA1+ TPA1- TPB1+ TPB1- AGND TPA2+ TPA2- TPB2+ TPB2- TPA3+ TPA3- TPB3+ TPB3- AGND PC2 PC1 PC0 CNA 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 CPS 26 27 28 29 30 31 CNA OUT 32 400 k 10 k Cable Power Bus Manager LKON Figure 5. External Component Connections POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 Power-Class Programming VDD VDD TP CABLES 15 TP CABLES TPBIAS RESET TPBIAS3 48 TSB21LV03BI IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER SGLS108 - FEBRUARY 1999 PRINCIPLES OF OPERATION The TSB21LV03B is designed to operate with an LLC such as the TI TSB12LV21A, TSB12LV31, and TSB12C01A. These devices use an interface as described in Annex J of the IEEE 1394-1995 standard. Details of how the TSB12LV21A, TSB12LV31, and TSB12C01A LLC devices operate are described in the LLC data sheets (i.e.,TSB12LV21A, TSB12LV31, and TSB12C01A). The following paragraphs describe the operation of the phy-LLC interface. The TSB21LV03B supports 100-/200-Mbit/s data transfer and has four bidirectional data lines, D0 - D3, crossing the interface. In 100-Mbit/s operation only D0 and D1 terminals are used. In 200 Mbit/s operation, all Dn terminals are used for data transfer. The unused Dn terminals are driven low. In addition, there are two bidirectional control lines CTL0 and CTL1, the 50-MHz SYSCLK line from the phy to the LLC, and the LLC request terminal LREQ from the LLC to the phy. The TSB21LV03B has control of all bidirectional terminals. The LLC is allowed to drive these terminals only after it has been given permission by the phy. The dedicated LREQ request terminal is used by the LLC for any activity that it wishes to initiate. There are four operations that may occur in the phy-LLC interface: request, status, transmit, and receive. With the exception of the request operation, all actions are initiated by the phy. When the phy has control of the bus the CTL0 and CTL1 lines are encoded as shown in Table 3. Table 3. CTLn Status When Phy Has Control of the Bus CTL0 0 0 1 1 CTL1 0 1 0 1 STATUS NAME Idle Status Receive Transmit DESCRIPTION No activity is occurring (this is the default mode). Status information is being sent from the phy to the LLC. An incoming packet is being sent from the phy to the LLC. The LLC has been given control of the bus to send an outgoing packet. When the LLC has control of the bus (phy permission) the CTL0 and CTL1 terminals are encoded as shown in Table 4. Table 4. CTLn Status When LLC Has Control of the Bus CTL0 0 0 1 1 CTL1 0 1 0 1 STATUS NAME Idle Hold Transmit Reserved DESCRIPTION The LLC releases the bus (transmission has been completed). The LLC is holding the bus while data is being prepared for transmission or is sending another packet without arbitrating. An outgoing packet is being sent from the LLC to the phy. None Request When the LLC requests the bus or accesses a register that is located in the TSB21LV03B, a serial stream of information is sent across the LREQ line. The length of the stream varies depending on whether the transfer is a bus request, a read command, or a write command. Regardless of the type of transfer, a start bit of 1 is required at the beginning of the stream, and a stop bit of 0 is required at the end of the stream. Bit 0 is the most significant bit and is transmitted first. The LREQ terminal is required to idle low (logic level 0). 16 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB21LV03BI IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER SGLS108 - FEBRUARY 1999 PRINCIPLES OF OPERATION Table 5. LLC Bus-Request or Register-Access-Request Bit Length REQUEST TYPE Bus request Read register request Write register request NUMBER OF BITS 7 9 17 For a Bus Request the length of the LREQ data stream is 7 bits as shown in Table 6. Table 6. LLC Bus Request BIT(S) 0 1-3 4-5 6 NAME Start bit Request type Request speed Stop bit DESCRIPTION Indicates the beginning of the transfer (always 1). Indicates the type of bus request (see Table 9 for the encoding of this field). Should be 00 for TSB21LV03B 100-Mbit/s speed and 01 for 200-Mbit/s speed. Indicates the end of the transfer (always 0). For a Read Register Request the length of the LREQ data stream is 9 bits as shown in Table 7. Table 7. LLC Read Register Access BIT(S) 0 1-3 4-7 8 NAME Start bit Request type Address Stop bit DESCRIPTION Indicates the beginning of the transfer (always 1). Always a 100 indicating that this is a read register request. Identifies the address of the phy register to be read. Indicates the end of the transfer (always 0). For a Write Register Request the Length of the LREQ data stream is 17 bits as shown in Table 8. Table 8. LLC Write Register Access BIT(S) 0 1-3 4-7 8-15 16 NAME Start bit Request type Address Data Stop bit DESCRIPTION Indicates the beginning of the transfer (always 1). Always a 101 indicating that this is a write register request. Identifies the address of the phy register to be written to. Gives the data that is to be written to the specified register address. Indicates the end of the transfer (always 0). The 3-bit Request Type field has the values shown in Table 9. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 17 TSB21LV03BI IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER SGLS108 - FEBRUARY 1999 PRINCIPLES OF OPERATION Table 9. LLC Bus Request Type LREQ1 0 0 0 0 1 1 1 1 LREQ2 0 0 1 1 0 0 1 1 LREQ3 0 1 0 1 0 1 0 1 NAME ImmReq IsoReq PriReq FairReq RdReg WrReg Reserved Reserved DESCRIPTION Immediate request. Upon detection of an idle, the LLC takes control of the bus immediately (no arbitration). Isochronous request: the LLC arbitrates for the bus, no gaps. Priority request: the LLC arbitrates after a subaction gap, ignores fair protocol. Fair request: the LLC arbitrates after a subaction gap, follows fair protocol. The LLC returns the specified register contents through a status transfer. The LLC writes to the specified register. Reserved Reserved LREQ timing (each cell represents one clock sample time): LR0 LR1 LR2 LR3 LR(n-2) LR(n-1) NOTE A: Each cell represents one clock sample time. Figure 6. LREQ Timing For fair or priority access, the LLC requests control of the bus at least one clock after the phy-LLC interface becomes idle. If the LLC senses that the CTLn terminals are in a receive state (CTL0 = 1, CTL1 = 0), this indicates that its request has been lost. This is true anytime during or after the LLC sends the bus request transfer. Additionally, the phy ignores any fair or priority requests if it asserts the receive state while the LLC is requesting the bus. The LLC then reissues the request one clock after the next interface idle. The cycle master uses a normal priority request to send a cycle-start message. After receiving a cycle-start message, the LLC can issue an isochronous bus request. When arbitration is won, the LLC proceeds with the isochronous transfer of data. The isochronous request register is cleared in the phy once the LLC sends another type of request or when the isochronous transfer has been completed. The isochronous request must be issued during a packet reception. Generally this request would be during reception of a cycle-start packet. The ImmReq request is issued when the LLC needs to send an acknowledgment after reception of a packet addressed to it. This request must be issued during packet reception. This is done to minimize the delays that a phy would have to wait between the end of a packet and the transmittal of an acknowledgment. As soon as the packet ends, the phy immediately grants access of the bus to the LLC. The LLC sends an acknowledgment to the sender unless the header CRC of the packet turns out to be bad. In this case, the LLC releases the bus immediately; it is not allowed to send another type of packet on this grant. To guarantee this, the LLC is forced to wait 160 ns after the end of the packet is received. The phy then gains control of the bus and the acknowledgement with the CRC error is sent. Then the bus is released and allowed to proceed with another request. Although highly improbable, it is conceivable that two separate nodes can believe that an incoming packet is intended for them. The nodes then issue an ImmReq request before checking the CRC of the packet. Since both phys seize control of the bus at the same time, a temporary, localized collision of the bus occurs somewhere between the competing nodes. This collision would be interpreted by the other nodes on the network as being a high-impedance line state, not a bus reset. As soon as the two nodes check the CRC, the mistaken node drops its request and the false line state is removed. The only side effect would be the loss of the intended acknowledgment packet (this is handled by the higher-layer protocol). 18 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB21LV03BI IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER SGLS108 - FEBRUARY 1999 PRINCIPLES OF OPERATION Read/Write Requests When the LLC requests to read the specified register contents, the phy sends the contents of the register to the LLC through a status transfer. When an incoming packet is received while the phy is transferring status information to the LLC, the phy continues to attempt to transfer the contents of the register until it is successful. For write requests, the phy loads the data field into the appropriately addressed register as soon as the transfer has been completed. The LLC is allowed to request read or write operations at any time. Status A status transfer is initiated by the phy when it has status information to transfer to the LLC. The phy waits until the interface is idle before starting the transfer. The transfer is initiated by asserting the following on the control terminals: CTL0 - CTL1 = 01 along with the first two bits of status information on the D0 - D3 terminals. The phy maintains CTL0 - CTL1 = 01 for the duration of status transfer. The phy may prematurely end a status transfer by asserting something else other than CTL0 - CTL1 = 01 on the control terminals. This could be caused by an incoming packet from another node. The phy continues to attempt to complete the transfer until the information has been successfully transmitted. There must be at least one idle cycle in between consecutive status transfers. The phy normally sends just the first 4 bits of status to the LLC. These bits are status flags that are needed by the LLC state machines. The phy sends an entire status packet to the LLC after a request transfer that contains a read request, or when the phy has pertinent information to send to the LLC or transaction layers. The only defined condition where the phy automatically sends a register to the LLC is after Self-ID, when it sends the physical-ID register, which contains the new node address. After a power-on reset, the TSB21LV03B sends two Self-ID status transfers. The first transfer is invalid (a status of not connected); later, during the same bus reset, a second, correct Root, Node Number, and connection status Self-ID is transferred. During all other bus resets, only one SElf-ID status is transmitted. The definition of the bits in the status transfer are shown in Table 10 and the timing is shown in Figure 7. Table 10. 16-Bit Stream Status Request BIT(S) 0 NAME Arbitration reset gap DESCRIPTION Bit 0 indicates that the phy has detected that the bus has been idle for an arbitration reset gap time (this time is defined in the IEEE 1394-1995 standard). Bit 0 is used by the LLC in its busy/retry state machine. Bit 1 indicates that the phy has detected that the bus has been idle for a subaction gap time (this time is defined in the IEEE 1394-1995 standard). Bit 1 is used by the LLC to detect the completion of an isochronous cycle. Bit 2 indicates that the phy has entered the bus reset state. Bit 3 indicates that the phy stayed in a particular state for too long a period, which is usually the effect of a loop in the cable topology, or that the cable power has dropped below the threshold for reliable operation. Bits 4 - 7 hold the address of the phy register whose contents are transferred to the LLC. Bits 8 - 15 contain the data that is to be sent to the LLC. 1 Subaction gap 2 3 Bus reset State timeout or CPS 4-7 8-15 Address Data POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 19 TSB21LV03BI IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER SGLS108 - FEBRUARY 1999 PRINCIPLES OF OPERATION Phy CTL0, CTL1 00 01 01 01 00 00 Phy D0, D1 00 S[0,1] S[2,3] S[14,15] 00 00 Figure 7. Status Transfer Timing Transmit When the LLC wants to transmit information, it first requests access to the bus through the LREQ terminal. Once the phy receives this request, it arbitrates to gain control of the bus. When the phy wins ownership of the serial bus, it grants the bus to the LLC by asserting the transmit state on the CTLn terminals for at least one SYSCLK cycle, followed by idle for one clock cycle. The LLC takes control of the bus by asserting either hold or transmit on the CTLn terminals. Hold is used by the LLC to keep control of the bus when it needs some time to prepare the data for transmission. The phy keeps control of the bus for the LLC by asserting a data-on state on the bus. It is not necessary for the LLC to use hold when it is ready to transmit as soon as bus ownership is granted. When the LLC is prepared to send data, it asserts the transmit state on the CTLn terminals as well as sending the first bits of the packet on the D0 - D3 lines (assuming 200 Mbits/s). The transmit state is held on the CTLn terminals until the last bits of data have been sent. The LLC then asserts an idle state on the CTLn terminals for one clock cycle after which it releases control of the interface. However, there are times when the LLC needs to send another packet without releasing the bus. For example, the LLC may want to send consecutive isochronous packets or it may want to attach a response to an acknowledgment. To do this, the LLC asserts a hold state instead of an idle state when the first packet of data has been completely transmitted. In this case, hold informs the phy that the LLC needs to send another packet without releasing control of the bus. The phy then waits a set amount of time before asserting a transmit state. The LLC can then proceed with the transmittal of the second packet. After all data has been transmitted and the LLC has asserted an idle state on the CTLn terminals, the phy asserts its own idle state on the CTLn terminals. When sending multiple packets in this fashion, it is required that all data be transmitted at the same speed. This is required because the transmission speed is set during arbitration, and since the arbitration step is skipped, there is no way of informing the network of a change in speed. 20 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB21LV03BI IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER SGLS108 - FEBRUARY 1999 PRINCIPLES OF OPERATION Single Packet Phy CTL0, CTL1 Phy D0 - D3 LLC CTL0, CTL1 LLC D0 - D3 00 11 00 ZZ ZZ ZZ ZZ ZZ ZZ ZZ ZZ 00 0000 0000 0000 ZZZZ ZZZZ ZZZZ ZZZZ ZZZZ ZZZZ ZZZZ ZZZZ 0000 ZZ ZZ ZZ 01 01 10 10 10 10 00 00 ZZ ZZZZ ZZZZ ZZZZ 0000 0000 D0 D1 D2 Dn 0000 0000 ZZZZ Continued Packet Phy CTL0, CTL1 Phy D0 - D3 LLC CTL0, CTL1 LLC D0 - D3 ZZ ZZ ZZ ZZ 00 00 11 00 ZZ ZZ ZZ ZZ ZZZZ ZZZZ ZZZZ ZZZZ 0000 0000 0000 0000 ZZZZ ZZZZ ZZZZ ZZZZ 10 10 01 00 ZZ ZZ ZZ ZZ 01 01 10 10 Dn-1 Dn 0000 0000 ZZZZ ZZZZ ZZZZ ZZZZ 0000 0000 D0 D1 NOTE A: ZZ = High-impedance state D0 => Dn = Packet data Figure 8. Transmit Timing Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 21 TSB21LV03BI IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER SGLS108 - FEBRUARY 1999 PRINCIPLES OF OPERATION Receive When data is received by the phy from the serial bus, the phy transfers the data to the LLC for further processing. The phy asserts a receive state on the CTLn terminals and asserts a 1 on each Dn terminal. The phy indicates the start of the packet by placing the speed code on the data bus. The phy then proceeds with the transmittal of the packet to the LLC on the Dn terminals while still keeping the receive status on the CTLn terminals. Once the packet has been completely transferred, the phy asserts an idle state on the CTLn terminals, completing the receive operation. NOTE: The speed is a phy-LLC protocol and not included in the CRC. Phy CTL0, CTL1 Phy D0 - D3 00 10 10 10 10 10 10 00 00 0000 1111 1111 SPD D0 D1 Dn 0000 0000 NOTE A: SPD = Speed Code D0 => Dn = Packet data Figure 9. Receive Timing Waveforms Table 11. Speed Code for the Receiver D0 - D3 00YY 0100 Data Rate 100 Mbit/s 200 Mbit/s Y = Transmitted as 0, ignored on receive. Power Class Bits in Self-ID Packet Table 12 describes the meaning of the power-class bits in the pwr field of the Self-ID packet. Bit 21 is transmitted first, followed by bit 22 and then bit 23. This power-field bit description complies with the IEEE 1394-1995 standard. Table 12. Self-ID Packet Pwr-Field Bit Description PC [21:23] 000 001 010 011 100 101 110 111 DESCRIPTION Node does not need power and does not repeat power. Node is self powered, and provides a minimum of 15 W to the bus. Node is self powered, and provides a minimum of 30 W to the bus. Node is self powered, and provides a minimum of 45 W to the bus. Node may be powered from the bus, and is using up to 1 W. Node may be powered from the bus, and is using up to 1 W. An additional 2 W is needed to enable the LLC and higher layers. Node may be powered from the bus, and is using up to 1 W. An additional 5 W is needed to enable the LLC and higher layers. Node may be powered from the bus, and is using up to 1 W. An additional 9 W is needed to enable the LLC and higher layers. 22 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TSB21LV03BI IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER SGLS108 - FEBRUARY 1999 gap times The gap times in the TSB21LV03B are set to: subaction-gap = ((gap_count*16) + state_machine_delay) *BASE_RATE_PERIOD arb-reset-gap = ((gap_count*32) + state_machine_delay) *BASE_RATE_PERIOD where the BASE_RATE_PERIOD is approximately 10.2 ns, and the state_machine_delay is approximately (8*BASE_RATE_PERIOD). All PHYs have a hysteresis time (arb delay time) built in, which is set to: delay-time = ((gap_count*4) + state_machine_delay) *BASE_RATE_PERIOD After a subaction-gap or arb-reset-gap has been detected, the PHY sends the appropriate status to the link. It then waits for the delay-time period before servicing any bus-requests made by the link. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 23 TSB21LV03BI IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER SGLS108 - FEBRUARY 1999 MECHANICAL INFORMATION PM (S-PQFP-G64) 0,27 0,17 48 33 PLASTIC QUAD FLATPACK 0,50 0,08 M 49 32 64 17 0,13 NOM 1 7,50 TYP 10,20 SQ 9,80 12,20 SQ 11,80 1,45 1,35 16 Gage Plane 0,25 0,05 MIN 0- 7 0,75 0,45 Seating Plane 1,60 MAX 0,08 4040152 / C 11/96 NOTES: B. C. D. E. All linear dimensions are in millimeters. This drawing is subject to change without notice. Falls within JEDEC MS-026 May also be thermally enhanced plastic with leads connected to the die pads. 24 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 1999, Texas Instruments Incorporated |
Price & Availability of SGLS108
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |