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MPT57481 240-CHANNEL 61-BIT SOURCE DRIVER FOR COLOR TFT LCDS
SGLS099 - MARCH 1997
D D D D D
436 Terminal 70-mm Tab Assembly Selection Of Start Driver Input From Right Or Left By L/R Function CMOS Technology 6-Bit x 3 RGB Color Data Inputs 64-Gray-Scale Sub-Pixel Outputs Generated By 6-Bit DAC
D D D D D
55-MHz Operation Gamma Correction RGB Voltage Adjust Automatic Low-Power Standby Function 5-V Digital and Analog Voltage Supply
description
The MPT57481 is a 240-channel output, low-power, 5-V, signal source (column) driver for an active matrix LCD panel. This device has a digital-to-analog converter for each output. The MPT57481 utilizes 10 reference voltages for a 64 gray-scale subpixel output. Eight drivers are required for a 640 x 480 color LCD and ten drivers are required for a 800 x 600 color LCD.
OUT240
OUT230
OUT11
MPT57481
D05 GMA2
GMA9
GMA1
GMA8 WB0
L/R D20
D25 TP1 TP2 EIO2 V DD2
D10
D15 D00
OUT1 WB2 VOP V DD1 V SS1
VOP WB1
V SS1 V SS1
V DD1
V DD1
CLK V SS2
EIO1
NOTES: A. This figure shows the copper foil side. This figure doesn't describe the TAB outline. B. There are 46 input terminals and 240 output terminals.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1997, Texas Instruments Incorporated
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V DD1
1
MPT57481 240-CHANNEL 61-BIT SOURCE DRIVER FOR COLOR TFT LCDS
SGLS099 - MARCH 1997
functional block diagram
OUT1 OUT2 OUT3 OUT239 OUT240
Output-Voltage Drivers (240 Channels)
GMA1 - GMA9 WB0, WB1, WB2 VOP
9 3 2 5 6 6 6 6 6 Digital-To-Analog Converter
TP1 TP2
Line Selection Output Voltage Selection
Storage Register For Line n-1 (240 x 6 Bit) Input Register For Line n (240 x 6 Bit)
6 D00 - DO5 D10 - D15 D20 - D25 6 6 6 Latch 6 6 6
6
6
6
6
6
6
6
6
1 EIO1 EIO2
2 Address Shift Register (80 Bit)
80
L/R
CLK
2
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MPT57481 240-CHANNEL 61-BIT SOURCE DRIVER FOR COLOR TFT LCDS
SGLS099 - MARCH 1997
detailed description
acquisition of line data Acquisition of line data begins when a start pulse is applied to the EIO1 or EIO2 input terminal and is complete when all 240 channels of the Input Register have been loaded with new RGB data. When the first clock pulse, CLK0, is applied while the EIO terminal is biased high by the start pulse, an enable pulse enters the Shift Register and RGB data enters the Data Latch on the clock's rising edge. The enable pulse, after entering the Shift Register, positions itself to address the Input Register for loading of RGB data from the Data Latch on the rising edge of succeeding clock pulses after CLK0. With each succeeding clock pulse, CLK (1 - 80), the Input Register is repeatedly addressed by the Shift Register and updated with new RGB data. One of 80 parallel outputs of the Shift Register addresses the Input Register with each transition of the clock pulse. Each output addresses three separate but adjacent channels of the Input Register simultaneously in a ascending or descending order between channels (1..240) as the enable pulse advances to the right or left from one output to the next. Channels (3n-2, 3n-1, and 3n ) are addressed on the rising edge of CLKn by each output where `n' is the number of clock pulse and addressing output. While channels (3n-2, 3n-1, and 3n) are being addressed by the Shift Register outputs, 18-bit (6 bit x 3) RGB data stored in the Data Latch is loaded into the channels that are enabled. RGB data, originating at three 6-bit data input terminals, D05..D00, D15..D10, and D25..D20, is routed through the 18-bit Data Latch to the input of channels (3n-2, 3n-1, and 3n), respectively. New RGB data can be entered at the data input terminals and routed to the Input Register with each transition of the clock pulse from 1 to 80. After CLK(80), all 240 channels of the Input Register are addressed and loaded completing the acquisition of RGB line data.
cascading drivers If the pixels of a LCD display are greater than what one MPT57481 can drive, additional drivers can be cascaded together to extend the RGB line data by connecting the EIO output terminals of one driver to the EIO input terminals of the next driver. Between the rising edges of clock pulse, CLK( d80-1 and d80: d = number of driver), the enable pulse exits the Shift Register of one driver at the EIO output terminal and enters at the EIO input terminal of the next driver. When the enable pulse exits a driver, the driver enters a low-power standby mode while the next driver is set up to receive new RGB input data. The driver in standby mode goes back into normal mode when the next enable start pulse enters at its EIO input terminal. transfer of line data RGB line data is transferred from the Input Register to subpixel outputs, OUT (1..240) by a sequence of transitions of the TP1 and TP2 inputs. TP1 and TP2 are biased high while data is being acquired. After line data is acquired, data is transferred to the Storage Register and enters each DAC on the rising edge of the last clock pulse, CLK(d80+1; d = number of last driver) after TP1 transitions to low while TP2 remains high. Transfer of data beyond the Storage Register is independent of the clock. When TP1 or TP2 are low, each DAC is disabled from the subpixel outputs while the panel is precharged by VDD1 using the outputs. During the precharging period, line data from the Storage Register, already inside each DAC, is converted to analog voltages during the second and third sequence when TP2 transitions to low with TP1 remaining low, and then when TP1 transitions back to high with TP2 remaining low. After TP1 goes high, line data, now represented as analog voltages, transfers to the output of each DAC. The last sequence, when TP2 goes back to high while TP1 remains high, the precharging period ends and all of the DACs are enabled allowing the analog voltages to transfer to the subpixel outputs. 64 gray scale subpixel outputs All 240 outputs of the MPT57481 are driven by separate 6-bit DACs. The output voltage of each DAC, 64 gray scale, is determined by the reference voltages GMA(0..9) and WB(0,1, or 2) selected by a 6-bit data input and by the VOP bias voltage. GMA (0..9) gamma correction voltages, WB(0..2) RGB Shift voltages , and VOP
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MPT57481 240-CHANNEL 61-BIT SOURCE DRIVER FOR COLOR TFT LCDS
SGLS099 - MARCH 1997
bias voltage can be adjusted to tailor the pixel output voltages needed for the particular LCD panel. GMA and VOP voltages affect all outputs, while WB0, WB1, and WB2 voltages affect only the 3n-2, 3n-1, or 3n outputs, respectively. calculation of subpixel output voltage Theoretical calculation of analog voltage with no process deviations assumed. VO
+ (m ) 1)
VA(n
) 1) ) (7 * m)
8
VA(n) m: Upper 3 bits of 6-bit data n: Lower 3 bits of 6-bit data
(1)
VAd
+ VOP ) 8 VOP * GMA(d ) 1) ) VOP7* Vk 7
(2) Vk:WB0, WB1, and WB2 d=0-8
graphical representation of output voltage Calculation of analog voltage is shown graphically in Figure 1. The graph represents the output voltage verse 6-bit data input.
(VA1 + VA0 x 7)/8 VA0 VA1 VA2 Output Voltage VA3 VA4
VA5 VA6 VA7 VA8 01 7 F 17 1F 27 2F 37 3E 3F
6 -Bit Data Input
Figure 1. Output Voltage Verse 6-Bit Data Input
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MPT57481 240-CHANNEL 61-BIT SOURCE DRIVER FOR COLOR TFT LCDS
SGLS099 - MARCH 1997
timing diagram terminal functions
0 CLK 1 2 3 64 0 1 64 0 1 2
EIOn
Driver 1 D0 - D25 Driver 2 D0 - D25 Driver 5 D0 - D25
1
2
3
62
63
64
1
2
Standby Mode
65
Standby Mode
320
Standby Mode
TP1
TP2
Storage Register
Line n-1
Line n
OUT 1 - 240
Line n-1
Precharge
Line n
Figure 2.
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MPT57481 240-CHANNEL 61-BIT SOURCE DRIVER FOR COLOR TFT LCDS
SGLS099 - MARCH 1997
Terminal Functions
TERMINAL NAME CLK NO. I/O I DESCRIPTION Shift Clock. CLK synchronizes internal control logic with its rising edge. Also, CLK generates a data clock for the Data Latch, a shift clock for the Address Shift Register, and a write enable for the Storage Register. Data Input. Data inputs consist of 6-bit words for each of three channels (18 bits) for color input data. D00-D05 D10-D15 D20-D25 I
D D D
D05..D00 (MSB to LSB) selects one of 64 gray-scale voltages on OUT (3n-2) with n = 1 - 80. D15..D10 selects one of 64 gray-scale voltages on OUT (3n-1) with n = 1 - 80. D25..D20 selects one of 64 gray-scale voltage on OUT (3n ) with n = 1 - 80.
EIO1 EIO2
Enable I/O. EIO enables the Data Latch and Input Register to load 18-bit RGB data into the input Register on the rising edge of the clocks. The cascade output is for adding additional drivers to extend the length of line data. This helps to accommodate any particular LCD panel being driven. I/O EIO1 EIO2 L/R = is asserted Right-shift input Right-shift output L/R is deasserted Left-shift output Left-shift input
GMA1...GMA9 L/R OUT1-OUT240
I I O
Analog circuit bias voltage. GMA supplies the bias voltage to the DAC and the gamma correction voltage adjust reference voltage. Shift Direction. L/R controls the direction in which the data is loaded into the input register. The data is loaded from OUT1 to OUT240 when L/R is asserted and from OUT240 to OUT1 when L/R is deasserted. Subpixel output. Out provides 64 gray-scale signals to the LCD panel. Transfer input register contents. The next CLK rising edge after TP1 is deasserted causes the contents of the input register (line n-1) to be transferred to the storage register (line n). After the transfer, the input register receives new line n-1 data from the data inputs. During the period that either TP1, TP2, or both are deasserted, pixel-driver output is in a precharge mode that supplies voltage to all the OUT terminals (LCD pixel drivers) Analog supply voltage. The four VDD1 terminals supply power for the analog circuitry. Power supply for digital circuitry. Bias voltage. VOP supplies the bias voltage for each DAC. Analog circuit ground. Digital circuit ground. Reference voltages. WB0, WB1, WB2 are reference voltages for each third DAC and RGB shift voltage adjust.
TP1, TP2
I
VDD1 VDD2 VOP VSS1 VSS2
I I I I I
WB0, WB1, WB2
I
D D D
WBO adjusts OUT (3 n - 2) outputs with (n = 1 - 80) WB1 adjusts OUT (3 n - 1) outputs with (n = 1 - 80) WB2 adjusts OUT (3 n) outputs with (n = 1 - 80)
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MPT57481 240-CHANNEL 61-BIT SOURCE DRIVER FOR COLOR TFT LCDS
SGLS099 - MARCH 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VDD (VDD1, VDD2) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to +7 V Input voltage, VI (GMA1 - GMA9, VOP, WB0-WB2) . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VDD1+ 0.3 V Input voltage, VI (all other terminals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VDD2+ 0.3 V Output voltage, VO (EIO1, EIO2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VDD2+ 0.3 V Output voltage, VO (OUT1 - OUT240) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VDD2+ 0.3 V Operating temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 125C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN Supply voltage, VDD, (VDD1,VDD2) (See Note 2) DAC bias supply voltage (VOP) DAC reference voltage (GMA1 - GMA9) DAC reference voltage (WB0...WB2) Clock frequency, fclk Load capacitance for pixel outputs, CL Operating Free-air Temperature, TA - 55 4.5 VDD1/2-0.2 0 0 NOM 5 VDD1/2 MAX 5.5 VDD1/2-0.2 VDD1 VDD 55 150 125 UNIT V V V MHz pF C
2. VDD1 and VDD2 are connected directly together. VSS1 and VSS2 are connected directly together. Power on sequence : VDD1 VDD2 GMA1...GMA9 input voltage.
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MPT57481 240-CHANNEL 61-BIT SOURCE DRIVER FOR COLOR TFT LCDS
SGLS099 - MARCH 1997
electrical characteristics over recommended operating conditions (unless otherwise noted), VDD1, VDD2 = 5 V (see Note 3)
PARAMETER VIH High level in ut voltage input Dx0 - Dx5, CLK, TP1, TP2, EIO1, EIO2 L/R VIL IIK IO(1) IO(2) IO(3) VO VO Subpixel output error (see Note 4) Subpixel output voltage range (see Note 5) OUT1 - 240 OUT1 - 240 VDD1 Hsync = 30 s, Hsync = 30 s, No load See Note 6 VSS1 + 0.2 9 5 mA Output current OUT1 - 240 Low level in ut voltage input Dx0 - Dx5, CLK, TP1, TP2, EIO1, EIO2 L/R Input leakage current Dx0 - Dx5, CLK, TP1, TP2, EIO1, EIO2, L/R TP1, TP2 = 0 V, TP1, TP2 = 5 V, Dx5 - Dx0 = 00h TP1, TP2 = 5 V, Dx5 - Dx0 = 63h VO = 4 V VO = 4 V, VO = 4 V, -10 -1.5 -10 0.8 30 VDD1- 0.2 mV V mA TEST CONDITIONS MIN 2.2 0.7 VDD2 0.8 0.3 VDD2 10 A V TYP MAX UNIT V
IDD
Supply current
VDD2 Hsync = 30 s, No load 5 All typical values are at VDD1, VDD2 = 5 V and TA = 25C. NOTES: 3. For this table, the following are true: GMA1 - GMA9 = 0.5 V to 4.5 V in increments of 0.5 V, VOP = 2.5 V and WB0 - WB2 = 2.5 V. 4. VO is the difference between the highest and the lowest reading across OUT1 - OUT240. 5. This is the range of output voltage between 6-bit input data 00h and 63h. 6. The load consists of a 75-pF capacitor connected from the output to VSS and in parallel with a series combination of a 75-pF capacitor and a 2-k resistor.
8
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MPT57481 240-CHANNEL 61-BIT SOURCE DRIVER FOR COLOR TFT LCDS
SGLS099 - MARCH 1997
timing requirements over recommended operating free-air temperature range, VDD1, VDD2 = 5 V, See Note 7
PARAMETER tc1 tw1 tw2 tsu1 th1 tsu2 th2 tsu3 t(pc) th3 tsu4 th4 tsu5 tdis1 t(last) tsu6 th5 Clock cycle time High-level pulse width duration Low-level pulse width duration Data setup time Data hold time Start pulse setup time Start pulse hold time Enable propagation setup time Precharge time TP1 hold time (with respect to TP2) TP1 setup time (with respect to TP2) TP2 hold time (with respect to TP1) TP1 shift input setup time Data input disable time Last data timing TP1 setup time (with respect to CLK) TP1, CLK hold time (with respect to CLK) TEST CONDITIONS See Figure 3 See Figure 3 See Figure 3 See Figure 3, Figure 4, and Figure 5 See Figure 3, Figure 4, and Figure 5 See Figure 3 and Figure 4 See Figure 3 and Figure 4 See Figure 3 See Figure 3 See Figure 3 See Figure 3 See Figure 3 See Figure 3 See Figure 4 See Figure 5 See Figure 5 See Figure 5 MIN 18 5 5 5 5 5 5 80 3 1 1 0.5 1 1 1 7 7 TYP MAX UNIT ns ns ns ns ns ns ns CLK s s s s CLK CLK CLK ns ns
NOTE 7: All VIH and VIL input voltage levels are 5 V and 0 V, respectively.
switching characteristics over recommended operating free-air temperature range, VDD1, VDD2 = 5 V, See Figure 3 and Note 7
PARAMETER td1 td2 td3 td4 Enable propagation delay time Enable propagation delay time Output propagation delay time Output propagation delay time CL = 35 pF CL = 35 pF CL1. CL2= 75 pF, See Note 6 CL1. CL2= 75 pF, See Note 6 RL = 2 k, RL = 2 k, TEST CONDITIONS MIN TYP MAX 11 15 3 10 UNIT ns ns ns ns
NOTES: 6. The load consists of a 75-pF capacitor connected from the output to VSS and in parallel with a series combination of a 75-pF capacitor and a 2-k resistor. 7. All VIH and VIL input voltage levels are 5 V and 0 V, respectively.
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MPT57481 240-CHANNEL 61-BIT SOURCE DRIVER FOR COLOR TFT LCDS
SGLS099 - MARCH 1997
PARAMETER MEASUREMENT INFORMATION
tw1 tc1 CLK LAST tsu1 Dxx th2 td2 tw2 FIRST th1 LAST-1 td1 LAST
tsu2 INPUT (See Note A)
tsu3 OUTPUT (See Note A) tsu5
t(pc) th4 TP1 th3 TP2
tsu4 td4
td3
OUT1 - 240 Precharge Period NOTES: A. EIO1 (L/R is asserted), EIO2 (L/R is asserted) B. The input pulse is supplied by a generator having the following characteristics: PRR < 1 MHz, duty cycle < 50%, tr, tf 15 ns, zO = 50 . C. The trip point for td3 is output voltage + 0.5 V. The trip point for td4 is output voltage 100 mV.
Figure 3. Input, Output, and Precharge Period Timing Waveforms
10
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MPT57481 240-CHANNEL 61-BIT SOURCE DRIVER FOR COLOR TFT LCDS
SGLS099 - MARCH 1997
PARAMETER MEASUREMENT INFORMATION
tdis1 CLK
tsu2 EIO1/EIO2 Input
th2
th1 tsu1
Dxx
Invalid
Valid
Valid
Valid
NOTE A. The input pulse is supplied by a generator having the following characteristics: PRR < 1 MHz, duty cycle < 50%, tr, tf 15 ns, zO = 50 .
Figure 4. EIO1/EIO2 Input and Data Valid Timing Waveforms
t(last) CLK
tsu6 th5 TP1 th1 tsu1 Dxx Valid Valid Valid Valid Invalid
NOTE A. The input pulse is supplied by a generator having the following characteristics: PRR < 1 MHz, duty cycle < 50%, tr, tf 15 ns, zO = 50 .
Figure 5. TP1 and Data Valid Timing Waveforms
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MPT57481 240-CHANNEL 61-BIT SOURCE DRIVER FOR COLOR TFT LCDS
SGLS099 - MARCH 1997
APPLICATION INFORMATION
R G B D00 - D05 D10 - D15 D20 - D25 OUT1 OUT2 OUT3 OUT4 OUT5 MPT57481 Right Shift (L/R is asserted)
R R R R
B B B B
G G G G
R R R R
B B B B
G G G G
R R R R
B B B B
G G G G
R R R R
R
B
G
R
B
G
R
B
G
R
OUT240 G R B D00 - D05 D10 - D15 D20 - D25
OUT239
OUT238
OUT237
OUT236
MPT57481
Right Shift (L/R is asserted)
Figure 6. MPT57481 Connections to a Strip-Type Color-Filter Panel
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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 1998, Texas Instruments Incorporated

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