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| SN54ABT18245 SCAN TEST DEVICE WITH 18-BIT BUS TRANSCEIVERS SGBS307A - AUGUST 1994 - REVISED JANUARY 1995 * * * * * * Member of the Texas Instruments SCOPE TM Family of Testability Products Member of the Texas Instruments Widebus TM Family Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture SCOPE TM Instruction Set - IEEE Standard 1149.1-1990 Required Instructions, CLAMP and HIGHZ - Parallel-Signature Analysis at Inputs - Pseudo-Random Pattern Generation From Outputs - Sample Inputs/Toggle Outputs - Binary Count From Outputs - Device Identification - Even-Parity Opcodes State-of-the-Art EPIC-BTM BiCMOS Design Significantly Reduces Power Dissipation Packaged in 380-mil Fine-Pitch Ceramic Flat Packages Using 25-mil Center-to-Center Spacings SN54ABT18245 . . . WD PACKAGE (TOP VIEW) description The SN54ABT18245 scan test device with 18-bit bus transceivers is a member of the Texas Instruments SCOPETM testability integrated circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface. 1DIR 1B1 1B2 GND 1B3 1B4 VCC 1B5 1B6 1B7 GND 1B8 1B9 2B1 2B2 2B3 2B4 GND 2B5 2B6 2B7 VCC 2B8 2B9 GND 2DIR TDO TMS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1OE 1A1 1A2 GND 1A3 1A4 VCC 1A5 1A6 1A7 GND 1A8 1A9 2A1 2A2 2A3 2A4 GND 2A5 2A6 2A7 VCC 2A8 2A9 GND 2OE TDI TCK In the normal mode, this device contains 18-bit noninverting bus transceivers. It can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPETM bus transceivers. Data flow is controlled by the direction-control (DIR) and output-enable (OE) inputs. Data transmission is allowed from the A bus to the B bus or from the B bus to the A bus depending upon the logic level at DIR. The output-enable (OE) can be used to disable the device so that the buses are effectively isolated. In the test mode, the normal operation of the SCOPETM bus transceivers is inhibited and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990. SCOPE, Widebus, and EPIC-B are trademarks of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1995, Texas Instruments Incorporated POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SN54ABT18245 SCAN TEST DEVICE WITH 18-BIT BUS TRANSCEIVERS SGBS307A - AUGUST 1994 - REVISED JANUARY 1995 description (continued) Four dedicated test pins observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface. The SN54ABT18245 is characterized for operation over the full military temperature range of - 55C to 125C. FUNCTION TABLE (normal mode, each 9-bit section) INPUTS OE L L H DIR L H X OPERATION B data to A bus A data to B bus Isolation 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ABT18245 SCAN TEST DEVICE WITH 18-BIT BUS TRANSCEIVERS SGBS307A - AUGUST 1994 - REVISED JANUARY 1995 functional block diagram Boundary-Scan Register 1DIR 1 1OE 56 1A1 55 2 1B1 One of Nine Channels 2DIR 26 2OE 31 2A1 43 14 2B1 One of Nine Channels Bypass Register Boundary-Control Register Identification Register VCC TDI 30 VCC TMS 28 TAP Controller Instruction Register 27 TDO TCK 29 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SN54ABT18245 SCAN TEST DEVICE WITH 18-BIT BUS TRANSCEIVERS SGBS307A - AUGUST 1994 - REVISED JANUARY 1995 Terminal Functions TERMINAL NAME GND TCK TDI TDO TMS VCC 1A1-1A9, 2A1- 2A9 1B1-1B9, 2B1- 2B9 1DIR, 2DIR 1OE, 2OE Ground Test clock. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the device are synchronous to TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK. Test data input. One of four terminals required by IEEE Standard 1149.1-1990. TDI is the serial input for shifting data through the instruction register or selected data register. An internal pullup forces TDI to a high level if left unconnected. Test data output. One of four terminals required by IEEE Standard 1149.1-1990. TDO is the serial output for shifting data through the instruction register or selected data register. Test mode select. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the device through its TAP controller states. An internal pullup forces TMS to a high level if left unconnected. Supply voltage Normal-function A-bus I/O ports. See function table for normal-mode logic. Normal-function B-bus I/O ports. See function table for normal-mode logic. Normal-function direction controls. See function table for normal-mode logic. Normal-function output enables. See function table for normal-mode logic. DESCRIPTION 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ABT18245 SCAN TEST DEVICE WITH 18-BIT BUS TRANSCEIVERS SGBS307A - AUGUST 1994 - REVISED JANUARY 1995 test architecture Serial-test information is conveyed by means of a 4-wire test bus or TAP that conforms to IEEE Standard 1149.1-1990. Test instructions, test data, and test control signals all are passed along this serial-test bus. The TAP controller monitors two signals from the test bus, namely TCK and TMS. The TAP controller extracts the synchronization (TCK) and state control (TMS) signals from the test bus and generates the appropriate on-chip control signals for the test structures in the device. Figure 1 shows the TAP-controller state diagram. The TAP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK and output data changes on the falling edge of TCK. This scheme ensures that data to be captured is valid for fully one-half of the TCK cycle. The functional block diagram illustrates the IEEE Standard 1149.1-1990 4-wire test bus and boundary-scan architecture and the relationship among the test bus, the TAP controller, and the test registers. As illustrated, the device contains an 8-bit instruction register and four test-data registers: a 44-bit boundary-scan register, a 3-bit boundary-control register, a 1-bit bypass register, and a 32-bit device-identification register. Test-Logic-Reset TMS = H TMS = L TMS = H Run-Test /Idle TMS = L Select-DR-Scan TMS = L TMS = H Capture-DR TMS = L Shift-DR TMS = L TMS = H TMS = H Exit1-DR TMS = L Pause-DR TMS = L TMS = H TMS = L Exit2-DR TMS = H Update-DR TMS = H TMS = L TMS = L Exit2-IR TMS = H Update-IR TMS = H TMS = L TMS = H Exit1-IR TMS = L Pause-IR TMS = L TMS = H TMS = H TMS = H Capture-IR TMS = L Shift-IR TMS = L TMS = H Select-IR-Scan TMS = L TMS = H Figure 1. TAP-Controller State Diagram POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SN54ABT18245 SCAN TEST DEVICE WITH 18-BIT BUS TRANSCEIVERS SGBS307A - AUGUST 1994 - REVISED JANUARY 1995 state diagram description The TAP controller is a synchronous finite state machine that provides test control signals throughout the device. The state diagram is illustrated in Figure 1 and is in accordance with IEEE Standard 1149.1-1990. The TAP controller proceeds through its states based on the level of TMS at the rising edge of TCK. As illustrated, the TAP controller consists of 16 states. There are six stable states (indicated by a looping arrow in the state diagram) and ten unstable states. A stable state is a state the TAP controller can retain for consecutive TCK cycles. Any state that does not meet this criterion is an unstable state. There are two main paths through the state diagram: one to access and control the selected data register and one to access and control the instruction register. Only one register can be accessed at a time. Test-Logic-Reset The device powers up in the Test-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset and is disabled so that the normal logic function of the device is performed. The instruction register is reset to an opcode that selects the optional IDCODE instruction, if supported, or the BYPASS instruction. Certain data registers also can be reset to their power-up values. The state machine is constructed such that the TAP controller returns to the Test-Logic-Reset state in no more than five TCK cycles if TMS is left high. The TMS pin has an internal pullup resistor that forces it high if left unconnected or if a board defect causes it to be open circuited. For the ABT18245, the instruction register is reset to the binary value 10000001, which selects the IDCODE instruction. Bits 43 - 40 in the boundary-scan register are reset to logic 0, ensuring that these cells, which control A-port and B-port outputs, are set to benign values (i.e., if test mode were invoked, the outputs would be at the high-impedance state). Reset values of other bits in the boundary-scan register should be considered indeterminate. The boundary-control register is reset to the binary value 010, which selects the PSA test operation. Run-Test /Idle The TAP controller must pass through the Run-Test/Idle state (from Test-Logic-Reset) before executing any test operations. The Run-Test/Idle state also can be entered following data-register or instruction-register scans. Run-Test/Idle is a stable state in which the test logic can be actively running a test or can be idle. The test operations selected by the boundary-control register are performed while the TAP controller is in the Run-Test/Idle state. Select-DR-Scan, Select-lR-Scan No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the TAP controller exits either of these states on the next TCK cycle. These states allow the selection of either data-register scan or instruction-register scan. Capture-DR When a data-register scan is selected, the TAP controller must pass through the Capture-DR state. In the Capture-DR state, the selected data register can capture a data value as specified by the current instruction. Such capture operations occur on the rising edge of TCK upon which the TAP controller exits the Capture-DR state. 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ABT18245 SCAN TEST DEVICE WITH 18-BIT BUS TRANSCEIVERS SGBS307A - AUGUST 1994 - REVISED JANUARY 1995 Shift-DR Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO, and on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO is enabled to the logic level present in the least significant bit of the selected data register. While in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during the TCK cycle in which the TAP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR). The last shift occurs on the rising edge of TCK upon which the TAP controller exits the Shift-DR state. Exit1-DR, Exit2-DR The Exit1-DR and Exit2-DR states are temporary states that end a data-register scan. It is possible to return to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register. On the first falling edge of TCK after entry to Exit1-DR, TDO goes from the active state to the high-impedance state. Pause-DR No specific function is performed in the stable Pause-DR state, in which the TAP controller can remain indefinitely. The Pause-DR state suspends and resumes data-register scan operations without loss of data. Update-DR If the current instruction calls for the selected data register to be updated with current data, such update occurs on the falling edge of TCK following entry to the Update-DR state. Capture-IR When an instruction-register scan is selected, the TAP controller must pass through the Capture-IR state. In the Capture-IR state, the instruction register captures its current status value. This capture operation occurs on the rising edge of TCK upon which the TAP controller exits the Capture-IR state. For the ABT18245, the status value loaded in the Capture-IR state is the fixed binary value 10000001. Shift-IR Upon entry to the Shift-IR state, the instruction register is placed in the scan path between TDI and TDO, and on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO is enabled to the logic level present in the least significant bit of the instruction register. While in the stable Shift-IR state, instruction data is serially shifted through the instruction register on each TCK cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-IR state (i.e., no shifting occurs during the TCK cycle in which the TAP controller changes from Capture-IR to Shift-IR or from Exit2-IR to Shift-IR). The last shift occurs on the rising edge of TCK upon which the TAP controller exits the Shift-IR state. Exit1-IR, Exit2-IR The Exit1-IR and Exit2-IR states are temporary states that end an instruction-register scan. It is possible to return to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register. On the first falling edge of TCK after entry to Exit1-IR, TDO goes from the active state to the high-impedance state. Pause-IR No specific function is performed in the stable Pause-IR state, in which the TAP controller can remain indefinitely. The Pause-IR state suspends and resumes instruction register scan operations without loss of data. Update-IR The current instruction is updated and takes effect on the falling edge of TCK following entry to the Update-IR state. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 SN54ABT18245 SCAN TEST DEVICE WITH 18-BIT BUS TRANSCEIVERS SGBS307A - AUGUST 1994 - REVISED JANUARY 1995 register overview With the exception of the bypass and device-identification registers, any test register can be thought of as a serial-shift register with a shadow latch on each bit. The bypass and device-identification registers differ in that they contain only a shift register. During the appropriate capture state (Capture-IR for instruction register, Capture-DR for data registers), the shift register can be parallel loaded from a source specified by the current instruction. During the appropriate shift state (Shift-IR or Shift-DR), the contents of the shift register are shifted out from TDO while new contents are shifted in at TDI. During the appropriate update state (Update-IR or Update-DR), the shadow latches are updated from the shift register. instruction register description The instruction register (IR) is eight bits long and tells the device what instruction is to be executed. Information contained in the instruction includes the mode of operation (either normal mode, in which the device performs its normal logic function, or test mode, in which the normal logic function is inhibited or altered), the test operation to be performed, which of the four data registers is to be selected for inclusion in the scan path during data-register scans, and the source of data to be captured into the selected data register during Capture-DR. Table 3 lists the instructions supported by the ABT18245. The even-parity feature specified for SCOPE TM devices is supported in this device. Bit 7 of the instruction opcode is the parity bit. Any instructions that are defined for SCOPETM devices but are not supported by this device default to BYPASS. During Capture-IR, the IR captures the binary value 10000001. As an instruction is shifted in, this value is shifted out via TDO and can be inspected as verification that the IR is in the scan path. During Update-IR, the value that has been shifted into the IR is loaded into shadow latches. At this time, the current instruction is updated and any specified mode change takes effect. At power up or in the Test-Logic-Reset state, the IR is reset to the binary value 10000001, which selects the IDCODE instruction. The IR order of scan is illustrated in Figure 2. Bit 7 Parity (MSB) TDI Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) TDO Figure 2. Instruction Register Order of Scan 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ABT18245 SCAN TEST DEVICE WITH 18-BIT BUS TRANSCEIVERS SGBS307A - AUGUST 1994 - REVISED JANUARY 1995 data register description boundary-scan register The boundary-scan register (BSR) is 44 bits long. It contains one boundary-scan cell (BSC) for each normal-function input pin, one BSC for each normal-function I/O pin (one single cell for both input data and output data), and one BSC for each of the internally decoded output-enable signals (1OEA, 2OEA, 1OEB, 2OEB). The BSR is used 1) to store test data that is to be applied externally to the device output pins, and/or 2) to capture data that appears internally at the outputs of the normal on-chip logic and/or externally at the device input pins. The source of data to be captured into the BSR during Capture-DR is determined by the current instruction. The contents of the BSR can change during Run-Test/Idle as determined by the current instruction. At power up or in Test-Logic-Reset, BSCs 43 - 40 are reset to logic 0, ensuring that cells, which control A-port and B-port outputs, are set to benign values (i.e., if test mode were invoked, the outputs would be at the high-impedance state). Reset values for other BSCs should be considered indeterminate. When external data is to be captured, the BSCs for signals 1OEA, 2OEA, 1OEB, and 2OEB capture logic values determined by the following positive-logic equations: 1OEA = 1OE * 1DIR, 2OEA = 2OE * 2DIR, 1OEB = 1OE * DIR, and 2OEB = 2OE * DIR. When data is to be applied externally, these BSCs control the drive state (active or high impedance) of their respective outputs. The BSR order of scan is from TDI through bits 43 - 0 to TDO. Table 1 shows the BSR bits and their associated device pin signals. Table 1. Boundary-Scan-Register Configuration BSR BIT NUMBER 43 42 41 40 39 38 37 36 -- DEVICE SIGNAL 2OEB 1OEB 2OEA 1OEA 2DIR 1DIR 2OE 1OE -- BSR BIT NUMBER 35 34 33 32 31 30 29 28 27 DEVICE SIGNAL 2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O BSR BIT NUMBER 26 25 24 23 22 21 20 19 18 DEVICE SIGNAL 1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O BSR BIT NUMBER 17 16 15 14 13 12 11 10 9 DEVICE SIGNAL 2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O BSR BIT NUMBER 8 7 6 5 4 3 2 1 0 DEVICE SIGNAL 1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O boundary-control register The boundary-control register (BCR) is three bits long. The BCR is used in the context of the boundary-run test (RUNT) instruction to implement additional test operations not included in the basic SCOPETM instruction set. Such operations include PRPG, PSA, and binary count up (COUNT). Table 4 shows the test operations that are decoded by the BCR. During Capture-DR, the contents of the BCR are not changed. At power up or in Test-Logic-Reset, the BCR is reset to the binary value 010, which selects the PSA test operation. The BCR order of scan is illustrated in Figure 3. TDI Bit 2 (MSB) Bit 1 Bit 0 (LSB) TDO Figure 3. Boundary-Control Register Order of Scan POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 SN54ABT18245 SCAN TEST DEVICE WITH 18-BIT BUS TRANSCEIVERS SGBS307A - AUGUST 1994 - REVISED JANUARY 1995 bypass register The bypass register is a 1-bit scan path that can be selected to shorten the length of the system scan path, reducing the number of bits per test pattern that must be applied to complete a test operation. During Capture-DR, the bypass register captures a logic 0. The bypass register order of scan is illustrated in Figure 4. TDI Bit 0 TDO Figure 4. Bypass Register Order of Scan device-identification register The device-identification register (IDR) is 32 bits long. It can be selected and read to identify the manufacturer, part number, and version of this device. During Capture-DR, the binary value 00000000000000000101000000101111 (0000502F, hex) is captured in the IDR to identify this device as Texas Instruments SN54ABT18245. The IDR order of scan is from TDI through bits 31 - 0 to TDO. Table 2 shows the IDR bits and their significance. Table 2. Device-Identification-Register Configuration IDR BIT NUMBER 31 30 29 28 -- -- -- -- -- -- -- -- -- -- -- -- IDENTIFICATION SIGNIFICANCE VERSION3 VERSION2 VERSION1 VERSION0 -- -- -- -- -- -- -- -- -- -- -- -- IDR BIT NUMBER 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 IDENTIFICATION SIGNIFICANCE PARTNUMBER15 PARTNUMBER14 PARTNUMBER13 PARTNUMBER12 PARTNUMBER11 PARTNUMBER10 PARTNUMBER09 PARTNUMBER08 PARTNUMBER07 PARTNUMBER06 PARTNUMBER05 PARTNUMBER04 PARTNUMBER03 PARTNUMBER02 PARTNUMBER01 PARTNUMBER00 IDR BIT NUMBER 11 10 9 8 7 6 5 4 3 2 1 0 -- -- -- -- IDENTIFICATION SIGNIFICANCE MANUFACTURER10 MANUFACTURER09 MANUFACTURER08 MANUFACTURER07 MANUFACTURER06 MANUFACTURER05 MANUFACTURER04 MANUFACTURER03 MANUFACTURER02 MANUFACTURER01 MANUFACTURER00 LOGIC1 -- -- -- -- Note that for TI products, bits 11- 0 of the device-identification register always contain the binary value 000000101111 (02F, hex). 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ABT18245 SCAN TEST DEVICE WITH 18-BIT BUS TRANSCEIVERS SGBS307A - AUGUST 1994 - REVISED JANUARY 1995 instruction-register opcode description The instruction-register opcodes are shown in Table 3. The following descriptions detail the operation of each instruction. Table 3. Instruction-Register Opcodes BINARY CODE BIT 7 BIT 0 MSB LSB 00000000 10000001 10000010 00000011 10000100 00000101 00000110 10000111 10001000 00001001 00001010 10001011 00001100 10001101 10001110 00001111 All others SCOPE OPCODE EXTEST IDCODE SAMPLE/PRELOAD BYPASS BYPASS BYPASS HIGHZ CLAMP BYPASS RUNT READBN READBT CELLTST TOPHIP SCANCN SCANCT BYPASS DESCRIPTION Boundary scan Identification read Sample boundary Bypass scan Bypass scan Bypass scan Control boundary to high impedance Control boundary to 1/0 Bypass scan Boundary-run test Boundary read Boundary read Boundary self test Boundary toggle outputs Boundary-control register scan Boundary-control register scan Bypass scan SELECTED DATA REGISTER Boundary scan Device identification Boundary scan Bypass Bypass Bypass Bypass Bypass Bypass Bypass Boundary scan Boundary scan Boundary scan Bypass Boundary control Boundary control Bypass MODE Test Normal Normal Normal Normal Normal Modified test Test Normal Test Normal Test Normal Test Normal Test Normal Bit 7 is used to maintain even parity in the 8-bit instruction. The BYPASS instruction is executed in lieu of a SCOPE TM instruction that is not supported in the ABT18245. boundary scan This instruction conforms to the IEEE Standard 1149.1-1990 EXTEST instruction. The BSR is selected in the scan path. Data appearing at the device input and I/O pins is captured in the associated BSCs. Data that has been scanned into the input BSCs is applied to the inputs of the normal on-chip logic, while data scanned into the I/O BSCs for pins in the output mode is applied to the device I/O pins. Data present at the device I/O pins is passed through the I/O BSCs to the normal on-chip logic. For I/O pins, the operation of a pin as input or output is determined by the contents of the output-enable BSCs (bits 43 - 40 of the BSR). When a given output enable is active (logic 1), the associated I/O pins operate in the output mode. Otherwise, the I/O pins operate in the input mode. The device operates in the test mode. identification read This instruction conforms to the IEEE Standard 1149.1-1990 IDCODE instruction. The IDR is selected in the scan path. The device operates in the normal mode. sample boundary This instruction conforms to the IEEE Standard 1149.1-1990 SAMPLE/PRELOAD instruction. The BSR is selected in the scan path. Data appearing at the device input pins and I/O pins in the input mode is captured in the associated BSCs, while data appearing at the outputs of the normal on-chip logic is captured in the BSCs associated with I/O pins in the output mode. The device operates in the normal mode. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 SN54ABT18245 SCAN TEST DEVICE WITH 18-BIT BUS TRANSCEIVERS SGBS307A - AUGUST 1994 - REVISED JANUARY 1995 bypass scan This instruction conforms to the IEEE Standard 1149.1-1990 BYPASS instruction. The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device operates in the normal mode. control boundary to high impedance This instruction conforms to the IEEE Standard 1149.1a-1993 HIGHZ instruction. The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device operates in a modified test mode in which all device I/O pins are placed in the high-impedance state, the device input pins remain operational, and the normal on-chip logic function is performed. control boundary to 1/0 This instruction conforms to the IEEE Standard 1149.1a-1993 CLAMP instruction. The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. Data in the input BSCs is applied to the inputs of the normal on-chip logic, while data in the I/O BSCs for pins in the output mode is applied to the device I/O pins. The device operates in the test mode. boundary-run test The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device operates in the test mode. The test operation specified in the BCR is executed during Run-Test/Idle. The five test operations decoded by the BCR are: sample inputs/toggle outputs (TOPSIP), PRPG, PSA, simultaneous PSA and PRPG (PSA/PRPG), and simultaneous PSA and binary count up (PSA/COUNT). boundary read The BSR is selected in the scan path. The value in the BSR remains unchanged during Capture-DR. This instruction is useful for inspecting data after a PSA operation. boundary self test The BSR is selected in the scan path. All BSCs capture the inverse of their current values during Capture-DR. In this way, the contents of the shadow latches can be read out to verify the integrity of both shift-register and shadow-latch elements of the BSR. The device operates in the normal mode. boundary toggle outputs The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. Data in the shift-register elements of the selected output-mode BSCs is toggled on each rising edge of TCK in Run-Test/Idle, updated in the shadow latches, and applied to the associated device I/O pins on each falling edge of TCK in Run-Test/Idle. Data in the input-mode BSCs remains constant. Data appearing at the device input or I/O pins is not captured in the input-mode BSCs. The device operates in the test mode. boundary-control-register scan The BCR is selected in the scan path. The value in the BCR remains unchanged during Capture-DR. This operation must be performed before a boundary-run test operation to specify which test operation is to be executed. 12 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ABT18245 SCAN TEST DEVICE WITH 18-BIT BUS TRANSCEIVERS SGBS307A - AUGUST 1994 - REVISED JANUARY 1995 boundary-control-register opcode description The BCR opcodes are decoded from BCR bits 2 - 0 as shown in Table 4. The selected test operation is performed while the RUNT instruction is executed in the Run-Test/Idle state. The following descriptions detail the operation of each BCR instruction and illustrate the associated PSA and PRPG algorithms. Table 4. Boundary-Control-Register Opcodes BINARY CODE BIT 2 BIT 0 MSB LSB X00 X01 X10 011 111 DESCRIPTION Sample inputs/toggle outputs (TOPSIP) Pseudo-random pattern generation/36-bit mode (PRPG) Parallel-signature analysis/36-bit mode (PSA) Simultaneous PSA and PRPG/18-bit mode (PSA/PRPG) Simultaneous PSA and binary count up/18-bit mode (PSA/COUNT) While the control input BSCs (bits 43 - 36) are not included in the toggle, PSA, PRPG, or COUNT algorithms, the output-enable BSCs (bits 43- 40 of the BSR) control the drive state (active or high impedance) of the selected device output pins. These BCR instructions are valid only when both bytes of the device are operating in one direction of data flow (i.e., 1OEA 1OEB and 2OEA 2OEB) and in the same direction of data flow (i.e.,1OEA = 2OEA and 1OEB = 2OEB). Otherwise, the bypass instruction is performed. sample inputs/toggle outputs (TOPSIP) Data appearing at the selected device input-mode I/O pins is captured in the shift-register elements of the associated BSCs on each rising edge of TCK. Data in the shift-register elements of the selected output-mode BSCs is toggled on each rising edge of TCK, updated in the shadow latches, and applied to the associated device I/O pins on each falling edge of TCK. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 13 SN54ABT18245 SCAN TEST DEVICE WITH 18-BIT BUS TRANSCEIVERS SGBS307A - AUGUST 1994 - REVISED JANUARY 1995 pseudo-random pattern generation (PRPG) A pseudo-random pattern is generated in the shift-register elements of the selected BSCs on each rising edge of TCK, updated in the shadow latches, and applied to the associated device output-mode I/O pins on each falling edge of TCK. Figures 5 and 6 illustrate the 36-bit linear-feedback shift-register algorithms through which the patterns are generated. An initial seed value should be scanned into the BSR before performing this operation. A seed value of all zeroes does not produce additional patterns. 2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O 1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O 2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O = 1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O Figure 5. 36-Bit PRPG Configuration (1OEA = 2OEA = 0, 1OEB = 2OEB = 1) 14 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ABT18245 SCAN TEST DEVICE WITH 18-BIT BUS TRANSCEIVERS SGBS307A - AUGUST 1994 - REVISED JANUARY 1995 2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O 1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O 2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O = 1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O Figure 6. 36-Bit PRPG Configuration (1OEA = 2OEA = 1, 1OEB = 2OEB = 0) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 15 SN54ABT18245 SCAN TEST DEVICE WITH 18-BIT BUS TRANSCEIVERS SGBS307A - AUGUST 1994 - REVISED JANUARY 1995 parallel-signature analysis (PSA) Data appearing at the selected device input-mode I/O pins is compressed into a 36-bit parallel signature in the shift-register elements of the selected BSCs on each rising edge of TCK. Data in the shadow latches of the selected output-mode BSCs remains constant and is applied to the associated device I/O pins. Figures 7 and 8 illustrate the 36-bit linear-feedback shift-register algorithms through which the signature is generated. An initial seed value should be scanned into the BSR before performing this operation. 2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O 1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O 2B9-I/O = 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O = 1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O Figure 7. 36-Bit PSA Configuration (1OEA = 2OEA = 0, 1OEB = 2OEB = 1) 16 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ABT18245 SCAN TEST DEVICE WITH 18-BIT BUS TRANSCEIVERS SGBS307A - AUGUST 1994 - REVISED JANUARY 1995 2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O 1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O 2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O = = 1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O Figure 8. 36-Bit PSA Configuration (1OEA = 2OEA = 1, 1OEB = 2OEB = 0) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 17 SN54ABT18245 SCAN TEST DEVICE WITH 18-BIT BUS TRANSCEIVERS SGBS307A - AUGUST 1994 - REVISED JANUARY 1995 simultaneous PSA and PRPG (PSA/PRPG) Data appearing at the selected device input-mode I/O pins is compressed into an 18-bit parallel signature in the shift-register elements of the selected input-mode BSCs on each rising edge of TCK. At the same time, an 18-bit pseudo-random pattern is generated in the shift-register elements of the selected output-mode BSCs on each rising edge of TCK, updated in the shadow latches, and applied to the associated device I/O pins on each falling edge of TCK. Figures 9 and 10 illustrate the 18-bit linear-feedback shift-register algorithms through which the signature and patterns are generated. An initial seed value should be scanned into the BSR before performing this operation. A seed value of all zeroes does not produce additional patterns. 2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O 1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O 2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O = = 1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O Figure 9. 18-Bit PSA/PRPG Configuration (1OEA = 2OEA = 0, 1OEB = 2OEB = 1) 18 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ABT18245 SCAN TEST DEVICE WITH 18-BIT BUS TRANSCEIVERS SGBS307A - AUGUST 1994 - REVISED JANUARY 1995 2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O 1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O 2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O = = 1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O Figure 10. 18-Bit PSA/PRPG Configuration (1OEA = 2OEA = 1, 1OEB = 2OEB = 0) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 19 SN54ABT18245 SCAN TEST DEVICE WITH 18-BIT BUS TRANSCEIVERS SGBS307A - AUGUST 1994 - REVISED JANUARY 1995 simultaneous PSA and binary count up (PSA/COUNT) Data appearing at the selected device input-mode I/O pins is compressed into an 18-bit parallel signature in the shift-register elements of the selected input-mode BSCs on each rising edge of TCK. At the same time, an 18-bit binary count-up pattern is generated in the shift-register elements of the selected output-mode BSCs on each rising edge of TCK, updated in the shadow latches, and applied to the associated device I/O pins on each falling edge of TCK. Figures 11 and 12 illustrate the 18-bit linear-feedback shift-register algorithms through which the signature is generated. An initial seed value should be scanned into the BSR before performing this operation. 2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O 1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O MSB 2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O LSB = = 1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O Figure 11. 18-Bit PSA/COUNT Configuration (1OEA = 2OEA = 0, 1OEB = 2OEB = 1) 20 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ABT18245 SCAN TEST DEVICE WITH 18-BIT BUS TRANSCEIVERS SGBS307A - AUGUST 1994 - REVISED JANUARY 1995 2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O 1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O MSB 2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O LSB = = 1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O Figure 12. 18-Bit PSA/COUNT Configuration (1OEA = 2OEA = 1, 1OEB = 2OEB = 0) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 21 SN54ABT18245 SCAN TEST DEVICE WITH 18-BIT BUS TRANSCEIVERS SGBS307A - AUGUST 1994 - REVISED JANUARY 1995 timing description All test operations of the ABT18245 are synchronous to the TCK. Data on the TDI, TMS, and normal-function inputs is captured on the rising edge of TCK. Data appears on the TDO and normal-function output pins on the falling edge of TCK. The TAP controller is advanced through its states (as illustrated in Figure 1) by changing the value of TMS on the falling edge of TCK and then applying a rising edge to TCK. A simple timing example is illustrated in Figure 13. In this example, the TAP controller begins in the Test-Logic-Reset state and is advanced through its states as necessary to perform one instruction-register scan and one data-register scan. While in the Shift-IR and Shift-DR states, TDI is used to input serial data and TDO is used to output serial data. The TAP controller is then returned to the Test-Logic-Reset state. Table 5 explains the operation of the test circuitry during each TCK cycle. Table 5. Explanation of Timing Example TCK CYCLE(S) 1 2 3 4 5 6 TAP STATE AFTER TCK Test-Logic-Reset Run-Test/Idle Select-DR-Scan Select-IR-Scan Capture-IR Shift-IR The IR captures the 8-bit binary value 10000001 on the rising edge of TCK as the TAP controller exits the Capture-IR state. TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP on the rising edge of TCK as the TAP controller advances to the next state. One bit is shifted into the IR on each TCK rising edge. With TDI held at a logic 1 value, the 8-bit binary value 11111111 is serially scanned into the IR. At the same time, the 8-bit binary value 10000001 is serially scanned out of the IR via TDO. In TCK cycle 13, TMS is changed to a logic 1 value to end the IR scan on the next TCK cycle. The last bit of the instruction is shifted as the TAP controller advances from Shift-IR to Exit1-IR. TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK. The IR is updated with the new instruction (BYPASS) on the falling edge of TCK. The bypass register captures a logic 0 value on the rising edge of TCK as the TAP controller exits the Capture-DR state. TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP on the rising edge of TCK as the TAP controller advances to the next state. The binary value 101 is shifted in via TDI, while the binary value 010 is shifted out via TDO. TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK. The selected data register is updated with the new data on the falling edge of TCK. DESCRIPTION TMS is changed to a logic 0 value on the falling edge of TCK to begin advancing the TAP controller toward the desired state. 7-13 Shift-IR 14 15 16 17 18 19 - 20 21 22 23 24 25 Exit1-IR Update-IR Select-DR-Scan Capture-DR Shift-DR Shift-DR Exit1-DR Update-DR Select-DR-Scan Select-IR-Scan Test-Logic-Reset Test operation completed 22 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ABT18245 SCAN TEST DEVICE WITH 18-BIT BUS TRANSCEIVERS SGBS307A - AUGUST 1994 - REVISED JANUARY 1995 1 TCK 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 TMS TDI TDO Test-Logic-Reset TAP Controller State 3-State (TDO) or Don't Care (TDI) Figure 13. Timing Example absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Input voltage range, VI (I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 5.5 V Voltage range applied to any output in the high state or power-off state, VO . . . . . . . . . . . . . - 0.5 V to 5.5 V Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 50 mA Continuous current through VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576 mA Continuous current through GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1152 mA Maximum power dissipation at TA = 55C (in still air) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950 mW Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output negative-voltage ratings can be exceeded if the input and output clamp-current ratings are observed. recommended operating conditions (see Note 2) MIN VCC VIH VIL VI IOH IOL t /v Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input transition rise or fall rate - 55 0 4.5 2 0.8 VCC - 24 48 10 125 MAX 5.5 UNIT V V V V mA mA ns / V C TA Operating free-air temperature NOTE 2: Unused or floating pins (input or I/O) must be held high or low. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 Test-Logic-Reset Select-IR-Scan Select-DR-Scan Select-DR-Scan Select-DR-Scan Select-IR-Scan Run-Test/Idle Exit1-IR Capture-IR Update-IR Exit1-DR Capture-DR Update-DR Shift-DR IIIIII IIIIII IIIIII IIIIII 23 IIIII IIIII IIIII IIIII II II IIIIIIII IIIIIIII IIIIIIII IIIIIIII Shift-IR SN54ABT18245 SCAN TEST DEVICE WITH 18-BIT BUS TRANSCEIVERS SGBS307A - AUGUST 1994 - REVISED JANUARY 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VCC = 4.5 V, VCC = 4.5 V, VCC = 5 V, VCC = 4.5 V, VCC = 4.5 V, VOL II IIH IIL IOZH IOZL Ioff ICEX IO ICC VCC = 4 5 V 4.5 VCC = 5.5 V, , VI = VCC or GND VCC = 5.5 V, VI = VCC VCC = 5.5 V, VI = GND VCC = 5.5 V, VCC = 5.5 V, VCC = 0, VCC = 5.5 V, VO = 5.5 V VCC = 5.5 V, VCC = 5.5 V, IO = 0, VI = VCC or GND VO = 2.7 V VO = 0.5 V VI or VO 4.5 V Outputs high VO = 2.5 V Outputs high A or B orts ports Outputs low Outputs disabled - 50 -110 3.5 33 2.9 TEST CONDITIONS II = -18 mA IOH = - 3 mA IOH = - 3 mA IOH = - 24 mA IOH = - 32 mA IOL = 48 mA IOL = 64 mA DIR, OE, TCK A or B ports TDI, TMS TDI, TMS MIN 2.5 3 2 2* 0.55 0.55* 1 100 10 -150 50 - 50 100 50 - 200 5 38 4.5 50 Control inputs A or B ports 3 10 - 50 1 100 10 -150 50 - 50 450 50 - 200 5 38 4.5 50 9.8 12.6 11.4 A pF pF pF mA 0.55 V A A A A A A A mA TA = 25C TYP MAX -1.2 2.5 3 2 V MIN MAX -1.2 UNIT V VOH ICC Ci Cio VCC = 5.5 V, One input at 3.4 V, , , Other inputs at VCC or GND VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V Co VO = 2.5 V or 0.5 V TDO 8 * On products compliant to MIL-STD-883, Class B, this parameter does not apply. All typical values are at VCC = 5 V. The parameters IOZH and IOZL include the input leakage current. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. 24 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ABT18245 SCAN TEST DEVICE WITH 18-BIT BUS TRANSCEIVERS SGBS307A - AUGUST 1994 - REVISED JANUARY 1995 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (test mode) (see Figure 14)123 MIN fclock tw tsu Clock frequency Pulse duration Setup time TCK TCK high or low A, B, DIR, or OE before TCK TDI before TCK TMS before TCK A, B, DIR, or OE after TCK th td tr Hold time Delay time TDI after TCK TMS after TCK Power up to TCK Rise time VCC power up * These parameters are not production tested for MIL-STD-883 compliant products. 0 8.1 9.5 4.5 3.6 0.7 0 0.5 50* 1* ns s ns ns MAX 50 UNIT MHz ns POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 25 SN54ABT18245 SCAN TEST DEVICE WITH 18-BIT BUS TRANSCEIVERS SGBS307A - AUGUST 1994 - REVISED JANUARY 1995 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (normal mode) (see Figure 14) PARAMETER tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) A or B TO (OUTPUT) B or A B or A B or A VCC = 5 V, TA = 25C MIN 1.5 1.5 3 3 3 3 TYP 2.8 3.1 5.9 6.3 7.4 6.6 MAX 4.1 4.6 6.8 7.2 8.6 8.6 1.5 1.5 3 3 3 3 5.1 5.8 9.9 10.1 12.2 10.9 ns ns ns MIN MAX UNIT OE OE switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (test mode) (see Figure 14)1 PARAMETER fmax tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ FROM (INPUT) TCK TCK TCK TCK TCK TCK TCK A or B TDO A or B TDO A or B TDO TO (OUTPUT) VCC = 5 V, TA = 25C MIN 50 3 3 2 2 4 4 2 2.5 3.5 2.5 2 1.5 TYP 90 7.1 7 3.4 3.9 7.5 7.6 3.8 4 7.7 7.1 3.9 3.5 10.1 10.1 5 5.6 10.6 10.5 5.5 5.7 10.8 10.1 5.7 5.4 MAX 50 2.8 3 2 2 4 4 2 2.3 2.9 2.5 2 1.5 14 13.8 6.4 7 14.1 14.3 7 7.3 14.4 13.8 7.5 6.7 MHz ns ns ns ns ns ns MIN MAX UNIT 26 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54ABT18245 SCAN TEST DEVICE WITH 18-BIT BUS TRANSCEIVERS SGBS307A - AUGUST 1994 - REVISED JANUARY 1995 PARAMETER MEASUREMENT INFORMATION 7V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 7V Open LOAD CIRCUIT FOR OUTPUTS 3V Timing Input tw 3V Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION Data Input tsu 1.5 V th 3V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 0V Input 3V 1.5 V tPLH 1.5 V 0V tPHL VOH 1.5 V 1.5 V VOL tPHL tPLH VOH 1.5 V 1.5 V VOL Output Control tPZL Output Waveform 1 S1 at 7 V (see Note B) Output Waveform 2 S1 at Open (see Note B) tPZH 3V 1.5 V 1.5 V 0V tPLZ 1.5 V tPHZ VOH - 0.3 V VOH 3.5 V VOL + 0.3 V VOL Output Output 1.5 V [0V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 14. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 27 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 1998, Texas Instruments Incorporated |
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