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| PCI2050, PCI2050I PCI to PCI Bridge Data Manual 2000 PCIBus Solutions SCPS053A IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 2000, Texas Instruments Incorporated Contents Section 1 Title Page 2 3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.3 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.5 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Terminal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Feature/Protocol Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 Introduction to the PCI2050 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.2 PCI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.3 Configuration Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.4 Special Cycle Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.5 Secondary Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.6 Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.6.1 Primary Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.6.2 Internal Secondary Bus Arbitration . . . . . . . . . . . . . . . . . . . . 3-5 3.6.3 External Secondary Bus Arbitration . . . . . . . . . . . . . . . . . . . 3-6 3.7 Decode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.8 System Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.8.1 Posted Write Parity Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.8.2 Posted Write Time-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.8.3 Target Abort on Posted Writes . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.8.4 Master Abort on Posted Writes . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.8.5 Master Delayed Write Time-Out . . . . . . . . . . . . . . . . . . . . . . 3-7 3.8.6 Master Delayed Read Time-Out . . . . . . . . . . . . . . . . . . . . . . 3-7 3.8.7 Secondary SERR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.9 Parity Handling and Parity Error Reporting . . . . . . . . . . . . . . . . . . . . . . 3-7 3.9.1 Address Parity Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.9.2 Data Parity Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.10 Master and Target Abort Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.11 Discard Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.12 Delayed Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.13 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.14 CompactPCI Hot-Swap Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.15 JTAG Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.15.1 Test Port Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.16 GPIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 iii 4 5 3.16.1 Secondary Clock Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.16.2 Transaction Forwarding Control . . . . . . . . . . . . . . . . . . . . . . . 3.17 PCI Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.17.1 Behavior in Low-Power States . . . . . . . . . . . . . . . . . . . . . . . . Bridge Configuration Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 Class Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 Cache Line Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8 Primary Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9 Header Type Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10 BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11 Base Address Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.12 Base Address Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.13 Primary Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.14 Secondary Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.15 Subordinate Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.16 Secondary Bus Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . 4.17 I/O Base Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.18 I/O Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.19 Secondary Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.20 Memory Base Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.21 Memory Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.22 Prefetchable Memory Base Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.23 Prefetchable Memory Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.24 Prefetchable Base Upper 32 Bits Register . . . . . . . . . . . . . . . . . . . . . . 4.25 Prefetchable Limit Upper 32 Bits Register . . . . . . . . . . . . . . . . . . . . . . 4.26 I/O Base Upper 16 Bits Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.27 I/O Limit Upper 16 Bits Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.28 Capability Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.29 Expansion ROM Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . 4.30 Interrupt Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.31 Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.32 Bridge Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Extension Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Chip Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Extended Diagnostic Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Arbiter Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 P_SERR Event Disable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 GPIO Output Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 GPIO Output Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3-14 3-15 3-15 4-1 4-2 4-2 4-3 4-4 4-5 4-5 4-5 4-6 4-6 4-6 4-7 4-7 4-7 4-8 4-8 4-8 4-9 4-9 4-10 4-11 4-11 4-11 4-12 4-12 4-13 4-13 4-13 4-14 4-14 4-14 4-15 4-15 5-1 5-1 5-2 5-3 5-4 5-5 5-5 iv 6 7 5.7 GPIO Input Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8 Secondary Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9 P_SERR Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.10 Power-Management Capability ID Register . . . . . . . . . . . . . . . . . . . . . 5.11 Power-Management Next-Item Pointer Register . . . . . . . . . . . . . . . . . 5.12 Power-Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . . 5.13 Power-Management Control/Status Register . . . . . . . . . . . . . . . . . . . . 5.14 PMCSR Bridge Support Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.15 Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.16 HS Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.17 HS Next-Item Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.18 Hot-Swap Control Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Absolute Maximum Ratings Over Operating Temperature Ranges . 6.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 Recommended Operating Conditions for PCI Interface . . . . . . . . . . . 6.4 Electrical Characteristics Over Recommended Operating Conditions 6.5 PCI Clock/Reset Timing Requirements Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature . . . 6.6 PCI Timing Requirements Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature . . . . . . . . . . . . 6.7 Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8 PCI Bus Parameter Measurement Information . . . . . . . . . . . . . . . . . . . Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 5-7 5-8 5-8 5-9 5-9 5-10 5-11 5-11 5-12 5-12 5-13 6-1 6-1 6-2 6-2 6-3 6-4 6-5 6-6 6-7 7-1 v List of Illustrations Figure 2-1 2-2 3-1 3-2 3-3 3-4 3-5 3-6 6-1 6-2 6-3 6-4 Title Page PCI2050 GHK Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 PCI2050 PDV Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 PCI AD31-AD0 During Address Phase of a Type 0 Configuration Cycle 3-2 PCI AD31-AD0 During Address Phase of a Type 1 Configuration Cycle 3-3 Bus Hierarchy and Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Secondary Clock Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Clock Mask Read Timing After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 Load Circuit and Voltage Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 PCLK Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 RSTIN Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 Shared-Signals Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 vi List of Tables Table 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 3-1 3-2 3-3 3-4 3-5 3-6 4-1 4-2 4-3 4-4 4-5 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 Title 208-Terminal PDV Signal Names Sorted by Terminal Number . . . . . . . . 209-Terminal GHK Signal Names Sorted by Terminal Number . . . . . . . . Signal Names Sorted Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Primary PCI System Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Primary PCI Address and Data Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . Primary PCI Interface Control Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . Secondary PCI System Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Secondary PCI Address and Data Terminals . . . . . . . . . . . . . . . . . . . . . . . Secondary PCI Interface Control Terminals . . . . . . . . . . . . . . . . . . . . . . . . . Miscellaneous Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Interface Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Command Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI S_AD31-S_AD16 During the Address Phase of a Type 0 Configuration Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration via MS0 and MS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Instructions and Op Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary Scan Terminal Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Mask Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bridge Configuration Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Secondary Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bridge Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chip Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Extended Diagnostic Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . Arbiter Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P_SERR Event Disable Register Description . . . . . . . . . . . . . . . . . . . . . . . GPIO Output Data Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Output Enable Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Input Data Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Secondary Clock Control Register Description . . . . . . . . . . . . . . . . . . . . . . P_SERR Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Management Capabilities Register Description . . . . . . . . . . . . . . . Power-Management Control/Status Register Description . . . . . . . . . . . . . PMCSR Bridge Support Register Description . . . . . . . . . . . . . . . . . . . . . . . Hot-Swap Control Status Register Description . . . . . . . . . . . . . . . . . . . . . . Page 2-3 2-5 2-7 2-9 2-9 2-10 2-11 2-12 2-13 2-13 2-14 2-14 3-2 3-4 3-9 3-10 3-10 3-14 4-1 4-3 4-4 4-10 4-15 5-1 5-2 5-3 5-4 5-5 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-13 vii viii 1 Introduction 1.1 Description The Texas Instruments PCI2050 PCI-to-PCI bridge provides a high-performance connection path between two peripheral component interconnect (PCI) buses. Transactions occur between masters on one PCI bus and targets on another PCI bus, and the PCI2050 allows bridged transactions to occur concurrently on both buses. The bridge supports burst-mode transfers to maximize data throughput, and the two bus traffic paths through the bridge act independently. The PCI2050 bridge is compliant with the PCI Local Bus Specification, and can be used to overcome the electrical loading limits of 10 devices per PCI bus and one PCI device per expansion slot by creating hierarchical buses. The PCI2050 provides two-tier internal arbitration for up to nine secondary bus masters and may be implemented with an external secondary PCI bus arbiter. The CompactPCITM hot-swap extended PCI capability is provided which makes the PCI2050 an ideal solution for multifunction CompactPCI cards and for adapting single-function cards to hot-swap compliance. The PCI2050 bridge is compliant with the PCI-to-PCI Bridge Specification 1.1. The PCI2050 provides compliance for PCI Power Management 1.0 and 1.1. The PCI2050 has been designed to lead the industry in power conservation. An advanced CMOS process is used to achieve low system power consumption while operating at PCI clock rates up to 33 MHz. The PCI2050I is an industrial version of the PCI2050 that has a larger operating temperature range. All references to the PCI2050 also apply to the PCI2050I unless otherwise noted. 1.2 Features The PCI2050 supports the following features: * * * * * * * * * * * * * * * Architecture configurable for PCI Bus Power Management Interface Specification CompactPCI hot-swap-friendly silicon 3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments Two 32-bit, 33-MHz PCI buses Internal two-tier arbitration for up to nine secondary bus masters and supports an external secondary bus arbiter Burst data transfers with pipeline architecture to maximize data throughput in both directions Independent read and write buffers for each direction Up to three delayed transactions in both directions Ten secondary PCI clock outputs Predictable latency per PCI Local Bus Specification Bus locking propagation Secondary bus is driven low during reset VGA/palette memory and I/O decoding options Advanced submicron, low-power CMOS technology 208-terminal QFP or 209-terminal MicroStar BGATM package 1-1 1.3 Related Documents * * * * * * Advanced Configuration and Power Interface (ACPI) Specification (Revision 1.0) IEEE Standard Test Access Port and Boundary-Scan Architecture PCI Local Bus Specification (Revision 2.2) PCI-to-PCI Bridge Specification (Revision 1.1) PCI Bus Power Management Interface Specification (Revision 1.1) PICMG CompactPCI Hot-Swap Specification (Revision 1.0) 1.4 Trademarks CompactPCI is a trademark of PICMG - PCI Industrial Computer Manufacturers Group, Inc. Intel is a trademark of Intel Corporation. MicroStar BGA and TI are trademarks of Texas Instruments. Other trademarks are the property of their respective owners. 1.5 Ordering Information ORDERING NUMBER PCI2050 PCI2050I NAME PCI-PCI Bridge PCI-PCI Bridge VOLTAGE 3.3 V, 5-V Tolerant I/Os 3.3 V, 5-V Tolerant I/Os PACKAGE 208-terminal QFP 209-terminal MicroStar BGATM 208-terminal QFP 209-terminal MicroStar BGATM 1-2 2 Terminal Descriptions The PCI2050 device is packaged either in a 209-terminal GHK MicroStar BGATM or a 208-terminal PDV package. Figure 2-1 is a GHK-package terminal diagram. Figure 2-2 is a PDV-package terminal diagram. Table 2-1 lists terminals on the PDV packaged device in increasing numerical order, with the signal name and corresponding GHK terminal number for each. Table 2-2 lists terminals on the GHK packaged device in increasing alphanumerical order, with the signal name and corresponding PDV terminal number for each. Table 2-3 lists signal names in alphabetical order, with corresponding terminal numbers for both package types. W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Figure 2-1. PCI2050 GHK Terminal Diagram 2-1 PDV LOW-PROFILE QUAD FLAT PACKAGE TOP VIEW GND MS0 S_AD10 S_M66ENA S_AD9 VCC S_AD8 S_C/BE0 GND S_AD7 S_AD6 VCC S_AD5 S_AD4 GND S_AD3 S_AD2 VCC S_AD1 S_AD0 GND S_VCCP TRST TCK TMS VCC TDO TDI HSLED HSENUM MSK_IN NC P_VCCP GND P_AD0 P_AD1 VCC P_AD2 P_AD3 GND P_AD4 P_AD5 VCC P_AD6 P_AD7 GND P_C/BE0 P_AD8 VCC P_AD9 MS1 VCC VCC GND S_AD11 GND S_AD12 S_AD13 VCC S_AD14 S_AD15 GND S_C/BE1 S_PAR S_SERR VCC S_PERR S_LOCK S_STOP GND S_DEVSEL S_TRDY S_IRDY VCC S_FRAME S_C/BE2 GND S_AD16 S_AD17 VCC S_AD18 S_AD19 GND S_AD20 S_AD21 VCC S_AD22 S_AD23 GND S_C/BE3 S_AD24 VCC S_AD25 S_AD26 GND S_AD27 S_AD28 VCC S_AD29 S_AD30 GND S_AD31 S_REQ0 VCC 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 PCI2050 GND VCC NC P_AD10 GND P_AD11 P_AD12 VCC P_AD13 P_AD14 GND P_AD15 P_C/BE1 VCC P_PAR P_SERR P_PERR P_LOCK GND P_STOP P_DEVSEL P_TRDY P_IRDY VCC P_FRAME P_C/BE2 GND P_AD16 P_AD17 VCC P_AD18 P_AD19 GND P_AD20 P_AD21 VCC P_AD22 P_AD23 GND P_IDSEL P_C/BE3 P_AD24 VCC P_AD25 P_AD26 GND P_AD27 P_AD28 VCC P_AD29 GND VCC 2-2 VCC S_REQ1 S_REQ2 S_REQ3 S_REQ4 S_REQ5 S_REQ6 S_REQ7 S_REQ8 S_GNT0 S_GNT1 GND S_GNT2 S_GNT3 S_GNT4 S_GNT5 S_GNT6 S_GNT7 S_GNT8 GND S_CLK S_RST S_CFN HSSWITCH/GPIO3 GPIO2 VCC GPIO1 GPIO0 S_CLKOUT0 S_CLKOUT1 GND S_CLKOUT2 S_CLKOUT3 VCC S_CLKOUT4 S_CLKOUT5 GND S_CLKOUT6 S_CLKOUT7 VCC S_CLKOUT8 S_CLKOUT9 P_RST BPCCE P_CLK P_GNT P_REQ GND P_AD31 P_AD30 VCC GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Figure 2-2. PCI2050 PDV Terminal Diagram Table 2-1. 208-Terminal PDV Signal Names Sorted by Terminal Number PDV NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 GHK NO. D1 E3 F5 G6 E2 E1 F3 F2 G5 F1 H6 G3 G2 G1 H5 H3 H2 H1 J1 J2 J3 J5 J6 K1 K2 K3 K5 K6 L1 L2 L3 L6 L5 M1 M2 M3 M6 M5 N1 N2 N3 N6 P1 SIGNAL NAME VCC S_REQ1 S_REQ2 S_REQ3 S_REQ4 S_REQ5 S_REQ6 S_REQ7 S_REQ8 S_GNT0 S_GNT1 GND S_GNT2 S_GNT3 S_GNT4 S_GNT5 S_GNT6 S_GNT7 S_GNT8 GND S_CLK S_RST S_CFN HSSWITCH/GPIO3 GPIO2 VCC GPIO1 GPIO0 S_CLKOUT0 S_CLKOUT1 GND S_CLKOUT2 S_CLKOUT3 VCC S_CLKOUT4 S_CLKOUT5 GND S_CLKOUT6 S_CLKOUT7 VCC S_CLKOUT8 S_CLKOUT9 P_RST PDV NO. 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 GHK NO. P2 N5 P3 R1 P6 R2 P5 R3 T1 W4 U5 R6 P7 V5 W5 U6 V6 R7 W6 P8 U7 V7 W7 R8 U8 V8 W8 W9 V9 U9 R9 P9 W10 V10 U10 R10 P10 W11 V11 U11 P11 R11 W12 SIGNAL NAME BPCCE P_CLK P_GNT P_REQ GND P_AD31 P_AD30 VCC GND VCC GND P_AD29 VCC P_AD28 P_AD27 GND P_AD26 P_AD25 VCC P_AD24 P_C/BE3 P_IDSEL GND P_AD23 P_AD22 VCC P_AD21 P_AD20 GND P_AD19 P_AD18 VCC P_AD17 P_AD16 GND P_C/BE2 P_FRAME VCC P_IRDY P_TRDY P_DEVSEL P_STOP GND PDV NO. 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 GHK NO. V12 U12 P12 R12 W13 V13 U13 P13 W14 V14 R13 U14 W15 P14 V15 R14 U15 W16 T19 R17 P15 N14 R18 R19 P17 P18 N15 P19 M14 N17 N18 N19 M15 M17 M18 M19 L19 L18 L17 L15 L14 K19 K18 SIGNAL NAME P_LOCK P_PERR P_SERR P_PAR VCC P_C/BE1 P_AD15 GND P_AD14 P_AD13 VCC P_AD12 P_AD11 GND P_AD10 NC VCC GND VCC MS1 P_AD9 VCC P_AD8 P_C/BE0 GND P_AD7 P_AD6 VCC P_AD5 P_AD4 GND P_AD3 P_AD2 VCC P_AD1 P_AD0 GND P_VCCP NC MSK_IN HSENUM HSLED TDI PDV NO. 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 GHK NO. K17 K15 K14 J19 J18 J17 J14 J15 H19 H18 H17 H14 H15 G19 G18 G17 G14 F19 F18 G15 F17 E19 F14 E18 F15 E17 D19 A16 C15 E14 F13 B15 A15 C14 B14 E13 A14 F12 C13 B13 A13 E12 C12 SIGNAL NAME TDO VCC TMS TCK TRST S_VCCP GND S_AD0 S_AD1 VCC S_AD2 S_AD3 GND S_AD4 S_AD5 VCC S_AD6 S_AD7 GND S_C/BE0 S_AD8 VCC S_AD9 S_M66ENA S_AD10 MS0 GND VCC GND S_AD11 GND S_AD12 S_AD13 VCC S_AD14 S_AD15 GND S_C/BE1 S_PAR S_SERR VCC S_PERR S_LOCK 2-3 Table 2-1. 208-Terminal PDV Signal Names Sorted by Terminal Number (continued) PDV NO. 173 174 175 176 177 178 179 180 181 GHK NO. B12 A12 A11 B11 C11 E11 F11 A10 B10 SIGNAL NAME S_STOP GND S_DEVSEL S_TRDY S_IRDY VCC S_FRAME S_C/BE2 GND PDV NO. 182 183 184 185 186 187 188 189 190 GHK NO. C10 E10 F10 A9 B9 C9 F9 E9 A8 SIGNAL NAME S_AD16 S_AD17 VCC S_AD18 S_AD19 GND S_AD20 S_AD21 VCC PDV NO. 191 192 193 194 195 196 197 198 199 GHK NO. B8 C8 F8 E8 A7 B7 C7 F7 A6 SIGNAL NAME S_AD22 S_AD23 GND S_C/BE3 S_AD24 VCC S_AD25 S_AD26 GND PDV NO. 200 201 202 203 204 205 206 207 208 GHK NO. B6 E7 C6 A5 F6 B5 E6 C5 A4 SIGNAL NAME S_AD27 S_AD28 VCC S_AD29 S_AD30 GND S_AD31 S_REQ0 VCC 2-4 Table 2-2. 209-Terminal GHK Signal Names Sorted by Terminal Number PDV NO. 208 203 199 195 190 185 180 175 174 170 166 162 157 205 200 196 191 186 181 176 173 169 164 161 207 202 197 192 187 182 177 172 168 163 158 1 156 6 5 2 E5 206 201 GHK NO. A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 D1 D19 E1 E2 E3 N/A E6 E7 SIGNAL NAME VCC S_AD29 GND S_AD24 VCC S_AD18 S_C/BE2 S_DEVSEL GND VCC GND S_AD13 VCC GND S_AD27 VCC S_AD22 S_AD19 GND S_TRDY S_STOP S_SERR S_AD14 S_AD12 S_REQ0 VCC S_AD25 S_AD23 GND S_AD16 S_IRDY S_LOCK S_PAR VCC GND VCC GND S_REQ5 S_REQ4 S_REQ1 NC S_AD31 S_AD28 GHK NO. E8 E9 E10 E11 E12 E13 E14 E17 E18 E19 F1 F2 F3 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F17 F18 F19 G1 G2 G3 G5 G6 G14 G15 G17 G18 G19 H1 H2 H3 H5 H6 H14 PDV NO. 194 189 183 178 171 165 159 155 153 151 10 8 7 3 204 198 193 188 184 179 167 160 152 154 150 148 147 14 13 12 9 4 146 149 145 144 143 18 17 16 15 11 141 SIGNAL NAME S_C/BE3 S_AD21 S_AD17 VCC S_PERR S_AD15 S_AD11 MS0 S_M66ENA VCC S_GNT0 S_REQ7 S_REQ6 S_REQ2 S_AD30 S_AD26 GND S_AD20 VCC S_FRAME S_C/BE1 GND S_AD9 S_AD10 S_AD8 GND S_AD7 S_GNT3 S_GNT2 GND S_REQ8 S_REQ3 S_AD6 S_C/BE0 VCC S_AD5 S_AD4 S_GNT7 S_GNT6 S_GNT5 S_GNT4 S_GNT1 S_AD3 GHK NO. H15 H17 H18 H19 J1 J2 J3 J5 J6 J14 J15 J17 J18 J19 K1 K2 K3 K5 K6 K14 K15 K17 K18 K19 L1 L2 L3 L5 L6 L14 L15 L17 L18 L19 M1 M2 M3 M5 M6 M14 M15 M17 M18 PDV NO. 142 140 139 138 19 20 21 22 23 136 137 135 134 133 24 25 26 27 28 132 131 130 129 128 29 30 31 33 32 127 126 125 124 123 34 35 36 38 37 115 119 120 121 SIGNAL NAME GND S_AD2 VCC S_AD1 S_GNT8 GND S_CLK S_RST S_CFN GND S_AD0 S_VCCP TRST TCK HSSWITCH/GPIO3 GPIO2 VCC GPIO1 GPIO0 TMS VCC TDO TDI HSLED S_CLKOUT0 S_CLKOUT1 GND S_CLKOUT3 S_CLKOUT2 HSENUM MSK_IN NC P_VCCP GND VCC S_CLKOUT4 S_CLKOUT5 S_CLKOUT6 GND P_AD5 P_AD2 VCC P_AD1 GHK NO. M19 N1 N2 N3 N5 N6 N14 N15 N17 N18 N19 P1 P2 P3 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P17 P18 P19 R1 R2 R3 R6 R7 R8 R9 R10 R11 R12 R13 R14 R17 R18 R19 PDV NO. 122 39 40 41 45 42 108 113 116 117 118 43 44 46 50 48 56 63 75 80 84 89 94 100 107 111 112 114 47 49 51 55 61 67 74 79 85 90 97 102 106 109 110 SIGNAL NAME P_AD0 S_CLKOUT7 VCC S_CLKOUT8 P_CLK S_CLKOUT9 VCC P_AD6 P_AD4 GND P_AD3 P_RST BPCCE P_GNT P_AD30 GND VCC P_AD24 VCC P_FRAME P_DEVSEL P_SERR GND GND P_AD9 GND P_AD7 VCC P_REQ P_AD31 VCC P_AD29 P_AD25 P_AD23 P_AD18 P_C/BE2 P_STOP P_PAR VCC NC MS1 P_AD8 P_C/BE0 Terminal E5 is used as a key to indicate the location of the A1 corner. It is a no-connect terminal. 2-5 Table 2-2. 209-Terminal GHK Signal Names Sorted by Terminal Number (continued) GHK NO. T1 T19 U5 U6 U7 U8 U9 U10 U11 U12 PDV NO. 52 105 54 59 64 68 73 78 83 88 SIGNAL NAME GND VCC GND GND P_C/BE3 P_AD22 P_AD19 GND P_TRDY P_PERR GHK NO. U13 U14 U15 V5 V6 V7 V8 V9 V10 V11 PDV NO. 93 98 103 57 60 65 69 72 77 82 SIGNAL NAME P_AD15 P_AD12 VCC P_AD28 P_AD26 P_IDSEL VCC GND P_AD16 P_IRDY GHK NO. V12 V13 V14 V15 W4 W5 W6 W7 W8 W9 PDV NO. 87 92 96 101 53 58 62 66 70 71 SIGNAL NAME P_LOCK P_C/BE1 P_AD13 P_AD10 VCC P_AD27 VCC GND P_AD21 P_AD20 GHK NO. W10 W11 W12 W13 W14 W15 W16 PDV NO. 76 81 86 91 95 99 104 SIGNAL NAME P_AD17 VCC GND VCC P_AD14 P_AD11 GND 2-6 Table 2-3. Signal Names Sorted Alphabetically SIGNAL NAME BPCCE GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GPIO0 GPIO1 GPIO2 HSENUM HSLED HSSWITCH/GPIO3 MS0 MS1 MSK_IN NC NC PDV NO. 44 12 20 31 37 48 52 54 59 66 72 78 86 94 100 104 111 117 123 136 142 148 156 158 160 166 174 181 187 193 199 205 28 27 25 127 128 24 155 106 126 N/A 102 GHK NO. P2 G3 J2 L3 M6 P6 T1 U5 U6 W7 V9 U10 W12 P13 P14 W16 P17 N18 L19 J14 H15 F18 D19 C15 F13 A14 A12 B10 C9 F8 A6 B5 K6 K5 K2 L14 K19 K1 E17 R17 L15 E5 R14 SIGNAL NAME NC P_AD0 P_AD1 P_AD2 P_AD3 P_AD4 P_AD5 P_AD6 P_AD7 P_AD8 P_AD9 P_AD10 P_AD11 P_AD12 P_AD13 P_AD14 P_AD15 P_AD16 P_AD17 P_AD18 P_AD19 P_AD20 P_AD21 P_AD22 P_AD23 P_AD24 P_AD25 P_AD26 P_AD27 P_AD28 P_AD29 P_AD30 P_AD31 P_C/BE0 P_C/BE1 P_C/BE2 P_C/BE3 P_CLK P_DEVSEL P_FRAME P_GNT P_IDSEL P_IRDY PDV NO. 125 122 121 119 118 116 115 113 112 109 107 101 99 98 96 95 93 77 76 74 73 71 70 68 67 63 61 60 58 57 55 50 49 110 92 79 64 45 84 80 46 65 82 GHK NO. L17 M19 M18 M15 N19 N17 M14 N15 P18 R18 P15 V15 W15 U14 V14 W14 U13 V10 W10 R9 U9 W9 W8 U8 R8 P8 R7 V6 W5 V5 R6 P5 R2 R19 V13 R10 U7 N5 P11 P10 P3 V7 V11 SIGNAL NAME P_LOCK P_PAR P_PERR P_REQ P_RST P_SERR P_STOP P_TRDY P_VCCP S_AD0 S_AD1 S_AD2 S_AD3 S_AD4 S_AD5 S_AD6 S_AD7 S_AD8 S_AD9 S_AD10 S_AD11 S_AD12 S_AD13 S_AD14 S_AD15 S_AD16 S_AD17 S_AD18 S_AD19 S_AD20 S_AD21 S_AD22 S_AD23 S_AD24 S_AD25 S_AD26 S_AD27 S_AD28 S_AD29 S_AD30 S_AD31 S_C/BE0 S_C/BE1 PDV NO. 87 90 88 47 43 89 85 83 124 137 138 140 141 143 144 146 147 150 152 154 159 161 162 164 165 182 183 185 186 188 189 191 192 195 197 198 200 201 203 204 206 149 167 GHK NO. V12 R12 U12 R1 P1 P12 R11 U11 L18 J15 H19 H17 H14 G19 G18 G14 F19 F17 F14 F15 E14 B15 A15 B14 E13 C10 E10 A9 B9 F9 E9 B8 C8 A7 C7 F7 B6 E7 A5 F6 E6 G15 F12 SIGNAL NAME S_C/BE2 S_C/BE3 S_CFN S_CLK S_CLKOUT0 S_CLKOUT1 S_CLKOUT2 S_CLKOUT3 S_CLKOUT4 S_CLKOUT5 S_CLKOUT6 S_CLKOUT7 S_CLKOUT8 S_CLKOUT9 S_DEVSEL S_FRAME S_GNT0 S_GNT1 S_GNT2 S_GNT3 S_GNT4 S_GNT5 S_GNT6 S_GNT7 S_GNT8 S_IRDY S_LOCK S_M66ENA S_PAR S_PERR S_REQ0 S_REQ1 S_REQ2 S_REQ3 S_REQ4 S_REQ5 S_REQ6 S_REQ7 S_REQ8 S_RST S_SERR S_STOP S_TRDY PDV NO. 180 194 23 21 29 30 32 33 35 36 38 39 41 42 175 179 10 11 13 14 15 16 17 18 19 177 172 153 168 171 207 2 3 4 5 6 7 8 9 22 169 173 176 GHK NO. A10 E8 J6 J3 L1 L2 L6 L5 M2 M3 M5 N1 N3 N6 A11 F11 F1 H6 G2 G1 H5 H3 H2 H1 J1 C11 C12 E18 C13 E12 C5 E3 F5 G6 E2 E1 F3 F2 G5 J5 B13 B12 B11 2-7 Table 2-3. Signal Names Sorted Alphabetically (continued) SIGNAL NAME S_VCCP TCK TDI TDO TMS TRST VCC VCC VCC VCC PDV NO. 135 133 129 130 132 134 1 26 34 40 GHK NO. J17 J19 K18 K17 K14 J18 D1 K3 M1 N2 SIGNAL NAME VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC PDV NO. 51 53 56 62 69 75 81 91 97 103 GHK NO. R3 W4 P7 W6 V8 P9 W11 W13 R13 U15 SIGNAL NAME VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC PDV NO. 105 108 114 120 131 139 145 151 202 208 GHK NO. T19 N14 P19 M17 K15 H18 G17 E19 C6 A4 SIGNAL NAME VCC VCC VCC VCC VCC VCC VCC PDV NO. 157 163 170 178 184 190 196 GHK NO. A16 C14 A13 E11 F10 A8 B7 2-8 The terminals are grouped in tables by functionality, such as PCI system function and power-supply function (see Table 2-4 through Table 2-12). The terminal numbers also are listed for convenient reference. Table 2-4. Primary PCI System Terminals TERMINAL NAME P_CLK PDV NO. 45 GHK NO. N5 I/O DESCRIPTION Primary PCI bus clock. P_CLK provides timing for all transactions on the primary PCI bus. All primary PCI signals are sampled at rising edge of P_CLK. PCI reset. When the primary PCI bus reset is asserted, P_RST causes the bridge to put all output buffers in a high-impedance state and reset all internal registers. When asserted, the device is completely nonfunctional. During P_RST, the secondary interface is driven low. After P_RST is deasserted, the bridge is in its default state. I P_RST 43 P1 I Table 2-5. Primary PCI Address and Data Terminals TERMINAL NAME P_AD31 P_AD30 P_AD29 P_AD28 P_AD27 P_AD26 P_AD25 P_AD24 P_AD23 P_AD22 P_AD21 P_AD20 P_AD19 P_AD18 P_AD17 P_AD16 P_AD15 P_AD14 P_AD13 P_AD12 P_AD11 P_AD10 P_AD9 P_AD8 P_AD7 P_AD6 P_AD5 P_AD4 P_AD3 P_AD2 P_AD1 P_AD0 P_C/BE3 P_C/BE2 P_C/BE1 P_C/BE0 PDV NO. 49 50 55 57 58 60 61 63 67 68 70 71 73 74 76 77 93 95 96 98 99 101 107 109 112 113 115 116 118 119 121 122 64 79 92 110 GHK NO. R2 P5 R6 V5 W5 V6 R7 P8 R8 U8 W8 W9 U9 R9 W10 V10 U13 W14 V14 U14 W15 V15 P15 R18 P18 N15 M14 N17 N19 M15 M18 M19 U7 R10 V13 R19 I/O DESCRIPTION I/O Primary address/data bus. These signals make up the multiplexed PCI address and data bus on the primary interface. During the address phase of a primary bus PCI cycle, P_AD31-P_AD0 contain a 32-bit address or other destination information. During the data phase, P_AD31-P_AD0 contain data. I/O Primary bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During the address phase of a primary bus PCI cycle, P_C/BE3-P_C/BE0 define the bus command. During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. P_C/BE0 applies to byte 0 (P_AD7-P_AD0), P_C/BE1 applies to byte 1 (P_AD15-P_AD8), P_C/BE2 applies to byte 2 (P_AD23-P_AD16), and P_C/BE3 applies to byte 3 (P_AD31-P_AD24). 2-9 Table 2-6. Primary PCI Interface Control Terminals TERMINAL NAME PDV NO. 84 GHK NO. P11 I/O DESCRIPTION Primary device select. The bridge asserts P_DEVSEL to claim a PCI cycle as the target device. As a PCI master on the primary bus, the bridge monitors P_DEVSEL until a target responds. If no target responds before time-out occurs, then the bridge terminates the cycle with a master abort. Primary cycle frame. P_FRAME is driven by the master of a primary bus cycle. P_FRAME is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When P_FRAME is deasserted, the primary bus transaction is in the final data phase. Primary bus grant to bridge. P_GNT is driven by the primary PCI bus arbiter to grant the bridge access to the primary PCI bus after the current data transaction has completed. P_GNT may or may not follow a primary bus request, depending on the primary bus arbitration algorithm. Primary initialization device select. P_IDSEL selects the bridge during configuration space accesses. P_IDSEL can be connected to one of the upper 24 PCI address lines on the primary PCI bus. Note: There is no IDSEL signal interfacing the secondary PCI bus; thus, the entire configuration space of the bridge can only be accessed from the primary bus. Primary initiator ready. P_IRDY indicates ability of the primary bus master to complete the current data phase of the transaction. A data phase is completed on a rising edge of P_CLK where both P_IRDY and P_TRDY are asserted. Until P_IRDY and P_TRDY are both sampled asserted, wait states are inserted. Primary PCI bus lock. P_LOCK is used to lock the primary bus and gain exclusive access as a bus master. Primary parity. In all primary bus read and write cycles, the bridge calculates even parity across the P_AD and P_C/BE buses. As a bus master during PCI write cycles, the bridge outputs this parity indicator with a one-P_CLK delay. As a target during PCI read cycles, the calculated parity is compared to the parity indicator of the master; a miscompare can result in a parity error assertion (P_PERR). Primary parity error indicator. P_PERR is driven by a primary bus PCI device to indicate that calculated parity does not match P_PAR when P_PERR is enabled through bit 6 of the command register (PCI offset 04h, see Section 4.3). Primary PCI bus request. Asserted by the bridge to request access to the primary PCI bus as a master. Primary system error. Output pulsed from the bridge when enabled through the command register (PCI offset 04h, see Section 4.3) indicating a system error has occurred. The bridge needs not be the target of the primary PCI cycle to assert this signal. When bit 6 is enabled in the bridge control register (PCI offset 3Eh, see Section 4.32), this signal also pulses, indicating that a system error has occurred on one of the subordinate buses downstream from the bridge. Primary cycle stop signal. This signal is driven by a PCI target to request that the master stop the current primary bus transaction. This signal is used for target disconnects and is commonly asserted by target devices which do not support burst data transfers. Primary target ready. P_TRDY indicates the ability of the primary bus target to complete the current data phase of the transaction. A data phase is completed upon a rising edge of P_CLK where both P_IRDY and P_TRDY are asserted. Until both P_IRDY and P_TRDY are asserted, wait states are inserted. P_DEVSEL I/O P_FRAME 80 P10 I/O P_GNT 46 P3 I P_IDSEL 65 V7 I P_IRDY 82 V11 I/O P_LOCK 87 V12 I/O P_PAR 90 R12 I/O P_PERR P_REQ 88 47 U12 R1 I/O O P_SERR 89 P12 O P_STOP 85 R11 I/O P_TRDY 83 U11 I/O 2-10 Table 2-7. Secondary PCI System Terminals TERMINAL NAME S_CLKOUT9 S_CLKOUT8 S_CLKOUT7 S_CLKOUT6 S_CLKOUT5 S_CLKOUT4 S_CLKOUT3 S_CLKOUT2 S_CLKOUT1 S_CLKOUT0 S_CLK PDV NO. 42 41 39 38 36 35 33 32 30 29 21 GHK NO. N6 N3 N1 M5 M3 M2 L5 L6 L2 L1 J3 I/O DESCRIPTION O Secondary PCI bus clocks. Provide timing for all transactions on the secondary PCI bus. Each secondary bus device samples all secondary PCI signals at the rising edge of its corresponding S_CLKOUT input. I Secondary PCI bus clock input. This input synchronizes the PCI2050 to the secondary bus clocks. Secondary external arbiter enable. When this signal is high, the secondary external arbiter is enabled. When the external arbiter is enabled, the PCI2050 S_REQ0 terminal is reconfigured as a secondary bus grant input to the bridge and S_GNT0 is reconfigured as a secondary bus master request to the external arbiter on the secondary bus. Secondary PCI reset. S_RST is a logical OR of P_RST and the state of the secondary bus reset bit (bit 6) of the bridge control register (PCI offset 3Eh, see Section 4.32). S_RST is asynchronous with respect to the state of the secondary interface CLK signal. S_CFN 23 J6 I S_RST 22 J5 O 2-11 Table 2-8. Secondary PCI Address and Data Terminals TERMINAL NAME S_AD31 S_AD30 S_AD29 S_AD28 S_AD27 S_AD26 S_AD25 S_AD24 S_AD23 S_AD22 S_AD21 S_AD20 S_AD19 S_AD18 S_AD17 S_AD16 S_AD15 S_AD14 S_AD13 S_AD12 S_AD11 S_AD10 S_AD9 S_AD8 S_AD7 S_AD6 S_AD5 S_AD4 S_AD3 S_AD2 S_AD1 S_AD0 S_C/BE3 S_C/BE2 S_C/BE1 S_C/BE0 PDV NO. 206 204 203 201 200 198 197 195 192 191 189 188 186 185 183 182 165 164 162 161 159 154 152 150 147 146 144 143 141 140 138 137 194 180 167 149 GHK NO. E6 F6 A5 E7 B6 F7 C7 A7 C8 B8 E9 F9 B9 A9 E10 C10 E13 B14 A15 B15 E14 F15 F14 F17 F19 G14 G18 G19 H14 H17 H19 J15 E8 A10 F12 G15 I/O DESCRIPTION I/O Secondary address/data bus. These signals make up the multiplexed PCI address and data bus on the secondary interface. During the address phase of a secondary bus PCI cycle, S_AD31-S_AD0 contain a 32-bit address or other destination information. During the data phase, S_AD31-S_AD0 contain data. I/O Secondary bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During the address phase of a secondary bus PCI cycle, S_C/BE3-S_C/BE0 define the bus command. During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. S_C/BE0 applies to byte 0 (S_AD7-S_AD0), S_C/BE1 applies to byte 1 (S_AD15-S_AD8), S_C/BE2 applies to byte 2 (S_AD23-S_AD16), and S_C/BE3 applies to byte 3 (S_AD31-S_AD24). Secondary device select. The bridge asserts S_DEVSEL to claim a PCI cycle as the target device. As a PCI master on the secondary bus, the bridge monitors S_DEVSEL until a target responds. If no target responds before time-out occurs, then the bridge terminates the cycle with a master abort. Secondary cycle frame. S_FRAME is driven by the master of a secondary bus cycle. S_FRAME is asserted to indicate that a bus transaction is beginning and data transfers continue while S_FRAME is asserted. When S_FRAME is deasserted, the secondary bus transaction is in the final data phase. S_DEVSEL 175 A11 I/O S_FRAME S_GNT8 S_GNT7 S_GNT6 S_GNT5 S_GNT4 S_GNT3 S_GNT2 S_GNT1 S_GNT0 179 19 18 17 16 15 14 13 11 10 F11 J1 H1 H2 H3 H5 G1 G2 H6 F1 I/O O Secondary bus grant to the bridge. The bridge provides internal arbitration and these signals are used to grant potential secondary PCI bus masters access to the bus. Ten potential masters (including the bridge) can be located on the secondary PCI bus. When the internal arbiter is disabled, S_GNT0 is reconfigured as an external secondary bus request signal for the bridge. 2-12 Table 2-9. Secondary PCI Interface Control Terminals TERMINAL NAME PDV NO. 177 GHK NO. C11 I/O DESCRIPTION Secondary initiator ready. S_IRDY indicates the ability of the secondary bus master to complete the current data phase of the transaction. A data phase is completed on a rising edge of S_CLK where both S_IRDY and S_TRDY are asserted; until S_IRDY and S_TRDY are asserted, wait states are inserted. Secondary PCI bus lock. S_LOCK is used to lock the secondary bus and gain exclusive access as a master. Secondary parity. In all secondary bus read and write cycles, the bridge calculates even parity across the S_AD and S_C/BE buses. As a master during PCI write cycles, the bridge outputs this parity indicator with a one-S_CLK delay. As a target during PCI read cycles, the calculated parity is compared to the master parity indicator. A miscompare can result in a parity error assertion (S_PERR). Secondary parity error indicator. S_PERR is driven by a secondary bus PCI device to indicate that calculated parity does not match S_PAR when enabled through the command register (PCI offset 04h, see Section 4.3). S_IRDY I/O S_LOCK 172 C12 I/O S_PAR 168 C13 I/O S_PERR S_REQ8 S_REQ7 S_REQ6 S_REQ5 S_REQ4 S_REQ3 S_REQ2 S_REQ1 S_REQ0 S_SERR 171 9 8 7 6 5 4 3 2 207 169 E12 G5 F2 F3 E1 E2 G6 F5 E3 C5 B13 I/O I Secondary PCI bus request signals. The bridge provides internal arbitration, and these signals are used as inputs from secondary PCI bus masters requesting the bus. Ten potential masters (including the bridge) can be located on the secondary PCI bus. When the internal arbiter is disabled, the S_REQ0 signal is reconfigured as an external secondary bus grant for the bridge. I Secondary system error. S_SERR is passed through the primary interface by the bridge if enabled through the bridge control register (PCI offset 3Eh, see Section 4.32). S_SERR is never asserted by the bridge. Secondary cycle stop signal. S_STOP is driven by a PCI target to request that the master stop the current secondary bus transaction. S_STOP is used for target disconnects and is commonly asserted by target devices that do not support burst data transfers. Secondary target ready. S_TRDY indicates the ability of the secondary bus target to complete the current data phase of the transaction. A data phase is completed on a rising edge of S_CLK where both S_IRDY and S_TRDY are asserted; until S_IRDY and S_TRDY are asserted, wait states are inserted. S_STOP 173 B12 I/O S_TRDY 176 B11 I/O Table 2-10. Miscellaneous Terminals TERMINAL NAME PDV NO. GHK NO. I/O DESCRIPTION Bus/power clock control management terminal. When signal BPCCE is tied high, and when the PCI2050 is placed in the D3 power state, it enables the PCI2050 to place the secondary bus in the B2 power state. The PCI2050 disables the secondary clocks and drives them to 0. When tied low, placing the PCI2050 in the D3 power state has no effect on the secondary bus clocks. General-purpose I/O terminals I GPIO3 is HSSWITCH in cPCI mode. HSSWITCH provides the status of the ejector handle switch to the cPCI logic. O O I I NC O Hot-swap ENUM Hot-swap LED output Mode select 0 Mode select 1 These terminals have no function on the PCI2050. Secondary bus 66-MHz enable terminal. This terminal is always driven low to indicate that the secondary bus speed is 33 MHz. BPCCE 44 P2 I GPIO3/HSSWITCH GPIO2 GPIO1 GPIO0 HSENUM HSLED MS0 MS1 NC S_M66ENA 24 25 27 28 127 128 155 106 102 125 153 K1 K2 K5 K6 L14 K19 E17 R17 R14 L17 E18 2-13 Table 2-11. JTAG Interface Terminals TERMINAL NAME TCK TDI TDO TMS TRST PDV NO. 133 129 130 132 134 GHK NO. J19 K18 K17 K14 J18 I/O I I O I I DESCRIPTION JTAG boundary-scan clock. TCK is the clock controlling the JTAG logic. JTAG serial data in. TDI is the serial input through which JTAG instructions and test data enter the JTAG interface. The new data on TDI is sampled on the rising edge of TCK. JTAG serial data out. TDO is the serial output through which test instructions and data from the test logic leave the PCI2050. JTAG test mode select. TMS causes state transitions in the test access port controller. JTAG TAP reset. When TRST is asserted low, the TAP controller is asynchronously forced to enter a reset state and initialize the test logic. Table 2-12. Power Supply Terminals TERMINAL NAME PDV NO. 12, 20, 31, 37, 48, 52, 54, 59, 66, 72, 78, 86, 94, 100, 104, 111, 117, 123, 136, 142, 148, 156, 158, 160, 166, 174, 181, 187, 193, 199, 205 1, 26, 34, 40, 51, 53, 56, 62, 69, 75, 81, 91, 97, 103, 105, 108, 114, 120, 131, 139, 145, 151, 157, 163, 170, 178, 184, 190, 196, 202, 208 124 135 GHK NO. A6, A12, A14, B5, B10, C9, C15, D19, F8, F13, F18, G3, H15, J2, J14, L3, L19, M6, N18, P6, P13, P14, P17, T1, U5, U6, U10, V9, W7, W12, W16 A4, A8, A13, A16, B7, C6, C14, D1, E11, E19, F10, G17, H18, K3, K15, M1, M17, N2, N14, P7, P9, P19, R3, R13, T19, U15, V8, W4, W6, W11, W13 L18 J17 DESCRIPTION GND Device ground terminals VCC Power-supply terminal for core logic (3.3 V) P_VCCP S_VCCP Primary bus-signaling environment supply. P_VCCP is used in protection circuitry on primary bus I/O signals. Secondary bus-signaling environment supply. S_VCCP is used in protection circuitry on secondary bus I/O signals. 2-14 3 Feature/Protocol Descriptions The following sections give an overview of the PCI2050 PCI-to-PCI bridge features and functionality. Figure 3-1 shows a simplified block diagram of a typical system implementation using the PCI2050. Host Bus CPU Memory Host Bridge PCI Bus 0 PCI Device PCI Device PCI Option Card PCI2050 PCI Bus 2 PCI Bus 1 PCI2050 PCI Device PCI Device (Option) PCI Option Card PCI Option Slot Figure 3-1. System Block Diagram 3.1 Introduction to the PCI2050 The PCI2050 is a bridge between two PCI buses and is compliant with both the PCI Local Bus Specification and the PCI-to-PCI Bridge Specification. The bridge supports two 32-bit PCI buses operating at a maximum of 33 MHz. The primary and secondary buses operate independently in either a 3.3-V or 5-V signaling environment. The core logic of the bridge, however, is powered at 3.3 V to reduce power consumption. Host software interacts with the bridge through internal registers. These internal registers provide the standard PCI status and control for both the primary and secondary buses. Many vendor-specific features that exist in the TI extension register set are included in the bridge. The PCI configuration header of the bridge is only accessible from the primary PCI interface. The bridge provides internal arbitration for the nine possible secondary bus masters, and provides each with a dedicated active-low request/grant pair (REQ/GNT). The arbiter features a two-tier rotational scheme with the PCI2050 bridge defaulting to the highest priority tier. Upon system power up, power-on self-test (POST) software configures the bridge according to the devices that exist on subordinate buses, and enables performance-enhancing features of the PCI2050. In a typical system, this is the only communication with the bridge internal register set. 3-1 3.2 PCI Commands The bridge responds to PCI bus cycles as a PCI target device based on internal register settings and on the decoding of each address phase. Table 3-1 lists the valid PCI bus cycles and their encoding on the command/byte enable (C/BE) bus during the address phase of a bus cycle. Table 3-1. PCI Command Definition C/BE3-C/BE0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 COMMAND Interrupt acknowledge Special cycle I/O read I/O write Reserved Reserved Memory read Memory write Reserved Reserved Configuration read Configuration write Memory read multiple Dual address cycle Memory read line Memory write and invalidate The bridge never responds as a PCI target to the interrupt acknowledge, special cycle, or reserved commands. The bridge does, however, initiate special cycles on both interfaces when a type 1 configuration cycle issues the special cycle request. The remaining PCI commands address either memory, I/O, or configuration space. The bridge accepts PCI cycles by asserting DEVSEL as a medium-speed device, i.e., DEVSEL is asserted two clock cycles after the address phase. The PCI2050 converts memory write and invalidate commands to memory write commands when forwarding transactions from either the primary or secondary side of the bridge if the bridge cannot guarantee that an entire cache line will be delivered. 3.3 Configuration Cycles PCI Local Bus Specification defines two types of PCI configuration read and write cycles: type 0 and type 1. The bridge decodes each type differently. Type 0 configuration cycles are intended for devices on the primary bus, while type 1 configuration cycles are intended for devices on some hierarchically subordinate bus. The difference between these two types of cycles is the encoding of the primary PCI (P_AD) bus during the address phase of the cycle. Figure 3-2 shows the P_AD bus encoding during the address phase of a type 0 configuration cycle. The 6-bit register number field represents an 8-bit address with the two lower bits masked to 0, indicating a doubleword boundary. This results in a 256-byte configuration address space per function per device. Individual byte accesses may be selected within a doubleword by using the P_C/BE signals during the data phase of the cycle. 31 Reserved 11 10 8 7 Register Number 2 1 0 0 0 Function Number Figure 3-2. PCI AD31-AD0 During Address Phase of a Type 0 Configuration Cycle The bridge claims only type 0 configuration cycles when its P_IDSEL terminal is asserted during the address phase of the cycle and the PCI function number encoded in the cycle is 0. If the function number is 1 or greater, then the 3-2 bridge does not recognize the configuration command. In this case, the bridge does not assert DEVSEL, and the configuration transaction results in a master abort. The bridge services valid type 0 configuration read or write cycles by accessing internal registers from the bridge configuration header (see Table 4-1). Because type 1 configuration cycles are issued to devices on subordinate buses, the bridge claims type 1 cycles based on the bus number of the destination bus. The P_AD bus encoding during the address phase of a type 1 cycle is shown in Figure 3-3. The device number and bus number fields define the destination bus and device for the cycle. 31 Reserved 24 23 Bus Number 16 15 Device Number 11 10 8 7 Register Number 2 1 0 0 1 Function Number Figure 3-3. PCI AD31-AD0 During Address Phase of a Type 1 Configuration Cycle Several bridge configuration registers shown in Table 4-1 are significant when decoding and claiming type 1 configuration cycles. The destination bus number encoded on the P_AD bus is compared to the values programmed in the bridge configuration registers 18h, 19h, and 1Ah, which are the primary bus number, secondary bus number, and subordinate bus number registers, respectively. These registers default to 00h and are programmed by host software to reflect the bus hierarchy in the system (see Figure 3-4 for an example of a system bus hierarchy and how the PCI2050 bus number registers would be programmed in this case). PCI Bus 0 PCI2050 Primary Bus Secondary Bus Subordinate Bus 00h 01h 02h PCI2050 Primary Bus Secondary Bus Subordinate Bus 00h 03h 03h PCI Bus 1 PCI Bus 3 PCI2050 Primary Bus Secondary Bus Subordinate Bus 01h 02h 02h PCI Bus 2 Figure 3-4. Bus Hierarchy and Numbering When the PCI2050 claims a type 1 configuration cycle that has a bus number equal to its secondary bus number, the PCI2050 converts the type 1 configuration cycle to a type 0 configuration cycle and asserts the proper S_AD line as the IDSEL (see Table 3-2). All other type 1 transactions that access a bus number greater than the bridge secondary bus number but less than or equal to its subordinate bus number are forwarded as type 1 configuration cycles. 3-3 Table 3-2. PCI S_AD31-S_AD16 During the Address Phase of a Type 0 Configuration Cycle DEVICE NUMBER 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh 10h-1Eh SECONDARY IDSEL S_AD31-S_AD16 0000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0001 0000 0000 0000 0010 0000 0000 0000 0100 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 S_AD ASSERTED 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 - 3.4 Special Cycle Generation The bridge is designed to generate special cycles on both buses through a type 1 cycle conversion. During a type 1 configuration cycle, if the bus number field matches the bridge secondary bus number, the device number field is 1Fh, and the function number field is 07h, then the bridge generates a special cycle on the secondary bus with a message that matches the type 1 configuration cycle data. If the bus number is a subordinate bus and not the secondary, then the bridge passes the type 1 special cycle request through to the secondary interface along with the proper message. Special cycles are never passed through the bridge. Type 1 configuration cycles with a special cycle request can propagate in both directions. 3.5 Secondary Clocks The PCI2050 provides 10 secondary clock outputs (S_CLKOUT[0:9]). Nine are provided for clocking secondary devices. The tenth clock should be routed back into the PCI2050 S_CLK input to ensure all secondary bus devices see the same clock. Figure 3-5 is a block diagram of the secondary clock function. 3-4 PCI2050 S_CLK S_CLKOUT9 S_CLKOUT8 PCI Device S_CLKOUT2 PCI Device S_CLKOUT1 PCI Device S_CLKOUT0 PCI Device Figure 3-5. Secondary Clock Block Diagram 3.6 Bus Arbitration The PCI2050 implements bus request (P_REQ) and bus grant (P_GNT) terminals for primary PCI bus arbitration. Nine secondary bus requests and nine secondary bus grants are provided on the secondary of the PCI2050. Ten potential initiators, including the bridge, can be located on the secondary bus. The PCI2050 provides a two-tier arbitration scheme on the secondary bus for priority bus-master handling. The two-tier arbitration scheme improves performance in systems in which master devices do not all require the same bandwidth. Any master that requires frequent use of the bus can be programmed to be in the higher priority tier. 3.6.1 Primary Bus Arbitration The PCI2050, acting as an initiator on the primary bus, asserts P_REQ when forwarding transactions upstream to the primary bus. If a target disconnect, a target retry, or a target abort is received in response to a transaction initiated on the primary bus by the PCI2050, then the device deasserts P_REQ for two PCI clock cycles. When the primary bus arbiter asserts P_GNT in response to a P_REQ from the PCI2050, the device initiates a transaction on the primary bus during the next PCI clock cycle after the primary bus is sampled idle. When P_REQ is not asserted and the primary bus arbiter asserts P_GNT to the PCI2050, the device responds by parking the P_AD31-P_AD0 bus, the C/BE3-C/BE0 bus, and primary parity (P_PAR) by driving them to valid logic levels. If the PCI2050 is parking the primary bus and wants to initiate a transaction on the bus, then it can start the transaction on the next PCI clock by asserting the primary cycle frame (P_FRAME) while P_GNT is still asserted. If P_GNT is deasserted, then the bridge must rearbitrate for the bus to initiate a transaction. 3.6.2 Internal Secondary Bus Arbitration S_CFN controls the state of the secondary internal arbiter. The internal arbiter can be enabled by pulling S_CFN low or disabled by pulling S_CFN high. The PCI2050 provides nine secondary bus request terminals and nine secondary 3-5 bus grant terminals. Including the bridge, there are a total of ten potential secondary bus masters. These request and grant signals are connected to the internal arbiter. When an external arbiter is implemented, S_REQ8-S_REQ1 and S_GNT8-S_GNT1 are placed in a high-impedance mode. 3.6.3 External Secondary Bus Arbitration An external secondary bus arbiter can be used instead of the PCI2050 internal bus arbiter. When using an external arbiter, the PCI2050 internal arbiter should be disabled by pulling S_CFN high. When an external secondary bus arbiter is used, the PCI2050 internally reconfigures the S_REQ0 and S_GNT0 signals so that S_REQ0 becomes the secondary bus grant for the bridge and S_GNT0 becomes the secondary bus request for the bridge. This is done because S_REQ0 is an input and can thus be used to provide the grant input to the bridge, and S_GNT0 is an output and can thus provide the request output from the bridge. When an external arbiter is used, all unused secondary bus grant outputs (S_GNT8-S_GNT1) are placed in a high impedance mode. Any unused secondary bus request inputs (S_REQ8-S_REQ1) should be pulled high to prevent the inputs from oscillating. 3.7 Decode Options The PCI2050 supports positive decoding on the primary interface and negative decoding on the secondary interface. Positive decoding is a method of address decoding in which a device responds only to accesses within an assigned address range. Negative decoding is a method of address decoding in which a device responds only to accesses outside of an assigned address range. 3.8 System Error Handling The PCI2050 can be configured to signal a system error (SERR) for a variety of conditions. The P_SERR event disable register (offset 64h, see Section 5.4) and the P_SERR status register (offset 6Ah, see Section 5.9) provide control and status bits for each condition for which the bridge can signal SERR. These individual bits enable SERR reporting for both downstream and upstream transactions. By default, the PCI2050 will not signal SERR. If the PCI2050 is configured to signal SERR by setting bit 8 in the command register (offset 04h, see Section 4.3), then the bridge signals SERR if any of the error conditions in the P_SERR event disable register occur and that condition is enabled. By default, all error conditions are enabled in the P_SERR event disable register. When the bridge signals SERR, bit 14 in the secondary status register (offset 1Eh, see Section 4.19) is set. 3.8.1 Posted Write Parity Error If bit 1 in the P_SERR event disable register (offset 64h, see Section 5.4) is 0, then parity errors on the target bus during a posted write are passed to the initiating bus as a SERR. When this occurs, bit 1 of the P_SERR status register (offset 6Ah, see Section 5.9) is set. The status bit is cleared by writing a 1. 3.8.2 Posted Write Time-Out If bit 2 in the P_SERR event disable register (offset 64h, see Section 5.4) is 0 and the retry timer expires while attempting to complete a posted write, then the PCI2050 signals SERR on the initiating bus. When this occurs, bit 2 of the P_SERR status register (offset 6Ah, see Section 5.9) is set. The status bit is cleared by writing a 1. 3.8.3 Target Abort on Posted Writes If bit 3 in the P_SERR event disable register (offset 64h, see Section 5.4) is 0 and the bridge receives a target abort during a posted write transaction, then the PCI2050 signals SERR on the initiating bus. When this occurs, bit 3 of the P_SERR status register (offset 6Ah, see Section 5.9) is set. The status bit is cleared by writing a 1. 3-6 3.8.4 Master Abort on Posted Writes If bit 4 in the P_SERR event disable register (PCI offset 64h, see Section 5.4) is 0 and a posted write transaction results in a master abort, then the PCI2050 signals SERR on the initiating bus. When this occurs, bit 4 of the P_SERR status register (PCI offset 6Ah, see Section 5.9) is set. The status bit is cleared by writing a 1. 3.8.5 Master Delayed Write Time-Out If bit 5 in the P_SERR event disable register (PCI offset 64h, see Section 5.4) is 0 and the retry timer expires while attempting to complete a delayed write, then the PCI2050 signals SERR on the initiating bus. When this occurs, bit 5 of the P_SERR status register (PCI offset 6Ah, see Section 5.9) is set. The status bit is cleared by writing a 1. 3.8.6 Master Delayed Read Time-Out If bit 6 in the P_SERR event disable register (offset 64h, see Section 5.4) is 0 and the retry timer expires while attempting to complete a delayed read, then the PCI2050 signals SERR on the initiating bus. When this occurs, bit 6 of the P_SERR status register (offset 6Ah, see Section 5.9) is set. The status bit is cleared by writing a 1. 3.8.7 Secondary SERR The PCI2050 passes SERR from the secondary bus to the primary bus if it is enabled for SERR response, that is, if bit 8 in the command register (PCI offset 04h, see Section 4.3) is set, and if bit 1 in the bridge control register (PCI offset 3Eh, see Section 4.32) is set. 3.9 Parity Handling and Parity Error Reporting When forwarding transactions, the PCI2050 attempts to pass the data parity condition from one interface to the other unchanged, whenever possible, to allow the master and target devices to handle the error condition. 3.9.1 Address Parity Error If the parity error response bit (bit 6) in the command register (PCI offset 04h, see Section 4.3) is set, then the PCI2050 signals SERR on address parity errors and target abort transactions. 3.9.2 Data Parity Error If the parity error response bit (bit 6) in the command register (PCI offset 04h, see Section 4.3) is set, then the PCI2050 signals PERR when it receives bad data. When the bridge detects bad parity, bit 15 (detected parity error) in the status register (PCI offset 06h, see Section 4.4) is set. If the bridge is configured to respond to parity errors via bit 6 in the command register (PCI offset 04h, see Section 4.3), then bit 8 (data parity error detected) in the status register (PCI offset 06h, see Section 4.4) is set when the bridge detects bad parity. The data parity error detected bit is also set when the bridge, as a bus master, asserts PERR or detects PERR. 3.10 Master and Target Abort Handling If the PCI2050 receives a target abort during a write burst, then it signals target abort back on the initiator bus. If it receives a target abort during a read burst, then it provides all of the valid data on the initiator bus and disconnects. Target aborts for posted and nonposted transactions are reported as specified in the PCI-to-PCI Bridge Specification. Master aborts for posted and nonposted transactions are reported as specified in the PCI-to-PCI Bridge Specification. If a transaction is attempted on the primary bus after a secondary reset is asserted, then the PCI2050 follows bit 5 (master abort mode) in the bridge control register (PCI offset 3Eh, see Section 4.32) for reporting errors. 3.11 Discard Timer The PCI2050 is free to discard the data or status of a delayed transaction that was completed with a delayed transaction termination when a bus master has not repeated the request within 210 or 215 PCI clocks (approximately 3-7 30 s and 993 s, respectively). The PCI Local Bus Specification recommends that a bridge wait 215 PCI clocks before discarding the transaction data or status. The PCI2050 implements a discard timer for use in delayed transactions. After a delayed transaction is completed on the destination bus, the bridge may discard it under two conditions. The first condition occurs when a read transaction is made to a region of memory that is inside a defined prefetchable memory region, or when the command is a memory read line or a memory read multiple, implying that the memory region is prefetchable. The other condition occurs when the master originating the transaction (either a read or a write, prefetchable or nonprefetchable) has not retried the transaction within 210 or 215 clocks. The number of clocks is tracked by a timer referred to as the discard timer. When the discard timer expires, the bridge is required to discard the data. The PCI2050 default value for the discard timer is 215 clocks; however, this value can be set to 210 clocks by setting bit 9 in the bridge control register (offset 3Eh, see Section 4.32). For more information on the discard timer, see error conditions in the PCI Local Bus Specification. 3.12 Delayed Transactions The bridge supports delayed transactions as defined in PCI Local Bus Specification. A target must be able to complete the initial data phase in 16 PCI clocks or less from the assertion of the cycle frame (FRAME), and subsequent data phases must complete in eight PCI clocks or less. A delayed transaction consists of three phases: * * * An initiator device issues a request. The target completes the request on the destination bus and signals the completion to the initiator. The initiator completes the request on the originating bus. If the bridge is the target of a PCI transaction and it must access a slow device to write or read the requested data, and the transaction takes longer than 16 clocks, then the bridge must latch the address, the command, and the byte enables, and then issue a retry to the initiator. The initiator must end the transaction without any transfer of data and is required to retry the transaction later using the same address, command, and byte enables. This is the first phase of the delayed transaction. During the second phase, if the transaction is a read cycle, the bridge fetches the requested data on the destination bus, stores it internally, and obtains the completion status, thus completing the transaction on the destination bus. If it is a write transaction, then the bridge writes the data and obtains the completion status, thus completing the transaction on the destination bus. The bridge stores the completion status until the master on the initiating bus retries the initial request. During the third phase, the initiator rearbitrates for the bus. When the bridge sees the initiator retry the transaction, it compares the second request to the first request. If the address, command, and byte enables match the values latched in the first request, then the completion status (and data if the request was a read) is transferred to the initiator. At this point, the delayed transaction is complete. If the second request from the initiator does not match the first request exactly, then the bridge issues another retry to the initiator. The PCI supports up to three delayed transactions in each direction at any given time. 3.13 Mode Selection Table 3-3 shows the mode selection via MS0 (PDV terminal 155, GHK terminal E17) and MS1 (PDV terminal 106, GHK terminal R17). 3-8 Table 3-3. Configuration via MS0 and MS1 MS0 0 MS1 0 MODE CompactPCI hot-swap friendly PCI Bus Power Management Interface Specification Revision 1.1 HSSWITCH/GPIO(3) functions as HSSWITCH CompactPCI hot-swap disabled PCI Bus Power Management Interface Specification Revision 1.1 HSSWITCH/GPIO(3) functions as GPIO(3) IntelTM compatible No cPCI hot swap PCI Bus Power Management Interface Specification Revision 1.0 0 1 1 X 3.14 CompactPCI Hot-Swap Support The PCI2050 is hot-swap friendly silicon that supports all of the hot-swap capable features, contains support for software control, and integrates circuitry required by the PICMG CompactPCI Hot-Swap Specification. To be hot-swap capable, the PCI2050 supports the following: * * * * * * * * Compliance with PCI Local Bus Specification Tolerance of VCC from early power Asynchronous reset Tolerance of precharge voltage I/O buffers that meet modified V/I requirements Limited I/O terminal voltage at precharge voltage Hot-swap control and status programming via extended PCI capabilities linked list Hot-swap terminals: HS_ENUM, HS_SWITCH, and HS_LED cPCI hot-swap defines a process for installing and removing PCI boards without adversely affecting a running system. The PCI2050 provides this functionality such that it can be implemented on a board that can be removed and inserted in a hot-swap system. The PCI2050 provides three terminals to support hot-swap when configured to be in hot-swap mode: HS_ENUM (output), HS_SWITCH (input), and HS_LED (output). The HS_ENUM output indicates to the system that an insertion event occurred or that a removal event is about to occur. The HS_SWITCH input indicates the state of a board ejector handle, and the HS_LED output lights a blue LED to signal insertion- and removal-ready status. 3-9 3.15 JTAG Support The PCI2050 implements a JTAG test port based on IEEE Standard 1149.1, IEEE Standard Test Access Port and Boundary-Scan Architecture. The JTAG test port consists of the following: * * * * * A 5-wire test access port A test access port controller An instruction register A bypass register A boundary-scan register 3.15.1 Test Port Instructions The PCI2050 supports the following JTAG instructions: * EXTEST, BYPASS, and SAMPLE * HIGHZ and CLAMP * Private (various private instructions used by TI for test purposes) Table 3-4 lists and describes the different test port instructions, and gives the op code of each one. The information in Table 3-5 is for implementation of boundary scan interface signals to permit in-circuit testing. Table 3-4. JTAG Instructions and Op Codes INSTRUCTION EXTEST SAMPLE CLAMP HIGHZ BYPASS OP CODE 00000 00001 00100 00101 11111 Sample I/O terminals Drives terminals from the boundary scan register and selects the bypass register for shifts Puts all outputs and I/O terminals except for the TDO terminal in a high-impedance state Selects the bypass register for shifts DESCRIPTION External test: drives terminals from the boundary scan register Table 3-5. Boundary Scan Terminal Order BOUNDARY SCAN REGISTER NO. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 PDV TERMINAL NUMBER 137 138 140 141 143 144 146 147 149 150 152 153 154 155 158 161 162 164 165 - GHK TERMINAL NUMBER J15 H19 H17 H14 G19 G18 G14 F19 G15 F17 F14 E18 F15 E17 C15 B15 A15 B14 E13 - TERMINAL NAME S_AD0 S_AD1 S_AD2 S_AD3 S_AD4 S_AD5 S_AD6 S_AD7 S_C/BE0 S_AD8 S_AD9 S_M66ENA S_AD10 MS0 S_AD11 S_AD12 S_AD13 S_AD14 S_AD15 - GROUP DISABLE REGISTER 19 19 19 19 19 19 19 19 19 19 19 19 19 - 19 19 19 19 19 - BOUNDARY-SCAN CELL TYPE Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Input Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Control 3-10 Table 3-5. Boundary Scan Terminal Order (continued) BOUNDARY SCAN REGISTER NO. 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 PDV TERMINAL NUMBER 167 168 169 171 172 173 - 175 176 177 179 180 182 183 185 186 188 189 191 192 194 195 197 198 200 201 203 204 - 206 207 2 3 4 5 6 7 8 9 10 11 - GHK TERMINAL NUMBER F12 C13 B13 E13 C12 B12 - A11 B11 C11 F11 A10 C10 E10 A9 B9 F9 E9 B8 C8 E8 A7 C7 F7 B6 E7 A5 F6 - E6 C5 E3 F5 G6 E2 E1 F3 F2 G5 F1 H6 - TERMINAL NAME S_C/BE1 S_PAR S_SERR S_PERR S_LOCK S_STOP - S_DEVSEL S_TRDY S_IRDY S_FRAME S_C/BE2 S_AD16 S_AD17 S_AD18 S_AD19 S_AD20 S_AD21 S_AD22 S_AD23 S_C/BE3 S_AD24 S_AD25 S_AD26 S_AD27 S_AD28 S_AD29 S_AD30 - S_AD31 S_REQ0 S_REQ1 S_REQ2 S_REQ3 S_REQ4 S_REQ5 S_REQ6 S_REQ7 S_REQ8 S_GNT0 S_GNT1 - GROUP DISABLE REGISTER 19 19 - 26 26 26 - 26 26 26 26 48 48 48 48 48 48 48 48 48 48 48 48 48 48 48 48 48 - 48 - - - - - - - - - 61 61 - BOUNDARY-SCAN CELL TYPE Bidirectional Bidirectional Input Bidirectional Bidirectional Bidirectional Control Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Control Bidirectional Input Input Input Input Input Input Input Input Input Output Output Control 3-11 Table 3-5. Boundary Scan Terminal Order (continued) BOUNDARY SCAN REGISTER NO. 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 PDV TERMINAL NUMBER 13 14 15 16 17 18 19 21 22 23 24 25 27 28 29 30 - 32 33 35 36 38 39 41 42 43 44 45 46 47 - 49 50 55 57 58 60 61 63 64 65 67 68 GHK TERMINAL NUMBER G2 G1 H5 H3 H2 H1 J1 J3 J5 J6 K1 K2 K5 K6 L1 L2 - L6 L5 M2 M3 M5 N1 N3 N6 P1 P2 N5 P3 R1 - R2 P5 R6 V5 W5 V6 R7 W6 U7 V7 R8 U8 TERMINAL NAME S_GNT2 S_GNT3 S_GNT4 S_GNT5 S_GNT6 S_GNT7 S_GNT8 S_CLK S_RST S_CFN GPIO3 GPIO2 GPIO1 GPIO0 S_CLKOUT0 S_CLKOUT1 - S_CLKOUT2 S_CLKOUT3 S_CLKOUT4 S_CLKOUT5 S_CLKOUT6 S_CLKOUT7 S_CLKOUT8 S_CLKOUT9 P_RST BPCCE P_CLK P_GNT P_REQ - P_AD31 P_AD30 P_AD29 P_AD28 P_AD27 P_AD26 P_AD25 P_AD24 P_C/BE3 P_IDSEL P_AD23 P_AD22 GROUP DISABLE REGISTER 61 61 61 61 61 61 61 - 78 - 78 78 78 78 - - - - - - - - - - - - - - - 92 - 111 111 111 111 111 111 111 111 111 - 111 111 BOUNDARY-SCAN CELL TYPE Output Output Output Output Output Output Output Input Output Input Bidirectional Bidirectional Bidirectional Bidirectional Output Output Output Output Output Output Output Output Output Output Output Input Input Input Input Output Control Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Input Bidirectional Bidirectional 3-12 Table 3-5. Boundary Scan Terminal Order (continued) BOUNDARY SCAN REGISTER NO. 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 PDV TERMINAL NUMBER 70 71 73 74 76 77 - 79 80 82 83 84 85 - 87 88 89 90 92 93 95 96 98 99 101 106 107 109 110 112 113 115 116 118 119 121 122 - 126 - 127 128 GHK TERMINAL NUMBER W8 W9 U9 R9 W10 V10 - R10 P10 V11 U11 P11 R11 - V12 U12 P12 R12 V13 U13 W14 V14 U14 W15 V15 R17 P15 R18 R19 P18 N15 M14 N17 N19 M15 M18 M19 - L15 - L14 K19 GROUP DISABLE REGISTER 111 111 111 111 111 111 - 111 118 118 118 118 118 - 118 118 142 142 142 142 142 142 142 142 142 - 142 142 142 142 142 142 142 142 142 142 142 - - - 144 144 BOUNDARY-SCAN CELL TYPE Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Control Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Control Input Bidirectional Output Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Input Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional - Input Control Output Output TERMINAL NAME P_AD21 P_AD20 P_AD19 P_AD18 P_AD17 P_AD16 - P_C/BE2 P_FRAME P_IRDY P_TRDY P_DEVSEL P_STOP - P_LOCK P_PERR P_SERR P_PAR P_C/BE1 P_AD15 P_AD14 P_AD13 P_AD12 P_AD11 P_AD10 MS1 P_AD9 P_AD8 P_C/BE0 P_AD7 P_AD6 P_AD5 P_AD4 P_AD3 P_AD2 P_AD1 P_AD0 - MSK_IN - HS_ENUM HS_LED 3-13 3.16 GPIO Interface The PCI2050 implements a four-terminal general-purpose I/O interface. Besides functioning as a general-purpose I/O interface, the GPIO terminals can be used to read in the secondary clock mask and to stop the bridge from accepting I/O and memory transactions. 3.16.1 Secondary Clock Mask The PCI2050 uses GPIO0, GPIO2, and MSK_IN to shift in the secondary clock mask from an external shift register. A secondary clock mask timing diagram is shown in Figure 3-6. Table 3-6 lists the format for clock mask data. MSK_IN Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GPIO2 GPIO0 P_RST S_RST Figure 3-6. Clock Mask Read Timing After Reset Table 3-6. Clock Mask Data Format BIT [0:1] [2:3] [4:5] [6:7] 8 9 10 11 12 13 [14:15] CLOCK S_CLKOUT0 S_CLKOUT1 S_CLKOUT2 S_CLKOUT3 S_CLKOUT4 S_CLKOUT5 S_CLKOUT6 S_CLKOUT7 S_CLKOUT8 S_CLKOUT9 (PCI2050 S_CLK input) Reserved 3.16.2 Transaction Forwarding Control The PCI 2050 will stop forwarding I/O and memory transactions if bit 5 of the chip control register (offset 40h, see Section 5.1) is set to 1 and GPIO3 is driven high. The bridge will complete all queued posted writes and delayed requests, but delayed completions will not be returned until GPIO3 is driven low and transaction forwarding is resumed. The bridge will continue to accept configuration cycles in this mode. This feature is not available when in CompactPCI hot-swap mode because GPIO3 is used as the HS_SWITCH input in this mode. 3-14 3.17 PCI Power Management The PCI Power Management Specification establishes the infrastructure required to let the operating system control the power of PCI functions. This is done by defining a standard PCI interface and operations to manage the power of PCI functions on the bus. The PCI bus and the PCI functions can be assigned one of four software visible power management states, which result in varying levels of power savings. The four power management states of PCI functions are D0--fully on state, D1 and D2--intermediate states, and D3--off state. Similarly, bus power states of the PCI bus are B0-B3. The bus power states B0-B3 are derived from the device power state of the originating PCI2050 device. For the operating system to manage the device power states on the PCI bus, the PCI function supports four power management operations: * * * * Capabilities reporting Power status reporting Setting the power state System wake-up The operating system identifies the capabilities of the PCI function by traversing the new capabilities list. The presence of the new capabilities list is indicated by a bit in the status register (offset 06h, see Section 4.4) which provides access to the capabilities list. 3.17.1 Behavior in Low-Power States The PCI2050 supports D0, D1, D2, and D3hot power states when in TI mode. The PCI2050 only supports D0 and D3 power states when in Intel mode. The PCI2050 is fully functional only in D0 state. In the lower power states, the bridge does not accept any memory or I/O transactions. These transactions are aborted by the master. The bridge accepts type 0 configuration cycles in all power states except D3cold. The bridge also accepts type 1 configuration cycles but does not pass these cycles to the secondary bus in any of the lower power states. Type 1 configuration writes are discarded and reads return all 1s. All error reporting is done in the low power states. When in D2 and D3hot states, the bridge turns off all secondary clocks for further power savings. When going from D3hot to D0, an internal reset is generated. This reset initializes all PCI configuration registers to their default values. The TI specific registers (40h - FFh) are not reset. Power management registers also are not reset. 3-15 3-16 4 Bridge Configuration Header The PCI2050 bridge is a single-function PCI device. The configuration header is in compliance with the PCI-to-PCI Bridge Specification 1.1. Table 4-1 shows the PCI configuration header, which includes the predefined portion of the bridge configuration space. The PCI configuration offset is shown in the right column under the OFFSET heading. Table 4-1. Bridge Configuration Header REGISTER NAME Device ID Status Class code BIST Header type Primary latency timer Base address 0 Base address 1 Secondary bus latency timer Subordinate bus number Secondary bus number I/O limit Memory base Prefetchable memory base Prefetchable base upper 32 bits Prefetchable limit upper 32 bits I/O limit upper 16 bits Reserved Expansion ROM base address Bridge control Arbiter control GPIO input data Reserved GPIO output enable P_SERR status Reserved Power management capabilities Data Reserved PMCSR bridge support Hot swap control status Reserved PM next item pointer HS next item pointer PM capability ID HS capability ID Reserved GPIO output data P_SERR event disable Secondary clock control Interrupt pin Extended diagnostic Interrupt line Chip control I/O base upper 16 bits Capability pointer Primary bus number I/O base Secondary status Memory limit Prefetchable memory limit Vendor ID Command Revision ID Cache line size OFFSET 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch 40h 44h-60h 64h 68h 6Ch-D8h DCh E0h E4h E8h-FFh Power management control/status 4-1 4.1 Vendor ID Register This 16-bit value is allocated by the PCI Special Interest Group (SIG) and identifies TI as the manufacturer of this device. The vendor ID assigned to TI is 104Ch. Bit Name Type Default R 0 R 0 R 0 R 1 R 0 R 0 R 0 15 14 13 12 11 10 9 8 R 0 7 R 0 6 R 1 5 R 0 4 R 0 3 R 1 2 R 1 1 R 0 0 R 0 Vendor ID Register: Type: Offset: Default: Vendor ID Read-only 00h 104Ch 4.2 Device ID Register This 16-bit value is allocated by the vendor and identifies the PCI device. The device ID for the PCI2050 is AC28h. Bit Name Type Default R 1 R 0 R 1 R 0 R 1 R 1 R 0 15 14 13 12 11 10 9 8 R 0 7 R 0 6 R 0 5 R 1 4 R 0 3 R 1 2 R 0 1 R 0 0 R 0 Device ID Register: Type: Offset: Default: Device ID Read-only 02h AC28h 4-2 4.3 Command Register The command register provides control over the bridge interface to the primary PCI bus. VGA palette snooping is enabled through this register, and all other bits adhere to the definitions in the PCI Local Bus Specification. Table 4-2 describes the bit functions in the command register. Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 15 14 13 12 11 10 9 8 R/W 0 7 R 0 6 R/W 0 5 R/W 0 4 R 0 3 R 0 2 R/W 0 1 R/W 0 0 R/W 0 Command Register: Type: Offset: Default: BIT 15-10 9 8 TYPE R R/W R/W Command Read-only, Read/Write 04h 0000h Table 4-2. Command Register Description FUNCTION Reserved Fast back-to-back enable. This bit defaults to 0. System error (SERR) enable. Bit 8 controls the enable for the SERR driver on the primary interface. 0 = Disable SERR driver on primary interface (default) 1 = Enable the SERR driver on primary interface Wait cycle control. Bit 7 controls address/data stepping by the bridge on both interfaces. The bridge does not support address/data stepping and this bit is hardwired to 0. Parity error response enable. Bit 6 controls the bridge response to parity errors. 0 = Parity error response disabled (default) 1 = Parity error response enabled VGA palette snoop enable. When set, the bridge passes I/O writes on the primary PCI bus with addresses 3C6h, 3C8h, and 3C9h inclusive of ISA aliases (that is, only bits AD9-AD0 are included in the decode). Memory write and invalidate enable. In a PCI-to-PCI bridge, bit 4 must be read-only and return 0 when read. Special cycle enable. A PCI-to-PCI bridge cannot respond as a target to special cycle transactions, so bit 3 is defined as read-only and must return 0 when read. Bus master enable. Bit 2 controls the ability of the bridge to initiate a cycle on the primary PCI bus. When bit 2 is 0, the bridge does not respond to any memory or I/O transactions on the secondary interface since they cannot be forwarded to the primary PCI bus. 0 = Bus master capability disabled (default) 1 = Bus master capability enabled Memory space enable. Bit 1 controls the bridge response to memory accesses for both prefetchable and nonprefetchable memory spaces on the primary PCI bus. Only when bit 1 is set will the bridge forward memory accesses to the secondary bus from a primary bus initiator. 0 = Memory space disabled (default) 1 = Memory space enabled I/O space enable. Bit 0 controls the bridge response to I/O accesses on the primary interface. Only when bit 0 is set will the bridge forward I/O accesses to the secondary bus from a primary bus initiator. 0 = I/O space disabled (default) 1 = I/O space enabled 7 R 6 R/W 5 4 3 R/W R R 2 R/W 1 R/W 0 R/W 4-3 4.4 Status Register The status register provides device information to the host system. Bits in this register are cleared by writing a 1 to the respective bit; writing a 0 to a bit location has no effect. Table 4-3 describes the status register. Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 1 0 15 14 13 12 11 10 9 8 Status R/W R 1 R 0 R 0 R 1 R 0 R 0 R 0 R 0 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: Status Read-only, Read/Write 06h 0290h Table 4-3. Status Register Description BIT 15 TYPE R/W FUNCTION Detected parity error. Bit 15 is set when a parity error is detected. Signaled system error (SERR). Bit 14 is set if SERR is enabled in the command register (offset 04h, see Section 4.3) and the bridge signals a system error (SERR). See Section 3.8, System Error Handling. 0 = No SERR signaled (default) 1 = Signals SERR Received master abort. Bit 13 is set when a cycle initiated by the bridge on the primary bus has been terminated by a master abort. 0 = No master abort received (default) 1 = Master abort received Received target abort. Bit 12 is set when a cycle initiated by the bridge on the primary bus has been terminated by a target abort. 0 = No target abort received (default) 1 = Target abort received Signaled target abort. Bit 11 is set by the bridge when it terminates a transaction on the primary bus with a target abort. 0 = No target abort signaled by the bridge (default) 1 = Target abort signaled by the bridge DEVSEL timing. These read-only bits encode the timing of P_DEVSEL and are hardwired 01b, indicating that the bridge asserts this signal at a medium speed. Data parity error detected. Bit 8 is encoded as: 0 = The conditions for setting this bit have not been met. No parity error detected. (default) 1 = A data parity error occurred and the following conditions were met: a. P_PERR was asserted by any PCI device including the bridge. b. The bridge was the bus master during the data parity error. c. The parity error response bit (bit 6) was set in the command register (offset 04h, see Section 4.3). Fast back-to-back capable. The bridge supports fast back-to-back transactions as a target; therefore, bit 7 is hardwired to 1. User-definable feature (UDF) support. The PCI2050 does not support the user-definable features; therefore, bit 6 is hardwired to 0. 66-MHz capable. The PCI2050 operates at a maximum P_CLK frequency of 33 MHz; therefore, bit 5 is hardwired to 0. Capabilities list. Bit 4 is read-only and is hardwired to 1, indicating that capabilities additional to standard PCI are implemented. The linked list of PCI power management capabilities is implemented by this function. Reserved. Bits 3-0 return 0s when read. 14 R/W 13 R/W 12 R/W 11 R/W 10-9 R 8 R/W 7 6 5 4 3-0 R R R R R 4-4 4.5 Revision ID Register The revision ID register indicates the silicon revision of the PCI2050. Bit Name Type Default R 0 R 0 R 0 R 0 7 6 5 4 Revision ID R 0 R 0 R 0 R 0 3 2 1 0 Register: Type: Offset: Default: Revision ID Read-only 08h 00h (reflects the current revision of the silicon) 4.6 Class Code Register This register categorizes the PCI2050 as a PCI-to-PCI bridge device (0604h) with a 00h programming interface. Bit Name Base class Type Default R 0 R 0 R 0 R 0 R 0 R 1 R 1 R 0 R 0 R 0 R 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Class code Sub class R 0 R 0 R 1 R 0 R 0 R 0 R 0 Programming interface R 0 R 0 R 0 R 0 R 0 R 0 Register: Type: Offset: Default: Class code Read-only 09h 06 0400h 4.7 Cache Line Size Register The cache line size register is programmed by host software to indicate the system cache line size needed by the bridge for memory read line, memory read multiple, and memory write and invalidate transactions. The PCI2050 supports cache line sizes up to and including 16 doublewords for memory write and invalidate. If the cache line size is larger than 16 doublewords, the command is converted to a memory write command. Bit Name Type Default R/W 0 R/W 0 R/W 0 7 6 5 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Cache line size Register: Type: Offset: Default: Cache line size Read/Write 0Ch 00h 4-5 4.8 Primary Latency Timer Register The latency timer register specifies the latency timer for the bridge in units of PCI clock cycles. When the bridge is a primary PCI bus initiator and asserts P_FRAME, the latency timer begins counting from 0. If the latency timer expires before the bridge transaction has terminated, then the bridge terminates the transaction when its P_GNT is deasserted. Bit Name Type Default R/W 0 R/W 0 R/W 0 0 7 6 5 4 Latency timer R/W R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 Register: Type: Offset: Default: Latency timer Read/Write 0Dh 00h 4.9 Header Type Register The header type register is read-only and returns 01h when read, indicating that the PCI2050 configuration space adheres to the PCI-to-PCI bridge configuration. Only the layout for bytes 10h-3Fh of configuration space is considered. Bit Name Type Default R 0 R 0 R 0 R 0 7 6 5 4 Header type R 0 R 0 R 0 R 1 3 2 1 0 Register: Type: Offset: Default: Header type Read-only 0Eh 01h 4.10 BIST Register The PCI2050 does not support built-in self test (BIST). The BIST register is read-only and returns the value 00h when read. Bit Name Type Default R 0 R 0 R 0 R 0 7 6 5 4 BIST R 0 R 0 R 0 R 0 3 2 1 0 Register: Type: Offset: Default: BIST Read-only 0Fh 00h 4-6 4.11 Base Address Register 0 The bridge requires no additional resources. Base address register 0 is read-only and returns 0s when read. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 31 30 29 28 27 26 25 R 0 9 R 0 24 R 0 8 R 0 23 R 0 7 R 0 22 R 0 6 R 0 21 R 0 5 R 0 20 R 0 4 R 0 19 R 0 3 R 0 18 R 0 2 R 0 17 R 0 1 R 0 16 R 0 0 R 0 Base address register 0 Base address register 0 Register: Type: Offset: Default: Base address register 0 Read-only 10h 0000 0000h 4.12 Base Address Register 1 The bridge requires no additional resources. Base address register 1 is read-only and returns 0s when read. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 31 30 29 28 27 26 25 R 0 9 R 0 24 R 0 8 R 0 23 R 0 7 R 0 22 R 0 6 R 0 21 R 0 5 R 0 20 R 0 4 R 0 19 R 0 3 R 0 18 R 0 2 R 0 17 R 0 1 R 0 16 R 0 0 R 0 Base address register 1 Base address register 1 Register: Type: Offset: Default: Base address register 1 Read-only 14h 0000 0000h 4.13 Primary Bus Number Register The primary bus number register indicates the primary bus number to which the bridge is connected. The bridge uses this register, in conjunction with the secondary bus number and subordinate bus number registers, to determine when to forward PCI configuration cycles to the secondary buses. Bit Name Type Default R/W 0 R/W 0 R/W 0 7 6 5 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Primary bus number Register: Type: Offset: Default: Primary bus number Read/Write 18h 00h 4-7 4.14 Secondary Bus Number Register The secondary bus number register indicates the secondary bus number to which the bridge is connected. The PCI2050 uses this register, in conjunction with the primary bus number and subordinate bus number registers, to determine when to forward PCI configuration cycles to the secondary buses. Configuration cycles directed to the secondary bus are converted to type 0 configuration cycles. Bit Name Type Default R/W 0 R/W 0 R/W 0 7 6 5 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Secondary bus number Register: Type: Offset: Default: Secondary bus number Read/Write 19h 00h 4.15 Subordinate Bus Number Register The subordinate bus number register indicates the bus number of the highest numbered bus beyond the primary bus existing behind the bridge. The PCI2050 uses this register, in conjunction with the primary bus number and secondary bus number registers, to determine when to forward PCI configuration cycles to the subordinate buses. Configuration cycles directed to a subordinate bus (not the secondary bus) remain type 1 cycles as the cycle crosses the bridge. Bit Name Type Default R/W 0 R/W 0 R/W 0 7 6 5 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Subordinate bus number Register: Type: Offset: Default: Subordinate bus number Read/write 1Ah 00h 4.16 Secondary Bus Latency Timer Register The secondary bus latency timer specifies the latency time for the bridge in units of PCI clock cycles. When the bridge is a secondary PCI bus initiator and asserts S_FRAME, the latency timer begins counting from 0. If the latency timer expires before the bridge transaction has terminated, then the bridge terminates the transaction when its S_GNT is deasserted. The PCI-to-PCI bridge S_GNT is an internal signal and is removed when another secondary bus master arbitrates for the bus. Bit Name Type Default R/W 0 R/W 0 R/W 0 7 6 5 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Secondary bus latency timer Register: Type: Offset: Default: Secondary bus latency timer Read/Write 1Bh 00h 4-8 4.17 I/O Base Register The I/O base register is used in decoding I/O addresses to pass through the bridge. The bridge supports 32-bit I/O addressing; thus, bits 3-0 are read-only and default to 0001b. The upper four bits are writable and correspond to address bits AD15-AD12. The lower 12 address bits of the I/O base address are considered 0. Thus, the bottom of the defined I/O address range is aligned on a 4K-byte boundary. The upper 16 address bits of the 32-bit I/O base address corresponds to the contents of the I/O base upper 16 bits register (offset 30h, see Section 4.26). Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 I/O base R 0 R 0 R 0 R 1 3 2 1 0 Register: Type: Offset: Default: I/O base Read-only, Read/Write 1Ch 01h 4.18 I/O Limit Register The I/O limit register is used in decoding I/O addresses to pass through the bridge. The bridge supports 32-bit I/O addressing; thus, bits 3-0 are read-only and default to 0001b. The upper four bits are writable and correspond to address bits AD15-AD12. The lower 12 address bits of the I/O limit address are considered FFFh. Thus, the top of the defined I/O address range is aligned on a 4K-byte boundary. The upper 16 address bits of the 32-bit I/O limit address corresponds to the contents of the I/O limit upper 16 bits register (offset 32h, see Section 4.27). Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 I/O limit R 0 R 0 R 0 R 1 3 2 1 0 Register: Type: Offset: Default: I/O limit Read-only, Read/Write 1Dh 01h 4-9 4.19 Secondary Status Register The secondary status register is similar in function to the status register (offset 06h, see Section 4.4); however, its bits reflect status conditions of the secondary interface. Bits in this register are cleared by writing a 1 to the respective bit. Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 1 15 14 13 12 11 10 9 8 R/W 0 7 R 1 6 R 0 5 R 0 4 R 0 3 R 0 2 R 0 1 R 0 0 R 0 Secondary status Register: Type: Offset: Default: BIT 15 TYPE R/W Secondary status Read-only, Read/Write 1Eh 0280h Table 4-4. Secondary Status Register Description FUNCTION Detected parity error. Bit 15 is set when a parity error is detected on the secondary interface. 0 = No parity error detected on the secondary bus (default) 1 = Parity error detected on the secondary bus Received system error. Bit 14 is set when the secondary interface detects S_SERR asserted. Note that the bridge never asserts S_SERR. 0 = No S_SERR detected on the secondary bus (default) 1 = S_SERR detected on the secondary bus Received master abort. Bit 13 is set when a cycle initiated by the bridge on the secondary bus has been terminated by a master abort. 0 = No master abort received (default) 1 = Bridge master aborted the cycle Received target abort. Bit 12 is set when a cycle initiated by the bridge on the secondary bus has been terminated by a target abort. 0 = No target abort received (default) 1 = Bridge received a target abort Signaled target abort. Bit 11 is set by the bridge when it terminates a transaction on the secondary bus with a target abort. 0 = No target abort signaled (default) 1 = Bridge signaled a target abort DEVSEL timing. These read-only bits encode the timing of S_DEVSEL and are hardwired to 01b, indicating that the bridge asserts this signal at a medium speed. Data parity error detected. 0 = The conditions for setting this bit have not been met 1 = A data parity error occurred and the following conditions were met: a. S_PERR was asserted by any PCI device including the bridge. b. The bridge was the bus master during the data parity error. c. The parity error response bit (bit 1) was set in the bridge control register (offset 3Eh, see Section 4.32). Fast back-to-back capable. Bit 7 is hardwired to 1. User-definable feature (UDF) support. Bit 6 is hardwired to 0. 66-MHz capable. Bit 5 is hardwired to 0. Reserved. Bits 4-0 return 0s when read. 14 R/W 13 R/W 12 R/W 11 R/W 10-9 R 8 R/W 7 6 5 4-0 R R R R 4-10 4.20 Memory Base Register The memory base register defines the base address of a memory-mapped I/O address range used by the bridge to determine when to forward memory transactions from one interface to the other. The upper 12 bits of this register are read/write and correspond to the address bits AD31-AD20. The lower 20 address bits are considered 0s; thus, the address range is aligned to a 1M-byte boundary. The bottom four bits are read-only and return 0s when read. Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R 0 2 R 0 1 R 0 0 R 0 Memory base Register: Type: Offset: Default: Memory base Read-only, Read/Write 20h 0000h 4.21 Memory Limit Register The memory limit register defines the upper-limit address of a memory-mapped I/O address range used to determine when to forward memory transactions from one interface to the other. The upper 12 bits of this register are read/write and correspond to the address bits AD31-AD20. The lower 20 address bits are considered 1s; thus, the address range is aligned to a 1M-byte boundary. The bottom four bits are read-only and return 0s when read. Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R 0 2 R 0 1 R 0 0 R 0 Memory limit Register: Type: Offset: Default: Memory limit Read-only, Read/Write 22h 0000h 4.22 Prefetchable Memory Base Register The prefetchable memory base register defines the base address of a prefetchable memory address range used by the bridge to determine when to forward memory transactions from one interface to the other. The upper 12 bits of this register are read/write and correspond to the address bits AD31-AD20. The lower 20 address bits are considered 0; thus, the address range is aligned to a 1M-byte boundary. The bottom four bits are read-only and return 0s when read. Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 R/W 0 8 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R 0 2 R 0 1 R 0 0 R 0 Prefetchable memory base Register: Type: Offset: Default: Prefetchable memory base Read-only, Read/Write 24h 0000h 4-11 4.23 Prefetchable Memory Limit Register The prefetchable memory limit register defines the upper-limit address of a prefetchable memory address range used to determine when to forward memory transactions from one interface to the other. The upper 12 bits of this register are read/write and correspond to the address bits AD31-AD20. The lower 20 address bits are considered 1s; thus, the address range is aligned to a 1M-byte boundary. The bottom four bits are read-only and return 0s when read. Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 R/W 0 8 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R 0 2 R 0 1 R 0 0 R 0 Prefetchable memory limit Register: Type: Offset: Default: Prefetchable memory limit Read-only, Read/Write 26h 0000h 4.24 Prefetchable Base Upper 32 Bits Register The prefetchable base upper 32 bits register plus the prefetchable memory base register defines the base address of the 64-bit prefetchable memory address range used by the bridge to determine when to forward memory transactions from one interface to the other. The prefetchable base upper 32 bits register should be programmed to all zeros when 32-bit addressing is being used. Bit Name Type Default Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 R/W 0 10 31 30 29 28 27 26 25 R/W 0 9 R/W 0 24 R/W 0 8 R/W 0 23 R/W 0 7 R/W 0 22 R/W 0 6 R/W 0 21 R/W 0 5 R/W 0 20 R/W 0 4 R/W 0 19 R/W 0 3 R/W 0 18 R/W 0 2 R/W 0 17 R/W 0 1 R/W 0 16 R/W 0 0 R/W 0 Prefetchable base upper 32 bits Prefetchable base upper 32 bits Register: Type: Offset: Default: Prefetchable base upper 32 bits Read/Write 28h 0000 0000h 4-12 4.25 Prefetchable Limit Upper 32 Bits Register The prefetchable limit upper 32 bits register plus the prefetchable memory limit register defines the base address of the 64-bit prefetchable memory address range used by the bridge to determine when to forward memory transactions from one interface to the other. The prefetchable limit upper 32 bits register should be programmed to all zeros when 32-bit addressing is being used. Bit Name Type Default Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 R/W 0 10 31 30 29 28 27 26 25 R/W 0 9 R/W 0 24 R/W 0 8 R/W 0 23 R/W 0 7 R/W 0 22 R/W 0 6 R/W 0 21 R/W 0 5 R/W 0 20 R/W 0 4 R/W 0 19 R/W 0 3 R/W 0 18 R/W 0 2 R/W 0 17 R/W 0 1 R/W 0 16 R/W 0 0 R/W 0 Prefetchable limit upper 32 bits Prefetchable limit upper 32 bits Register: Type: Offset: Default: Prefetchable limit upper 32 bits Read/Write 2Ch 0000 0000h 4.26 I/O Base Upper 16 Bits Register The I/O base upper 16 bits register specifies the upper 16 bits corresponding to AD31-AD16 of the 32-bit address that specifies the base of the I/O range to forward from the primary PCI bus to the secondary PCI bus. Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 0 15 14 13 12 11 10 9 R/W 8 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 I/O base upper 16 bits Register: Type: Offset: Default: I/O base upper 16 bits Read/Write 30h 0000h 4.27 I/O Limit Upper 16 Bits Register The I/O limit upper 16 bits register specifies the upper 16 bits corresponding to AD31-AD16 of the 32-bit address that specifies the upper limit of the I/O range to forward from the primary PCI bus to the secondary PCI bus. Bit Name Type Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 0 15 14 13 12 11 10 9 R/W 8 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 I/O limit upper 16 bits Register: Type: Offset: Default: I/O limit upper 16 bits Read/Write 32h 0000h 4-13 4.28 Capability Pointer Register The capability pointer register provides the pointer to the PCI configuration header where the PCI power management register block resides. The capability pointer provides access to the first item in the linked list of capabilities. The capability pointer register is read-only and returns DCh when read, indicating the power management registers are located at PCI header offset DCh. Bit Name Type Default R 1 R 1 R 0 7 6 5 4 3 2 1 0 Capability pointer register R 1 R 1 R 1 R 0 R 0 Register: Type: Offset: Default: Capability pointer Read-only 34h DCh 4.29 Expansion ROM Base Address Register The PCI2050 does not implement the expansion ROM remapping feature. The expansion ROM base address register returns all 0s when read. Bit Name Type Default Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 R 0 14 R 0 13 R 0 12 R 0 11 R 0 10 31 30 29 28 27 26 25 R 0 9 R 0 24 R 0 8 R 0 23 R 0 7 R 0 22 R 0 6 R 0 21 R 0 5 R 0 20 R 0 4 R 0 19 R 0 3 R 0 18 R 0 2 R 0 17 R 0 1 R 0 16 R 0 0 R 0 Expansion ROM base address Expansion ROM base address Register: Type: Offset: Default: Expansion ROM base address Read-only 38h 0000 0000h 4.30 Interrupt Line Register The interrupt line register is read/write and is used to communicate interrupt line routing information. Since the bridge does not implement an interrupt signal terminal, this register defaults to 00h. Bit Name Type Default R/W 0 R/W 0 R/W 0 0 7 6 5 4 Interrupt line R/W R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 Register: Type: Offset: Default: Interrupt line Read/Write 3Ch 00h 4-14 4.31 Interrupt Pin Register The bridge default state does not implement any interrupt terminals. Reads from bits 7-0 of this register return 0s. Bit Name Type Default R 0 R 0 R 0 R 0 7 6 5 4 Interrupt pin R 0 R 0 R 0 R 0 3 2 1 0 Register: Type: Offset: Default: Interrupt pin Read-only 3Dh 00h 4.32 Bridge Control Register The bridge control register provides many of the same controls for the secondary interface that are provided by the command register for the primary interface. Some bits affect the operation of both interfaces. Bit Name Type Default R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 8 R/W 0 7 R 0 6 R/W 0 5 R/W 0 4 R 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bridge control Register: Type: Offset: Default: Bridge control Read-only, Read/Write 3Eh 0000h Table 4-5. Bridge Control Register Description BIT 15-12 11 TYPE R R/W Reserved. Bits 15-12 return 0s when read. FUNCTION Discard timer SERR enable. 0 = SERR signaling disabled for primary discard time-outs (default) 1 = SERR signaling enabled for primary discard time-outs Discard timer status. Once set, this bit must be cleared by writing 1 to this bit. 0 = No discard timer error (default) 1 = Discard timer error. Either primary or secondary discard timer expired and a delayed transaction was discarded from the queue in the bridge. Secondary discard timer. Selects the number of PCI clocks that the bridge will wait for a master on the secondary interface to repeat a delayed transaction request. 0 = Secondary discard timer counts 215 PCI clock cycles (default) 1 = Secondary discard timer counts 210 PCI clock cycles Primary discard timer. Selects the number of PCI clocks that the bridge will wait for a master on the primary interface to repeat a delayed transaction request. 0 = Primary discard timer counts 215 PCI clock cycles (default) 1 = Primary discard timer counts 210 PCI clock cycles Fast back-to-back capable. The bridge never generates fast back-to-back transactions to different secondary devices. Bit 7 returns 0 when read. Secondary bus reset. When bit 6 is set, the secondary reset signal (S_RST) is asserted. S_RST is deasserted by resetting this bit. Bit 6 is encoded as: 0 = Do not force the assertion of S_RST (default). 1 = Force the assertion of S_RST. 10 R/W 9 R/W 8 R/W 7 R 6 R/W 4-15 Table 4-5. Bridge Control Register Description (continued) BIT TYPE FUNCTION Master abort mode. Bit 5 controls how the bridge responds to a master abort that occurs on either interface when the bridge is the master. If this bit is set, the posted write transaction has completed on the requesting interface, and SERR enable (bit 8) of the command register (offset 04h, see Section 4.3) is 1, then P_SERR is asserted when a master abort occurs. If the transaction has not completed, then a target abort is signaled. If the bit is cleared, then all 1s are returned on reads and write data is accepted and discarded when a transaction that crosses the bridge is terminated with master abort. The default state of bit 5 after a reset is 0. 0 = Do not report master aborts (return FFFF FFFFh on reads and discard data on writes) (default). 1 = Report master aborts by signaling target abort if possible, or if SERR is enabled via bit 1 of this register, by asserting SERR. Reserved. Returns 0 when read. Writes have no effect. VGA enable. When bit 3 is set, the bridge positively decodes and forwards VGA-compatible memory addresses in the video frame buffer range 000A 0000h-000B FFFFh, I/O addresses in the range 03B0h-03BBh, and 03C0-03DFh from the primary to the secondary interface, independent of the I/O and memory address ranges. When this bit is set, the bridge blocks forwarding of these addresses from the secondary to the primary. Reset clears this bit. Bit 3 is encoded as: 0 = Do not forward VGA-compatible memory and I/O addresses from the primary to the secondary interface (default). 1 = Forward VGA-compatible memory and I/O addresses from the primary to the secondary, independent of the I/O and memory address ranges and independent of the ISA enable bit. ISA enable. When bit 2 is set, the bridge blocks the forwarding of ISA I/O transactions from the primary to the secondary, addressing the last 768 bytes in each 1K-byte block. This applies only to the addresses (defined by the I/O window registers) that are located in the first 64K bytes of PCI I/O address space. From the secondary to the primary, I/O transactions are forwarded if they address the last 768 bytes in each 1K-byte block in the address range specified in the I/O window registers. Bit 2 is encoded as: 0 = Forward all I/O addresses in the address range defined by the I/O base and I/O limit registers (default). 1 = Block forwarding of ISA I/O addresses in the address range defined by the I/O base and I/O limit registers when these I/O addresses are in the first 64K bytes of PCI I/O address space and address the top 768 bytes of each 1K-byte block. SERR enable. Bit 1 controls the forwarding of secondary interface SERR assertions to the primary interface. Only when this bit is set will the bridge forward S_SERR to the primary bus signal P_SERR. For the primary interface to assert SERR, bit 8 of the command register (offset 04h, see Section 4.3) must be set. 0 = SERR disabled (default) 1 = SERR enabled Parity error response enable. Bit 0 controls the bridge response to parity errors on the secondary interface. When this bit is set, the bridge asserts S_PERR to report parity errors on the secondary interface. 0 = Ignore address and parity errors on the secondary interface (default). 1 = Enable parity error reporting and detection on the secondary interface. 5 R/W 4 R 3 R/W 2 R/W 1 R/W 0 R/W 4-16 5 Extension Registers The TI extension registers are those registers that lie outside the standard PCI-to-PCI bridge device configuration space (i.e., registers 40h-FFh in PCI configuration space in the PCI2050). These registers can be accessed through configuration reads and writes. The TI extension registers add flexibility and performance benefits to the standard PCI-to-PCI bridge. Mapping of the extension registers is contained in Table 4-1. 5.1 Chip Control Register The chip control register contains read/write and read-only bits and has a default value of 00h. This register is used to control the functionality of certain PCI transactions. Bit Name Type Default R 0 R 0 R/W 0 0 7 6 5 4 Chip control R/W R 0 R 0 R/W 0 R 0 3 2 1 0 Register: Type: Offset: Default: BIT 7-6 5 TYPE R R/W Chip control Read/Write, Read-only 40h 00h Table 5-1. Chip Control Register Description FUNCTION Reserved. Bits 7-6 return 0s when read. Transaction forwarding control for I/O and memory cycles. 0 = Transaction forwarding controlled by bits 0 and 1 of the command register (offset 04h, see Section 4.3) (default). 1 = Transaction forwarding will be disabled if GPIO3 is driven high. Memory read prefetch. When set, bit 4 enables the memory read prefetch. 0 = Upstream memory reads are disabled (default). 1 = Upstream memory reads are enabled Reserved. Bits 3 and 2 return 0s when read. Memory write and memory write and invalidate disconnect control. 0 = Disconnects on queue full or 4-KB boundaries (default) 1 = Disconnects on queue full, 4-KB boundaries and cacheline boundaries. Reserved. Bit 0 returns 0 when read. 4 3-2 1 0 R/W R R/W R 5-1 5.2 Extended Diagnostic Register The extended diagnostic register is read or write and has a default value of 00h. Bit 0 of this register is used to reset both the PCI2050 and the secondary bus. Bit Name Type Default R 0 R 0 R 0 7 6 5 4 R 0 3 R 0 2 R 0 1 R 0 0 W 0 Extended diagnostic Register: Type: Offset: Default: BIT 7-1 0 TYPE R W Extended diagnostic Read-only, Write-only 41h 00h Table 5-2. Extended Diagnostic Register Description FUNCTION Reserved. Bits 7-1 return 0s when read. Writing a 1 to this bit causes the PCI2050 to set bit 6 of the bridge control register (offset 3Eh, see Section 4.32) and then internally reset the PCI2050. Bit 6 of the bridge control register will not be reset by the internal reset. Bit 0 is self-clearing. 5-2 5.3 Arbiter Control Register The arbiter control register is used for the bridge internal arbiter. The arbitration scheme used is a two-tier rotational arbitration. The PCI2050 bridge is the only secondary bus initiator that defaults to the higher priority arbitration tier. Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 R/W 1 15 14 13 12 11 10 9 8 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Arbiter control Register: Type: Offset: Default: BIT 15-10 9 TYPE R R/W Arbiter control Read-only, Read/Write 42h 0200h Table 5-3. Arbiter Control Register Description FUNCTION Reserved. Bits 15-10 return 0s when read. Bridge tier select. This bit determines in which tier the PCI2250 bridge is placed in the two-tier arbitration scheme. 0 = Low priority tier 1 = High priority tier (default) GNT8 tier select. This bit determines in which tier the S_GNT8 is placed in the arbitration scheme. This bit is encoded as: 0 = Low priority tier (default) 1 = High priority tier GNT7 tier select. This bit determines in which tier the S_GNT7 is placed in the arbitration scheme. This bit is encoded as: 0 = Low priority tier (default) 1 = High priority tier GNT6 tier select. This bit determines in which tier the S_GNT6 is placed in the arbitration scheme. This bit is encoded as: 0 = Low priority tier (default) 1 = High priority tier GNT5 tier select. This bit determines in which tier the S_GNT5 is placed in the arbitration scheme. This bit is encoded as: 0 = Low priority tier (default) 1 = High priority tier GNT4 tier select. This bit determines in which tier the S_GNT4 is placed in the arbitration scheme. This bit is encoded as: 0 = Low priority tier (default) 1 = High priority tier GNT3 tier select. This bit determines in which tier the S_GNT3 is placed in the arbitration scheme. This bit is encoded as: 0 = Low priority tier (default) 1 = High priority tier GNT2 tier select. This bit determines in which tier the S_GNT2 is placed in the arbitration scheme. This bit is encoded as: 0 = Low priority tier (default) 1 = High priority tier GNT1 tier select. This bit determines in which tier the S_GNT1 is placed in the arbitration scheme. This bit is encoded as: 0 = Low priority tier (default) 1 = High priority tier GNT0 tier select. This bit determines in which tier the S_GNT0 is placed in the arbitration scheme. This bit is encoded as: 0 = Low priority tier (default) 1 = High priority tier 8 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W 5-3 5.4 P_SERR Event Disable Register The P_SERR event disable register is used to enable/disable the SERR event on the primary interface. All events are enabled by default. Bit Name Type Default R 0 R/W 0 R/W 0 7 6 5 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R 0 P_SERR event disable Register: Type: Offset: Default: BIT 7 6 TYPE R R/W P_SERR event disable Read-only, Read/Write 64h 00h Table 5-4. P_SERR Event Disable Register Description FUNCTION Reserved. Bit 7 returns 0 when read. Master delayed read time-out. 0 = P_SERR signaled on a master time-out after 224 retries on a delayed read (default). 1 = P_SERR is not signaled on a master time-out. Master delayed write time-out. 0 = P_SERR signaled on a master time-out after 224 retries on a delayed write (default). 1 = P_SERR is not signaled on a master time-out. Master abort on posted write transactions. When set, bit 4 enables P_SERR reporting on master aborts on posted write transactions. 0 = Master aborts on posted writes enabled (default) 1 = Master aborts on posted writes disabled Target abort on posted writes. When set, bit 3 enables P_SERR reporting on target aborts on posted write transactions. 0 = Target aborts on posted writes enabled (default). 1 = Target aborts on posted writes disabled. Master posted write time-out. 0 = P_SERR signaled on a master time-out after 224 retries on a posted write (default). 1 = P_SERR is not signaled on a master time-out. Posted write parity error. 0 = P_SERR signaled on a posted write parity error (default). 1 = P_SERR is not signaled on a posted write parity error. Reserved. Bit 0 returns 0 when read. 5 R/W 4 R/W 3 R/W 2 R/W 1 0 R/W R 5-4 5.5 GPIO Output Data Register The GPIO output data register controls the data driven on the GPIO terminals configured as outputs. If both an output-high bit and an output-low bit are set for the same GPIO terminal, the output-low bit takes precedence. The output data bits have no effect on a GPIO terminal that is programmed as an input. Bit Name Type Default R/W 0 R/W 0 R/W 0 7 6 5 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 GPIO output data Register: Type: Offset: Default: BIT 7 6 5 4 3 2 1 0 TYPE R/W R/W R/W R/W R/W R/W R/W R/W GPIO output data Read/Write 65h 00h Table 5-5. GPIO Output Data Register Description FUNCTION GPIO3 output high. Writing a 1 to this bit causes the GPIO signal to be driven high. Writing a 0 has no effect. GPIO2 output high. Writing a 1 to this bit causes the GPIO signal to be driven high. Writing a 0 has no effect. GPIO1 output high. Writing a 1 to this bit causes the GPIO signal to be driven high. Writing a 0 has no effect. GPIO0 output high. Writing a 1 to this bit causes the GPIO signal to be driven high. Writing a 0 has no effect. GPIO3 output low. Writing a 1 to this bit causes the GPIO signal to be driven low. Writing a 0 has no effect. GPIO2 output low. Writing a 1 to this bit causes the GPIO signal to be driven low. Writing a 0 has no effect. GPIO1 output low. Writing a 1 to this bit causes the GPIO signal to be driven low. Writing a 0 has no effect. GPIO0 output low. Writing a 1 to this bit causes the GPIO signal to be driven low. Writing a 0 has no effect. 5.6 GPIO Output Enable Register The GPIO output enable register controls the direction of the GPIO signal. By default all GPIO terminals are inputs. If both an output-enable bit and an input-enable bit are set for the same GPIO terminal, the input-enable bit takes precedence. Bit Name Type Default R/W 0 R/W 0 R/W 0 7 6 5 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 GPIO output enable Register: Type: Offset: Default: BIT 7 6 5 4 3 2 1 0 TYPE R/W R/W R/W R/W R/W R/W R/W R/W GPIO output enable Read/Write 66h 00h Table 5-6. GPIO Output Enable Register Description FUNCTION GPIO3 output enable. Writing a 1 to this bit causes the GPIO signal to be configured as an output. Writing a 0 has no effect. GPIO2 output enable. Writing a 1 to this bit causes the GPIO signal to be configured as an output. Writing a 0 has no effect. GPIO1 output enable. Writing a 1 to this bit causes the GPIO signal to be configured as an output. Writing a 0 has no effect. GPIO0 output enable. Writing a 1 to this bit causes the GPIO signal to be configured as an output. Writing a 0 has no effect. GPIO3 input enable. Writing a 1 to this bit causes the GPIO signal to be configured as an input. Writing a 0 has no effect. GPIO3 input enable. Writing a 1 to this bit causes the GPIO signal to be configured as an input. Writing a 0 has no effect. GPIO3 input enable. Writing a 1 to this bit causes the GPIO signal to be configured as an input. Writing a 0 has no effect. GPIO3 input enable. Writing a 1 to this bit causes the GPIO signal to be configured as an input. Writing a 0 has no effect. 5-5 5.7 GPIO Input Data Register The GPIO input data register returns the current state of the GPIO terminals when read. Bit Name Type Default R X R X R X 7 6 5 4 R X 3 R 0 2 R 0 1 R 0 0 R 0 GPIO input data Register: Type: Offset: Default: BIT 7-4 3-0 TYPE R R GPIO input data Read-only 67h X0h Table 5-7. GPIO Input Data Register Description FUNCTION GPIO3-GPIO0 input data. These four bits return the current state of the GPIO terminals. Reserved. Bits 3-0 return 0s when read. 5-6 5.8 Secondary Clock Control Register The secondary clock control register is used to control the secondary clock outputs. Bit Name Type Default R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 11 10 9 R/W 0 8 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Secondary clock control Register: Type: Offset: Default: BIT 15-14 13 TYPE R R/W Secondary clock control Read-only, Read/Write 68h 0000h Table 5-8. Secondary Clock Control Register Description FUNCTION Reserved. These bits return 0 when read. S_CLKOUT9 disable. 0 = S_CLKOUT9 enabled (default). 1 = S_CLKOUT9 disabled and driven high. S_CLKOUT8 disable. 0 = S_CLKOUT8 enabled (Default). 1 = S_CLKOUT8 disabled and driven high. S_CLKOUT7 disable. 0 = S_CLKOUT7 enabled (default). 1 = S_CLKOUT7 disabled and driven high. S_CLKOUT6 disable. 0 = S_CLKOUT6 enabled (default). 1 = S_CLKOUT6 disabled and driven high. S_CLKOUT5 disable. 0 = S_CLKOUT5 enabled (default). 1 = S_CLKOUT5 disabled and driven high. S_CLKOUT4 disable. 0 = S_CLKOUT4 enabled (default). 1 = S_CLKOUT4 disabled and driven high. S_CLKOUT3 disable. 00, 01, 10 = S_CLKOUT3 enabled (00 is the default). 11 = S_CLKOUT3 disabled and driven high. S_CLKOUT2 disable. 00, 01, 10 = S_CLKOUT2 enabled (00 is the default). 11 = S_CLKOUT2 disabled and driven high. S_CLKOUT1 disable. 00, 01, 10 = S_CLKOUT1 enabled (00 is the default). 11 = S_CLKOUT1 disabled and driven high. S_CLKOUT0 disable. 00, 01, 10 = S_CLKOUT0 enabled (00 is the default). 11 = S_CLKOUT0 disabled and driven high. 12 R/W 11 R/W 10 R/W 9 R/W 8 R/W 7-6 R/W 5-4 R/W 3-2 R/W 1-0 R/W 5-7 5.9 P_SERR Status Register The P_SERR status register indicates what caused a SERR event on the primary interface. Bit Name Type Default R 0 R/W 0 R/W 0 7 6 5 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R 0 P_SERR status Register: Type: Offset: Default: BIT 7 6 5 4 3 2 1 0 TYPE R R/W R/W R/W R/W R/W R/W R P_SERR status Read-only Read/Write 6Ah 00h Table 5-9. P_SERR Status Register Description FUNCTION Reserved. Bit 7 returns 0 when read. Master delayed read time-out. A 1 indicates that P_SERR was signaled because of a master time-out after 224 retries on a delayed read. Master delayed write time-out. A 1 indicates that P_SERR was signaled because of a master time-out after 224 retries on a delayed write. Master abort on posted write transactions. A 1 indicates that P_SERR was signaled because of a master abort on a posted write. Target abort on posted writes. A 1 indicates that P_SERR was signaled because of a target abort on a posted write. Master posted write time-out. A 1 indicates that P_SERR was signaled because of a master time-out after 224 retries on a posted write. Posted write parity error. A 1 indicates that P_SERR was signaled because of parity error on a posted write. Reserved. Bit 0 returns 0 when read. 5.10 Power-Management Capability ID Register The power-management capability ID register identifies the linked list item as the register for PCI power management. The power-management capability ID register returns 01h when read, which is the unique ID assigned by the PCI SIG for the PCI location of the capabilities pointer and the value. Bit Name Type Default R 0 R 0 R 0 7 6 5 4 3 2 1 0 Power-management capability ID R 0 R 0 R 0 R 0 R 1 Register: Type: Offset: Default: Power-management capability ID Read-only DCh 01h 5-8 5.11 Power-Management Next-Item Pointer Register The power-management next-item pointer register is used to indicate the next item in the linked list of PCI power-management capabilities. The next-item pointer returns E4h in CompactPCI mode, indicating that the PCI2050 supports more than one extended capability, but in all other modes returns 00h, indicating that only one extended capability is provided. Bit Name Type Default R 1 R 1 R 1 7 6 5 4 3 2 1 0 Power-management next-item pointer R 0 R 0 R 1 R 0 R 0 Register: Type: Offset: Default: Power-management next-item pointer Read-only DDh E4h cPCI mode 00h All other modes 5.12 Power-Management Capabilities Register The power management capabilities register contains information on the capabilities of the PCI2050 functions related to power management. The PCI2050 function supports D0, D1, D2, and D3 power states when MS1 is low. The PCI2050 does not support any power states when MS1 is high. Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Power-management capabilities R 1 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 1 R 0 Register: Type: Offset: Default: Power-management capabilities Read-only DEh 0602h or 0001h Table 5-10. Power-Management Capabilities Register Description BIT 15-11 TYPE R FUNCTION PME support. This five-bit field indicates the power states that the device supports asserting PME. A 0 for any of these bits indicates that the PCI2050 cannot assert PME from that power state. For the PCI2050, these five bits return 00000b when read, indicating that PME is not supported. D2 support. This bit returns 1 when MS0 is 0, indicating that the bridge function supports the D2 device power state. This bit returns 0 when MS0 is 1, indicating that the bridge function does not support the D2 device power state. D1 support. This bit returns 1 when MS0 is 0, indicating that the bridge function supports the D1 device power state. This bit returns 0 when MS0 is 1, indicating that the bridge function does not support the D1 device power state. Reserved. Bits 8-6 return 0s when read. Device specific initialization. This bit returns 0 when read, indicating that the bridge function does not require special initialization (beyond the standard PCI configuration header) before the generic class device driver is able to use it. Auxiliary power source. This bit returns a 0 when read because the PCI2050 does not support PME signaling. PMECLK. This bit returns a 0 when read because the PME signaling is not supported. Version. This three-bit register returns the PCI Bus Power Management Interface Specification revision. 001 = Revision 1.0, MS0 = 1 010 = Revision 1.1, MS0 = 0 10 9 8-6 5 4 3 2-0 R R R R R R R 5-9 5.13 Power-Management Control/Status Register The power-management control/status register determines and changes the current power state of the PCI2050. The contents of this register are not affected by the internally generated reset caused by the transition from D3hot to D0 state. Bit Name Type Default R 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Power-management control/status R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 R/W 0 Register: Type: Offset: Default: Power-management control/status Read-only, Read/Write E0h 0000h Table 5-11. Power-Management Control/Status Register BIT 15 14-13 12-9 8 7-2 TYPE R R R R R FUNCTION PME status. This bit returns a 0 when read because the PCI2050 does not support PME. Data scale. This 2-bit read-only field indicates the scaling factor to be used when interpreting the value of the data register. These bits return only 00b, because the data register is not implemented. Data select. This 4-bit field is used to select which data is to be reported through the data register and data-scale field. These bits return only 0000b, because the data register is not implemented. PME enable. This bit returns a 0 when read because the PCI2050 does not support PME signaling. Reserved. Bits 7-2 return 0s when read. Power state. This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. The definition of this is given below: 00 - D0 01 - D1 10 - D2 11 - D3hot 1-0 R/W 5-10 5.14 PMCSR Bridge Support Register The PMCSR bridge support register is required for all PCI bridges and supports PCI-bridge-specific functionality. Bit Name Type Default R X R X R 0 7 6 5 4 3 2 1 0 PMCSR bridge support R 0 R 0 R 0 R 0 R 0 Register: Type: Offset: Default: PMCSR bridge support Read-only E2h X0h Table 5-12. PMCSR Bridge Support Register Description BIT 7 TYPE R FUNCTION Bus power control enable. This bit returns the value of the MS1/BCC input. 0 = Bus power/ clock control disabled. 1 = Bus power/clock control enabled. B2/B3 support for D3hot. This bit returns the value of MS1/BCC input. When this bit is 1, the secondary clocks are stopped when the device is placed in D3hot. When this bit is 0, the secondary clocks remain on in all device states. Note: If the primary clock is stopped, then the secondary clocks will stop because the primary clock is used to generate the secondary clocks. 6 R 5-0 R Reserved. 5.15 Data Register The data register is an optional, 8-bit read-only register that provides a mechanism for the function to report state-dependent operating data such as power consumed or heat dissipation. The PCI2050 does not implement the data register. Bit Name Type Default R 0 R 0 R 0 R 0 7 6 5 4 Data R 0 R 0 R 0 R 0 3 2 1 0 Register: Type: Offset: Default: Data Read-only E3h 00h 5-11 5.16 HS Capability ID Register The HS capability ID register identifies the linked list item as the register for cPCI hot-swap capabilities. The register returns 06h when read, which is the unique ID assigned by the PICMG for PCI location of the capabilities pointer and the value. In IntelTM-compatible mode, this register is read-only and defaults to 00h. Bit Name Type Default R 0 R 0 R 0 7 6 5 4 R 0 3 R 0 2 R 1 1 R 1 0 R 0 HS capability ID Register: Type: Offset: Default: HS capability ID Read-only E4h 06h TI mode 00h Intel-compatible mode 5.17 HS Next-Item Pointer Register The HS next-item pointer register is used to indicate the next item in the linked list of cPCI hot swap capabilities. Because this is the last extended capability that the PCI2050 supports, the next-item pointer returns all 0s. Bit Name Type Default R 0 R 0 R 0 7 6 5 4 R 0 3 R 0 2 R 0 1 R 0 0 R 0 HS next-item pointer Register: Type: Offset: Default: HS next-item pointer Read-only E5h 00h 5-12 5.18 Hot-Swap Control Status Register The hot-swap control status register contains control and status information for cPCI hot swap resources. Bit Name Type Default R 0 R 0 R 0 7 6 5 4 R 0 3 R/W 0 2 R 0 1 R/W 0 0 R 0 Hot swap control status Register: Type: Offset: Default: BIT TYPE Hot-swap control status Read-only, Read/Write E6h 00h Table 5-13. Hot-Swap Control Status Register Description FUNCTION 7 R ENUM insertion status. When set, the ENUM output is driven by the PCI2050. This bit defaults to 0, and will be set after a PCI reset occurs, the pre-load of serial ROM is complete, the ejector handle is closed, and bit 6 is 0. Thus, this bit is set following an insertion when the board implementing the PCI2050 is ready for configuration. This bit cannot be set under software control. ENUM extraction status. When set, the ENUM output is driven by the PCI2050. This bit defaults to 0, and is set when the ejector handle is opened and bit 7 is 0. Thus, this bit is set when the board implementing the PCI2050 is about to be removed. This bit cannot be set under software control. Reserved. Bits 5 and 4 return 0s when read. LED ON/OFF. This bit defaults to 0, and controls the external LED indicator (HSLED) under normal conditions. However, for a duration following a PCI_RST, the HSLED output is driven high by the PCI2050 and this bit is ignored. When this bit is interpreted, a 1 causes HSLED high and a 0 causes HSLED low. Following PCI_RST, the HSLED output is driven high by the PCI2050 until the ejector handle is closed. When these conditions are met, the HSLED is under software control via this bit. 6 5-4 R R 3 R/W 2 R Reserved. Bit 2 returns 0 when read. ENUM interrupt mask. This bit allows the HSENUM output to be masked by software. Bits 6 and 7 are set independently from this bit. 0 = Enable HSENUM output 1 = Mask HSENUM output Reserved. Bit 0 returns 0 when read. 1 R/W 0 R 5-13 5-14 6 Electrical Characteristics 6.1 Absolute Maximum Ratings Over Operating Temperature Ranges Supply voltage range: VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 3.6 V : S_VCCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 6 V : P_VCCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 6 V Input voltage range, VI: PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 6.5 V Output voltage range, VO: PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Applies for external input and bidirectional buffers. VI > VCC does not apply to fail-safe terminals. 2. Applies to external output and bidirectional buffers. VO > VCC does not apply to fail-safe terminals. 6-1 6.2 Recommended Operating Conditions (see Note 3) OPERATION VCC P_V P VCCP S_V S VCCP VIH VIL VI VO tt TA Supply voltage (core) PCI primary bus I/O clamping rail voltage PCI secondary bus I/O clamping rail voltage High-level input oltage High le el inp t voltage Low level input voltage Low-level Input voltage Output voltage Input transition time (tr and tf) Operating ambient temperature range PCI PCI2050 PCI2050I 3.3 V 3.3 V Commercial Commercial Commercial PCI PCI PCI 3.3 V 5V 3.3 V 3.3 V 5V 3.3 V 5V 3.3 V 5V 3.3 V 5V MIN 3 3 4.75 3 4.75 0.5 VCCP 2 0 0 0 0 0 1 0 -40 25 25 NOM 3.3 3.3 5 3.3 5 MAX 3.6 3.6 5.25 3.6 5.25 VCCP VCCP 0.3 VCCP 0.8 VCCP VCC VCC 4 70 85 115 V V V V V nS C C V UNIT V 5V 0 25 Virtual junction temperature TJ NOTES: 3. Unused or floating pins (input or I/O) must be held high or low. Applies for external input and bidirectional buffers without hysteresis Applies for external output buffers These junction temperatures reflect simulation conditions. The customer is responsible for verifying junction temperature. 6.3 Recommended Operating Conditions for PCI Interface OPERATION VCC P_V P VCCP S_V S VCCP VI VO VIH VIL Core voltage PCI supply voltage PCI supply voltage Input voltage Output voltage High-level input oltage High le el inp t voltage Low-level Low level input voltage CMOS compatible CMOS compatible Commercial Commercial Commercial 3.3 V 3.3 V 5V 3.3 V 5V 3.3 V 5V 3.3 V 5V 3.3 V 5V 3.3 V 5V MIN 3 3 4.75 3 4.75 0 0 0 0 0.5 VCCP 2 0.3 VCCP 0.8 NOM 3.3 3.3 5 3.3 5 MAX 3.6 3.6 5.25 3.6 5.25 VCCP VCCP VCCP VCCP V V V V V V UNIT V Applies to external output buffers Applies to external input and bidirectional buffers without hysteresis 6-2 6.4 Electrical Characteristics Over Recommended Operating Conditions PARAMETER TERMINALS OPERATION 3.3 V VOH High level output High-level out ut voltage TTL VOL IIH IIL Low-level Low level output voltage Input terminals, PCI High-level High level input current g I/O terminals Input terminals, PCI Low-level Low level input current I/O terminals VI = GND 5V 5V 3.3 V 5V TEST CONDITIONS IOH = -0.5 mA IOH = -2 mA IOH = -1.4 mA IOL = 1.5 mA IOL = 6 mA VI = VCCP VI = VCCP MIN 0.9 VCC 2.4 2.4 0.1 VCC 0.55 10 10 -1 -10 10 V A A A A MAX UNIT V IOZ High-impedance output current VO = VCCP or GND For I/O terminals, the input leakage current includes the off-state output current IOZ. For TTL signals, IOH = 1.4 mA is the test condition for the industrial-temperature-range PCI2050I. 6-3 6.5 PCI Clock/Reset Timing Requirements Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature (see Figure 6-2 and Figure 6-3) ALTERNATE SYMBOL tc twH twL v/t tw Cycle time, PCLK Pulse duration, PCLK high Pulse duration, PCLK low Slew rate, PCLK Pulse duration, RSTIN tcyc thigh tlow tr, tf trst MIN 30 11 11 1 1 MAX UNIT ns ns ns 4 V/ns ms tsu Setup time, PCLK active at end of RSTIN (see Note 4 ) trst-clk 100 ms NOTE 4: The setup and hold times for the secondary are identical to those for the primary; however, the times are relative to the secondary PCI clock. 6-4 6.6 PCI Timing Requirements Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature (see Note 5 and Figure 6-1 and Figure 6-4) ALTERNATE SYMBOL PCLK to shared signal valid delay time tpd Propagation delay time PCLK to shared signal invalid delay time tval CL = 50 pF, See Note 6 pF tinv ton toff tsu, See Note 4 th, See Note 4 7 0 2 2 28 ns ns ns ns TEST CONDITIONS MIN MAX 11 UNIT ns ten tdis tsu th Enable time, high-impedance-to-active delay time from PCLK Disable time, active-to-high-impedance delay time from PCLK Setup time before PCLK valid Hold time after PCLK high 5. This data sheet uses the following conventions to describe time (t) intervals. The format is: tA, where subscript A indicates the type of dynamic parameter being represented. The following are used: tpd = propagation delay time, tsu = setup time, and th = hold time. 6. PCI shared signals are AD31-AD0, C/BE3-C/BE0, FRAME, TRDY, IRDY, STOP, IDSEL, DEVSEL, and PAR. 6-5 6.7 Parameter Measurement Information LOAD CIRCUIT PARAMETERS TIMING PARAMETER tPZH ten tPZL tPHZ tdis tPLZ tpd CLOAD (pF) 50 50 50 IOL (mA) 8 8 8 IOH (mA) -8 -8 -8 VLOAD (V) 0 3 1.5 From Output Under Test Test Point VLOAD CLOAD IOH IOL CLOAD includes the typical load-circuit distributed capacitance. VLOAD - VOL = 50 , where V OL = 0.6 V, IOL = 8 mA IOL LOAD CIRCUIT Timing Input (see Note A ) tsu Data 90% VCC Input 10% VCC tr VCC 50% VCC 0V th VCC 50% VCC 50% VCC tf 0V Low-Level Input tw 50% VCC High-Level Input 50% VCC VCC 50% VCC 0V VCC 50% VCC 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES INPUT RISE AND FALL TIMES Output Control (low-level enabling) tPZL 0V tpd In-Phase Output tpd Out-of-Phase Output 50% VCC 50% VCC tpd VOH 50% VCC VOL tpd VOH 50% VCC VOL Waveform 1 (see Note B) tPZH Waveform 2 (see Note B) VOLTAGE WAVEFORMS PULSE DURATION VCC 50% VCC 50% VCC 0V tPLZ VCC 50% VCC VOL + 0.3 V VOL VOH VOH - 0.3 V 50% VCC 0V Input (see Note A) VCC 50% VCC 50% VCC 50% VCC tPHZ 50% VCC VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by pulse generators having the following characteristics: PRR = 1 MHz, ZO = 50 , tr 6 ns, tf 6 ns. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. For tPLZ and tPHZ, VOL and VOH are measured values. Figure 6-1. Load Circuit and Voltage Waveforms 6-6 6.8 PCI Bus Parameter Measurement Information twH 2V 0.8 V tr tc tf twL 2 V min Peak-to-Peak Figure 6-2. PCLK Timing Waveform PCLK tw RSTIN tsu Figure 6-3. RSTIN Timing Waveforms PCLK 1.5 V tpd tpd Valid toff Valid tsu th PCI Output 1.5 V ton PCI Input Figure 6-4. Shared-Signals Timing Waveforms 6-7 6-8 7 Mechanical Data GHK (S-PBGA-N209) 16,10 SQ 15,90 0,80 W V U T R P N M L K J H G F E D C B A 1 2 0,95 0,85 1,40 MAX 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 PLASTIC BALL GRID ARRAY 14,40 TYP Seating Plane 0,12 0,08 0,55 0,45 0,08 M 0,10 0,45 0,35 4145273-2/B 12/98 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. MicroStar BGATM configuration MicroStar BGA is a trademark of Texas Instruments. 0,80 7-1 PDV (S-PQFP-G208) 156 105 PLASTIC QUAD FLATPACK 157 104 0,27 0,17 0,08 M 0,50 0,13 NOM 208 53 1 25,50 TYP 28,05 SQ 27,95 30,20 SQ 29,80 1,45 1,35 52 Gage Plane 0,25 0,05 MIN 0- 7 0,75 0,45 Seating Plane 0,08 1,60 MAX 4087729/D 11/98 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 7-2 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 2000, Texas Instruments Incorporated |
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