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SN54LV161A, SN74LV161A 4-BIT SYNCHRONOUS BINARY COUNTERS
SCLS404A - APRIL 1998 - REVISED MAY 2000
D D D D D D D D D D
5 6 7 8
17 16 15 14 9 10 11 12 13
description
The 'LV161A devices are 4-bit synchronous binary counters designed for 2-V to 5.5-V VCC operation.
These synchronous, presettable counters feature NC - No internal connection an internal carry look-ahead for application in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes that normally are associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform. These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs. The clear function for the 'LV161A devices is asynchronous. A low level at the clear (CLR) input sets all four of the flip-flop outputs low, regardless of the levels of the CLK, load (LOAD), or enable inputs. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are ENP, ENT, and a ripple-carry output (RCO). Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a high-level pulse while the count is maximum (9 or 15 with QA high). This high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
Copyright (c) 2000, Texas Instruments Incorporated
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PRODUCT PREVIEW
EPIC TM (Enhanced-Performance Implanted CMOS) Process Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25C Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25C 2-V to 5.5-V VCC Operation Support Mixed-Mode Voltage Operation on All Ports Internal Look-Ahead for Fast Counting Carry Output for n-Bit Cascading Synchronous Counting Synchronously Programmable Package Options Include Plastic Small-Outline (D, NS), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages, Ceramic Flat (W) Packages, Chip Carriers (FK), and DIPs (J)
SN54LV161A . . . J OR W PACKAGE SN74LV161A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW)
CLR CLK A B C D ENP GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC RCO QA QB QC QD ENT LOAD
SN54LV161A . . . FK PACKAGE (TOP VIEW)
A B NC C D
CLK CLR NC VCC RCO
4 3 2 1 20 19 18
QA QB NC QC QD
LOAD ENT
ENP GND NC
SN54LV161A, SN74LV161A 4-BIT SYNCHRONOUS BINARY COUNTERS
SCLS404A - APRIL 1998 - REVISED MAY 2000
description (continued)
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times. The SN54LV161A is characterized for operation over the full military temperature range of -55C to 125C. The SN74LV161A is characterized for operation from -40C to 85C.
logic symbol
1 9 10 7 2 3 4 5 6 CTRDIV16 CT=0 M1 M2 G3 G4 C5/2,3,4+ 1,5D [1] [2] [4] [8] 14 13 12 11 QA QB QC QD 15
CLR LOAD ENT ENP CLK
3CT=15
RCO
PRODUCT PREVIEW
A B C D
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
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SN54LV161A, SN74LV161A 4-BIT SYNCHRONOUS BINARY COUNTERS
SCLS404A - APRIL 1998 - REVISED MAY 2000
logic diagram (positive logic)
LOAD ENT ENP 9 10 7 LD CK CLK CLR 2 1 CK R LD 15
RCO
A
3
B
4
M1 G2 1, 2T/1C3 G4 3D 4R
13
QB
C
5
M1 G2 1, 2T/1C3 G4 3D 4R
12
QC
D
6
M1 G2 1, 2T/1C3 G4 3D 4R
11
QD
For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown on the logic diagram of the D/T flip-flops. Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
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PRODUCT PREVIEW
M1 G2 1, 2T/1C3 G4 3D 4R
14
QA
SN54LV161A, SN74LV161A 4-BIT SYNCHRONOUS BINARY COUNTERS
SCLS404A - APRIL 1998 - REVISED MAY 2000
logic symbol, each D/T flip-flop
LD (Load) TE (Toggle Enable) CK (Clock) M1 G2 1, 2T/1C3 G4 3D 4R Q (Output)
D (Inverted Data) R (Inverted Reset)
logic diagram, each D/T flip-flop (positive logic)
CK LD TE LD
PRODUCT PREVIEW
TG
TG LD D TG TG TG CK CK TG
Q
CK R The origins of LD and CK are shown in the logic diagram of the overall device.
CK
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SN54LV161A, SN74LV161A 4-BIT SYNCHRONOUS BINARY COUNTERS
SCLS404A - APRIL 1998 - REVISED MAY 2000
typical clear, preset, count, and inhibit sequence
The following sequence is illustrated below: 1. Clear outputs to zero (asynchronous) 2. Preset to binary 12 3. Count to 13, 14, 15, 0, 1, and 2 4. Inhibit
CLR LOAD A B C D CLK ENP ENT QA QB QC QD RCO 12 13 14 15 0 1 2 Inhibit Count Sync Preset Clear Async Clear
Data Inputs
Data Outputs
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PRODUCT PREVIEW
SN54LV161A, SN74LV161A 4-BIT SYNCHRONOUS BINARY COUNTERS
SCLS404A - APRIL 1998 - REVISED MAY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51.
PRODUCT PREVIEW
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SN54LV161A, SN74LV161A 4-BIT SYNCHRONOUS BINARY COUNTERS
SCLS404A - APRIL 1998 - REVISED MAY 2000
recommended operating conditions (see Note 4)
SN54LV161A MIN VCC Supply voltage VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 0 0 VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 0 0 0 2 1.5 VCC x 0.7 VCC x 0.7 VCC x 0.7 0.5 VCC x 0.3 VCC x 0.3 VCC x 0.3 5.5 VCC -50 -2 -6 -12 50 2 6 12 200 100 20 0 0 0 0 0 MAX 5.5 SN74LV161A MIN 2 1.5 VCC x 0.7 VCC x 0.7 VCC x 0.7 0.5 VCC x 0.3 VCC x 0.3 VCC x 0.3 5.5 VCC -50 -2 -12 50 2 6 12 200 100 20 ns/V mA A -6 V V MAX 5.5 UNIT V
VIH
High-level High level input voltage
VIL
Low-level Low level input voltage
VI VO
Input voltage Output voltage
V V A mA
IOH
High-level High level output current
IOL
Low-level Low level output current
t/v
Input transition rise or fall rate
TA Operating free-air temperature -55 125 -40 85 C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS IOH = -50 A IOH = -2 mA IOH = -6 mA IOH = -12 mA IOL = 50 A IOL = 2 mA IOL = 6 mA IOL = 12 mA VI = VCC or GND VI = VCC or GND, VI or VO = 0 to 5.5 V VI = VCC or GND IO = 0 SN54LV161A VCC 2 V to 5.5 V 2.3 V 3V 4.5 V 2 V to 5.5 V 2.3 V 3V 4.5 V 0 V to 5.5 V 5.5 V 0V 3.3 V 5V MIN VCC-0.1 2 2.48 3.8 0.1 0.4 0.44 0.55 1 20 5 TYP MAX SN74LV161A MIN VCC-0.1 2 2.48 3.8 0.1 0.4 0.44 0.55 1 20 5 A A A pF V TYP MAX UNIT
VOH
V
VOL
II ICC Ioff Ci
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SN54LV161A, SN74LV161A 4-BIT SYNCHRONOUS BINARY COUNTERS
SCLS404A - APRIL 1998 - REVISED MAY 2000
timing requirements over recommended operating free-air temperature range, VCC = 2.5 V 0.2 V (unless otherwise noted) (see Figure 1)
TA = 25C MIN MAX tw Pulse duration CLK high or low CLR low CLR tsu Data (A, B, C, and D) Setup Set p time before CLK ENP, ENT LOAD low th Hold time, all synchronous inputs after CLK ns ns SN54LV161A MIN MAX SN74LV161A MIN MAX UNIT ns
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
TA = 25C MIN MAX SN54LV161A MIN MAX SN74LV161A MIN MAX UNIT ns
PRODUCT PREVIEW
tw
Pulse duration
CLK high or low CLR low CLR Data (A, B, C, and D)
tsu
Setup Set p time before CLK
ENP, ENT LOAD low
ns
th
Hold time, all synchronous inputs after CLK
ns
timing requirements over recommended operating free-air temperature range, VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25C MIN MAX tw Pulse duration CLK high or low CLR low CLR tsu Data (A, B, C, and D) Setup Set p time before CLK ENP, ENT LOAD low th Hold time, all synchronous inputs after CLK ns ns SN54LV161A MIN MAX SN74LV161A MIN MAX UNIT ns
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SN54LV161A, SN74LV161A 4-BIT SYNCHRONOUS BINARY COUNTERS
SCLS404A - APRIL 1998 - REVISED MAY 2000
switching characteristics over recommended operating free-air temperature range, VCC = 2.5 V 0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER fmax tPLH* tPHL* tPLH* tPHL* tPLH* tPHL* tPLH* tPHL* tPHL* tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL CLK CLK CLK Q RCO (count mode) RCO (preset mode) RCO Q CLR RCO Q RCO (count mode) RCO (preset mode) RCO Q RCO CL = 50 pF ns CL = 15 pF ns FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE CL = 15 pF* CL = 50 pF MIN TA = 25C TYP MAX SN54LV161A MIN MAX SN74LV161A MIN MAX UNIT MHz
ENT
CLK CLK CLK
ENT CLR
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
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PRODUCT PREVIEW
SN54LV161A, SN74LV161A 4-BIT SYNCHRONOUS BINARY COUNTERS
SCLS404A - APRIL 1998 - REVISED MAY 2000
switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER fmax tPLH* tPHL* tPLH* tPHL* tPLH* tPHL* tPLH* tPHL* tPHL* CLK CLK CLK Q RCO (count mode) RCO (preset mode) RCO Q CLR RCO Q RCO (count mode) RCO (preset mode) RCO Q RCO CL = 50 pF ns CL = 15 pF ns FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE CL = 15 pF* CL = 50 pF MIN TA = 25C TYP MAX SN54LV161A MIN MAX SN74LV161A MIN MAX UNIT MHz
ENT
PRODUCT PREVIEW
tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL
CLK CLK CLK
ENT CLR
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
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SN54LV161A, SN74LV161A 4-BIT SYNCHRONOUS BINARY COUNTERS
SCLS404A - APRIL 1998 - REVISED MAY 2000
switching characteristics over recommended operating free-air temperature range, VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER fmax tPLH* tPHL* tPLH* tPHL* tPLH* tPHL* tPLH* tPHL* tPHL* tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL CLK CLK CLK Q RCO (count mode) RCO (preset mode) RCO Q CLR RCO Q RCO (count mode) RCO (preset mode) RCO Q RCO CL = 50 pF ns CL = 15 pF ns FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE CL = 15 pF* CL = 50 pF MIN TA = 25C TYP MAX SN54LV161A MIN MAX SN74LV161A MIN MAX UNIT MHz
ENT
CLK CLK CLK
ENT CLR
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25C (see Note 5)
PARAMETER VOL(P) VOL(V) VOH(V) VIH(D) Quiet output, maximum dynamic VOL Quiet output, minimum dynamic VOL Quiet output, minimum dynamic VOH High-level dynamic input voltage SN74LV161A MIN TYP MAX UNIT V V V V V
VIL(D) Low-level dynamic input voltage NOTE 5: Characteristics are for surface-mount packages only.
operating characteristics, TA = 25C
PARAMETER Cpd Power dissi ation ca acitance dissipation capacitance TEST CONDITIONS CL = 50 pF F, f = 10 MHz VCC 3.3 V 5V TYP UNIT pF F
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PRODUCT PREVIEW
SN54LV161A, SN74LV161A 4-BIT SYNCHRONOUS BINARY COUNTERS
SCLS404A - APRIL 1998 - REVISED MAY 2000
PARAMETER MEASUREMENT INFORMATION
RL = 1 k S1 VCC Open GND
From Output Under Test CL (see Note A)
Test Point
From Output Under Test CL (see Note A)
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain
S1 Open VCC GND VCC
LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS VCC Timing Input 50% VCC 0V VCC tsu Data Input 0V 50% VCC th VCC 50% VCC 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC VCC 50% VCC tPZL Output Waveform 1 S1 at VCC (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZH tPLZ 50% VCC tPHZ VOH - 0.3 V VOH 0V 50% VCC 0V VCC VOL + 0.3 V VOL
tw
Input
50% VCC
50% VCC
PRODUCT PREVIEW
VOLTAGE WAVEFORMS PULSE DURATION
Input tPLH In-Phase Output tPHL Out-of-Phase Output
50% VCC
50% VCC tPHL
0V
Output Control
50% VCC
VOH 50% VCC VOL tPLH
50% VCC
VOH 50% VCC VOL
50% VCC
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr 3 ns, tf 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated

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