View SCLS396B_1001231.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SN54LV139A, SN74LV139A DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS
SCLS396B - APRIL 1998 - REVISED MAY 2000
D D D D D D D D
EPIC TM (Enhanced-Performance Implanted CMOS) Process 2-V to 5.5-V VCC Operation Support Mixed-Mode Voltage Operation on All Ports Designed Specifically for High-Speed Memory Decoders and Data-Transmission Systems Incorporate Two Enable Inputs to Simplify Cascading and/or Data Reception Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Package Options Include Plastic Small-Outline (D, NS), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages, Ceramic Flat (W) Packages, Chip Carriers (FK), and DIPs (J)
SN54LV139A . . . J OR W PACKAGE SN74LV139A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW)
1G 1A 1B 1Y0 1Y1 1Y2 1Y3 GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC 2G 2A 2B 2Y0 2Y1 2Y2 2Y3
SN54LV139A . . . FK PACKAGE (TOP VIEW)
1A 1G NC VCC 2G 1B 1Y0 NC 1Y1 1Y2
4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
2A 2B NC 2Y0 2Y1
description
The 'LV139A devices are dual 2-line to 4-line decoders/demultiplexers designed for 2-V to 5.5-V VCC operation.
NC - No internal connection
These devices are designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay time of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. The 'LV139A devices comprise two individual 2-line to 4-line decoders in a single package. The active-low enable (G) input can be used as a data line in demultiplexing applications. These decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit. The SN54LV139A is characterized for operation over the full military temperature range of -55C to 125C. The SN74LV139A is characterized for operation from -40C to 85C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
Copyright (c) 2000, Texas Instruments Incorporated
* DALLAS, TEXAS 75265
1Y3 GND NC 2Y3 2Y2
1
SN54LV139A, SN74LV139A DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS
SCLS396B - APRIL 1998 - REVISED MAY 2000
FUNCTION TABLE INPUTS SELECT G H L L L L B X L L H H A X L H L H Y0 H L H H H OUTPUTS Y1 H H L H H Y2 H H H L H Y3 H H H H L
logic symbols (alternatives)
X/Y 1A 1B 1G 2 3 1 0 1 2 EN 1 2 3 4 5 6 7 12 11 10 9 DMUX 1Y0 1A 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 1B 1G 2 3 1 0 0 1 0 G 3 1 2 3 14 13 15 4 5 6 7 12 11 10 9 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3
2A 2B 2G
14 13 15
2A 2B 2G
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
2
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54LV139A, SN74LV139A DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS
SCLS396B - APRIL 1998 - REVISED MAY 2000
logic diagram (positive logic)
4 1Y0
1G
1
5 1Y1
6 2 1A 7 1B 3
1Y2
1Y3
12 2Y0 15 2G 11 2Y1
10 2Y2 2A 2B Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages. 14 13 9 2Y3
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
3
SN54LV139A, SN74LV139A DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS
SCLS396B - APRIL 1998 - REVISED MAY 2000
recommended operating conditions (see Note 4)
SN54LV139A MIN VCC Supply voltage VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 0 0 VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 0 0 0 2 1.5 VCC x 0.7 VCC x 0.7 VCC x 0.7 0.5 VCC x 0.3 VCC x 0.3 VCC x 0.3 5.5 VCC -50 -2 -6 -12 50 2 6 12 200 100 20 0 0 0 0 0 MAX 5.5 SN74LV139A MIN 2 1.5 VCC x 0.7 VCC x 0.7 VCC x 0.7 0.5 VCC x 0.3 VCC x 0.3 VCC x 0.3 5.5 VCC -50 -2 -6 -12 50 2 6 12 200 100 20 ns/V mA A mA V V MAX 5.5 UNIT V
VIH
High-level High level input voltage
VIL
Low-level Low level input voltage
VI VO
Input voltage Output voltage
V V A
IOH
High-level High level output current
IOL
Low-level Low level output current
t/v
Input transition rise or fall rate
TA Operating free-air temperature -55 125 -40 85 C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS IOH = -50 A IOH = -2 mA IOH = -6 mA IOH = -12 mA IOL = 50 A IOL = 2 mA IOL = 6 mA IOL = 12 mA VI = VCC or GND VI = VCC or GND, VI or VO = 0 to 5.5 V VI = VCC or GND IO = 0 SN54LV139A VCC 2 V to 5.5 V 2.3 V 3V 4.5 V 2 V to 5.5 V 2.3 V 3V 4.5 V 0 V to 5.5 V 5.5 V 0V 3.3 V 1.9 MIN VCC-0.1 2 2.48 3.8 0.1 0.4 0.44 0.55 1 20 5 1.9 TYP MAX SN74LV139A MIN VCC-0.1 2 2.48 3.8 0.1 0.4 0.44 0.55 1 20 5 A A A pF V TYP MAX UNIT
VOH
V
VOL
II ICC Ioff Ci
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
4
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54LV139A, SN74LV139A DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS
SCLS396B - APRIL 1998 - REVISED MAY 2000
switching characteristics over recommended operating VCC = 2.5 V 0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER tpd d tpd d FROM (INPUT) A or B G A or B G TO (OUTPUT) Y Y Y Y LOAD CAPACITANCE CL = 15 pF CL = 50 pF MIN
free-air
temperature
SN74LV139A MIN 1 1 1 1 MAX 21 19 26.5 24
range,
UNIT ns ns
TA = 25C TYP MAX 7.7* 7.4* 10.2 9.9 17.6* 15.8* 22.5 20.2
SN54LV139A MIN 1* 1* 1 1 MAX 21* 19* 26.5 24
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating VCC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER tpd d tpd d FROM (INPUT) A or B G A or B G TO (OUTPUT) Y Y Y Y LOAD CAPACITANCE CL = 15 pF CL = 50 pF MIN
free-air
temperature
SN74LV139A MIN 1 1 1 1 MAX 13 11 16.5 14.5
range,
UNIT ns ns
TA = 25C TYP MAX 5.3* 5.1* 7.3 7 11* 9.2* 14.5 12.7
SN54LV139A MIN 1* 1* 1 1 MAX 13* 11* 16.5 14.5
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER tpd d tpd d FROM (INPUT) A or B G A or B G TO (OUTPUT) Y Y Y Y LOAD CAPACITANCE CL = 15 pF CL = 50 pF MIN
free-air
temperature
SN74LV139A MIN 1 1 1 1 MAX 8.5 7.5 10.5 9.5
range,
UNIT ns ns
TA = 25C TYP MAX 3.7* 3.5* 5.2 4.9 7.2* 6.3* 9.2 8.3
SN54LV139A MIN 1* 1* 1 1 MAX 8.5* 7.5* 10.5 9.5
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
operating characteristics, TA = 25C
PARAMETER Cpd d Power dissipation capacitance TEST CONDITIONS CL = 50 pF pF, f = 10 MHz VCC 3.3 V 5V TYP 17.3 18.2 UNIT pF
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
5
SN54LV139A, SN74LV139A DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS
SCLS396B - APRIL 1998 - REVISED MAY 2000
PARAMETER MEASUREMENT INFORMATION
RL = 1 k S1 VCC Open GND
From Output Under Test CL (see Note A)
Test Point
From Output Under Test CL (see Note A)
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain
S1 Open VCC GND VCC
LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS VCC Timing Input 50% VCC 0V VCC tsu Data Input 0V 50% VCC th VCC 50% VCC 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC VCC 50% VCC tPZL Output Waveform 1 S1 at VCC (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZH tPLZ 50% VCC tPHZ VOH - 0.3 V VOH 0V 50% VCC 0V VCC VOL + 0.3 V VOL
tw
Input
50% VCC
50% VCC
VOLTAGE WAVEFORMS PULSE DURATION
Input tPLH In-Phase Output tPHL Out-of-Phase Output
50% VCC
50% VCC tPHL
0V
Output Control
50% VCC
VOH 50% VCC VOL tPLH
50% VCC
VOH 50% VCC VOL
50% VCC
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr 3 ns, tf 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated

▲Up To Search▲

Price & Availability of SCLS396B

	To Download SCLS396B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .