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CD74FCT861A
Data sheet acquired from Harris Semiconductor SCHS268
January 1997
Features
D ENDE OMM IGNS EC NOT R NEW DES ology Techn FOR
Use C MOS
* * * * * *
BiCMOS FCT Interface Logic, 10-Bit Bus Transceiver, Three-State
Circuit Design Speed of Bipolar FASTTM/AS/S 48mA Output Sink Current Output Voltage Swing Limited to 3.7V at VCC = 5V Controlled Output Edge Rates Input/Output Isolation to VCC BiCMOS Technology with Low Quiescent Power
* Buffered Inputs * Typical Propagation Delay: 6.0ns at VCC = 5V, TA = 25oC, CL = 50pF * CD74FCT861A - Noninverting * SCR Latchup Resistant BiCMOS Process and
Ordering Information
PART NUMBER CD74FCT861AM TEMP. RANGE (oC) 0 to 70 PACKAGE 24 Ld SOIC PKG. NO. M24.3
NOTE: When ordering the suffix M package, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel.
Pinout
CD74FCT861A (SOIC) TOP VIEW
OEBA 1 A0 2 A1 3 A2 4 A3 5 A4 6 A5 7 A6 8 A7 9 A8 10 A9 11 GND 12
24 VCC 23 B0 22 B1 21 B2 20 B3 19 B4 18 B5 17 B6 16 B7 15 B8 14 B9 13 OEAB
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. FASTTM is a trademark of Fairchild Semiconductor. Copyright (c) Harris Corporation 1996
File Number
2392.2
8-1
CD74FCT861A Functional Diagram
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 OEAB OEBA 2 3 4 5 6 7 8 9 10 11 13 1 GND = PIN 12 VCC = PIN 24 23 22 21 20 19 18 17 16 15 14 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9
TRUTH TABLE (Note 1) INPUTS OEBA L L H H H L NOTE: 1. H= HIGH Voltage Level L = LOW Voltage Level N/A = Not Applicable X = Immaterial Z = HIGH Impedance OEAB H H L L H L B L H N/A N/A X A N/A N/A L H X OUTPUTS B N/A N/A L H Z A L H N/A N/A Z FUNCTION B Data to A Bus B Data to A Bus A Data to B Bus A Data to B Bus High Z A Data to B Bus, B Data to A Bus
IEC Logic Symbol
CD74FCT861A
13 1 2 3 4 5 6 7 8 9 10 11
EN 1 2 22 21 20 19 18 17 16 15 14 23
8-2
CD74FCT861A
Absolute Maximum Ratings
DC Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V DC Diode Current, IIK (For VI < -0.5V) . . . . . . . . . . . . . . . . . . -20mA DC Output Diode Current, IOK (for VO < -0.5V) . . . . . . . . . . . -50mA DC Output Sink Current per Output Pin, IO . . . . . . . . . . . . . . . 70mA DC Output Source Current per Output Pin, IO . . . . . . . . . . . . -30mA DC VCC Current (ICC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264mA DC Ground Current (IGND). . . . . . . . . . . . . . . . . . . . . . . . . . . 500mA
Thermal Information
Thermal Resistance (Typical, Note 2) JA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (Lead Tips Only)
Operating Conditions
Operating Temperature Range, TA . . . . . . . . . . . . . . . . .0oC to 70oC Supply Voltage Range, VCC . . . . . . . . . . . . . . . . . . .4.75V to 5.25V DC Input Voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC DC Output Voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC Input Rise and Fall Slew Rate, dt/dv. . . . . . . . . . . . . . . . 0 to 10ns/V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 2. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications Commercial Temperature Range 0oC to 70oC, VCC Max = 5.25V, VCC Min = 4.75V
AMBIENT TEMPERATURE (TA) TEST CONDITIONS PARAMETER High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage High Level Input Current Low Level Input Current Three State Leakage Current SYMBOL VIH VIL VOH VOL IIH IIL IOZH IOZL Input Clamp Voltage Short Circuit Output Current (Note 3) Quiescent Supply Current, MSI Additional Quiescent Supply Current per Input Pin TTL Inputs High, 1 Unit Load NOTES: 3. Not more than one output should be shorted at one time. Test duration should not exceed 100ms. 4. Inputs that are not measured are at VCC or GND. 5. FCT Input Loading: All inputs are 1 unit load. Unit load is ICC limit specified in Static Characteristics Chart, e.g., 1.6mA Max at 70oC. VIK IOS VIH or VIL VIH or VIL VCC GND VCC GND VCC or GND VO = 0 VCC or GND VCC or GND 3.4V (Note 4) 0 -18 -15 48 VI (V) IO (mA) VCC (V) 4.75 to 5.25 4.75 to 5.25 Min Min Max Max Max Max Min Max MIN 2 2.4 -75 25oC MAX 0.8 0.55 0.1 -0.1 0.5 -0.5 -1.2 0oC TO 70oC MIN 2 2.4 -75 MAX 0.8 0.55 1 -1 10 -10 -1.2 UNITS V V V V A A A A V mA
ICC ICC
Max Max
-
8 1.6
-
80 1.6
A mA
8-3
CD74FCT861A
Switching Specifications Over Operating Range FCT Series tr, tf = 2.5ns, CL = 50pF, RL (Figure 1)
25oC PARAMETER Propagation Delays Data to Outputs Output Enable to Output Output Disable to Output Power Dissipation Capacitance Minimum (Valley) VOHV During Switching of Other Outputs (Output Under Test Not Switching) Maximum (Peak) VOLP During Switching of Other Outputs (Output Under Test Not Switching) Input Capacitance Three-State Output Capacitance NOTES: 6. 5V: Minimum is at 5.25V for 0oC to 70oC, Maximum is at 4.75V for 0oC to 70oC, Typical is at 5V. 7. CPD, measured per flip-flop, is used to determine the dynamic power consumption. PD (per package) = VCC ICC + (VCC2 fI CPD + VO2 fOCL + VCC ICC D) where: VCC = supply voltage ICC = flow through current x unit load CL = output load capacitance D = duty cycle of input high fO = output frequency fI = input frequency tPLH, tPHL tPZL, tPZH tPLZ, tPHZ CPD (Note 7) VOHV VOLP CI CO 5 (Note 6) 5 5 5 5 6 9 7.5 0.5 1 1.5 1.5 1.5 8 12 10 10 15 ns ns ns pF V V pF pF SYMBOL VCC (V) TYP 0oC TO 70oC MIN MAX UNITS
8-4
CD74FCT861A
8-5
Test Circuits and Waveforms
tr, tf = 2.5ns (NOTE 8) PULSE ZO GEN RT = ZO RT VI 3V 0 DUT CL 50pF VCC 7V V0 500 RL 500 RL
SWITCH POSITION TEST tPLZ, tPZL, Open Drain tPHZ, tPZH, tPLH, tPHL SWITCH Closed Open
NOTE: 8. Pulse Generator for All Pulses: Rate 1.0MHz; ZOUT 50; tf, tr 2.5ns. FIGURE 1. TEST CIRCUIT
DEFINITIONS: CL = Load capacitance, includes jig and probe capacitance. RT = Termination resistance, should be equal to ZOUT of the Pulse Generator. VIN = 0V to 3V. Input: tr = tf = 2.5ns (10% to 90%), unless otherwise specified
DATA INPUT tSH TIMING INPUT ASYNCHRONOUS CONTROL tREM tH
3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
LOW-HIGH-LOW PULSE tW
1.5V
SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. 3V 1.5V 0V HIGH-LOW-HIGH PULSE
tSH
tH
1.5V
FIGURE 2. SETUP, HOLD, AND RELEASE TIMING
FIGURE 3. PULSE WIDTH
ENABLE CONTROL INPUT tPZL 3.5V OUTPUT NORMALLY LOW SWITCH CLOSED tPZH OUTPUT NORMALLY HIGH SWITCH OPEN 1.5V 0V 1.5V
DISABLE 3V 1.5V 0V tPLZ 3.5V OUTPUT 0.3V tPHZ 0.3V VOL VOH 0V OPPOSITE PHASE INPUT TRANSITION tPLH tPHL SAME PHASE INPUT TRANSITION tPLH tPHL
3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V
FIGURE 4. ENABLE AND DISABLE TIMING
FIGURE 5. PROPAGATION DELAY
8-6
Test Circuits and Waveforms
(Continued)
VOH
OTHER OUTPUTS VOL OUTPUT UNDER TEST VOH VOHV VOLP VOL
NOTES: 9. VOLP is measured with respect to a ground reference near the output under test. VOHV is measured with respect to VOH. 10. Input pulses have the following characteristics: PRR 1MHz, tr = 2.5ns, tf = 2.5ns, skew 1ns. 11. R.F. fixture with 700MHz design rules required. IC should be soldered into test board and bypassed with 0.1F capacitor. Scope and probes require 700MHz bandwidth. FIGURE 6. SIMULTANEOUS SWITCHING TRANSIENT WAVEFORMS
8-7
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Copyright (c) 1998, Texas Instruments Incorporated

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