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SN74GTLPH1655 16-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER
SCES294 - OCTOBER 1999
D D D D D D D D D D D
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
description
The SN74GTLPH1655 is a high-drive 16-bit universal bus transceiver (UBT) that provides LVTTL-to-GTL+ and GTL+-to-LVTTL signal-level translation. It is partitioned as two 8-bit transceivers and allows for transparent, latched, and clocked modes of data transfer similar to the '16501 function. The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTL+ signal levels. High-speed (about two times faster than standard LVTTL or TTL) backplane operation is a direct result of GTLP's reduced output swing (<1 V), reduced input threshold levels, improved differential input, and output edge control (OECTM). Improved GTLP OEC circuits minimize bus settling time and have been designed and tested using several backplane models. The high drive is suitable for driving double-terminated low-impedance backplanes using incident-wave switching.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. OEC and UBT are trademarks of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
Copyright (c) 1999, Texas Instruments Incorporated
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PRODUCT PREVIEW
UBT TM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode Bidirectional Interface Between GTL+ Signal Levels and LVTTL Logic Levels Partitioned as Two 8-Bit Transceivers With Individual Latch Timing and Output Control but With a Common Clock LVTTL Interfaces Are 5-V Tolerant High-Drive GTL+ Outputs (100 mA) LVTTL Outputs (-24 mA/24 mA) Variable Edge-Rate Control (ERC) Input Selects GTL+ Rise and Fall Times for Optimal Data-Transfer Rate and Signal Integrity Ioff, Power-Up 3-State, and BIAS VCC Support Live Insertion Bus Hold on A-Port Data Inputs Distributed VCC and GND-Pin Configuration Minimizes High-Speed Switching Noise Package Option Includes Plastic Thin Shrink Small-Outline Package
DGG PACKAGE (TOP VIEW)
1OEAB 1OEBA VCC 1A1 GND 1A2 1A3 GND 1A4 GND 1A5 GND 1A6 1A7 VCC 1A8 2A1 GND 2A2 2A3 GND 2A4 2A5 GND 2A6 GND 2A7 VCC 2A8 GND 2OEAB 2OEBA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
CLK 1LEAB 1LEBA ERC GND 1B1 1B2 GND 1B3 1B4 1B5 GND 1B6 1B7 VCC 1B8 2B1 GND 2B2 2B3 GND 2B4 2B5 VREF 2B6 GND 2B7 2B8 BIAS VCC 2LEAB 2LEBA OE
SN74GTLPH1655 16-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER
SCES294 - OCTOBER 1999
description (continued)
GTL+ is the Texas Instruments derivative of the Gunning transceiver logic (GTL) JEDEC standard JESD 8-3. The AC specification of the SN74GTLPH1655 is given only at the preferred higher noise margin GTL+, but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTL+ (VTT = 1.5 V and VREF = 1 V) signal levels. Normally, the B port operates at GTL or GTL+ levels, while the A-port and control inputs are compatible with LVTTL logic levels and are 5-V tolerant. VREF is the reference input voltage for the B port. This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-insertion capability. High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC input voltage between GND and VCC adjusts the B-port output rise and fall times. This allows the designer to optimize system data-transfer rate and signal integrity to the backplane load.
PRODUCT PREVIEW
Active bus-hold circuitry holds unused or undriven LVTTL inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74GTLPH1655 is characterized for operation from -40C to 85C.
functional description
The SN74GTLPH1655 is a high-drive (100 mA) 16-bit UBT containing D-type latches and D-type flip-flops for data-path operation in transparent, latched, or clocked modes and is similar to a '16501 function. The device is uniquely partitioned as two 8-bit transceivers with individual latch timing and output signals and a common clock for both transceiver words. It can replace any of the functions shown in Table 1. Table 1. SN74GTLPH1655 UBT Replacement Functions
FUNCTION Transceiver Buffer/driver Latched transceiver Latch Registered transceiver Flip-flop 8 BIT '245, '623, '645 '241, '244, '541 '543 '373, '573 '646, '652 '374, '574 '821 '843 '841 9 BIT '863 10 BIT '861 '827 16 BIT '16245, '16623 '16241, '16244, '16541 '16543 '16373 '16646, '16652 '16374
SN74GTLPH1655 UBT replaces all above functions
Data flow for each word is determined by the respective latch enables (xLEAB and xLEBA), output enables (xOEAB and xOEBA), and clock (CLK). The output enables (1OEAB, 1OEBA, 2OEAB, and 2OEBA) control byte 1 and byte 2 data for the A-to-B and B-to-A directions, respectively. Note that CLK is common to both directions and both 8-bit words. OE also is common and disables all I/O ports simultaneously.
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SN74GTLPH1655 16-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER
SCES294 - OCTOBER 1999
functional description (continued)
For A-to-B data flow, the devices operate in the transparent mode when LEAB is high. When LEAB transitions low, the A data is latched independent of CLK high or low. If LEAB is low, the A data is registered on the CLK low-to-high transition. When OEAB is low, the outputs are active. With OEAB high, the outputs are in the high-impedance state. Data flow for the B-to-A direction is identical, but uses OEBA, LEBA, and CLK. Function Tables
FUNCTION INPUTS OEAB H L L L L L LEAB X H H L L L CLK X X X H A X L H L H X OUTPUT B Z L H L H B0 B0 MODE Isolation Transparent Transparent Registered Registered Previous state
L L L X Previous state A-to-B data flow is shown. B-to-A flow is similar but uses OEBA, LEBA, and CLK. Output level before the indicated steady-state input conditions were established, provided that CLK was high before LEAB went low Output level before the indicated steady-state input conditions were established OUTPUT ENABLE INPUTS OE L L L L H OEAB L L H H X OEBA L H L H X OUTPUTS A PORT Active Z Active Z Z B PORT Active Active Z Z Z
B-PORT EDGE-RATE CONTROL (ERC) INPUT ERC LOGIC LEVEL H L NOMINAL VOLTAGE VCC GND OUTPUT B-PORT EDGE RATE Slow Fast
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PRODUCT PREVIEW
SN74GTLPH1655 16-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER
SCES294 - OCTOBER 1999
logic diagram (positive logic)
41 VREF 61 ERC 64 CLK 63 1LEAB 62 1LEBA 2 1 1OEAB 33
1OEBA
PRODUCT PREVIEW
OE
1A1
4 1D C1 CLK 1D C1 CLK 59 1B1
To Seven Other Channels
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SN74GTLPH1655 16-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER
SCES294 - OCTOBER 1999
logic diagram (positive logic) (continued)
41 VREF 61 ERC 64 CLK 35 2LEAB 34 2LEBA 32 31 2OEAB 33
2OEBA
2A1
17 1D C1 CLK 1D C1 CLK 48 2B1
To Seven Other Channels
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PRODUCT PREVIEW
OE
SN74GTLPH1655 16-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER
SCES294 - OCTOBER 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC and BIAS VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Input voltage range, VI (see Note 1):A-port and control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V B port, ERC, and VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1): A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Voltage range applied to any output in the high or low state, VO (see Note 1): A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Current into any output in the low state, IO: A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA Current into any A-port output in the high state, IO (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Package thermal impedance, JA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
PRODUCT PREVIEW
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The package thermal impedance is calculated in accordance with JESD 51.
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SN74GTLPH1655 16-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER
SCES294 - OCTOBER 1999
recommended operating conditions (see Notes 4 through 6)
MIN VCC, BIAS VCC VTT VREF VI Supply voltage Termination voltage Supply voltage Input voltage GTL GTL+ GTL GTL+ B port Except B port B port VIH High-level input voltage ERC Except B port and ERC B port VIL IIK IOH IOL Low-level input voltage Input clamp current High-level output current Low-level Low level output current A port A port B port ERC Except B port and ERC GND VREF+0.05 VCC-0.6 2 VREF-0.05 0.6 0.8 -18 -24 24 100 mA mA mA V VCC 3.15 1.14 1.35 0.74 0.87 NOM 3.3 1.2 1.5 0.8 1 MAX 3.45 1.26 1.65 0.87 1.1 VTT VCC UNIT V V V V
V
TA Operating free-air temperature -40 85 C NOTES: 4. All unused control and B-port inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 5. Normal connection sequence is GND first, BIAS VCC = 3.3 V second, and VCC = 3.3 V, I/O, control inputs, VTT and VREF (any order) last. However, if the B-port I/O precharge is not required, the acceptable connection sequence is GND first and VCC = 3.3 V, BIAS VCC = 3.3 V, I/O, control inputs, VTT and VREF (any order) last. When VCC is connected, the BIAS VCC circuitry is disabled. 6. VTT and RTT can be adjusted to accommodate backplane impedances as long as they do not exceed the DC absolute IOL ratings. Similarly, VREF can be adjusted to optimize noise margins, but normally is 2/3 VTT.
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PRODUCT PREVIEW
SN74GTLPH1655 16-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER
SCES294 - OCTOBER 1999
electrical characteristics over recommended operating free-air temperature range for GTL+ (unless otherwise noted)
PARAMETER VIK VOH A port TEST CONDITIONS VCC = 3.15 V, VCC = 3.15 V to 3.45 V, VCC = 3 15 V 3.15 VCC = 3.15 V to 3.45 V, A port VOL B port VCC = 3.15 V VCC = 3.45 V, VCC = 3 45 V 3.45 VCC = 3.15 V, VCC = 3.15 V, VCC = 3.45 V, VCC = 3.45 V, VCC = 3.45 V, IO = 0, VI (A-port or control input) = VCC or GND VI (B port) = VTT or GND VCC = 3 15 V 3.15 II = -18 mA IOH = -100 A IOH = -12 mA IOH = -24 mA IOL = 100 A IOL = 12 mA IOL = 24 mA IOL = 10 mA IOL = 64 mA IOL = 100 mA VI = 0 to 1.5 V VI = 0 or VCC VI = 5.5 V VI = 0.8 V VI = 2 V VI = 0 to VCC VI = 0 to VCC Outputs high Outputs low Outputs disabled 75 -75 500 -500 40 40 40 1.5 mA pF pF mA MIN VCC-0.2 2.4 2 0.2 0.4 0.5 0.2 0.4 0.55 10 10 20 A A A A A V TYP MAX -1.2 UNIT V V
B port II IBHL IBHH IBHLO# IBHHO|| ICC ICCk Ci Ci io Control inputs A port B port A-port and control inputs A port A port A port A port A or B port
PRODUCT PREVIEW
VCC = 3.45 V, One A-port or control input at VCC - 0.6 V, Other A-port or control inputs at VCC or GND VI = 3.15 V or 0 VO = 3.15 V or 0 VO = 1.5 V or 0
All typical values are at VCC = 3.3 V, TA = 25C. For I/O ports, the parameter II includes the off-state output leakage current. The bus-hold circuit can sink at least the minimum low sustaining current at VILmax. IBHL should be measured after lowering VIN to GND and then raising it to VILmax. The bus-hold circuit can source at least the minimum high sustaining current at VIHmin. IBHH should be measured after raising VIN to VCC and then lowering it to VIHmin. # An external driver must source at least IBHLO to switch this node from low to high. || An external driver must sink at least IBHHO to switch this node from high to low. kThis is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
live-insertion specifications for A port over recommended operating free-air temperature range
PARAMETER Ioff IOZPU IOZPD VCC = 0, VCC = 0 to 1.5 V, VCC = 1.5 V to 0, TEST CONDITIONS BIAS VCC = 0, VO = 0.5 V to 3 V, VO = 0.5 V to 3 V, VI or VO = 0 to 5.5 V OE = 0 OE = 0 MIN MAX 100 100 100 UNIT A A A
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SN74GTLPH1655 16-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER
SCES294 - OCTOBER 1999
live-insertion specifications for B port over recommended operating free-air temperature range
PARAMETER Ioff IOZPU IOZPD ICC (BIAS VCC) VO IO VCC = 0, VCC = 0 to 1.5 V, VCC = 1.5 V to 0, VCC = 0 to 3.15 V VCC = 3.15 V to 3.45 V VCC = 0, VCC = 0, TEST CONDITIONS BIAS VCC = 0, VO = 0.5 V to 1.5 V, VO = 0.5 V to 1.5 V, BIAS VCC = 3 15 V to 3 45 V 3.15 3.45 V, BIAS VCC = 3.3 V BIAS VCC = 3.15 V to 3.45 V, VO (B port) = 0.6 V VI or VO = 0 to 1.5 V OE = 0 OE = 0 VO (B port) = 0 to 1.5 V 15 0.95 -1 MIN MAX 100 100 100 5 10 1.05 UNIT A A A mA A V A
timing requirements over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTL+ (unless otherwise noted)
MIN fclock tw Clock frequency Pulse duration LEAB or LEBA high CLK high or low A before CLK tsu Setup time B before CLK A before LEAB, CLK = don't care B before LEBA, CLK = don't care A after CLK th Hold time B after CLK A after LEAB, CLK = don't care B after LEBA, CLK = don't care ns ns MAX UNIT MHz ns
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PRODUCT PREVIEW
SN74GTLPH1655 16-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER
SCES294 - OCTOBER 1999
switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTL+ (see Figure 1)
PARAMETER fmax A tpd d LEAB CLK ten tdis ten tdis ten tdis B B B B B B B Slow Fast Slow Fast Slow Fast Slow Fast Slow Fast Slow Fast Slow Fast A ns ns ns ns ns ns ns FROM (INPUT) TO (OUTPUT) EDGE RATE MIN TYP MAX UNIT MHz
OE OE OEAB OEAB Rise time, B outputs , (0.6 V to 1.3 V) Fall time, B outputs , (1.3 V to 0.6 V) B
PRODUCT PREVIEW
ten tdis tr tf
tpd ten tdis ten tdis
LEBA CLK OE OEBA
ns
A A
ns ns
Slow (ERC = VCC) and Fast (ERC = GND) All typical values are at VCC = 3.3 V, TA = 25C.
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SN74GTLPH1655 16-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER
SCES294 - OCTOBER 1999
PARAMETER MEASUREMENT INFORMATION
6V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 6V GND 1.5 V 12.5 From Output Under Test CL = 30 pF (see Note A) Test Point
LOAD CIRCUIT FOR A OUTPUTS
LOAD CIRCUIT FOR B OUTPUTS
tw 3V Input 1.5 V VOLTAGE WAVEFORMS PULSE DURATION 3V Input 1.5 V tPLH 1.5 V 0V tPHL VOH Output 1V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (A port to B port) 1.5 V Input 1V 1V 0V tPLH tPHL VOH Output 1.5 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (B port to A port) 1.5 V VOL Output Waveform 2 S1 at GND (see Note B) 1V VOL Output Control tPZL Output Waveform 1 S1 at 6 V (see Note B) tPZH 1.5 V 1.5 V 1.5 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES (VM = 1.5 V for A port and 1 V for B port) (VH = 3 V for A port and 1.5 V for B port) 1.5 V 0V Timing Input tsu Data Input VM 1.5 V
3V
0V th VH 0V VM
3V 0V tPLZ 3V VOL + 0.3 V VOL tPHZ VOH VOH - 0.3 V 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES (A port)
1.5 V
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , slew rate 1 V/ns. D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
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PRODUCT PREVIEW
SN74GTLPH1655 16-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER
SCES294 - OCTOBER 1999
DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS
This data sheet is specified for and tested to the lump load shown in Figure 1. However, the designer probably uses this GTLP device in a distributed load like that shown in Figure 2, in which actual B-port backplane switching characteristics are different. Therefore, the device is modeled as shown in Figure 3, which very closely matches the results obtained using Figure 2. Switching characteristics based on Figure 3 more closely match actual backplane design requirements.
VTT
RTT
VTT
RTT
.25"
.875"
.875"
.25"
.625" Conn. 1"
.625" Conn. 1"
Rcvr
.625" Conn. 1"
Rcvr
.625" 1.5 V Conn. 1"
Rcvr
From Output Under Test
LL = 21 nH
14 Test Point CL = 13 pF
PRODUCT PREVIEW
Drvr
Slot 1
Slot 2
Slot 15
Slot 16
Figure 2. Test Backplane Model
Figure 3. Distributed-Load Circuit for B Outputs
switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTL+ (see Figure 3)
PARAMETER fmax A tpd d LEAB CLK ten tdis ten tdis ten tdis ten tdis tr tf B B B B B B B Slow Fast Slow Fast Slow Fast Slow Fast Slow Fast Slow Fast Slow Fast ns ns ns ns ns ns ns FROM (INPUT) TO (OUTPUT) EDGE RATE MIN TYP MAX UNIT MHz
OE OE OEAB OEAB Rise time, B outputs , (0.6 V to 1.3 V) Fall time, B outputs (1.3 V to 0.6 V)
Slow (ERC = VCC) and Fast (ERC = GND) All typical values are at VCC = 3.3 V, TA = 25C.
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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 1999, Texas Instruments Incorporated

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