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SN74LVCZ16244A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES277B - JUNE 1999 - REVISED MARCH 2000
D D D D D D D D D
Member of the Texas Instruments Widebus TM Family EPICTM (Enhanced-Performance Implanted CMOS) Submicron Process Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25C Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25C Ioff and Power-Up 3-State Support Hot Insertion Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC) Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101) Package Options Include Plastic Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages
DGG OR DL PACKAGE (TOP VIEW)
description
This 16-bit buffer/driver is designed for 3-V to 3.6-V VCC operation.
1OE 1Y1 1Y2 GND 1Y3 1Y4 VCC 2Y1 2Y2 GND 2Y3 2Y4 3Y1 3Y2 GND 3Y3 3Y4 VCC 4Y1 4Y2 GND 4Y3 4Y4 4OE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
2OE 1A1 1A2 GND 1A3 1A4 VCC 2A1 2A2 GND 2A3 2A4 3A1 3A2 GND 3A3 3A4 VCC 4A1 4A2 GND 4A3 4A4 3OE
The SN74LVCZ16244A is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and symmetrical active-low output-enable (OE) inputs. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The SN74LVCZ16244A is characterized for operation from -40C to 85C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2000, Texas Instruments Incorporated
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
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SN74LVCZ16244A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES277B - JUNE 1999 - REVISED MARCH 2000
FUNCTION TABLE (each 4-bit buffer) INPUTS OE L L H A H L X OUTPUT Y H L Z
logic symbol
1OE 2OE 3OE 4OE 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 3A1 3A2 3A3 3A4 4A1 4A2 4A3 4A4 24 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 1 4 1 3 1 2 1 48 25 EN1 EN2 EN3 EN4 1 1 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 3Y1 3Y2 3Y3 3Y4 4Y1 4Y2 4Y3 4Y4
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN74LVCZ16244A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES277B - JUNE 1999 - REVISED MARCH 2000
logic diagram (positive logic)
1OE 1 3OE 2 25
1A1
47
1Y1
3A1
36
13
3Y1
1A2
46
3
1Y2
3A2
35
14
3Y2
1A3
44
5
1Y3
3A3
33
16
3Y3
1A4
43
6
1Y4
3A4
32
17
3Y4
2OE
48
4OE 8
24
2A1
41
2Y1
4A1
30
19
4Y1
2A2
40
9
2Y2
4A2
29
20
4Y2
2A3
38
11
2Y3
4A3
27
22
4Y3
2A4
37
12
2Y4
4A4
26
23
4Y4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Package thermal impedance, JA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51.
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3
SN74LVCZ16244A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES277B - JUNE 1999 - REVISED MARCH 2000
recommended operating conditions (see Note 4)
MIN VCC VIH VIL VI VO IOH IOL t/v t/VCC TA Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise or fall rate Power-up ramp rate Operating free-air temperature 150 -40 85 High or low state 3-state VCC = 3 V VCC = 3 V VCC = 3 V to 3.6 V VCC = 3 V to 3.6 V 3 2 0.8 0 0 0 5.5 VCC 5.5 -24 24 10 MAX 3.6 UNIT V V V V V mA mA ns/V s/V C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VOH IOH = -100 A IOH = -12 mA IOH = -24 mA IOL = 100 A VOL II Ioff IOZ IOZPU IOZPD ICC ICC Ci IOL = 12 mA IOL = 24 mA VI = 0 to 5.5 V VI or VO = 5.5 V VO = 0 to 5.5 V VO = 0.5 to 2.5 V, VO = 0.5 to 2.5 V, VI = VCC or GND 3.6 V VI 5.5 V One input at VCC - 0.6 V, VI = VCC or GND OE = don't care OE = don't care IO = 0 Other inputs at VCC or GND TEST CONDITIONS VCC 3 V to 3.6 V 3V 3V 3 V to 3.6 V 3V 3V 3.6 V 0 3.6 V 0 to 1.5 V 1.5 V to 0 36V 3.6 3 V to 3.6 V 3.3 V 3.3 V 4.5 6 MIN VCC-0.2 2.4 2.2 0.2 0.4 0.55 5 5 5 5 5 100 100 100 A A A A A A A pF pF V TYP MAX UNIT V
Co VO = VCC or GND All typical values are at VCC = 3.3 V, TA = 25C. This applies in the disabled state only.
switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
PARAMETER tpd ten tdis FROM (INPUT) A or B OE OE TO (OUTPUT) B or A A or B A or B VCC = 3.3 V 0.3 V MIN 1.1 1 1.8 MAX 4.1 4.6 5.8 ns ns ns UNIT
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN74LVCZ16244A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES277B - JUNE 1999 - REVISED MARCH 2000
operating characteristics, TA = 25C
PARAMETER Cpd Power dissipation capacitance per buffer/driver Outputs enabled Outputs disabled TEST CONDITIONS f = 10 MHz TYP 32 5.5 UNIT pF
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5
SN74LVCZ16244A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES277B - JUNE 1999 - REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION VCC = 3.3 V 0.3 V
2 x VCC From Output Under Test CL = 30 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
LOAD CIRCUIT
tw VCC
Timing Input
VCC VCC/2 0V tsu th VCC VCC/2 VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 0V
Input
VCC/2
VCC/2 0V
VOLTAGE WAVEFORMS PULSE DURATION
Data Input
Output Control (low-level enabling) tPZL
VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 tPZH VOL + 0.3 V VOL tPHZ VOH VOH - 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
VCC Input VCC/2 VCC/2 0V tPLH tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL
Output Waveform 1 S1 at 2 x VCC (see Note B)
Output Waveform 2 S1 at GND (see Note B)
VCC/2
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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Copyright (c) 2000, Texas Instruments Incorporated

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