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SN74AVC16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES141L - JULY 1998 - REVISED JUNE 2000
D D D D D
Member of the Texas Instruments Widebus TM Family EPICTM (Enhanced-Performance Implanted CMOS) Submicron Process DOCTM (Dynamic Output Control) Circuit Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed Degradation Less Than 2-ns Maximum Propagation Delay at 2.5-V and 3.3-V VCC Dynamic Drive Capability Is Equivalent to Standard Outputs With IOH and IOL of 24 mA at 2.5-V VCC
D D D D D
Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications Ioff Supports Partial-Power-Down Mode Operation ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II Package Options Include Plastic Thin Shrink Small-Outline (DGG) and Thin Very Small-Outline (DGV) Packages
description
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOCTM) Circuitry Technology and Applications, literature number SCEA009.
3.2 2.8 VOL - Output Voltage - V 2.4 2.0 1.6 VCC = 2.5 V 1.2 VCC = 1.8 V 0.8 0.4 0 17 34 51 68 85 102 119 IOL - Output Current - mA 136 153 170 VCC = 3.3 V TA = 25C Process = Nominal - Output Voltage - V TA = 25C Process = Nominal
2.8 2.4 2.0 1.6 1.2 0.8
V
OH
VCC = 3.3 V 0.4
VCC = 2.5 V VCC = 1.8 V -32 -16 0
-160 -144 -128 -112 -96 -80 -64 -48 IOH - Output Current - mA
Figure 1. Output Voltage vs Output Current This 16-bit buffer/driver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V VCC operation. The SN74AVC16244 is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and symmetrical active-low output-enable (OE) inputs.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DOC, EPIC, and Widebus are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2000, Texas Instruments Incorporated
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SN74AVC16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES141L - JULY 1998 - REVISED JUNE 2000
description (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The SN74AVC16244 is characterized for operation from -40C to 85C.
terminal assignments
DGG OR DGV PACKAGE (TOP VIEW)
1OE 1Y1 1Y2 GND 1Y3 1Y4 VCC 2Y1 2Y2 GND 2Y3 2Y4 3Y1 3Y2 GND 3Y3 3Y4 VCC 4Y1 4Y2 GND 4Y3 4Y4 4OE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
2OE 1A1 1A2 GND 1A3 1A4 VCC 2A1 2A2 GND 2A3 2A4 3A1 3A2 GND 3A3 3A4 VCC 4A1 4A2 GND 4A3 4A4 3OE
FUNCTION TABLE (each 4-bit buffer) INPUTS OE L L H A L H X OUTPUT Y L H Z
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SN74AVC16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES141L - JULY 1998 - REVISED JUNE 2000
logic symbol
1OE 2OE 3OE 4OE 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 3A1 3A2 3A3 3A4 4A1 4A2 4A3 4A4 24 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 1 4 1 3 1 2 1 48 25 EN1 EN2 EN3 EN4 1 1 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 3Y1 3Y2 3Y3 3Y4 4Y1 4Y2 4Y3 4Y4
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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SN74AVC16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES141L - JULY 1998 - REVISED JUNE 2000
logic diagram (positive logic)
1OE 1 3OE 2 25
1A1
47
1Y1
3A1
36
13
3Y1
1A2
46
3
1Y2
3A2
35
14
3Y2
1A3
44
5
1Y3
3A3
33
16
3Y3
1A4
43
6
1Y4
3A4
32
17
3Y4
2OE
48
4OE 8
24
2A1
41
2Y1
4A1
30
19
4Y1
2A2
40
9
2Y2
4A2
29
20
4Y2
2A3
38
11
2Y3
4A3
27
22
4Y3
2A4
37
12
2Y4
4A4
26
23
4Y4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Package thermal impedance, JA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed. 3. The package thermal impedance is calculated in accordance with JESD 51.
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SN74AVC16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES141L - JULY 1998 - REVISED JUNE 2000
recommended operating conditions (see Note 4)
MIN VCC Supply voltage Operating Data retention only VCC = 1.2 V VCC = 1.4 V to 1.6 V VIH High-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 1.2 V VCC = 1.4 V to 1.6 V VIL Low-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V 0 Active state 3-state VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V 0 0 1.4 1.2 VCC 0.65 x VCC 0.65 x VCC 1.7 2 GND 0.35 x VCC 0.35 x VCC 0.7 0.8 3.6 VCC 3.6 -2 -4 -8 -12 2 4 8 12 mA mA V V V V MAX 3.6 UNIT V
VI VO
Input voltage Output voltage
IOHS
Static high-level output current high level
IOLS
Static low-level output current low level
Input transition rise or fall rate VCC = 1.4 V to 3.6 V 5 ns/V TA Operating free-air temperature -40 85 C Dynamic drive capability is equivalent to standard outputs with IOH and IOL of 24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and VOH vs IOH characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC TM) Circuitry Technology and Applications, literature number SCEA009. NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
t/v
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SN74AVC16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES141L - JULY 1998 - REVISED JUNE 2000
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS IOHS = -100 A IOHS = -2 mA, VOH IOHS = -4 mA, IOHS = -8 mA, IOHS = -12 mA, IOLS = 100 A VOL IOLS = 2 mA, IOLS = 4 mA, IOLS = 8 mA, IOLS = 12 mA, II Ioff IOZ ICC Control inputs Ci Data inputs Co Out uts Outputs VI = VCC or GND VO = VCC or GND VI = VCC or GND VI or VO = 3.6 V VO = VCC or GND VI = VCC or GND, VI = VCC or GND IO = 0 VCC 1.4 V to 3.6 V 1.4 V 1.65 V 2.3 V 3V 1.4 V to 3.6 V VIL = 0.49 V VIL = 0.57 V VIL = 0.7 V VIL = 0.8 V 1.4 V 1.65 V 2.3 V 3V 3.6 V 0 3.6 V 3.6 V 2.5 V 3.3 V 2.5 V 3.3 V 2.5 V 3.3 V 3.5 3.5 6 6 6.5 6.5 pF F pF MIN TYP MAX UNIT VCC-0.2 1.05 1.2 1.75 2.3 0.2 0.4 0.45 0.55 0.7 2.5 10 10 40 A A A A V V
VIH = 0.91 V VIH = 1.07 V VIH = 1.7 V VIH = 2 V
Typical values are measured at TA = 25C.
switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 2 through 5)
PARAMETER tpd ten tdis FROM (INPUT) A OE OE TO (OUTPUT) Y Y Y VCC = 1.2 V TYP 3.1 7.6 7.2 VCC = 1.5 V 0.1 V MIN 0.6 1.4 1.7 MAX 3.3 8 7.3 VCC = 1.8 V 0.15 V MIN 0.7 1.3 1.6 MAX 2.9 6.8 6.2 VCC = 2.5 V 0.2 V MIN 0.6 0.9 1 MAX 1.9 4 4.3 VCC = 3.3 V 0.3 V MIN 0.5 0.7 1 MAX 1.7 3.5 3.5 ns ns ns UNIT
operating characteristics, TA = 25C
PARAMETER Cpd d Power dissipation capacitance Outputs enabled Outputs disabled TEST CONDITIONS CL = 0, 0 f = 10 MHz VCC = 1.8 V TYP 23 0.1 VCC = 2.5 V TYP 27 0.1 VCC = 3.3 V TYP 33 0.1 UNIT pF
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SN74AVC16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES141L - JULY 1998 - REVISED JUNE 2000
PARAMETER MEASUREMENT INFORMATION VCC = 1.2 V AND 1.5 V 0.1 V
2 x VCC From Output Under Test CL = 15 pF (see Note A) 2 k S1 Open GND 2 k TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
LOAD CIRCUIT tw Timing Input tsu Data Input VCC/2 VCC VCC/2 0V th VCC VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH VCC Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V
VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.1 V VOL tPHZ VOH VOH - 0.1 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
VCC/2
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
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SN74AVC16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES141L - JULY 1998 - REVISED JUNE 2000
PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V 0.15 V
1 k S1 2 x VCC Open GND 1 k TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
From Output Under Test CL = 30 pF (see Note A)
LOAD CIRCUIT tw Timing Input tsu Data Input VCC/2 VCC VCC/2 0V th VCC VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH VCC Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V
VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.15 V VOL tPHZ VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
VCC/2
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
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SN74AVC16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES141L - JULY 1998 - REVISED JUNE 2000
PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V 0.2 V
2 x VCC From Output Under Test CL = 30 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
LOAD CIRCUIT VCC VCC/2 0V tsu Data Input VCC/2 th VCC VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH
tw VCC Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V
Timing Input
VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.15 V VOL tPHZ VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
VCC/2
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 4. Load Circuit and Voltage Waveforms
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SN74AVC16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES141L - JULY 1998 - REVISED JUNE 2000
PARAMETER MEASUREMENT INFORMATION VCC = 3.3 V 0.3 V
2 x VCC From Output Under Test CL = 30 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
LOAD CIRCUIT
tw VCC
Timing Input tsu Data Input VCC/2
VCC VCC/2 0V th VCC VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES
Input
VCC/2
VCC/2 0V
VOLTAGE WAVEFORMS PULSE DURATION
Output Control (low-level enabling) tPZL
VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 tPZH VOL + 0.3 V VOL tPHZ VOH VOH - 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES
VCC Input VCC/2 VCC/2 0V tPLH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPHL VOH VCC/2 VOL
Output Waveform 1 S1 at 2 x VCC (see Note B)
Output Waveform 2 S1 at GND (see Note B)
VCC/2
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd.
Figure 5. Load Circuit and Voltage Waveforms
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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.
Copyright (c) 2000, Texas Instruments Incorporated

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