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| SN74ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES111E - JULY 1997 - REVISED FEBRUARY 1999 D D D D EPIC TM (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Package Options Include Plastic Small-Outline (D), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages D, DGV, OR PW PACKAGE (TOP VIEW) 1OE 1A 1Y 2OE 2A 2Y GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC 4OE 4A 4Y 3OE 3A 3Y description This quadruple bus buffer gate is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVC126 features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. The SN74ALVC126 is characterized for operation from -40C to 85C. FUNCTION TABLE (each buffer) INPUTS OE H H L A H L X OUTPUT Y H L Z logic symbol 1OE 1A 2OE 2A 3OE 3A 4OE 4A 1 2 4 5 10 9 13 12 11 8 6 EN 1 3 1Y 2Y 3Y 4Y This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1999, Texas Instruments Incorporated POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SN74ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES111E - JULY 1997 - REVISED FEBRUARY 1999 logic diagram (positive logic) 1OE 1A 1 2 3 3OE 1Y 3A 10 9 8 3Y 2OE 2A 4 5 6 4OE 2Y 4A 13 12 11 4Y absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Package thermal impedance, JA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN74ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES111E - JULY 1997 - REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) MIN VCC VIH Supply voltage High-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VI VO Input voltage Output voltage VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V 0 0 1.65 0.65 x VCC 1.7 2 0.35 x VCC 0.7 0.8 VCC VCC -4 -12 -12 -24 4 12 12 24 5 ns/V mA mA V V V V MAX 3.6 UNIT V VIL Low-level input voltage IOH High-level High level output current IOL Low-level Low level output current t/v Input transition rise or fall rate TA Operating free-air temperature -40 85 C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SN74ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES111E - JULY 1997 - REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER IOH = -100 A IOH = -4 mA IOH = -6 mA VOH IOH = -12 mA IOH = -24 mA IOL = 100 A IOL = 4 mA IOL = 6 mA IOL = 12 mA IOL = 24 mA VI = VCC or GND VO = VCC or GND VI = VCC or GND, One input at VCC - 0.6 V, Control inputs Data inputs VI = VCC or GND IO = 0 Other inputs at VCC or GND TEST CONDITIONS VCC 1.65 V to 3.6 V 1.65 V 2.3 V 2.3 V 2.7 V 3V 3V 1.65 V to 3.6 V 1.65 V 2.3 V 2.3 V 2.7 V 3V 3.6 V 3.6 V 3.6 V 3 V to 3.6 V 3.3 33V 3.3 V 3.5 3.5 5.5 pF MIN TYP MAX UNIT VCC-0.2 1.2 2 1.7 2.2 2.4 2 0.2 0.45 0.4 0.7 0.4 0.55 5 10 10 750 A A A A pF F V V VOL II IOZ ICC ICC Ci Co Outputs VO = VCC or GND All typical values are at VCC = 3.3 V, TA = 25C. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) PARAMETER tpd ten tdis FROM (INPUT) A OE OE TO (OUTPUT) Y Y Y VCC = 1.8 V 0.15 V MIN 1.3 1 1.8 MAX 5.6 5.9 5.6 VCC = 2.5 V 0.2 V MIN 1 1 1 MAX 3.4 3.8 3.3 VCC = 2.7 V MIN MAX 3.4 3.8 4.4 VCC = 3.3 V 0.3 V MIN 1.1 1 1 MAX 3.1 3.3 3.7 ns ns ns UNIT operating characteristics, TA = 25C PARAMETER Cpd Power dissipation capacitance per gate Outputs enabled Outputs disabled TEST CONDITIONS CL = 0, f = 10 MHz VCC = 1.8V TYP 15 2 VCC = 2.5 V TYP 17 2 VCC = 3.3 V TYP 19 3 pF UNIT 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN74ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES111E - JULY 1997 - REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V 0.15 V 2 x VCC From Output Under Test CL = 30 pF (see Note A) 1 k S1 Open GND 1 k TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND LOAD CIRCUIT tw Timing Input tsu Data Input VCC/2 VCC VCC/2 0V th VCC VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at Open (see Note B) Output Control tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.15 V VOL tPHZ VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VCC Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V VCC VCC/2 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SN74ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES111E - JULY 1997 - REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V 0.2 V 2 x VCC From Output Under Test CL = 30 pF (see Note A) 500 S1 Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND LOAD CIRCUIT tw Timing Input tsu Data Input VCC/2 VCC VCC/2 0V th VCC VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Waveform 1 S1 at 2 x VCC (see Note B) tPZH VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Output Control tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.15 V VOL tPHZ VOH VOH - 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VCC Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V VCC VCC/2 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN74ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES111E - JULY 1997 - REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V 0.3 V 500 S1 6V Open GND 500 TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 6V GND From Output Under Test CL = 50 pF (see Note A) LOAD CIRCUIT tw 2.7 V Timing Input tsu Data Input 1.5 V 2.7 V 1.5 V 0V th 2.7 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION 2.7 V Output Control 1.5 V 1.5 V 0V tPZL 2.7 V Output Waveform 1 S1 at 6 V (see Note B) tPZH VOH Output Waveform 2 S1 at GND (see Note B) tPLZ 3V 1.5 V VOL + 0.3 V tPHZ VOH - 0.3 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOL Input 1.5 V 1.5 V 0V tPLH tPHL Output 1.5 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.5 V VOL 1.5 V NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 3. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 1999, Texas Instruments Incorporated |
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