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| CD74FCT273 BiCMOS OCTAL D-TYPE FLIP-FLOP WITH RESET SCBS737A - JULY 2000 - REVISED JULY 2000 D D D D D D D D D D BiCMOS Technology With Low Quiescent Power Buffered Inputs Direct Clear Input 48-mA Output Sink Current Output Voltage Swing Limited to 3.7 V Controlled Output Edge Rates Input/Output Isolation From VCC SCR Latch-Up-Resistant BiCMOS Process and Circuit Design Applications Include: - Buffer/Storage Registers - Shift Registers - Pattern Generators Package Options Include Plastic Small-Outline (M) Package and Standard Plastic (E) DIP E OR M PACKAGE (TOP VIEW) CLR 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q CLK description The CD74FCT273 is a positive-edge-triggered, D-type flip-flop with a direct clear (CLR) input. This device uses a small-geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS transistors that limits the output high level to two diode drops below VCC. This resultant lowering of output swing (0 V to 3.7 V) reduces power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes VCC bounce and ground bounce and their effects during simultaneous output switching. The output configuration also enhances switching speed and is capable of sinking 48 mA. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. All eight flip-flops are controlled by a common clock (CLK) and a common reset (CLR). The outputs are placed in a low state when CLR is taken low, independent of the CLK. The CD74FCT273 is characterized for operation from 0C to 70C. FUNCTION TABLE (each flip-flop) INPUTS CLR L H H H CLK X L D X H L X OUTPUT Q L H L Q0 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright (c) 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 CD74FCT273 BiCMOS OCTAL D-TYPE FLIP-FLOP WITH RESET SCBS737A - JULY 2000 - REVISED JULY 2000 logic symbol CLR CLK 1D 2D 3D 4D 5D 6D 7D 8D 1 11 3 4 7 8 13 14 17 18 R C1 1D 2 5 6 9 12 15 16 19 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) 1D 3 CLK 11 2D 4 3D 7 4D 8 5D 13 6D 14 7D 17 8D 18 1D C1 R 1 2 1Q 1D C1 R 1D C1 R 1D C1 R 1D C1 R 1D C1 R 1D C1 R 1D C1 R CLR 5 2Q 6 3Q 9 4Q 12 5Q 15 6Q 16 7Q 19 8Q logic diagram, each flip-flop (positive logic) C C D TG C C TG TG Q C C C C C CLK(I) TG C R 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 CD74FCT273 BiCMOS OCTAL D-TYPE FLIP-FLOP WITH RESET SCBS737A - JULY 2000 - REVISED JULY 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) DC supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6 V DC input diode current, IIK (VI < -0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20 mA DC output diode current, IOK (VO < -0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA DC output sink current per output pin, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA DC output source current per output pin, IOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -30 mA Continuous current through VCC, ICC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 mA Continuous current through GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 mA Package thermal impedance, JA (see Note 1): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69C/W M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 2) MIN VCC VIH VIL VI VO IOH IOL t/v Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise or fall rate 0 0 0 4.75 2 0.8 VCC VCC -15 48 10 MAX 5.25 UNIT V V V V V mA mA ns/V TA Operating free-air temperature 0 70 C NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating temperature range (unless otherwise noted) PARAMETER VIK VOH VOL II IOZ IOS ICC ICC II = -18 mA IOH = -15 mA IOL = 48 mA VI = VCC or GND VO = VCC or GND VI = VCC or GND, VI = VCC or GND, One input at 3.4 V, Other inputs at VCC or GND VO = 0 IO = 0 TEST CONDITIONS VCC 4.75 V 4.75 V 4.75 V 5.25 V 5.25 V 5.25 V 5.25 V 5.25 V -60 8 1.6 2.4 0.55 0.1 0.5 -60 80 1.6 10 TA = 25C MIN MAX -1.2 2.4 0.55 1 10 MIN MAX -1.2 UNIT V V V mA mA mA mA mA pF Ci VI = VCC or GND Not more than one output should be tested at a time, and the duration of the test should not exceed 100 ms. This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 CD74FCT273 BiCMOS OCTAL D-TYPE FLIP-FLOP WITH RESET SCBS737A - JULY 2000 - REVISED JULY 2000 timing requirements over recommended operating conditions (unless otherwise noted) (see Figure 1) MIN fclock tw tsu th Clock frequency Pulse duration CLR low CLK high or low Data before CLK Setup time Hold time CLR before CLK Data after CLK 7 7 3 4 2 MAX 70 UNIT MHz ns ns ns switching characteristics over recommended operating conditions, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER fmax tpd d CLK CLR Any An Q 7 8 FROM (INPUT) TO (OUTPUT) TA = 25C TYP MIN 70 2 2 13 13 MAX UNIT MHz ns operating characteristics, TA = 25C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS No load, f = 1 MHz TYP 36 UNIT pF 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 CD74FCT273 BiCMOS OCTAL D-TYPE FLIP-FLOP WITH RESET SCBS737A - JULY 2000 - REVISED JULY 2000 PARAMETER MEASUREMENT INFORMATION 7V From Output Under Test CL = 50 pF (see Note A) Test Point 500 From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS S1 Open 7V Open 7V 1.5 V 10% 90% 90% 3V 1.5 V 10% 0 V tf 3V Timing Input 1.5 V 0V 3V tsu Data Input 0V 1.5 V th 3V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 3V 1.5 V tPZL VOH Output Waveform 1 (see Note B) tPZH VOH Output Waveform 2 (see Note B) 1.5 V 1.5 V 1.5 V 0V tPLZ 3.5 V VOL + 0.3 V VOL tPHZ V VOH - 0.3 V OH 0 V tr VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES tw Input 1.5 V 1.5 V VOLTAGE WAVEFORMS PULSE DURATION Input tPLH In-Phase Output tPHL Out-of-Phase Output 1.5 V 1.5 V 0V tPHL 1.5 V 1.5 V VOL tPLH 1.5 V 1.5 V VOL Output Control VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr and tf = 2.5 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 2000, Texas Instruments Incorporated |
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