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CD74FCT841A BiCMOS 10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS
SCBS725 - JULY 2000
D D D D D D D D D
BiCMOS Technology With Low Quiescent Power Buffered Inputs Noninverted Outputs Input/Output Isolation From VCC Controlled Output Edge Rates 48-mA Output Sink Current Output Voltage Swing Limited to 3.7 V SCR Latch-Up-Resistant BiCMOS Process and Circuit Design Package Options Include Plastic Small-Outline (M) Package and Standard Plastic (EN) DIP
EN OR M PACKAGE (TOP VIEW)
OE 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q LE
description
The CD74FCT841A is a 10-bit, D-type latch with 3-state outputs, designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The device provides extra data width for wider address/data paths or buses carrying parity. The latches are transparent D-type latches. The device provides noninverted outputs. The device uses a small-geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS transistors that limits the output high level to two diode drops below VCC. This resultant lowering of output swing (0 V to 3.7 V) reduces power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes VCC bounce and ground bounce and their effects during simultaneous output switching. The output configuration also enhances switching speed and is capable of sinking 48 mA. The CD74FCT841A outputs are transparent to the inputs when the latch enable (LE) is high. When LE goes low, the data is latched. The output-enable (OE) input controls the 3-state outputs. When OE is high, the outputs are in the high-impedance state. The latch operation is independent of the state of OE. OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state. The CD74FCT841A is characterized for operation from 0C to 70C.
FUNCTION TABLE (each latch) INPUTS OE L L L H LE H H L X D H L X X OUTPUT Q H L Q0 Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright (c) 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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CD74FCT841A BiCMOS 10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS
SCBS725 - JULY 2000
logic symbol
OE LE 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D 1 13 2 3 4 5 6 7 8 9 10 11 EN C1 1D 23 22 21 20 19 18 17 16 15 14 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
OE 1
LE
13 C1 2 23 1Q
1D
1D
To Nine Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
DC supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6 V DC input clamp current, IIK (VI < -0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20 mA DC output clamp current, IOK (VO < -0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA DC output sink current per output pin, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA DC output source current per output pin, IOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -30 mA Continuous current through VCC, (ICC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 mA Continuous current through GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA Package thermal impedance, JA (see Note 1): EN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67C/W M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.
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CD74FCT841A BiCMOS 10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS
SCBS725 - JULY 2000
recommended operating conditions (see Note 2)
MIN VCC VIH VIL VI VO IOH IOL t/v Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise or fall rate 0 0 0 4.75 2 0.8 VCC VCC -15 48 10 MAX 5.25 UNIT V V V V V mA mA ns/V
TA Operating free-air temperature 0 70 C NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating temperature range (unless otherwise noted)
PARAMETER VIK VOH VOL II IOZ IOS ICC ICC Ci Co II = -18 mA IOH = -15 mA IOL = 48 mA VI = VCC or GND VO = VCC or GND VI = VCC or GND, VI = VCC or GND, One input at 3.4 V, Other inputs at VCC or GND VI = VCC or GND VO = VCC or GND VO = 0 IO = 0 TEST CONDITIONS VCC 4.75 V 4.75 V 4.75 V 5.25 V 5.25 V 5.25 V 5.25 V 5.25 V -75 8 1.6 10 15 2.4 0.55 0.1 0.5 -75 80 1.6 10 15 TA = 25C MIN MAX -1.2 2.4 0.55 1 10 MIN MAX -1.2 UNIT V V V
mA mA
mA
mA
mA pF pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 100 ms. This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC.
timing requirements over recommended operating temperature conditions (unless otherwise noted) (see Figure 1)
MIN tw tsu th Pulse duration Setup time Hold time Data before LE Data after LE 4 2.5 2.5 MAX UNIT ns ns ns
switching characteristics over recommended operating temperature conditions (unless otherwise noted) (see Figure 1)
PARAMETER tpd d ten tdis FROM (INPUT) D LE OE OE Q Q Q TO (OUTPUT) TA = 25C TYP 6.8 9 8.6 6 MIN 1.5 2 1.5 1.5 MAX 9 12 11.5 8 UNIT ns ns ns
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3
CD74FCT841A BiCMOS 10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS
SCBS725 - JULY 2000
noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25C
PARAMETER VOL(P) VOH(V) VIH(D) VIL(D) Quiet output, maximum dynamic VOL Quiet output, minimum dynamic VOH High-level dynamic input voltage Low-level dynamic input voltage 2 0.8 MIN TYP 1 0.5 MAX UNIT V V V V
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CD74FCT841A BiCMOS 10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS
SCBS725 - JULY 2000
PARAMETER MEASUREMENT INFORMATION
7V From Output Under Test CL = 50 pF (see Note A) Test Point 500 From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS S1 Open 7V Open 7V
1.5 V 10%
90%
90%
3V 1.5 V 10% 0 V tf 3V Timing Input 1.5 V 0V 3V tsu Data Input 0V 1.5 V th 3V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 3V 1.5 V tPZL VOH Output Waveform 1 (see Note B) tPZH VOH Output Waveform 2 (see Note B) 1.5 V 1.5 V 1.5 V 0V tPLZ 3.5 V VOL + 0.3 V VOL tPHZ V VOH - 0.3 V OH 0 V
tr VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES tw
Input
1.5 V
1.5 V
VOLTAGE WAVEFORMS PULSE DURATION
Input tPLH In-Phase Output tPHL Out-of-Phase Output
1.5 V
1.5 V 0V tPHL 1.5 V 1.5 V VOL tPLH 1.5 V 1.5 V VOL
Output Control
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr and tf = 2.5 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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Copyright (c) 2000, Texas Instruments Incorporated

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