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SN54LVTH2952, SN74LVTH2952 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCBS710D - OCTOBER 1997 - REVISED APRIL 1999
D D D D D D D D D
State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation Ioff and Power-Up 3-State Support Hot Insertion Bus-Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) Support Unregulated Battery Operation Down to 2.7 V Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25C Latch-Up Performance Exceeds 500 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and Thin Very Small-Outline (DGV) Packages, Ceramic Chip Carriers (FK), and Ceramic (JT) DIPs
SN54LVTH2952 . . . JT PACKAGE SN74LVTH2952 . . . DB, DGV, DW, OR PW PACKAGE (TOP VIEW)
B8 B7 B6 B5 B4 B3 B2 B1 OEAB CLKAB CLKENAB GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC A8 A7 A6 A5 A4 A3 A2 A1 OEBA CLKBA CLKENBA
SN54LVTH2952 . . . FK PACKAGE (TOP VIEW)
B5 B4 B3 NC B2 B1 OEAB
5 6 7 8 9
B6 B7 B8 NC VCC A8 A7
4 3 2 1 28 27 26 25 24 23 22 21 20 10 19 11 12 13 14 15 16 17 18
A6 A5 A4 NC A3 A2 A1
CLKAB CLKENAB GND NC
These octal bus transceivers and registers are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
NC - No internal connection
The 'LVTH2952 devices consist of two 8-bit back-to-back registers that store data flowing in both directions between two bidirectional buses. Data on the A or B bus is stored in the registers on the low-to-high transition of the clock (CLKAB or CLKBA) input, provided that the clock-enable (CLKENAB or CLKENBA) input is low. Taking the output-enable (OEAB or OEBA) input low accesses the data on either port. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
Copyright (c) 1999, Texas Instruments Incorporated
* DALLAS, TEXAS 75265
CLKENBA CLKBA OEBA
description
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SN54LVTH2952, SN74LVTH2952 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCBS710D - OCTOBER 1997 - REVISED APRIL 1999
description (continued)
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The SN54LVTH2952 is characterized for operation over the full military temperature range of -55C to 125C. The SN74LVTH2952 is characterized for operation from -40C to 85C.
FUNCTION TABLE INPUTS CLKENAB H X L L CLKAB X H or L OEAB L L L L A X X L H OUTPUT B B0 B0 L H
X X H X Z A-to-B data flow is shown; B-to-A data flow is similar but uses CLKENBA, CLKBA, and OEBA. Level of B before the indicated steady-state input conditions were established
logic symbol
OEBA CLKENBA CLKBA OEAB CLKENAB CLKAB A1 15 13 14 9 11 10 16 EN3 G1 1 C5 EN4 G2 2 C6 3 6D A2 A3 A4 A5 A6 A7 A8 17 18 19 20 21 22 23 1 1 5D 4 7 6 5 4 3 2 1 B2 B3 B4 B5 B6 B7 B8 8 B1
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DB, DGV, DW, JT, and PW packages.
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54LVTH2952, SN74LVTH2952 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCBS710D - OCTOBER 1997 - REVISED APRIL 1999
logic diagram (positive logic)
11 CLKENAB
CLKAB
10
9 OEAB
13 CLKENBA
14 CLKBA 15 OEBA C1 16 A1 1D 8 B1
C1 1D
To Seven Other Channels Pin numbers shown are for the DB, DGV, DW, JT, and PW packages.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
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SN54LVTH2952, SN74LVTH2952 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCBS710D - OCTOBER 1997 - REVISED APRIL 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Current into any output in the low state, IO: SN54LVTH2952 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74LVTH2952 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Current into any output in the high state, IO (see Note 2): SN54LVTH2952 . . . . . . . . . . . . . . . . . . . . . . 48 mA SN74LVTH2952 . . . . . . . . . . . . . . . . . . . . . . 64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Package thermal impedance, JA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
SN54LVTH2952 MIN VCC VIH VIL VI IOH IOL t/v t/VCC TA Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input transition rise or fall rate Power-up ramp rate Operating free-air temperature Outputs enabled 200 -55 125 2.7 2 0.8 5.5 -24 48 10 200 -40 85 MAX 3.6 SN74LVTH2952 MIN 2.7 2 0.8 5.5 -32 64 10 MAX 3.6 UNIT V V V V mA mA ns/V s/V C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54LVTH2952, SN74LVTH2952 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCBS710D - OCTOBER 1997 - REVISED APRIL 1999
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK TEST CONDITIONS VCC = 2.7 V, VCC = 2.7 V to 3.6 V, VCC = 2.7 V, VCC = 3 V VCC = 2 7 V 2.7 VOL VCC = 3 V II = -18 mA IOH = -100 A IOH = -8 mA IOH = -24 mA IOH = -32 mA IOL = 100 A IOL = 24 mA IOL = 16 mA IOL = 32 mA IOL = 48 mA IOL = 64 mA VI = VCC or GND VI = 5.5 V VI = 5.5 V VI = VCC VI = 0 VI or VO = 0 to 4.5 V VI = 0.8 V VI = 2 V VI = 0 to 3.6 V 75 -75 MIN SN54LVTH2952 TYP MAX -1.2 VCC-0.2 2.4 2 2 0.2 0.5 0.4 0.5 0.55 0.55 1 10 20 1 -5 75 -75 500 100 100 0.19 5 0.19 0.2 4 4 100 100 0.19 5 0.19 0.2 mA pF mA A A A 1 10 20 1 -5 100 A A 0.2 0.5 0.4 0.5 V VCC-0.2 2.4 MIN SN74LVTH2952 TYP MAX -1.2 UNIT V
VOH
V
Control inputs II A or B ports Ioff II(hold) ( ) A or B ports
VCC = 3.6 V, VCC = 0 or 3.6 V, VCC = 3.6 V VCC = 0, VCC = 3 V VCC = 3.6 V,
IOZPU IOZPD
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE = don't care VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE = don't care VCC = 3.6 V, IO = 0, VI = VCC or GND Outputs high Outputs low Outputs disabled
ICC
ICC Ci
VCC = 3 V to 3.6 V, One input at VCC - 0.6 V, Other inputs at VCC or GND VI = 3 V or 0 VO = 3 V or 0
Cio 9 9 pF On products compliant to MIL-PRF-38535, this parameter is not production tested. All typical values are at VCC = 3.3 V, TA = 25C. Unused terminals at VCC or GND This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
5
SN54LVTH2952, SN74LVTH2952 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCBS710D - OCTOBER 1997 - REVISED APRIL 1999
timing requirement over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
SN54LVTH2952 VCC = 3.3 V 0.3 V MIN fclock tw Clock frequency Pulse duration CLK high CLK low Data high A or B before CLK tsu Setup time CE before CLK th Hold time A or B after CLK CE after CLK Data low Data high Data low 3.3 3.3 1.6 1.6 1.6 2 1 1.2 MAX 150 3.3 3.3 2.2 2.2 1.9 2.6 0.2 0.2 VCC = 2.7 V MIN MAX 150 3.3 3.3 1.5 1.5 1.5 1.9 1 1.2 SN74LVTH2952 VCC = 3.3 V 0.3 V MIN MAX 150 3.3 3.3 2.1 2.1 1.8 2.5 0.2 0.2 ns ns VCC = 2.7 V MIN MAX 150 MHz ns UNIT
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
SN54LVTH2952 PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V 0.3 V MIN fmax tPLH tPHL tPZH tPZL tPHZ 150 CLKBA or CLKAB OEBA or OEAB OEBA or OEAB A or B A or B A or B 1.2 1.2 1 1 1.2 1.5 4.8 4.8 4.8 4.8 5.6 5.4 MAX VCC = 2.7 V MIN 150 5.5 5.5 5.9 5.9 6 5.6 MAX SN74LVTH2952 VCC = 3.3 V 0.3 V MIN 150 1.3 1.3 1.1 1.1 1.3 1.6 2.9 3.1 2.6 3 3.6 3.6 4.6 4.6 4.6 4.6 5.4 5.1 TYP MAX VCC = 2.7 V MIN 150 5.3 5.3 5.8 5.8 5.9 5.3 MAX MHz ns ns ns UNIT
tPLZ All typical values are at TA = 25C.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
6
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN54LVTH2952, SN74LVTH2952 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCBS710D - OCTOBER 1997 - REVISED APRIL 1999
PARAMETER MEASUREMENT INFORMATION
6V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 6V GND
LOAD CIRCUIT FOR OUTPUTS Timing Input tw 2.7 V Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION 2.7 V Input tPLH Output tPHL Output 1.5 V 1.5 V 1.5 V 1.5 V 0V tPHL VOH 1.5 V VOL tPLH VOH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Control tPZL 1.5 V tPZH 1.5 V 1.5 V 1.5 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Data Input tsu 1.5 V th 1.5 V
2.7 V 0V
2.7 V 1.5 V 0V
2.7 V 0V tPLZ 3V VOL + 0.3 V VOL tPHZ VOH - 0.3 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING
Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B)
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
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Copyright (c) 1999, Texas Instruments Incorporated

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