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| SN54LVT240, SN74LVT240 3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS134F - SEPTEMBER 1992 - REVISED JULY 1995 D D D D D D D D D State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low-Static Power Dissipation Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC ) Support Unregulated Battery Operation Down to 2.7 V Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25C ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Bus-Hold Data Inputs Eliminate the Need for External Pullup Resistors Support Live Insertion Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), and Ceramic (J) DIPs SN54LVT240 . . . J PACKAGE SN74LVT240 . . . DB, DW, OR PW PACKAGE (TOP VIEW) 1OE 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC 2OE 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 SN54LVT240 . . . FK PACKAGE (TOP VIEW) 1A2 2Y3 1A3 2Y2 1A4 4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13 2Y4 1A1 1OE VCC 2OE 1Y1 2A4 1Y2 2A3 1Y3 These octal buffers and line drivers are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices are organized as two 4-bit buffer/line drivers with separate output-enable (OE) inputs. When OE is low, the devices pass data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74LVT240 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area. The SN54LVT240 is characterized for operation over the full military temperature range of - 55C to 125C. The SN74LVT240 is characterized for operation from - 40C to 85C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 2Y1 GND 2A1 1Y4 2A2 Copyright (c) 1995, Texas Instruments Incorporated description 1 SN54LVT240, SN74LVT240 3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS134F - SEPTEMBER 1992 - REVISED JULY 1995 FUNCTION TABLE (each buffer) INPUTS OE L L H A H L X OUTPUT Y L H Z logic symbol 1OE 1 EN 18 16 14 12 logic diagram (positive logic) 1OE 1 1A1 1A2 1A3 1A4 2 4 6 8 1Y1 1Y2 1Y3 1Y4 1A1 2 18 1Y1 4 1A2 6 16 1Y2 14 1A3 2OE 19 EN 1A4 2A1 2A2 2A3 2A4 11 13 15 17 9 7 5 3 2Y1 2Y2 2Y3 2Y4 2A1 2OE 1Y3 8 12 1Y4 19 11 9 This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2Y1 13 2A2 15 7 2Y2 2A3 5 2Y3 2A4 17 3 2Y4 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54LVT240, SN74LVT240 3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS134F - SEPTEMBER 1992 - REVISED JULY 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Voltage range applied to any output in the high state or power-off state, VO (see Note 1) . . . . - 0.5 V to 7 V Current into any output in the low state, IO: SN54LVT240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74LVT240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Current into any output in the high state, IO (see Note 2): SN54LVT240 . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA SN74LVT240 . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 50 mA Maximum power dissipation at TA = 55C (in still air) (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . 0.6 W DW package . . . . . . . . . . . . . . . . . . . 1.6 W PW package . . . . . . . . . . . . . . . . . . . 0.7 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B. recommended operating conditions (see Note 4) SN54LVT240 MIN VCC VIH VIL VI IOH IOL t /v Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input transition rise or fall rate Outputs enabled - 55 2.7 2 0.8 5.5 - 24 48 10 125 - 40 MAX 3.6 SN74LVT240 MIN 2.7 2 0.8 5.5 - 32 64 10 85 MAX 3.6 UNIT V V V V mA mA ns / V C TA Operating free-air temperature NOTE 4: Unused control inputs must be held high or low to prevent them from floating. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SN54LVT240, SN74LVT240 3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS134F - SEPTEMBER 1992 - REVISED JULY 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK TEST CONDITIONS VCC = 2.7 V, VCC = MIN to MAX, VCC = 2.7 V, VCC = 3 V VCC = 2 7 V 2.7 VOL VCC = 3 V II = -18 mA IOH = -100 A IOH = - 8 mA IOH = - 24 mA IOH = - 32 mA IOL = 100 A IOL = 24 mA IOL = 16 mA IOL = 32 mA IOL = 48 mA IOL = 64 mA VI = 5.5 V VI = VCC or GND VI = VCC VI = 0 VI or VO = 0 to 4.5 V VI = 0.8 V VI = 2 V VO = 3 V VO = 0.5 V Outputs high ICC VCC = 3.6 V, VI = VCC or GND IO = 0, Outputs low Outputs disabled 0.12 8.6 0.12 Control inputs Data inputs MIN SN54LVT240 TYP MAX -1.2 VCC - 0.2 2.4 2 2 0.2 0.5 0.4 0.5 0.55 0.55 10 1 1 -5 75 -75 5 -5 0.19 12 0.19 0.2 4 4 8 0.12 8.6 0.12 75 -75 5 -5 0.19 12 0.19 0.2 mA pF pF mA 10 1 1 -5 100 Data inputs A A A A A 0.2 0.5 0.4 0.5 V VCC - 0.2 2.4 MIN SN74LVT240 TYP MAX -1.2 UNIT V VOH V VCC = 0 or MAX, II VCC = 3.6 V VCC = 0, VCC = 3 V VCC = 3.6 V, VCC = 3.6 V, Ioff II(hold) I(h ld) IOZH IOZL ICC Ci VCC = 3 V to 3.6 V, One input at VCC - 0.6 V, Other inputs at VCC or GND VI = 3 V or 0 VO = 3 V or 0 Co 8 All typical values are at VCC = 3.3 V, TA = 25C. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54LVT240, SN74LVT240 3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS134F - SEPTEMBER 1992 - REVISED JULY 1995 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54LVT240 PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V 0.3 V MIN tPLH tPHL tPZH tPZL tPHZ tPLZ A Y Y Y 1 1.3 1.2 1.5 2 1.9 MAX 4.2 3.7 4.7 4.8 5.3 4.6 VCC = 2.7 V MIN MAX 5.2 4.1 5.7 5.9 5.7 4.6 SN74LVT240 VCC = 3.3 V 0.3 V MIN TYP MAX 1 1.3 1.2 1.4 2 1.9 2.9 2.5 3.2 3.5 3.6 3.2 4.1 3.5 4.6 4.7 5.2 4.4 VCC = 2.7 V MIN MAX 5.2 4 5.6 5.8 5.5 4.4 ns ns ns UNIT OE OE All typical values are at VCC = 3.3 V, TA = 25C. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SN54LVT240, SN74LVT240 3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS134F - SEPTEMBER 1992 - REVISED JULY 1995 PARAMETER MEASUREMENT INFORMATION 6V From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 6V GND 2.7 V LOAD CIRCUIT FOR OUTPUTS tw 2.7 V Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V tPZL Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZH tPLZ 1.5 V tPHZ VOH - 0.3 V VOH 3V VOL + 0.3 V VOL 1.5 V 0V Data Input tsu 1.5 V th 2.7 V 1.5 V 0V Timing Input 1.5 V 0V 2.7 V Input tPLH Output 1.5 V 1.5 V 1.5 V 0V tPHL VOH 1.5 V VOL tPHL Output 1.5 V tPLH VOH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Control 1.5 V [0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright (c) 1998, Texas Instruments Incorporated |
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