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SN64BCT657 OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS
SCBS090A - NOVEMBER 1991 - REVISED JANUARY 1994
* * * * *
State-of-the-Art BiCMOS Design Significantly Reduces ICCZ ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) High-Impedance State During Power Up and Power Down 3-State B Outputs Sink 64 mA and Source 15 mA Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic 300-mil DIPs (NT)
DW OR NT PACKAGE (TOP VIEW)
description
T/R A1 A2 A3 A4 A5 VCC A6 A7 A8 ODD/EVEN ERR
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
OE B1 B2 B3 B4 GND GND B5 B6 B7 B8 PARITY
The SN64BCT657 contains eight noninverting buffers with parity generator/checker circuits and control signals. The transmit/receive (T/R) input determines the direction of data flow. When T/R is high, data flows from the A port to the B port (transmit mode); when T/R is low, data flows from the B port to the A port (receive mode). When the output-enable (OE) input is high, both the A and B ports are in the high-impedance state. Odd or even parity is selected by a logic high or low level on the ODD/EVEN input. PARITY carries the parity bit value; it is an output from the parity generator/checker in the transmit mode and an input to the parity generator/checker in the receive mode. In the transmit mode, after the A bus is polled to determine the number of high bits, PARITY is set to the logic level that maintains the parity sense selected by the level at the ODD/EVEN input. For example, if ODD/EVEN is low (even parity selected) and there are five high bits on the A bus, then PARITY is set to the logic high level so that an even number of the nine total bits (eight A-bus bits plus parity bit) are high. In the receive mode, after the B bus is polled to determine the number of high bits, the error (ERR) output logic level indicates whether or not the data to be received exhibits the correct parity sense. For example, if ODD/EVEN is high (odd parity selected), PARITY is high, and there are three high bits on the B bus, then ERR is low, indicating a parity error. The SN64BCT657 is characterized for operation from - 40C to 85C and 0C to 70C.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 1994, Texas Instruments Incorporated
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SN64BCT657 OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS
SCBS090A - NOVEMBER 1991 - REVISED JANUARY 1994
FUNCTION TABLE NUMBER OF A OR B INPUTS THAT ARE HIGH INPUTS OE L L 0, 2 4 6, 0 2, 4, 6 8 L L L L L L 1 3, 5 7 1, 3 5, L L L L Don't care H T/R H H L L L L H H L L L L X ODD/EVEN H L H H L L H L H H L L X INPUT/OUTPUT PARITY H L H L H L L H H L H L Z OUTPUTS ERR Z Z H L L H Z Z L H H L Z OUTPUT MODE Transmit Transmit Receive Receive Receive Receive Transmit Transmit Receive Receive Receive Receive Z
logic symbol
OE T/R ODD/EVEN A1 A2 A3 A4 A5 A6 A7 A8 24 1 11 2 3 4 5 6 8 9 10 11 12 13 14 15 16 17 18 2k 4, 2 5 4, 1 12 ERR G3 3 EN1/3G5 [REC] 3 EN2 [XMIT] N4 1 Z11 1 2 23 B1
22 21 20 17 16 15 14
B2 B3 B4 B5 B6 B7 B8
13
PARITY
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
SN64BCT657 OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS
SCBS090A - NOVEMBER 1991 - REVISED JANUARY 1994
logic diagram (positive logic)
T/R 1
OE 24 2 A1 3
23 22
B1
A2
B2
A3
4
21
B3
A4
5
20
B4
A5
6
17
B5
A6
8
16
B6
A7
9
15
B7
A8
10
14
B8
ODD/EVEN
11
13 12
PARITY ERR
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
3-3
SN64BCT657 OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS
SCBS090A - NOVEMBER 1991 - REVISED JANUARY 1994
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to 7 V Voltage range applied to any output in the disabled or power-off state, VO . . . . . . . . . . . . . . . . - 0.5 V to 5.5 V Voltage range applied to any output in the high state, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 V to VCC Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 30 mA Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 mA Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 85C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
recommended operating conditions (see Note 2)
MIN VCC VIH VIL IIK IOH IOL t /VCC Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level High level output current Low-level Low level output current Power-up ramp rate A port B port, PARITY, ERR A port B port, PARITY, ERR 2 - 40 85 4.5 2 0.8 -18 -3 -15 24 64 NOM 5 MAX 5.5 UNIT V V V mA mA mA s / V C
TA Operating free-air temperature NOTE 2: Unused or floating pins (input or I/O) must be held high or low.
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* DALLAS, TEXAS 75265
SN64BCT657 OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS
SCBS090A - NOVEMBER 1991 - REVISED JANUARY 1994
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK Any output VOH B port, PARITY, ERR Any output VOL A port B port, PARITY, ERR T/R OE II ODD/EVEN A port B port, PARITY A or B port, PARITY IIH T/R, OE ODD/EVEN A or B port, PARITY IIL T/R, OE ODD/EVEN IOS IOZH IOZL ICCL ICCH ICCZ Ci Cio i Control inputs A port B port, PARITY A port B port, PARITY, ERR ERR ERR VCC = 5 5 V 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5 V, VCC = 5 V V, VO = 0 VO = 2.7 V VO = 0.5 V Outputs open Outputs open Outputs open VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V 25 05 6.5 10 14 10 - 60 - 125 VCC = 5.5 V, VI = 0.5 V VCC = 5.5 V, VI = 2.7 V VCC = 4.5 V, VCC = 4.5 V, VCC = 4.5 V, VCC = 4.75 V, VCC = 4.5 V, VCC = 4.5 V, VCC = 0, 0 VCC = 0, VCC = 0 to 5.5 V, 55V TEST CONDITIONS II = -18 mA IOH = - 3 mA IOH = - 15 mA IOH = - 3 mA IOL = 24 mA IOL = 64 mA VI = 7 V VI = 7 V VI = 5 5 V 5.5 OE = 4.5 V T/R = 4.5 V MIN 2.4 2 2.7 0.35 0.42 0.5 0.55 20 20 20 100 200 200 20 20 - 70 - 20 - 20 - 200 - 300 50 - 50 90 2 1 mA A A mA mA mA pF pF pF A A A V TYP 3.3 3.1 V MAX -1.2 UNIT V
Co ERR VCC = 5 V, VO = 2.5 V or 0.5 V All typical values are at VCC = 5 V, TA = 25C. For I/O ports, the parameters IIH and IIL include the off-state output current. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
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SN64BCT657 OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS
SCBS090A - NOVEMBER 1991 - REVISED JANUARY 1994
switching characteristics over recommended range of supply voltage, CL = 50 pF (unless otherwise noted) (see Note 3)
PARAMETER tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) A or B A TO (OUTPUT) B or A PARITY VCC = 5 V, TA = 25C MIN 1.1 2 3 4.6 1.1 2.6 3.1 4.4 3.4 5.5 1.8 3.2 2.6 2 TYP 3.1 5.3 7.4 8.6 4.1 5.5 7.4 6.5 7.7 8.8 5.1 6.7 5.7 5 MAX 6 8.5 12.7 14.1 6.4 8.3 12.6 13.3 10.7 12 7.7 14.2 8 7.4 TA = - 40C to 85C MIN 1.1 2 3 4.6 1.1 2.6 3.1 4.4 3.4 5.5 1.8 3.2 2.6 2 MAX 6.9 9.3 16.4 16.9 7.7 9.3 16.4 16.6 14.4 14.9 9.5 17 9.5 8.8 TA = 0C to 70C MIN 1.1 2 3 4.6 1.1 2.6 3.1 4.4 3.4 5.5 1.8 3.2 2.6 2 MAX 6.6 9 15.4 15.9 7.1 9 15.3 15.5 13.2 13.9 9.1 16.3 9.1 8 ns ns ns ns ns ns ns UNIT
ODD/EVEN B PARITY
PARITY, PARITY ERR ERR ERR A B PARITY or ERR A, B, PARITY, A, B, PARITY, A B PARITY or ERR
OE OE
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
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Copyright (c) 1998, Texas Instruments Incorporated

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