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54AC16646, 74AC16646 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCAS241A - MARCH 1990 - REVISED APRIL 1996
D D D D D D D D
Members of the Texas Instruments Widebust Family Independent Registers for A and B Buses Multiplexed Real-Time and Stored Data Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Pin Configurations Minimize High-Speed Switching Noise EPICt (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125C Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings
54AC16646 . . . WD PACKAGE 74AC16646 . . . DL PACKAGE (TOP VIEW)
description
The 'AC16646 are 16-bit bus transceivers that consist of D-type flip-flops and control circuitry, with 3-state outputs arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. The devices can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the bus transceivers and registers.
1DIR 1CLKAB 1SAB GND 1A1 1A2 VCC 1A3 1A4 1A5 GND 1A6 1A7 1A8 2A1 2A2 2A3 GND 2A4 2A5 2A6 VCC 2A7 2A8 GND 2SAB 2CLKAB 2DIR
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1OE 1CLKBA 1SBA GND 1B1 1B2 VCC 1B3 1B4 1B5 GND 1B6 1B7 1B8 2B1 2B2 2B3 GND 2B4 2B5 2B6 VCC 2B7 2B8 GND 2SBA 2CLKBA 2OE
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both. The select controls (SAB and SBA) can multiplex stored and real-time (transparent mode) data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. DIR determines which bus receives data when OE is active (low). In the isolation mode (OE high), A data may be stored in one register and/or B data may be stored in the other register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time. The 74AC16646 is packaged in the TI shrink small-outline package, which provides twice the functionality of standard small-outline packages in the same printed-circuit-board area. The 54AC16646 is characterized for operation over the full military temperature range of -55C to 125C. The 74AC16646 is characterized for operation from -40C to 85C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303
Copyright (c) 1996, Texas Instruments Incorporated
* DALLAS, TEXAS 75265
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54AC16646, 74AC16646 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCAS241A - MARCH 1990 - REVISED APRIL 1996
BUS B
OE L
DIR L
CLKAB CLKBA X X
SAB X
SBA L
OE L
DIR H
CLKAB X
CLKBA X
SAB L
BUS B SBA X REAL-TIME TRANSFER BUS A TO BUS B CLKAB X H or L CLKBA H or L X SAB X H BUS B SBA H X TRANSFER STORED DATA TO A AND/OR B
BUS A
REAL-TIME TRANSFER BUS B TO BUS A
BUS B
BUS A
OE X X H
DIR X X X
CLKAB CLKBA X X
SAB X X X
SBA X X X
OE L L
STORAGE FROM A, B, OR A AND B
Figure 1. Bus-Management Functions
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BUS A DIR L H
BUS A
54AC16646, 74AC16646 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCAS241A - MARCH 1990 - REVISED APRIL 1996
FUNCTION TABLE INPUTS OE X X H H L L L L DIR X X X X L L H H CLKAB X H or L X X X H or L CLKBA X H or L X H or L X X SAB X X X X X X L H SBA X X X X L H X X A1-A8 Input Unspecified Input Input Output Output Input Input DATA I/O B1-B8 Unspecified Input Input Input Input Input Output Output OPERATION OR FUNCTION Store A, B unspecified{ Store B, A unspecified{ Store A and B data Isolation, hold storage Real-time B data to A bus Stored B data to A bus Real-time A data to B Bus
Stored A data to bus The data-output functions may be enabled or disabled by various signals at OE or DIR. Data-input functions are always enabled, i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.
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54AC16646, 74AC16646 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCAS241A - MARCH 1990 - REVISED APRIL 1996
logic symbol
1OE 1DIR 1CLKBA 1SBA 1CLKAB 1SAB 2OE 2DIR 2CLKBA 2SBA 2CLKAB 2SAB 56 1 55 54 2 3 29 28 30 31 27 26 G3 3 EN1 [BA] 3 EN2 [AB] C4 G5 C6 G7 G10 10 EN8 [BA] 10 EN9 [AB] C11 G12 C13 G14 1 1 6D 6 8 9 10 12 13 14 15 1 8 13D 14 16 17 19 20 21 23 24 1 14 12 11D 12 1 1 9 41 40 38 37 36 34 33 2B2 2B3 2B4 2B5 2B6 2B7 2B8 1 7 7 5 51 1 2 51 49 48 47 45 44 43 42 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 4D 52 1B1
1A1
5
1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1
2A2 2A3 2A4 2A5 2A6 2A7 2A8
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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54AC16646, 74AC16646 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCAS241A - MARCH 1990 - REVISED APRIL 1996
logic diagram (positive logic)
1OE 56
1 1DIR 55 1CLKBA 54 1SBA 2 1CLKAB 3 1SAB TG 1A1 5 TG C1 1D TG 52 TG 6 8 9 10 12 13 14 51 49 48 47 45 44 43 B1 C1 1D
1A2 1A3 1A4 1A5 1A6 1A7 1A8
Seven Channels Identical to Channel One Above
B2 B3 B4 B5 B6 B7 B8
2OE
29
2DIR 2CLKBA 2SBA 2CLKAB 2SAB
28 30 31 27 26
15 2A1
TG
C1 1D
TG C1 1D TG 42 TG 16 17 19 20 21 23 24 41 40 38 37 36 34 33 B1
2A2 2A3 2A4 2A5 2A6 2A7 2A8
Seven Channels Identical to Channel One Above
B2 B3 B4 B5 B6 B7 B8
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54AC16646, 74AC16646 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCAS241A - MARCH 1990 - REVISED APRIL 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous output current, IO (VO = 0 to VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 mA Maximum power dissipation at TA = 55C (in still air) (see Note 2): DL package . . . . . . . . . . . . . . . . . . . 1.4 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils.
recommended operating conditions
54AC16646 MIN VCC VIH Supply voltage (see Note 3) High-level input voltage VCC = 3 V VCC = 4.5 V VCC = 5.5 V VCC = 3 V VIL VI VO IOH Low-level input voltage Input voltage Output voltage High-level output current VCC = 3 V VCC = 4.5 V VCC = 5.5 V VCC = 3 V IOL t/v Low-level output current Input transition rise or fall rate VCC = 4.5 V VCC = 5.5 V 0 VCC = 4.5 V VCC = 5.5 V 0 0 3 2.1 3.15 3.85 0.9 1.35 1.65 VCC VCC -4 -24 -24 12 24 24 10 125 0 -40 0 0 NOM 5 MAX 5.5 74AC16646 MIN 3 2.1 3.15 3.85 0.9 1.35 1.65 VCC VCC -4 -24 -24 12 24 24 10 85 ns/V C mA mA V V V V NOM 5 MAX 5.5 UNIT V
TA Operating free-air temperature -55 NOTE 3: All VCC and GND pins must be connected to the proper voltage power supply.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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54AC16646, 74AC16646 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCAS241A - MARCH 1990 - REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC 3V IOH = -50 A IOH = -4 mA 4.5 V 5.5 V VOH 3V 4.5 V 5.5 V IOH = -50 mA IOH = -75 mA IOL = 50 A IOL = 12 mA 5.5 V 5.5 V 3V 4.5 V 5.5 V VOL 3V 4.5 V 5.5 V IOL = 50 mA IOL = 75 mA II IOZ ICC Ci VI = VCC or GND VI = VCC or GND VI = VCC or GND, VI = VCC or GND IO = 0 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5V 4.5 0.1 0.5 8 1 10 160 0.1 0.1 0.1 0.36 0.36 0.36 0.1 0.1 0.1 0.5 0.5 0.5 1.65 1.65 1 5 80 A A A pF pF MIN 2.9 4.4 5.4 2.58 3.94 4.94 TA = 25C TYP MAX 54AC16646 MIN 2.9 4.4 5.4 2.4 3.7 4.7 3.85 3.85 0.1 0.1 0.1 0.44 0.44 0.44 V MAX 74AC16646 MIN 2.9 4.4 5.4 2.48 3.8 4.8 V MAX UNIT
Co VI = VCC or GND 5V 16 Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. For I/O ports, the parameter IOZ includes the input leakage current.
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 2)
TA = 25C MIN MAX fclock tw tsu th Clock frequency Pulse duration, CLKAB or CLKBA high or low Setup time, A before CLKAB or B before CLKBA Hold time, A after CLKAB or B after CLKBA 0 7 6.5 1 65 54AC16646 MIN 0 7 6.5 1 MAX 65 74AC16646 MIN 0 7 6.5 1 MAX 65 UNIT MHz ns ns ns
timing requirements over recommended operating free-air temperature range, VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 2)
TA = 25C MIN MAX fclock tw tsu th Clock frequency Pulse duration, CLKAB or CLKBA high or low Setup time, A before CLKAB or B before CLKBA Hold time, A after CLKAB or B after CLKBA 0 6.5 5 1 75 54AC16646 MIN 0 6.5 5 1 MAX 75 74AC16646 MIN 0 6.5 5 1 MAX 75 UNIT MHz ns ns ns
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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54AC16646, 74AC16646 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCAS241A - MARCH 1990 - REVISED APRIL 1996
switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 2)
PARAMETER fmax tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) MIN 65 A or B B or A A or B A or B A or B A or B A or B A or B A or B 3.4 3.6 3.8 4.8 4.4 4 4.7 4.8 4.7 4.5 4 5.2 3.6 4.7 4.6 3.9 9.3 10 10.5 13.9 7.6 7 12.1 12.2 12 11.4 10.5 13.3 10.3 13.5 7.8 7 13.2 13.4 TA = 25C TYP MAX 54AC16646 MIN 65 3.4 3.6 3.8 4.8 4.4 4 4.7 4.8 4.7 4.5 4 5.2 3.6 4.7 4.6 3.9 15.7 15.1 17.6 22.1 11 10.4 19.9 18.8 19.9 17.2 17.3 20.3 17.9 22.1 11.6 11 MAX 74AC16646 MIN 65 3.4 3.6 3.8 4.8 4.4 4 4.7 4.8 4.7 4.5 4 5.2 3.6 4.7 4.6 3.9 14.8 4.5 16.4 20.9 10.7 10.1 18.7 18 18.5 16.4 16.3 19.3 16.8 20.8 11.2 10.6 MAX UNIT MHz ns ns ns ns ns ns ns ns
OE OE CLKBA or CLKAB SAB or SBA (with A or B high) SBA or SAB (with A or B low) DIR DIR
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
switching characteristics over recommended operating free-air temperature range, VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 2)
PARAMETER fmax tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) MIN 75 A or B B or A A or B A or B A or B A or B A or B A or B A or B 2.9 2.9 3.1 4.1 4 3.8 3.9 3.9 4 3.6 3.3 4.3 3 3.6 4 3.7 5.5 5.7 6.1 7.3 6.1 5.7 7 7.1 7.4 6.7 6.1 8 5.9 7 6.2 5.7 8.5 8.9 9.4 11 8.4 8 10.8 10.8 11.1 10.2 9.5 11.7 9.6 11.1 8.8 8.2 TA = 25C TYP MAX 54AC16646 MIN 75 2.9 2.9 3.1 4.1 4 3.8 3.9 3.9 4 3.6 3.3 4.3 3 3.6 4 3.7 10.1 10.1 11.1 12.9 9.1 8.9 12.8 12.5 13.4 11.8 11.2 13.9 11.6 12.9 9.6 9 MAX 74AC16646 MIN 75 2.9 2.9 3.1 4.1 4 3.8 3.9 3.9 4 3.6 3.3 4.3 3 3.6 3 3.7 9.5 9.7 10.5 12.2 8.9 8.6 12.1 11.9 12.5 11.2 10.6 13.1 10.9 12.2 9.4 8.8 MAX UNIT MHz ns ns ns ns ns ns ns ns
OE OE CLKBA or CLKAB SAB or SBA (with A or B high) SBA or SAB (with A or B low) DIR DIR
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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54AC16646, 74AC16646 16-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SCAS241A - MARCH 1990 - REVISED APRIL 1996
operating characteristics, VCC = 5 V, TA = 25C
PARAMETER Cpd d Power dissipation capacitance Outputs enabled Outputs disabled TEST CONDITIONS CL = 50 pF pF, f = 1 MHz TYP 62 14 UNIT pF
PARAMETER MEASUREMENT INFORMATION
2 x VCC From Output Under Test CL = 50 pF (see Note A) 500 S1 Open GND 500 TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 2 x VCC GND
LOAD CIRCUIT Timing Input tw VCC Input 50% 50% 0V VOLTAGE WAVEFORMS Output Control (low-level enabling) Output Waveform 1 S1 at 2 x VCC (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZH VOLTAGE WAVEFORMS Data Input tsu 50% 50% th VCC 50% 0V VCC 0V
VCC Input tPLH In-Phase Output tPHL Out-of-Phase Output 50% VCC 50% VCC 50% 50% 0V tPHL VOH 50% VCC VOL tPLH VOH 50% VCC VOL
VCC 50% tPZL tPLZ 50% VCC tPHZ 80% VCC VOH 20% VCC 50% 0V
[ VCC
VOL
50% VCC
[0V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 3 ns, tf = 3 ns. D. The outputs are measured one at a time with one input transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
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Copyright (c) 1998, Texas Instruments Incorporated

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