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DEVICE SPECIFICATION
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SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER BiCMOS PECL CLOCK GENERATOR SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER OC-3/OC-12 TRANSCEIVER GENERAL DESCRIPTION
S3028 S3028 S3028
FEATURES
* Complies with Bellcore and ITU-T specifications * Jitter generation better than ITU-T requirements * On-chip high-frequency PLL for clock generation * Supports 155.52 Mbps (OC-3) and 622.08 Mbps (OC-12) * Selectable reference frequencies of 19.44, 38.88, 51.84, or 77.76 MHz * Interface to both PECL and TTL logic * 4-bit or 8-bit OC-3 TTL datapath * 8-bit OC-12 TTL datapath * Compact 64 PQFP package * Diagnostic loopback mode * Line loopback mode * Lock detect * LOS input * Low jitter PECL interface * 0.9W typical power dissipation * Loop Timing (S3028B only) * Forward Clocking (S3028B only) * "Squelched Clock" operation (S3028B only) * 5 V Power supply
The S3028 SONET/SDH transceiver chip is a fully integrated serialization/deserialization SONET OC-12 (622.08 Mbit/s) and OC-3 (155.52 Mbit/s) interface device. The chip performs all necessary serial-to-parallel and parallel-to-serial functions in conformance with SONET/SDH transmission standards. The device is suitable for SONET-based ATM applications and can be used in conjunction with AMCC's S3026 Clock Recovery Unit (CRU). Figure 1 shows a typical network application. On-chip clock synthesis is performed by the highfrequency phase-locked loop on the S3028 transceiver chip allowing the use of a slower external transmit clock reference. The S3028 also performs SONET/SDH frame detection. The chip can be used with a 19.44, 38.88, 51.84 or 77.76 MHz reference clock, in support of existing system clocking schemes. The low jitter PECL interface guarantees compliance with the bit-error rate requirements of the Bellcore and ITU-T standards. The S3028 is packaged in a 64 PQFP, offering designers a small package outline. Since the S3028 jitter generation is better than the ITU-T requirements over all reference frequencies, the designer can meet the overall system requirement including the optical interface devices (refer to Table 9 for jitter generation specifications).
APPLICATIONS
* * * * * * * * * SONET/SDH-based transmission systems SONET/SDH modules SONET/SDH test equipment ATM over SONET/SDH Section repeaters Add Drop Multiplexers (ADM) Broad-band cross-connects Fiber optic terminators Fiber optic test equipment
Figure 1. System Block Diagram
8 Transceiver Controller 8 S3028 S3026 Fiber Optic Module Fiber Optic Module
S3026
8 Transceiver Controller S3028 8
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S3028 SONET OVERVIEW
Synchronous Optical Network (SONET) is a standard for connecting one fiber system to another at the optical level. SONET, together with the Synchronous Digital Hierarchy (SDH) administered by the ITU-T, forms a single international standard for fiber interconnect between telephone networks of different countries. SONET is capable of accommodating a variety of transmission rates and applications. The SONET standard is a layered protocol with four separate layers defined. These are: * Photonic * Section * Line * Path Figure 2 shows the layers and their functions. Each of the layers has overhead bandwidth dedicated to administration and maintenance. The photonic layer simply handles the conversion from electrical to optical and back with no overhead. It is responsible for transmitting the electrical signals in optical form over the physical media. The section layer handles the transport of the framed electrical signals across the optical cable from one end to the next. Key functions of this layer are framing, scrambling, and error monitoring. The line layer is responsible for the reliable transmission of the path layer information stream carrying voice, data, and video signals. Its main functions are synchronization, multiplexing, and reliable transport. The path layer is responsible for the actual transport of services at the appropriate signaling rates.
SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER
up of N byte-interleaved STS-1 signals. The optical counterpart of each STS-N signal is an optical carrier level-N signal (OC-N). The S3028 chip supports OC-3 and OC-12 rates (155.52 and 622.08 Mbit/s). Frame and Byte Boundary Detection The SONET/SDH fundamental frame format for STS12 consists of 36 transport overhead bytes followed by Synchronous Payload Envelope (SPE) bytes. This pattern of 36 overhead and 1044 SPE bytes is repeated nine times in each frame. Frame and byte boundaries are detected using the A1 and A2 bytes found in the transport overhead. (See Figure 3.) For more details on SONET operations, refer to the Bellcore SONET standard document.
Table 1. SONET Signal Hierarchy
Elec.
STS-1 STS-3 STS-12 STS-24 STS-48
CCITT
STM-1 STM-4 STM-8 STM-16
Optical Data Rate (Mbit/s)
OC-1 OC-3 OC-12 OC-24 OC-48 51.84 155.52 622.08 1244.16 2488.32
Figure 2. SONET Structure
Functions
Payload to SPE mapping Maintenance, protection, switching Scrambling, framing Optical transmission
Layer Overhead (Embedded Ops Channel) Path layer Line layer Section layer Path layer Line layer Section layer
576 Kbps
Data Rates and Signal Hierarchy
Table 1 contains the data rates and signal designations of the SONET hierarchy. The lowest level is the basic SONET signal referred to as the synchronous transport signal level-1 (STS-1). An STS-N signal is made
192 Kbps
Photonic layer
Photonic layer 0 bps
End Equipment
Fiber Cable End Equipment
Figure 3. STS-12/OC-12 Frame Format
A1 A1 A1 A1 12 A1 Bytes A2 A2 A2 A2 12 A2 Bytes
9 Rows
Transport Overhead 36 Columns 36 x 9 = 324 bytes
Synchronous Payload Envelope 1044 Columns 1044 x 9 = 9396 bytes
v
125 sec
2
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v
SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER
Figure 4. S3028 Transceiver Functional Block Diagram
Transmitter
LLEB 8 8:1 PARALLEL TO SERIAL M U X D TSDP/N
S3028 S3028 OVERVIEW
The S3028 transceiver implements SONET/SDH serialization/deserialization, transmission, and frame detection/recovery functions. The block diagram in Figure 4 shows basic operation of the chip. This chip can be used to implement the front end of SONET equipment, which consists primarily of the serial transmit interface and the serial receive interface. The chip handles all the functions of these two elements, including parallel-to-serial and serial-toparallel conversion, clock generation, and system timing. The system timing circuitry consists of management of the data stream, framing, and clock distribution throughout the front end. The S3028 is divided into a transmitter section and a receiver section. The sequence of operations is as follows: Transmitter Operations: 1. 4 or 8-bit parallel input 2. Parallel-to-serial conversion 3. Serial output Receiver Operations: 1. Serial input 2. Frame detection 3. Serial-to-parallel conversion 4. 4 or 8-bit parallel output Internal clocking and control functions are transparent to the user. Details of data timing can be seen in Figures 7 through 10.
PIN[7:0] PICLK
M U X TIMING GEN
TSCLKP/N PCLK
TESTEN CLOCK SYNTHESIZER
LOCKDET
19MCK
RSTB TESTRST
CAP1
CAP2
REFSEL[1:0] MODE REFCLKP/N
2
BUSWIDTH
Receiver
SDTTL SDPECL
1:8 SERIAL TO PARALLEL
8
POUT[7:0]
Suggested Interface Devices
OOF TIMING FRAME GEN BYTE DETECT POCLK
AMCC AMCC AMCC AMCC
S3026 S3027
622/155 Mbit/s 622/155 Mbit/s
Clock Recovery Device Clock Recovery Device POS/ATM SONET Mapper ATM SONET Mapper
DLEB D M U X
FP
CONGO (S1201) NILE (S1202)
RSDP/N
RSCLKP/N
M U X
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S3028 TRANSCEIVER FUNCTIONAL DESCRIPTION
TRANSMITTER OPERATION
The S3028 transceiver chip performs the serializing stage in the processing of a transmit SONET STS-3 or STS-12 bit serial data stream. It converts the 8-bit parallel 19.44, 38.88 or 77.76 Mbyte/sec data stream into bit serial format at 155.52 or 622.08 Mbit/sec. Diagnostic loopback is provided (transmitter to receiver). Line loopback is also provided (receiver-totransmitter). A high-frequency bit clock can be generated from a 19.44, 38.88, 51.84 or 77.76 MHz frequency reference by using an integral frequency synthesizer consisting of a phase-locked loop circuit with a divider in the loop.
SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER
Table 3. Reference Frequency Options
REFSEL[1:0] 00 01 10 11 Reference Clock Frequency 19.44 MHz 38.88 MHz 51.84 MHz 77.76 MHz Operating Mode STS-12, STS-3 STS-12, STS-3 STS-12, STS-3 STS-12
Table 4. Reference Jitter Limits
Frequency Band 12 kHz to 5 MHz 12 kHz to 1 MHz Maximum Reference Clock Jitter 14 ps rms 56 ps rms Operating Mode STS-12 STS-3
Clock Synthesizer
The clock synthesizer, shown in the block diagram in Figure 4, is a monolithic PLL that generates the serial output clock phase synchronized with the input Reference Clock (REFCLK). There are three selectable output clock frequencies that are synthesizable from any of four selectable reference frequencies for SONET/SDH operation. The MODE inputs select the output serial clock frequency to be 622.08 MHz for STS-12, or 155.52 MHz for STS-3. Their frequencies are selected as shown in Table 2.
In order to meet the 0.01 UI SONET jitter generation specifications, the maximum reference clock jitter must be guaranteed over the 12 kHz to 1 MHz bandwidth for the STS-3 operating mode. For details of reference clock jitter requirements, see Table 4. The on-chip PLL consists of a phase detector, which compares the phase relationship between the VCO output and the REFCLK input, a loop filter which converts the phase detector output into a smooth DC voltage, and a VCO, whose frequency is varied by this voltage. The loop filter generates a VCO control voltage based on the average DC level of the phase discriminator output pulses. The loop filter's corner frequency is optimized to minimize output phase jitter.
Timing Generator
Table 2. Clock Frequency Options
MODE 1 0 Output Clock Frequency 622.08 MHz 155.52 MHz Operating Mode STS-12 STS-3
The timing generator function, seen in Figure 4, provides two separate functions. It provides a byte rate version of the TSCLK, and a mechanism for aligning the phase between the incoming byte clock and the clock which loads the parallel-to-serial shift register. The PCLK output is a byte rate version of TSCLK. For STS-12, the PCLK frequency is 77.76 MHz, and for STS-3, its frequency is 19.44 or 38.88 MHz. PCLK is intended for use as an 8-bit parallel clock for upstream multiplexing and overhead processing circuits. Using PCLK for upstream circuits will ensure a stable frequency and phase relationship between the data coming into and leaving the S3028 device. In the parallel-to-serial conversion process, the incoming data is passed from the PICLK 8-bit parallel clock timing domain to the internally generated serial clock timing domain, which is phase aligned to TSCLK.
The REFSEL[1:0] inputs in combination with the MODE input select the ratio between the output clock frequency and the reference input frequency, as shown in Table 3. This ratio is adjusted for each of the four operating modes so that the reference frequency selected by the REFSEL[1:0] is the same for all modes. The REFCLK input must be generated from a differential PECL crystal oscillator which has a frequency accuracy that meets the value specified in Table 9 in order for the TSCLK frequency to have the same accuracy required for operation in a SONET system.
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The timing generator also produces a feedback reference clock to the clock synthesizer. A counter divides the synthesized clock down to the same frequency as the Reference Clock REFCLK. The PLL in the clock synthesizer maintains the stability of the synthesized clock by comparing the phase of the internal clock with that of the reference clock (REFCLK). The modulus of the counter is a function of the reference clock frequency and the operating frequency.
S3028
put on the parallel output data bus (POUT[7:0]). When framing pattern detection is enabled, the frame boundary is reported on the Frame Pulse (FP) output when any 48-bit pattern matching the framing pattern is detected on the incoming data stream. When framing pattern detection is disabled, the byte boundary is frozen to the location found when detection was previously enabled. Only framing patterns aligned to the fixed byte boundary are indicated on the FP output. The probability that random data in an STS-3 or STS-12 stream will generate the 48-bit framing pattern is extremely small. It is highly improbable that a mimic pattern would occur within one frame of data. Therefore, the time to match the first frame pattern and to verify it with down-stream circuitry, at the next occurrence of the pattern, is expected to be less than the required 250 s, even for extremely high bit error rates. Once down-stream overhead circuitry has verified that frame and byte synchronization are correct, the OOF input can be set low to disable the frame search process from trying to synchronize to a mimic frame pattern.
Parallel-to-Serial Converter
The parallel-to-serial converter shown in Figure 4 is comprised of two 8-bit wide registers. The first register latches the data from the PIN[7:0] bus on the rising edge of PICLK. The second register is a parallel loadable shift register which takes its parallel input from the first register. An internally generated byte clock, which is phase aligned to the transmit serial clock as described in the Timing Generator description, activates the parallel data transfer between registers. The serial data is shifted out of the second register at the TSCLK rate.
RECEIVER OPERATION
The S3028 transceiver chip provides the first stage of the digital processing of a receive SONET STS-3 or STS-12 bit-serial stream. It converts the bit-serial 155.52 or 622.08 Mbit/sec data stream into a 19.44, 38.88 or 77.76 Mbyte/sec parallel data format. A loopback mode is provided for diagnostic loopback (transmitter to receiver). An additional loopback mode is provided for line loopback (receiver to transmitter).
Serial to Parallel Converter
The serial to parallel converter consists of three 8-bit registers. The first is a serial-in, parallel-out shift register, which performs serial to parallel conversion clocked by the clock recovery block. The second is an 8-bit internal holding register, which transfers data from the serial to parallel register on byte boundaries as determined by the frame and byte boundary detection block. On the falling edge of the free running POCLK, the data in the holding register is transferred to an output holding register which drives POUT[7:0]. The delay through the serial to parallel converter can vary from 1.5 to 2.5 byte periods (12 to 20 serial bit periods) measured from the first bit of an incoming byte to the beginning of the parallel output of that byte. The variation in the delay is dependent on the alignment of the internal parallel load timing, which is synchronized to the data byte boundaries, with respect to the falling edge of POCLK, which is independent of the byte boundaries. The advantage of this serial to parallel converter is that POCLK is neither truncated nor extended during reframe sequences.
Frame and Byte Boundary Detection
The frame and byte boundary detection circuitry searches the incoming data for three consecutive A1 bytes followed immediately by three consecutive A2 bytes. Framing pattern detection is enabled and disabled by the Out Of Frame (OOF) input. Detection is enabled by a rising edge on OOF, and remains enabled for the duration that OOF is set High. It is disabled when a framing pattern is detected after OOF is set Low. When framing pattern detection is enabled, the framing pattern is used to locate byte and frame boundaries in the incoming data stream (RSD or looped transmitter data). The timing generator block takes the located byte boundary and uses it to block the incoming data stream into bytes for out-
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S3028 OTHER OPERATING MODES
Diagnostic Loopback
When the Diagnostic Loopback Enable (DLEB) input is active, a loopback from the transmitter to the receiver at the serial data rate can be set up for diagnostic purposes. The differential serial output data from the transmitter is routed to the serial-to-parallel block in place of the normal data stream (RSD).
SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER
For operation at 19.44 MHz and 51.84 MHz references, separate timing paths are use for PLL control and PCLK generation, and forward clocking is not recommended.
"Squelched Clock" Operation
Some integrated optical receiver/clock recovery modules force their recovered serial receive clock output to the logic zero state if the optical signal is removed or reduced below a fixed threshold. This condition is accompanied by the expected deassertion of the signal detect output. The S3028B has been designed for operation with clock recovery devices that provide continuous serial clock for seamless down stream clocking in the event of optical signal loss. For operation with an optical transceiver that provides the "squelched clock" behavior as described above, the S3028B can be operated in the "squelched clock mode" by setting the BUSWIDTH input low, (4 bit mode at 155.52 Mbit/s rate) while the MODE input is set high (622.08 Mbit/s rate). "Squelched Clock" mode is available in 622.08 Mbit/s mode only. The Receive Serial Clock, RSCLKP/N, is used for all receiver timing when the SDPECL/SDTTL inputs are in the active state. When the SDPECL/SDTTL inputs are placed in the inactive state, (usually by the deassertion of LOCKDET or signal detect from the optical transceiver/clock recovery unit) the transmitter serial clock will be used to maintain timing in the receiver section. This will allow the POCLK to continue to run and the parallel outputs to flush out the last received characters and assume the all zero state imposed at the serial data input. In this mode there will be a random 1.6 nsec shortening or lengthening of the POCLK cycle, resulting in an apparent phase shift in the POCLK at the deassertion of the signal detect condition. Another similar phase shift will occur when the signal detect condition is reasserted. In the normal operating mode with both MODE and BUSWIDTH inputs high, there will be no phase discontinuities at the POCLK output during signal loss or reacquisition (assuming operation with continuous clocking from the CRU device such as the AMCC S3026 or S3027)
Line Loopback
The line loopback circuitry consists of alternate clock and data output drivers. For the S3028, it selects the source of the data and clock which is output on TSD and TSCLK. When the Line Loopback Enable (LLEB) input is inactive, it selects data and clock from the parallel to serial converter block. When LLEB is active, it forces the output data multiplexer to select data and clock from the RSD and RSCLK inputs, and a receive-to-transmit loopback can be established at the serial data rate. Diagnostic loopback and line loopback can be active at the same time.
Loop Timing
In loop timing mode, the clock synthesizer PLL of the S3028 is bypassed, and the timing of the entire transmitter section is controlled by the Receive Serial Clock, RSCLKP/N. This mode is entered by setting the TESTEN input to a TTL high level. The internal PLL continues to operate in this mode, and continues as the source for the 19MCK. If this signal is being used (e.g. as the reference for an external clock recovery device such as the AMCC S3026), the REFCLKP/N and REFSEL[1:0] inputs must be properly driven in either 19.44 MHz or 51.84 MHz mode. The 19MCK output should not be used in loop timing mode if 77.76 or 38.88 MHz reference operation is selected. The MODE input has no effect on the transmitter operation if loop timing is selected.
Forward Clocking
For both 77.76 MHz and 38.88 MHz reference operation, the S3028 operates in the forward clocking mode. The PLL locks the PCLK output of the transmitter section to the REFCLK with a fixed and repeatable phase relation. This allows the transmitter data source to also be the timing source for the serial clock synthesis.
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Table 5. S3028 Transceiver Pin Assignment and Descriptions
Pin Name PIN7 PIN6 PIN5 PIN4 PIN3 PIN2 PIN1 PIN0 PICLK Level TTL I/O I Pin # 60 59 58 57 56 55 54 53 61 Description
S3028
Parallel Data Input, a 77.76, 51.84, 38.88 or 19.44 Mbyte/s word, aligned to the PICLK, Paralle Input Clock. PIN7 is the most significant bit (corresponding to bit 1 of each PCM word, the first bit transmitted). PIN0 is the least significant bit (corresponding to bit 8 of each PCM word, the last bit transmitted). PIN[7:0] is sampled on the rising edge of PICLK. If a 4-bit bus width is selected, PIN7 is the most significant bit, and bit 4 is the least significant bit. Parallel Input Clock, a 77.76, 51.84, 38.88 or 19.44 MHz, nominally 50% duty cycle input clock, to which PIN[7:0] is aligned. PICLK is used to transfer the data on the PIN inputs into a holding register in the parallel-to-serial converter. The rising edge of PICLK samples PIN[7:0]. After a master reset, two rising edges of PICLK are required to fully initialize the internal datapath. The loop filter capacitor is connected to these pins. The capacitor value should be 0.01F 10% tolerance, X7'R dielectric. 50 volt is recommended (16 volt is acceptable). Transmit Serial Data. Serial data stream signals, normally connected to an optical transmitter module. Transmit Serial Clock that can be used to retime the TSD signal. This clock will be 622.08 MHz or 155.52 MHz, depending on the operating mode. A reference clock generated by dividing the internal bit clock by eight (or by four when BUSWIDTH is low). It is normally used to coordinate 8-bit wide transfers between upstream logic and the S3028 device. Lock Detect signal. Active High. When active, this output indicates that the transmit PLL is locked onto the reference clock input.
TTL
I
CAP1 CAP2 TSDP TSDN TSCLKP TSCLKN PCLK
Analog
I
10 11 17 18 21 20 62
Diff. PECL Diff. PECL TTL
O
O
O
LOCKDET
TTL
O
63
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S3028
SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER
Table 5. S3028 Transceiver Pin Assignment and Descriptions (continued)
Pin Name RSDP RSDN RSCLKP RSCLKN Level Diff. PECL Diff. PECL I/O I Pin # 24 25 27 28 Description Receive Serial Data stream signals normally connected to an optical receiver module. These inputs are clocked by the RSCLK inputs. Receive Serial Clock. Recovered clock signal that is synchronous with the RSD inputs. This clock is used by the receive section as the master clock to perform framing and deserialization functions. Out Of Frame indicator used to enable framing pattern detection logic in the S3028. This logic is enabled by a rising edge on OOF, and remains enabled until frame boundary is detected or when OOF is set low, whichever is longer. OOF is an asynchronous signal with a minimum pulse width of one POCLK period. (See Figures 12 and 13.) PECL Signal Detect. PECL with internal 1k pull-down. Active High when SDTTL is held at a logic 0. Active Low when SDTTL is held at a logic 1. A single-ended 10K PECL input to be driven by the external optical receiver module to indicate a loss of received optical power. When SDPECL is inactive, the data on the Serial Data in (RSDP/N) pins will be internally forced to a constant zero. When SDPECL is active, data on the RSDP/N pins will be processed normally. When SDTTL is to be connected to the optical receiver module instead of SDPECL, then SDPECL should be tied High to implement an active low signal detect, or left unconnected to implement an active high signal detect. TTL Signal Detect. Active High when SDPECL is unconnected (logic 0). Active Low when SDPECL is held at a logic 1. A single-ended TTL input to be driven by the external optical receiver module to indicate a loss of received optical power. When SDTTL is inactive, the data on the RSDP/N pins will be internally forced to a constant zero. When SDTTL is active, data on the RSDP/N pins will be processed normally. Parallel Output Data bus, a 77.76, 51.84, 38.88 or 19.44 Mbyte/s word, aligned to the POCLK Parallel Output Clock. POUT7 is the most significant bit (corresponding to bit 1 of each PCM word, the first bit received). POUT0 is the least significant bit (corresponding to bit 8 of each PCM word, the last bit received). POUT[7:0] is updated on the falling edge of POCLK. If a 4-bit bus width is selected, POUT7 is the most significant bit, and bit 4 is the least significant bit. 19 MHz clock output from the clock synthesizer. This output should be connected to the reference clock input of the external clock recovery function (such as the S3026).
I
OOF
TTL
I
33
SDPECL
PECL
I
23
SDTTL
TTL
I
22
POUT7 POUT6 POUT5 POUT4 POUT3 POUT2 POUT1 POUT0 19MCK
TTL
O
45 44 43 41 40 39 37 36 64
TTL
O
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Table 5. S3028 Transceiver Pin Assignment and Descriptions (Continued)
Pin Name FP Level TTL I/O O Pin # 35 Description
S3028
Frame Pulse. Indicates frame boundaries in the incoming data stream (RSD). If framing pattern detection is enabled, as controlled by the OOF input, FP pulses high for one POCLK cycle when a 48-bit sequence matching the framing is detected on the RSD inputs. When framing pattern detection is disabled, FP pulses high when the incoming data stream, after byte alignment, matches the framing pattern. FP is updated on the falling edge of POCLK. A 77.76, 51.84, 38.88, or 19.44 MHz nominally 50% duty cycle, byte rate output clock that is aligned to POUT[7:0] byte serial output data. POUT[7:0] and FP are updated on the falling edge of POCLK.
POCLK
TTL
O
47
Table 6. S3028 Common Control Pin Assignment and Descriptions
Pin Name TESTEN Level TTL I/O I Pin # 13 Description Test Enable. Test clock/loop timing enable signal. Active High. Set high to provide access to the PLL during production tests. Also used to enable loop timing mode when High (S3028B only). Bus Width selection. Used to select 4-bit or 8-bit operation of the transmit and receive parallel interfaces. Low selects a 4-bit bus width. High selects an 8-bit bus width. Must be high for 622.08 Mbit/s normal operation (S3028). Low in 622.08 Mbit/s mode enables squelched clock operation (S3028B only). Reference Clock input. Used as the reference for the internal bit clock frequency synthesizer. Diagnostic Loopback Enable. Active Low. Selects diagnostic loopback. When DLEB is high, the S3028 device uses the primary data (RSD) and clock (RSCLK) inputs. When low, the S3028 device uses the diagnostic loopback clock and data from the transmitter. Master Reset. Reset input for the device, active Low. During reset, PCLK does not toggle. Line Loopback Enable. Active Low. Selects line loopback. When LLEB is active, the S3028 will route the data from the RSD/RSCLK inputs to the TSD/TSCLK outputs. Reference Select inputs. Used to select the reference clock frequency. See Table 3. Mode select, used to select the serial bit rate. Low selects 155.52 Mbit/s. High selects 622.08 Mbit/s. For 155.52 Mbit/s mode, the parallel interface can operate with 4 bits. Test Reset input. Active High. Used to reset portions of the PLL during production testing. Held Low for normal operation.
BUSWIDTH
TTL
I
30
REFCLKP REFCLKN DLEB
Diff. PECL TTL
I
15 14 32
I
RSTB
TTL
I
48
LLEB
TTL
I
31
REFSEL1 REFSEL0 MODE
TTL
I
4 3 49
TTL
I
TESTRST
TTL
I
50
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S3028
SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER
Table 7. S3028 Power Pin Assignment and Descriptions
Pin Name AGND AVCC CGND TXOUTGND TXOUTVCC RXCOREVCC RXCOREGND TTLVCC TTLGND TXCOREGND TXCOREVCC Level 0V +5V 0V 0V +5V +5V 0V +5V 0V 0V +5V I/O - - - - - - - - - - - Pin # 5, 8 6, 7 9, 12 19 16 26, 52 29, 51 38, 46 34, 42 2 1 Description Analog 0V Analog +5V via individual Ferrite bead (BLM32A06) and individual decoupling. Ground ring to guard CAP1 and CAP2 pins connect to ground plane at a single point. Digital 0V Digital +5V, Individually decoupled. Digital +5V, individually decoupled. Digital 0V Digital +5V, Individually decoupled. Digital 0V Digital 0V Digital +5V, individually decoupled.
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Figure 5. 64 PQFP Package
S3028
TOP VIEW
SIDE VIEW
Table 8. Thermal Management
Max Power
1.37 W
ja
52.0 C/W
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S3028
Figure 6. S3028 64 PQFP Pinout
SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER
TXCOREVCC TXCOREGND REFSEL0 REFSEL1 AGND1 AVCC1 AVCC0 AGND0 CGND CAP1 CAP2 CGND TESTEN REFCLKN REFCLKP TXOUTVCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
19MCK LOCKDET PCLK PICLK PIN7 PIN6 PIN5 PIN4 PIN3 PIN2 PIN1 PIN0 RXCOREVCC RXCOREGND TESTRST MODE
S3028 64 PQFP TOP VIEW
RSTB POCLK TTLVCC POUT7 POUT6 POUT5 TTLGND POUT4 POUT3 POUT2 TTLVCC POUT1 POUT0 FP TTLGND OOF
TSDP TSDN TXOUTGND TSCLKN TSCLKP SDTTL SDPECL RSDP RSDN RXCOREVCC RSCLKP RSCLKN RXCOREGND BUSWIDTH LLEB DLEB
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
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Table 9. Performance Specifications
Parameter Nominal VCO Center Frequency Data Output Jitter* STS-12 -19.44 MHz Ref. Clk. -38.88 MHz Ref. Clk. -51.84 MHz Ref. Clk. -77.76 MHz Ref. Clk. STS-3 -19.44 MHz Ref. Clk. -38.88 MHz Ref. Clk. -51.84 MHz Ref. Clk. Reference Clock Frequency Tolerance* Reference Clock Input Duty Cycle Reference Clock Rise & Fall Times ECL Output Rise & Fall Times -20 Min Typ 622.08 12% Max Units MHz UI (rms) 0.007 0.006 0.005 0.004 0.002 0.001 0.001 +20 pp m rms jitter, in lock Condition
S3028
Required to meet SONET output frequency specification
30
70 2.0 450
% of UI ns ps 10% to 90% of amplitude 10% to 90%, 50 load, 5 pF cap
* Noise on REFCLKP/N should be less than 14 ps rms in a jitter frequency band from 12 KHz to 5 MHz for STS-12.
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S3028
SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER
Table 10. Absolute Maximum Ratings
Parameter Storage Temperature Voltage on VCC with respect to GND Voltage on Any TTL Input Pin Voltage on Any PECL Input Pin TTL Output Sink Current TTL Output Source Current High Speed PECL Output Source Current Min -65 -0.5 -0.5 0 Typ Max 150 +7.0 +5.5 VCC 8 8 50 Units C V V V mA mA mA
ESD Ratings The S3028 is rated to the following ESD voltages based on the human body model: 1. All pins are rated at or above 1000 V, except Pin 6, Pin 10, Pin 11, Pin 16, and Pin 21.
Table 11. Recommended Operating Conditions
Parameter Ambient Temperature Under Bias Junction Temperature Under Bias Voltage on VCC with respect to GND Voltage on Any TTL Input Pin Voltage on Any PECL Input Pin ICC Supply Current PD Power Dissipation Capacitive Load on Any TTL Pin Min -40 -40 4.75 0 VCC -2 180 0.900 Typ Max 85 +130 5.25 VCC VCC 260 1.37 15 Units C C V V V mA W pF Outputs open, VCC = VCC max Outputs open, VCC = VCC max Conditions See Note 1.
1. Applications above 70C ambient require one or more power/GND planes in the circuit board.
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SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER
Table 12. TTL Input/Output DC Characteristics
Parameter VOH VOL VIH VIL IIH IIL II IOS VIK Description Output High Voltage (TTL) Output Low Voltage (TTL) Input High Voltage (TTL) Input Low Voltage (TTL) Input High Current (TTL) Input Low Current (TTL) Input High Current at Max VCC Output Short Circuit Current Input Clamp Diode Voltage -100.0 -1.2 -500 2.0 0 Min 2.7 .5 5.5 0.8 50 -50 1.0 -25.0 Typ Max Units V V V V A A mA mA V VIN = 2.4V VIN = 0.5V
S3028
Conditions VCC = min, IOH = -1mA VCC = min, IOL = 4mA1 IH 1mA at VIH = 5.5V
VCC = max, VIN = 5.5V VCC = max, VOUT = 0.5V VCC = min, VIN = -18mA
1. 19MCK output: IOL = 2mA
Table 13. PECL Input/Output DC Characteristics
Parameter VIL Description PECL Input Low Voltage Mi n VCC -2.000 VCC -2.000 VCC -2.000 VCC -1.225 VCC -1.105 VCC -1.023 VCC -2.500 VCC -2.500 VCC -2.500 VCC -1.500 VCC -1.422 VCC -1.342 100 600 Typ Max VCC -1.504 VCC -1.475 VCC -1.441 VCC -0.778 VCC -0.680 VCC -0.573 VCC -1.647 VCC -1.620 VCC -1.573 VCC -0.828 VCC -0.730 VCC -0.623 1300 1600 Units V Conditions -40 C 25 C 85 C -40 C 25 C 85 C -40 C 25 C 85 C -40 C 25 C 85 C
VIH
PECL Input High Voltage
V
VOL
PECL Output Low Voltage for Differential PECL Outputs PECL Output High Voltage for Differential PECL Outputs Min. Differential Input Voltage Swing for Differential PECL Inputs Serial Output Voltage Swing for Differential PECL Outputs
V
VOH VDIFF VOUT
V
mV mV 50 to VCC -2.0V
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S3028
Table 14. AC Receiver Timing Characteristics
Symbol POCLK Duty Cycle tPPOUT tSPOUT tHPOUT tSRSD tHRSD Description
SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER
Min 45 -8 -8 -3 4 3 400 400
Max 55 0 0 1
Units % ns ns ns ns ns ps ps
POCLK Low to POUT[7:0] valid prop. delay at STS-3, 8-bit POCLK Low to POUT[7:0] valid prop. delay at STS-3, 4-bit POCLK Low to POUT[7:0] valid prop. delay at STS-12 POUT[7:0] and FP Setup Time w.r.t. POCLK1 POUT[7:0] and FP Hold Time w.r.t. POCLK1 RSDP/N Setup Time w.r.t. RSCLKP/N RSDP/N Hold Time w.r.t. RSCLKP/N
1. Set-up and hold times are specified for an interface which directly connects the S3028 receiver parallel outputs to the data and clock inputs on an external register.
Figure 7. Receiver Output Timing
Duty Cycle MAX
POCLK
tHPOUT tPPOUT MIN
50% tSPOUT 70% 30%
Duty Cycle MIN tHPOUT tPPOUT MIN
tPPOUT MAX
POUT[7:0], FP
Notes on TTL Output Timing: 1. Output propagation delay time of TTL outputs is the time in nanoseconds from the 50% point of the reference signal to the 30% or 70% point of the output. 2. Maximum output propagation delays and duty cycles of TTL outputs are measured with a 15 pF load. 3. When a set-up time is specified on TTL signals between an output and a clock, the set-up time is the time in nano seconds from the 50% point of the output to the 50% point of the clock. 4. When a hold time is specified on TTL signals between an output and a clock, the hold time is the time in nano seconds from the 50% point of the clock to the 50% point of the output.
Figure 8. Receiver Input Timing
RSCLKP tSRSD RSDP/N
Notes on High-Speed PECL Input Timing 1.Timing is measured from the cross-over point of the reference signal to the cross-over point of the input.
tHRSD
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December 13, 1999 / Revision H
SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER
Table 15. AC Transmitter Timing Characteristics
Symbol Description TSCLK Frequency (nom. 155.52 or 622.08 MHz) TSCLK Duty Cycle PICLK Duty Cycle tPPPI tSPIN tHPIN tPTSD tSTSD tHTSD PCLK to PICLK Propagation Delay PIN[7.0] Set-up Time w.r.t. PICLK PIN[7.0] Hold Time w.r.t. PICLK TSCLK Low to TSD Valid Propagation Delay TSD Set-up Time w.r.t. TSCLK TSD Hold Time w.r.t. TSCLK 300 300 1.5 1.0 440 40 33 Min Max 640 60 67 5.0
S3028
Units MHz % % ns ns ns ps ps ps
Figure 9. Transmitter Input Timing
PCLK tPPPI PICLK tSPIN PIN[7:0] tHPIN
Figure 10. Transmitter Output Timing
TSCLKP
tPTSD tSTSD tHTSD
TSD
1. When a set-up time is specified on TTL signals between an input and a clock, the set-up time is the time in nano seconds from the 50% point of the input to the 50% point of the clock. 2. When a hold time is specified on TTL signals between an input and a clock, the hold time is the time in nano seconds from the 50% point of the clock to the 50% point of the input.
Notes on High-Speed PECL Output Timing 1. Timing is measured from the cross-over point of the reference signal to the cross-over point of the output.
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S3028 RECEIVER FRAMING
Figure 11 shows a typical reframe sequence in which a byte realignment is made. The frame and byte boundary detection is enabled by the rising edge of OOF and remains enabled while OOF is High. Both boundaries are recognized upon receipt of the third A2 byte which is the first data byte to be reported with the correct byte alignment on the outgoing data bus (POUT[7:0]). Concurrently, the Frame Pulse (FP) is set High for one POCLK cycle. When interfacing with a section terminating device, the OOF input remains high for one full frame after the first frame pulse while the section terminating device verifies internally that the frame and byte alignment are correct, as shown in Figure 12. Since at least one framing pattern has been detected since the rising edge of OOF, boundary detection is disabled when OOF is set Low.
SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER
The frame and byte boundary detection block is activated by the rising edge of OOF, and stays active until the first FP or until OOF goes Low, whichever occurs last. Figure 12 shows a typical OOF timing pattern which occurs when the S3028 is connected to a down stream section terminating device. OOF remains high for one full frame after the first FP. The frame and byte boundary detection block is active until OOF goes Low. Figure 13 shows the frame and byte boundary detection activation by a rising edge of OOF, and deactivated by the first FP.
Figure 11. Frame and Byte Detection
RECOVERED CLOCK / REFCLK OOF RSD A1 A1 A1 A2 A2 A2 NOTE 1
POUT[7:0] INVALID DATA
A2 (28H) VALID DATA
POCLK
FP
NOTE 1: Range of input to output delay can be 1.5 to 2.5 POCLK cycles.
Figure 12. OOF Operation Timing with PM5312 STTX or PM5355 SUNI-622
BOUNDARY DETECTION ENABLED OOF FP
Figure 13. Alternate OOF Timing
BOUNDARY DETECTION ENABLED OOF
FP
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December 13, 1999 / Revision H
S3028 WITH DATA CLOCK SYNCHRONOUS TO REFERENCE CLOCK SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER INTRODUCTION
In some applications it is necessary to "forward clock" the data in a SONET/SDH system. In this application the reference clock from which the high speed serial clock is synthesized and the parallel data clock both originate from the same (usually TTL/CMOS) clock source. This application note explains how the AMCC S3028 can be configured to operate in this mode. Clock Control Logic Description The timing control logic in the S3028 automatically generates an internal load signal which has a fixed relationship to the reference clock. The logic takes into account the variation of the reference clock to the internal load signal over temperature and voltage.
S3028
The connections required to implement the design are shown in Figure 14, and the timing specifications are shown in Figure 15. The setup and hold times for the reference clock to the data must be met by the controller ASIC. It is recommended to latch the data on the falling edge of the reference clock in order to meet the required specifications. Possible Problems In order to meet the jitter generation specifications required by SONET, the jitter of the reference clock must be minimized. It may be difficult to meet the SONET jitter generation specifications using a reference clock input with a TTL reference source.
Figure 14. S3028 with Data Clocked by Reference Clock
TTL/PECL Converter tpd < 3.5 ns PECL 2 REFCLK PICLK
ASIC
8 Data
S3028
PIN[7:0]
Serial Data
Figure 15. Data Timing with Respect to Reference Clock
PICLK PIN [7:0] tsu = 1.5 ns tH = 1 ns
tsu
tH
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S3028
Ordering Information
PREFIX DEVICE
SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER
PACKAGE/FEATURES B - 64 PQFP, Loop Timing, Forward Clocking, "Squelched Clock" Operation
SPEED GRADE
S - Integrated Circuit
3028
Blank - 155/622 Mbps 1 - 155 Mbps only
X
Prefix
XXXX
Device
X
Package/Features
-
X
Speed/Grade
IS
O 90 0
RT
IFI
Applied Micro Circuits Corporation * 6290 Sequence Dr., San Diego, CA 92121 Phone: (858) 450-9333 * (800) 755-2622 * Fax: (858) 450-9885 http://www.amcc.com
AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered trademark of Applied Micro Circuits Corporation. Copyright (R) 1999 Applied Micro Circuits Corporation
E
D
1
CE
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December 13, 1999 / Revision H

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