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IDTQS3ST253 HIGH-SPEED CMOS SYNCHROSWITCH DUAL 4:1 MUX/DEMUX
INDUSTRIAL TEMPERATURE RANGE
QUICKSWITCH(R) PRODUCTS HIGH-SPEED CMOS SYNCHROSWITCHTM DUAL 4:1 MUX/DEMUX WITH ACTIVE TERMINATORS
FEATURES:
* * * * * * * * * * * *
IDTQS3ST253
DESCRIPTION:
Enhanced N channel FET with no inherent diode to Vcc Bidirectional signal flow Flow-through pinout Zero propagation delay, zero ground bounce 2 banks of 4:1 Mux/Demux Port select synchronous to the clock Undershoot clamp diodes on all switch and control inputs Clock enable and Asynchronous enable "Bus-hold" terminators on the Demux side Asynchronous SEL option Break-before-make feature Bus-hold eliminates floating bus lines and reduces static power consumption * Available in QSOP package
The QS3ST253 is a high-speed CMOS dual 4:1 multiplexer/demultiplexer with active terminators (bus-hold circuits) on the demux side. Port selection and connection, controlled by SEL signals, can be either asynchronous or synchronous. In the synchronous mode, the A, B, C, or D port to Y port connection is updated on the rising edge of the input clock CLK. Once the port-to-port connection is made, data flow can be bi-directional with a typical 250ps propagation delay through the switch. Clock Enable, overriding Asynchronous Enable, and Asynchronous Select controls provide additional design flexibility. The bus-hold circuits latch the last data driven on the demux side, providing infinite hold time and glitch-free signal transitions. Synchronous controls and bus-hold ease timing constraints in many high speed data mux/ demux applications, such as bank interleaving. The QS3ST253 can be used in 5V to 3.3V translation.
APPLICATIONS:
* Video, audio, graphics switching, muxing
FUNCTIONAL BLOCK DIAGRAM
T =
OE0 OE1 SEL0 SEL1 CLKn CLKENn SYNCn A0 T Bank 0 Y0 T T T T Bank 1 Y1 T T T
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
CONTROL LOGIC
B0 C0 D0 A1 B1 C1 D1
INDUSTRIAL TEMPERATURE RANGE
1
c 1999 Integrated Device Technology, Inc.
NOVEMBER 1999
DSC-5533/1
IDTQS3ST253 HIGH-SPEED CMOS SYNCHROSWITCH DUAL 4:1 MUX/DEMUX
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM(2) VTERM(3) Description Supply Voltage to Ground DC Switch Voltage Vs DC Input Voltage VIN AC Input Voltage (pulse width 20ns) DC Output Current Maximum Power Dissipation (TA = 85C) Storage Temperature Max -0.5 to +7 -0.5 to +7 -0.5 to +7 -3 120 0.82 -65 to +150 Unit V V V V mA W C
NC A0 A1 B0 B1 C0 C1 D0 D1 GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
Vcc OE0 OE1 SEL0 SEL1 Y0 Y1 CLKEN CLK SYNC
VTERM(3) VAC IOUT PMAX TSTG
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Vcc terminals. 3. All terminals except Vcc.
CAPACITANCE (TA = +25C, f = 1MHz, VIN = 0V, VOUT = 0V)
Pins Typ. 4 Demux Mux 5 13 Max. (1) 5 7 14 Unit pF pF
QSOP TOP VIEW
Control Inputs Quickswitch Channels (Switch OFF)
NOTE: 1. This parameter is guaranteed but not production tested.
PIN DESCRIPTION
Pin Names A0 - D0 A1 - D1 Y0, Y1 SEL0, SEL1 CLK CLKEN OE0, OE1 SYNC I/O I/O I/O I/O I I I I I Description Bank 0 Demux Ports Bank 1 Demux Ports Mux Port Select Inputs Clock Clock Enable Output Enable Synchronous Enable
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IDTQS3ST253 HIGH-SPEED CMOS SYNCHROSWITCH DUAL 4:1 MUX/DEMUX
INDUSTRIAL TEMPERATURE RANGE
FUNCTION TABLE(1)
Control Inputs SYNC L L L L L L L H H H H H OE0 L L L L H L H L L L L H OE 1 L L L L H L H L L L L H CLK X X X X X CLKEN L L L L L H H X X X X X SEL0 L H L H X X X L H L H X SEL1 L L H H X X X L L H H X Y0 A0 B0 C0 D0 Hold Previous Data (2) (Switch OFF) Hold Previous Mux connection (3) (Switch ON) Hold Previous Data (4) (Switch OFF) A0 B0 C0 D0 Hold Previous Data (2) (Switch OFF) Port Status Y1 A1 B1 C1 D1 Hold Previous Data (2) (Switch OFF) Hold Previous Mux connection (3) (Switch ON) Hold Previous Data (4) (Switch OFF) A1 B1 C1 D1 Hold Previous Data (2) (Switch OFF)
NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-Impedence = LOW-to-HIGH Transition 2. Mux switches are turned off and the terminators (last value latches) hold the previous data state. The port connections can be changed by the SEL input. 3. The contents of the "Mux select register" are unchanged and the previous Mux connection is unchanged. The output (Mux port) data state will depend on the present data state of the input (Demux port). 4. The contents of the "Mux select register" are unchanged and the last value latch holds the previous data state.
CONTROL LOGIC
OE0
2:1 MUX SEL0
D
Q 2:1 MUX To Bank 0 Switches
CLKEN CLK SYNC
DECODE LOGIC AND SWITCH CONTROL 2:1 MUX 2:1 MUX D Q
SEL1
To Bank 1 Switches
OE1
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IDTQS3ST253 HIGH-SPEED CMOS SYNCHROSWITCH DUAL 4:1 MUX/DEMUX
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial: TA = -40C to +85C, VCC = 5.0V 10%
Symbol VIH VIL IIN IOZ RON IBHL IBHH IBH Parameter Input HIGH Level Input LOW Level Input Leakage Current (Control Inputs) Off-State Current (Hi-Z) Switch ON Resistance(2) Input Hold Current (3,4) (A, B, C, D) Input Current (5) (A, B, C, D) Test Conditions Guaranteed Logic HIGH for Control Pins Guaranteed Logic LOW for Control Pins 0V VIN VCC 0V Y VCC VCC = Min., VIN = 0V, ION = 30mA VCC = Min., VIN = 2.4V, ION =15mA Vcc = Min. Switch OFF Vcc = Max. VIN = 0.8V VIN = 2V VIN = 0V or Vcc 0.8 < VIN < 2V Min. 2 -- -- -- -- -- 60 Typ.(1) -- -- 0.01 --0.01 7 10 -- -- -- -- Max. -- 0.8 1 1 9 13 -- -- 50 500 A A Unit V V A A
- 60
-- --
NOTES: 1. Typical values are at VCC = 5.0V, TA = 25C. 2. Measured by voltage drop between A/B/C/D and Y pin at indicated current through the switch. 3. IBHL is the minimum sustaining "sink" current at the input for VIN = 0.8V. This parameter signifies the latching capability of the bus-hold circuit in logic LOW state. 4. IBHH is the minimum sustaining "source" current at the input for VIN = 2V. This parameter signifies the latching capability of the bus-hold circuit in logic HIGH state. 5. IBH is the magnitude of the input current specified under two conditions: a) Input voltage at GND or Vcc. This indicates the input current under steady-state condition. b) Input voltage between 0.8V and 2V (TTL input threshold range). This indicates the maximum input current during transient condition. The driver connected to the input must overcome this current requirement in order to switch the logic state of the bus-hold circuit.
TYPICAL ON RESISTANCE vs VIN AT VCC = 5V
16
RON
(ohms)
14 12 10 8 6 4 2 0 0.0 0.5 1.0 1.5
VIN
(Volts)
2.0
2.5
3.0
3.5
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IDTQS3ST253 HIGH-SPEED CMOS SYNCHROSWITCH DUAL 4:1 MUX/DEMUX
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol ICCQ ICC ICCD Parameter Quiescent Power Supply Current Power Supply Current per Control Input HIGH (2) Dynamic Power Supply Current per MHz(3) Test Conditions(1) VCC = Max., VIN = GND or Vcc, f = 0 VCC = Max., VIN = 3.4V, f = 0 VCC = Max., A/B/C/D and Y pins open Control Inputs Toggling at 50% Duty Cycle
NOTES: 1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics. 2. Per TLL driven input (VIN = 3.4V, control inputs only). A/B/C/D and Y pins do not contribute to Icc. 3. This current applies to the control inputs only and represents the current required to switch internal capacitance at the specified frequency. The A/B/C/D and Y inputs generate no significant AC or DC currents as they transition. This parameter is guaranteed but not production tested.
Max. 3 1.5 0.25
Unit A mA mA/MHz
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
TA = -40C to +85C, VCC = 5.0V 10%; CLOAD = 50pF, RLOAD = 500 unless otherwise noted.
Symbol tPLH tPHL tSEC tHEC tCSO tASO tW tSCS tHCS tPZL tPZH tPLZ tPHZ Parameter Data Propagation Delays (1,2) A/B/C/D to Y, Y to A/B/C/D Clock Enable to Clock Setup Time Clock Enable to Clock Hold Time Clock to Switch Turn-On Delay (3) Asynchronous Select to Switch Turn-On Delay (3) Clock Pulse Width HIGH SEL to Clock Setup Time SEL to Clock Hold Time Asynchronous Enable to Switch Turn-On Delay (3) Asynchronous Enable to Switch Turn-Off Delay (1,3) Min. (1) -- 3 0 0.5 0.5 3 3 0 1.5 1.5 Typ. 0.25 -- -- -- -- -- -- -- -- -- Max. -- -- -- 7 7 -- -- -- 5.2 4.8 Unit
ns ns ns ns ns ns ns ns ns ns
NOTES: 1. This parameter is guaranteed but not tested. 2. The bus switch contributes no propagation delay other than the RC delay of the ON resistance of the switch and the load capacitance. The time constraint for the switch alone is of the order of 0.25ns for CL = 50pF. Since this time constant is much smaller than the rise and fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay of the bus switch, when used in a system, is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side. 3. Minimums guaranteed but not tested.
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IDTQS3ST253 HIGH-SPEED CMOS SYNCHROSWITCH DUAL 4:1 MUX/DEMUX
INDUSTRIAL TEMPERATURE RANGE
TIMING WAVEFORMS - SYNCHRONOUS MODE, DEMUX FUNCTION
SYNC tSEC tHEC CLKEN
CLK tSCS tHCS SEL0, SEL1 tSCS tHCS
OE0, OE1
Port Y
DATA 0
DATA 1 tPLH, tPHL
DATA 2
tCSO Port A INVALID DATA DATA 0 DATA 1 HOLD PREVIOUS DATA, DATA 1 tPLH, tPHL tCSO Port D INVALID DATA DATA 1 DATA 2 HOLD PREVIOUS DATA, DATA 2
Example: Port A to Port D / Port Y
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IDTQS3ST253 HIGH-SPEED CMOS SYNCHROSWITCH DUAL 4:1 MUX/DEMUX
INDUSTRIAL TEMPERATURE RANGE
TIMING WAVEFORMS - SYNCHRONOUS MODE, MUX FUNCTION
SYNC tSEC tHEC CLKEN
CLK tSCS tHCS SEL0 tSCS tHCS
Port A
DATA1
DATA2
Port B tCSO tPLH, tPHL Port Y INVALID DATA
DATA1
DATA3
DATA4
tCSO
tPLH, tPHL DATA3 DATA4
DATA2
Example: Port A / Port D to Port Y
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IDTQS3ST253 HIGH-SPEED CMOS SYNCHROSWITCH DUAL 4:1 MUX/DEMUX
INDUSTRIAL TEMPERATURE RANGE
TIMING WAVEFORMS - ASYNCHRONOUS MODE, MUX FUNCTION
SYNC
SEL0, SEL1
OE0, OE1
Port A
INVALID DATA
DATA1 tPLH, tPHL
DATA2 tPLH, tPHL
Port D
INVALID DATA
DATA3 tASO tPLZ, tPHZ DATA3 tPZL, tPZH DATA3
Port Y
INVALID DATA
DATA1
DATA2
Example: Port A / Port D to Port Y
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IDTQS3ST253 HIGH-SPEED CMOS SYNCHROSWITCH DUAL 4:1 MUX/DEMUX
INDUSTRIAL TEMPERATURE RANGE
ACTIVE TERMINATOR OR "BUS-HOLD" CIRCUIT
The Active Terminator circuit, also known as the bus-hold circuit, is configured as a "weak latch" with positive feedback. When connected to a TTL or CMOS input port, the bus-hold circuit holds the last logic state at the input when the input is "disconnected" from the driver. When the output of a device connected to such an input attempts a logic level transition, it will overdrive the bus-hold circuit. The primary benefit of a bus-hold circuit is that it prevents CMOS inputs from floating, a situation which should be avoided to prevent spurious switching of inputs and unnecessary power dissipation. Bus-hold is a better solution than the traditional approach of using resistive termination to Vcc or GND to prevent bus floating, because the bus-hold circuit does not consume any static power.
V-I CHARACTERISTICS OF BUS-HOLD CIRCUIT
IBH
+500
Sinking Current (+)
IBHL IBH IBHH Sourcing Current (-)
+60 +20 - 20 - 60
+60 IBHL
VT
Voltage +20 IBH - 20 IBH - 60 IBHL Vcc
VIL
VIH
IBH
- 500
0.8V
2V
VT Threshold Voltage 1.5V VIL .8 VIH 2V
This figure shows the input V-I characteristics of a typical bus-hold implementation. The input characteristics resemble a resistor. As the input voltage is increased from 0 volts, the input "sink" current increases linearly. When the TTL threshold of the circuit is reached (typically 1.5 volts), the latch changes the logic state due to positive feedback and the direction of the current is reversed. As the input voltage is further increased towards Vcc, the input "source" current begins to decrease, reaching the lowest level at VIN = Vcc.
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IDTQS3ST253 HIGH-SPEED CMOS SYNCHROSWITCH DUAL 4:1 MUX/DEMUX
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDTQS XXXXX Device Type XX Package X Process
Blank
Industrial (-40C to +85C)
Q
Quarter Size Small Outline Package
3ST253
High Speed CMOS SynchroSwitch Dual 4:1 Mux/Demux with Active Terminators
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