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GM71V17800C GM71VS17800CL
2,097,152 WORDS x 8 BIT CMOS DYNAMIC RAM
Description
The GM71V(S)17800C/CL is the new generation dynamic RAM organized 2,097,152 x 8 bit. GM71V(S)17800C/CL has realized higher density, higher performance and various functions by utilizing advanced CMOS process technology. The GM71V(S)17800C/CL offers Fast Page Mode as a high speed access mode. Multiplexed address inputs permit the GM71V(S)17800C/CL to be packaged in standard 400 mil 28pin plastic SOJ, and standard 400mil 28pin plastic TSOP II. The package size provides high system bit densities and is compatible with widely available automated testing and insertion equipment.
Features
* 2,097,152 Words x 8 Bit Organization * Fast Page Mode Capability * Single Power Supply (3.3V+/-0.3V) * Fast Access Time & Cycle Time
(Unit: ns)
tRAC tCAC
GM71V(S)17800C/CL-5 GM71V(S)17800C/CL-6 GM71V(S)17800C/CL-7 50 60 70 13 15 18
tRC
90 110 130
tPC
35 40 45
Pin Configuration 28 SOJ
VCC I/O0 I/O1 I/O2 I/O3 WE RAS NC A10
1 2 3 4 5 6 7 8 9 28 VSS 27 I/O7 26 I/O6 25 I/O5 24 I/O4 23 CAS 22 OE 21 A9 20 A8 19 A7 18 A6 17 A5 16 A4 15 VSS
* Low Power Active : 468/432/396mW (MAX) Standby : 7.2mW (CMOS level : MAX) 0.54mW (L- version : MAX) * RAS Only Refresh, CAS before RAS Refresh, Hidden Refresh Capability * All inputs and outputs TTL Compatible * 2048 Refresh Cycles/32ms * 2048 Refresh Cycles/128ms (L-version) * Self Refresh Operation (L-version) * Battery Back Up Operation (L- version)
VCC I/O0 I/O1 I/O2 I/O3 WE RAS NC
1 2 3 4 5 6 7 8
28 VSS 27 I/O7 26 I/O6 25 I/O5 24 I/O4 23 CAS 22 OE 21 A9 20 A8 19 A7 18 A6 17 A5 16 A4 15 VSS
A10 9 A0 10 A1 11 A2 12 A3 13 VCC 14
A0 10 A1 11
om .c 4u et he as at .d w w w
A2 12 A3 13 VCC 14
(Top View)
Rev 0.1 / Apr'01
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28 TSOP II
GM71V17800C GM71VS17800CL
Pin Description
Pin
A0-A10 A0-A10 I/O0-I/O7 RAS CAS
Function
Address Inputs Refresh Address Inputs Data Input / Data Output Row Address Strobe Column Address Strobe
Pin
WE OE VCC VSS NC
Function
Read/Write Enable Output Enable Power (+3.3V) Ground No Connection
Ordering Information
Type No.
GM71V(S)17800CJ/CLJ-5 GM71V(S)17800CJ/CLJ-6 GM71V(S)17800CJ/CLJ-7 GM71V(S)17800CT/CLT-5 GM71V(S)17800CT/CLT-6 GM71V(S)17800CT/CLT-7
Access Time
50ns 60ns 70ns 50ns 60ns 70ns
Package
400 Mil 28 Pin Plastic SOJ 400 Mil 28 Pin Plastic TSOP II
Absolute Maximum Ratings
Symbol TA TSTG VIN/OUT VCC IOUT PD Parameter
Ambient Temperature under Bias Storage Temperature (Plastic) Voltage on any Pin Relative to VSS Supply Voltage Relative to VSS Short Circuit Output Current Power Dissipation
Rating
0 ~ +70 -55 ~ +125 -0.5 ~ +4.6 -0.5 ~ +4.6 50 1.0
Unit
C C V V mA W
Recommended DC Operating Conditions (TA = 0 ~ +70C)
Symbol VCC VIH VIL Parameter
Supply Voltage Input High Voltage Input Low Voltage
Min
3.0 2.0 -0.3
Typ
3.3 -
Max
3.6 Vcc+0.3 0.8
Unit
V V V
Note: All voltage referred to Vss.
Rev 0.1 / Apr'01
GM71V17800C GM71VS17800CL
DC Electrical Characteristics (VCC = 3.3V+/-0.3, Vss = 0V, TA = 0 ~ 70C)
Symbol VOH VOL ICC1 Parameter
Output Level Output "H" Level Voltage (IOUT = -2mA) Output Level Output "L" Level Voltage (IOUT = 2mA) Operating Current Average Power Supply Operating Current (RAS, CAS Cycling: tRC = tRC min) Standby Current (TTL) Power Supply Standby Current (RAS, CAS = VIH, DOUT = High-Z) RAS Only Refresh Current Average Power Supply Current RAS Only Refresh Mode (tRC = tRC min) Fast Page Mode Current Average Power Supply Current Fast Page Mode (tPC = tPC min) Standby Current (CMOS) Power Supply Standby Current (RAS, CAS >= VCC - 0.2V, DOUT = High-Z) CAS-before-RAS Refresh Current (tRC = tRC min) 50ns 60ns 70ns 50ns 60ns 70ns 50ns 60ns 70ns 50ns 60ns 70ns
Min
2.4 0 -
Max
VCC 0.4 110 100 90 2 110 100 90 100 90 85 1 150 110 100 90 400
Unit
V V
Note
mA
1, 2
ICC2
mA
ICC3
mA
2
ICC4
mA
1, 3
ICC5
mA uA 5
ICC6
mA
ICC7 ICC8
Battery Back Up Operating Current (Standby with CBR Refresh) (tRC=62.5us, tRAS<=0.3us, DOUT=High-Z) Standby Current RAS = VIH CAS = VIL DOUT = Enable Self-Refresh Mode Current (RAS, CAS<=0.2V, DOUT=High-Z) Input Leakage Current Any Input (0V<=VIN<= 4.6V) Output Leakage Current (DOUT is Disabled, 0V<=VOUT<= 4.6V) ICC(max) is specified at the output open condition.
uA
4,5
-10 -10
5 250 10 10
mA uA uA uA
1 5
ICC9 IL(I) IL(O)
Note: 1. ICC depends on output load condition when the device is selected. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 4. CAS = L (<=0.2V) while RAS = L (<=0.2V). 5. L-version.
Rev 0.1 / Apr'01
GM71V17800C GM71VS17800CL
Capacitance (VCC = 3.3V+/-0.3V, TA = 25C)
Symbol CI1 CI2 CI/O Parameter
Input Capacitance (Address) Input Capacitance (Clocks) Output Capacitance (Data-In/Out)
Min
-
Max
5 7 7
Unit
pF pF pF
Note
1 1 1, 2
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable DOUT.
AC Characteristics (VCC = 3.3V+/-0.3V, TA = 0 ~ +70C, Vss = 0V, Note 1, 2,18)
Test Conditions
Input rise and fall times : 5 ns Input timing reference levels : 0.8V, 2.0V Output timing reference levels : 0.8V, 2.0V Output load : 1TTL gate + CL (100 pF) (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)
Symbol Parameter
Random Read or Write Cycle Time RAS Precharge Time CAS Precharge Time RAS Pulse Width CAS Pulse Width Row Address Set up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time RAS to CAS Delay Time RAS to Column Address Delay Time RAS Hold Time CAS Hold Time CAS to RAS Precharge Time OE to DIN Delay Time OE Delay Time from DIN CAS Delay Time from DIN Transition Time (Rise and Fall)
GM71V(S)17800 GM71V(S)17800 GM71V(S)17800 C/CL-6 C/CL-7 C/CL-5
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note
Min Max Min Max Min Max
tRC tRP tCP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tODD tDZO tDZC tT
90 30 8
-
110 40 10
-
130 50 13
-
50 10,000 13 10,000 0 8 0 8 18 13 13 50 5 13 0 0 3 45 30 50
60 10,000 15 10,000 0 10 0 10 20 15 15 60 5 15 0 0 3 45 30 50
70 10,000 18 10,000 0 10 0 15 20 15 18 70 5 18 0 0 3 52 35 50
3 4
5 6 6 7
Rev 0.1 / Apr'01
GM71V17800C GM71VS17800CL
Read Cycle
Symbol Parameter
Access Time from RAS Access Time from CAS Access Time from Address Access Time from OE Read Command Setup Time Read Command Hold Time to CAS Read Command Hold Time to RAS Column Address to RAS Lead Time Column Address to CAS Lead Time CAS to Output in Low-Z Output Data Hold Time Output Data Hold Time from OE Output Buffer Turn-off Time Output Buffer Turn-off Time to OE CAS to DIN Delay Time
GM71V(S)17800 GM71V(S)17800 GM71V(S)17800 C/CL-5 C/CL-6 C/CL-7
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note
8,9
9,10,17 9,11,17
Min Max
Min Max Min Max 0 0 5 30 30 0 3 3 15 60 15 30 15 15 15 0 0 5 35 35 0 3 3 18 70 18 35 18 15 15 -
tRAC tCAC tAA tOAC tRCS tRCH tRRH tRAL tCAL tCLZ tOH tOHO tOFF tOEZ tCDD
0 0 5 25 25 0 3 3 13
50 13 25 13 13 13 -
9
12 12
13 13 5
Write Cycle
Symbol Parameter
Write Command Setup Time Write Command Hold Time Write Command Pulse Width Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Setup Time Data-in Hold Time
GM71V(S)17800 GM71V(S)17800 GM71V(S)17800 C/CL-5 C/CL-6 C/CL-7
Unit
ns ns ns ns ns ns ns
Note
14
Min Max Min Max Min Max
tWCS tWCH
0 8 8 13 13 0 8
-
0 10 10 15 15 0 10
-
0 15 10 18 18 0 15
-
tWP
tRWL tCWL tDS tD
H
15 15
Rev 0.1 / Apr'01
GM71V17800C GM71VS17800CL
Read- Modify-Write Cycle
Symbol Parameter
Read-Modify-Write Cycle Time RAS to WE Delay Time CAS to WE Delay Time Column Address to WE Delay Time OE Hold Time from WE
GM71V(S)17800 GM71V(S)17800 GM71V(S)17800 C/CL-5 C/CL-6 C/CL-7
Unit
ns ns ns ns ns
Note
Min Max Min Max Min Max
tRWC tRWD tCWD tAWD tOEH
131 73 36 48 13
-
155 85 40 55 15
-
181 98 46 63 18
-
14 14 14
Refresh Cycle
Symbol Parameter
CAS Setup Time (CAS-before-RAS Refresh Cycle) CAS Hold Time (CAS-before-RAS Refresh Cycle) WE Setup Time (CAS-before-RAS Refresh Cycle) WE Hold Time (CAS-before-RAS Refresh Cycle) RAS Precharge to CAS Hold Time
GM71V(S)17800 GM71V(S)17800 GM71V(S)17800 C/CL-5 C/CL-6 C/CL-7
Unit
Note
Min Max Min Max Min Max
tCSR tCHR tWRP tWRH tRPC
5 8 0 10 5
-
5 10 0 10 5
-
5 10 0 10 5
-
ns ns ns ns ns
Fast Page Mode Cycle
Symbol Parameter
Fast Page Mode Cycle Time Fast Page Mode RAS Pulse Width Access Time from CAS Precharge RAS Hold Time from CAS Precharge
GM71V(S)17800 GM71V(S)17800 GM71V(S)17800 C/CL-5 C/CL-6 C/CL-7
Unit
ns ns ns ns
Note
Min Max Min Max Min Max
tPC tRASP tACP tRHCP
35 30
100,000
40 35
100,000
45 40
100,000
16 9,17
30 -
35 -
40 -
Rev 0.1 / Apr'01
GM71V17800C GM71VS17800CL
Fast Page Mode Read-Modify-Write Cycle
Symbol Parameter
Fast Page Mode Read-Modify-Write Cycle Time WE Delay Time from CAS Precharge
GM71V(S)17800 GM71V(S)17800 GM71V(S)17800 C/CL-5 C/CL-6 C/CL-7
Unit
ns ns
Note
Min Max Min Max Min Max
tPRWC tCPW
76 53
-
85 60
-
96 68
-
14
Refresh
Symbol Parameter
Refresh Period Refresh Period(L-series)
GM71V(S)17800 GM71V(S)17800 GM71V(S)17800 C/CL-5 C/CL-6 C/CL-7
Unit
Note
2048 cycles 2048 cycles
Min Max Min Max Min Max
tREF tREF
-
32 128
-
32 128
-
32 128
ms ms
Self Refresh Mode(L-version)
Symbol Parameter
RAS Pulse Width(Self-Refresh) RAS Precharge Time(Self-Refresh) CAS Hold Time(Self-Refresh)
GM71VS17800 CL-5 GM71VS17800 CL-6 GM71VS17800 CL-7
Unit
us ns ns
Note
Min Max
Min Max Min Max 100 110 -50 100 130 -50 -
tRASS tRPS tCHS
100 90 -50
-
Rev 0.1 / Apr'01
GM71V17800C GM71VS17800CL
Notes: 1. AC Measurements assume tT = 5ns 2. An initial pause of 200uA is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS-beforeRAS refresh). if the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are required. 3. Operation with the tRCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a reference point only; if tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 4. Operation with the tRAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a reference point only; if tRAD is greater than the specified tRAD(max) limit, then access time is controlled exclusively by tAA. 5. Either tODD or tCDD must be satisfied. 6. Either tDZO or tDZC must be satisfied. 7. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH(min) and VIL(max). 8. Assumes that tRCD <= tRCD(max) and tRAD <= tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1TTL loads and 100pF.(VOH =2.0V , V= 0.8V) 10. Assumes that tRCD >= tRCD(max) and tRAD <= tRAD(max). 11. Assumes that tRCD <= tRCD(max) and tRAD >= tRAD(max). 12. Either tRCH or tRRH must be satisfied for a read cycles. 13. tOFF(max) and tOEZ(max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. tWCS, tRWD, tCWD and tAWD and tCPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if tWCS >=tWCS(min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD>=tRWD(min), tCWD>=tCWD(min), and tAWD>=tAWD(min) or tCWD>=tCWD(min), tAWD>=tAWD(min), and tCPW>=tCPW(min), the cycle is a read -modify- write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. These parameters are referred to CAS leading edge in early write cycle and to WE leading edge in a delayed write or a read modify write cycle. 16. tRASP defines RAS pulse width in fast page mode cycles. 17. Access time is determined by the longer of tAA or tCAC or tACP. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. After RAS is reset, if tOEH>=tCWL, the I/O pin will remain open circuit (high impedance): if tOEH<=tCWL, invalid data will be out at each I/O.
Rev 0.1 / Apr'01
GM71V17800C GM71VS17800CL
Package Dimensions
28 SOJ
0.025(0.64) MIN 0.445(11.30) MAX 0.405(10.29) MAX 0.395(10.03) MIN 0.435(11.06) MIN 0.375(9.55) MAX MIN 0.366(9.30) MIN
0 ~ 5
Unit: Inches (mm)
0.710(18.04) MIN 0.720(18.30) MAX
0.083(2.10)
0.128(3.25) MIN 0.148(3.75) MAX 0.050(1.27) TYP 0.015(0.38) MIN 0.020(0.50) MAX 0.026(0.66) MIN 0.032(0.81) MAX
28 TSOP (TYPE II)
0.016(0.40) MIN 0.024(0.60) MAX
0.405(10.29) MAX
0.720(18.28) MIN 0.730(18.54) MAX 0.037(0.95) MIN 0.041(1.05) MAX 0.047(1.20) MAX 0.012(0.30) MIN 0.020(0.50) MAX 0.050(1.27) TYP 0.003(0.08) MIN 0.007(0.18) MAX
0.455(11.56) MIN
0.471(11.96) MAX
0.394(10.03) MIN
0.004(0.12) MIN 0.008(0.21) MAX
Rev 0.1 / Apr'01

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