 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| CALIFORNIA MICRO DEVICES PACVGA105 VGA Port Companion Circuit Features * 7 channels of ESD protection designed to meet IEC-1000-4-2 Level-4 ESD requirements (8KV contact discharge) * Very low loading capacitance from ESD protection diodes, < 5pF typical * TTL to CMOS level-translating buffers for the HSYNC and VSYNC lines * Three independent supply pins (V CC, V RGB and VAUX) to facilitate operation with sub-micron Graphics Controller ICs * High impedance pull-ups (50K nominal to VAUX) for HSYNC & VSYNC inputs * Pull-up resistors (1.8K nominal to VCC) for DDC_CLK and DDC_DATA lines * Compact 16-pin QSOP package Pin Diagram Top View HSYNC_OUT HSYNC GNDD VRGB B G R GNDA 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC VSYNC_OUT VSYNC VAUX DDC_CLK GNDD DCC_DATA VCC PACVGA105 16-Lead QSOP PACKAGE Product Description The PACVGA105 incorporates 7 channels of ESD protection for signal lines commonly found in a VGA port for PCs. ESD protection is implemented with current steering diodes designed to safely handle the high peak surge currents associated with the IEC-1000-4-2 Level-4 ESD Protection Standard (8KV contact discharge). When the channels are subjected to an electrostatic discharge, the ESD current pulse is diverted via the protection diodes into the positive supply rails or ground where they may be safely dissipated. The upper ESD diodes for the R, G & B channels are connected to a separate supply rail (VRGB) to facilitate interfacing to graphics controller ICs with low voltage supplies. The remaining channels are connected to the main 5V rail (VCC). The lower diodes for the R, G & B channels are also connected to a dedicated ground pin (GNDA) to minimize crosstalk due to common ground impedance. Two non-inverting buffers are also included in this IC for buffering the HSYNC and VSYNC signals from the graphics controller IC. These buffers will accept TTL input levels and convert them to CMOS output levels that swing between GND and VCC. These drivers have a nominal 60 output impedance to match the characteristic impedance of the HSYNC and VSYNC lines of the video cables typically used. The inputs of these drivers also have high impedance pull-ups (50K nom.) pulling up to the VAUX rail. In addition, the DDC_CLOCK and DDC_DATA channels have 1.8K pull-up resistors pulling these inputs up to the main 5V (VCC) rail. Schematic Diagram VRGB VCC VAUX R 1.8K DDC_CLK GNDA GNDD 1.8K 50K 50K VSYNC_OUT G B DDC_DATA HSYNC VSYNC HSYNC_OUT (c) 2001 California Micro Devices Corp. All rights reserved. C1780401 215 Topaz Street, Milpitas, California 95035 4/25/2001 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 1 CALIFORNIA MICRO DEVICES Absolute Maximum Ratings Parameter VCC Supply Voltage VRGB Supply Voltage VAUX Supply Voltage Diode Forward Current (only one diode conducting at a time) DC Voltage at Inputs R, G, B HSYNC, VSYNC DDC_CLK, DDC_DATA Storage Temperature Operating Ambient Temperature Package Power Dissipation Rating GND-0.5, 6.0 GND-0.5, 6.0 GND-0.5, 6.0 20 GND -0.5, VRGB +0.5 GND -0.5, VAUX +0.5 GND -0.5, VCC +0.5 -40 to 150 0 to 70 0.75 Unit V V V mA V V V C C W PACVGA105 Recommended Operating Conditions Symbol VCC VRGB VAUX VIH VIL VI Parameter Main Supply Voltage RGB Supply Voltage Auxiliary Supply Voltage Logic High Input Voltage (Note 1) Logic Low Input Voltage (Note 1) Input Voltage RGB HSYNC, VSYNC DDC_CLK, DDC_DATA IOH IOL TA Note 1: MIN 4.5 1.7 2.9 2.0 MAX 5.5 3.7 3.7 0.8 UNIT V V V V V V V V mA mA C 0 0 0 VRGB VAUX VCC -8 8 High Level Output Current (Note 1) Low Level Output Current (Note 1) Operating Free-Air Temperature These parameters apply only to the HSYNC and VSYNC signals. 0 70 (c)2001 California Micro Devices Corp. All rights reserved. 2 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 4/25/2001 CALIFORNIA MICRO DEVICES Electrical Characteristics at T A = 25C Symbol VF VOH VOL IIN Parameter Diode Forward Voltage Logic High Output Voltage Logic Low Output Voltage Input Current IF = 10mA IOH = -4mA, VCC = 4.5V IOL = 4mA, VCC = 4.5V R, G, B pins; VRGB = 3.63V; VIN = VRGB or GND HSYNC, VSYNC pins; VAUX = 3.63V; VIN = VAUX HSYNC, VSYNC pins; VAUX = 3.63V; VIN = GND ICC IRGB CIN VCC Supply Current VRGB Supply Current Input Capacitance VCC = 5.5V; VAUX = VRGB = 2.97V; All inputs and outputs floating R, G, B pins at VCC or GND; All other input and output floating R,G, B (Note 1) HSYNC, VSYNC (Note 1) DDC_DATA, DDC_CLK (Note 1) RPU VESD tPLH tPHL tR, tF Note 1: Note 2: PACVGA105 Conditions MIN 4.0 0.4 1 1 -30 -72.5 35 -95 100 10 5 10 5 1.62 8 7 7 7 15 15 1.8 1.98 TYP MAX 1 UNIT V V V A A A A A pF pF pF K KV ns ns ns Pull-up Resistance ESD Withstand Voltage L-H Propagation Delay H-L Propagation Delay Output Rise and Fall Time DDC_DATA, DDC_CLK VCC = 5V; VRGB = 3.3V; VAUX = 3.3V; (Note 2) CL = 50pF; VCC = 5V; RL = 500; (Note 3) CL = 50pF; VCC = 5V; RL = 500; (Note 3) CL = 50pF; VCC = 5V; RL = 500; (Note 3) Note 3: Measured at 1MHz. R/G/B inputs biased at 1.65V, with VRGB = 3.3V. DDC_CLK and DDC_DATA biased at 2.5V, with VCC = 5V. HSYNC and VSYNC inputs biased at VAUX or GND, with VAUX = 3.3V and VCC = 5V. These parameters are guaranteed by design and characterization. Per the IEC-1000-4-2 ESD Standard, Level 4 contact discharge method. VRGB and VCC must each be bypassed to GND with a 0.2F, low inductance, chip ceramic capacitor at the appropriate supply pin. This parameter is guaranteed by design and device characterization. ESD pulse is applied between the applicable pins and GND. ESD pulse can be positive or negative with respect to GND. Applicable pins are: R, G, B, HSYNC_OUT, VSYNC_OUT, DDC_CLK and DDC_DATA. The HSYNC and VSYNC inputs are ESD protected to the industry standard 2KV per the Human Body model (MIL-STD-883, Method 3015). Applicable to the SYNC buffers only. Input signals swing between 0V and 3.0V, with rise and fall times 5nS. Guaranteed by correlation to buffer output drive currents. (c) 2001 California Micro Devices Corp. All rights reserved. 215 Topaz Street, Milpitas, California 95035 4/25/2001 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 3 CALIFORNIA MICRO DEVICES PACVGA105 Typical Applications Diagram To video DAC VDD +5V 3.3V 0.2 0.2 ANALOG GND GNDD VIDEO CONTROLLER 4 9,16 13 VRGB VCC VAUX GNDA 8 DIGITAL GND HSYNC VSYNC 2 14 HSYNC VSYNC HSYNC_OUT VSYNC_OUT 1 15 DDC_CLK DDC_DATA PACVGA105 DDC_DATA DDC_CLK VGA CONNECTOR GNDD 3,11 SF** SF** HSYNC VSYNC G 6 R RED GREEN BLUE 7 B 5 12 10 DDC_CLK DDC_DATA GNDA, the negative voltage rail for the R,G,B diodes is not connected internally to GNDD. GNDA should ideally be connected to the ground of the video DAC IC. This will prevent any ground bounce caused by digital signals from injecting noise onto the R,G,B signals. Analog GND and digital GND will typically be connected on the pcb. VF** VF** - VIDEO EMI FILTER Standard Part Ordering Information Package Pins 16 Style QSOP Ordering Part Number Part Marking PACVGA105Q VF** VF** RED GREEN BLUE SF** - SYNC EMI FILTER (c)2001 California Micro Devices Corp. All rights reserved. 4 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 4/25/2001 |
Price & Availability of PACVGA105
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |