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INTEGRATED CIRCUITS
P82B715 I2C bus extender
Product data Supersedes data of 2001 Mar 06 2003 Feb 20
Philips Semiconductors
Philips Semiconductors
Product data
I2C bus extender
P82B715
PIN CONFIGURATIONS
8-Pin Dual In-Line or SO P82B715
N.C. 1 LX SX GND 2 3 4 8 7 6 5 VCC LY SY N.C.
DESCRIPTION
The P82B715 is a bipolar integrated circuit intended for application in I2C bus systems. While retaining all the operating modes and features of the system it permits extension of the practical separation distance between components on the I2C bus by buffering both the data (SDA) and the clock (SCL) lines. The I2C bus capacitance limit of 400 pF restricts practical communication distances to a few meters. Using one P82B715 at each end of longer cables reduces the cable loading capacitance on the I2C bus by a factor of 10 times and may allow the use of low cost general purpose wiring to extend bus lengths. I2C
SU00290
PINNING
PIN 1 2 3 4 5 6 7 8 LX SX GND N.C. SY LY VCC SYMBOL N.C. No connect Buffered Bus, LDA or LCL I2C Bus, SDA or SCL Negative Supply No connect I2C Bus, SCL or SDA Buffered Bus, LCL or LDA Positive Supply FUNCTION
FEATURES
* Dual, bi-directional, unity voltage gain buffer * I2C bus compatible * Logic signal levels may include both supply and ground * X10 impedance transformation * Supply voltage range of 4.5 to 12 V * 100 kHz operation * ESD protection exceeds 2500 V HBM per Mil. Std 883C-3015.7 * Latch-up free (bipolar process with no latching structures)
ORDERING INFORMATION
PACKAGES 8-pin plastic dual In-line package TEMPERATURE RANGE -40 to +85 C ORDER CODE P82B715PN TOPSIDE MARK P82B715PN DRAWING NUMBER SOT97-1
8-pin plastic small outline package -40 to +85 C P82B715TD P82B715 SOT96-1 NOTES: 1. For applications requiring lower voltage operation, or additional buffer performance, see AN255 I2C and SMBus Repeaters, Hubs and Expanders Application Note. 2. Standard packing quantities and other packaging data are available at www.philipslogic.com/packaging.
2003 Feb 20
2
Philips Semiconductors
Product data
I2C bus extender
P82B715
VCC
P82B715
SDA BUFFER LDA
SCL
BUFFER
LCL
GND SU00291
Figure 1. Block Diagram: P82B715
ISx = ILx
ISx I2C BUS SX CURRENT SENSE 30 VCC
ISx
ILx = 10 x ISx LX BUFFERED BUS 9 x ISx
GND SU01732
Figure 2. Equivalent Circuit: One Half P82B715
Sx, Sy, I2C Bus, SDA or SCL
On the normal side, because the two buffer circuits in the P82B715 are identical, either the Sx or Sy input pins can be used as the I2C Bus SDA data line, or the SCL clock line.
VCC, GND -- Positive and Negative Supply Pins
In normal use the power supply voltages at each end of the low impedance buffered bus line should be the same. If these differ by a significant amount, noise margin is sacrificed.
Lx, Ly, Buffered Bus, LDA or LCL
On the special low impedance or buffered line side, the corresponding output becomes the LDA data line or LCL clock line.
2003 Feb 20
3
Philips Semiconductors
Product data
I2C bus extender
P82B715
FUNCTIONAL DESCRIPTION
The P82B715 bipolar integrated circuit is a dual bi-directional logic signal driver that increases the allowable total I2C system wiring capacitance. It contains identical circuits, one for each bus signal, and requires no external directional control. It uses unidirectional analog current amplification to increase the current sink capability of I2C chips by a factor 10 and to change the 400 pF I2C bus specification limit into a 4nF bus wiring capacitance limit. This allows I2C, or similar bus systems, to be extended over long distances without degradation of system performance or the use of special cables. P82B715 provides current amplification from its I2C bus to its low impedance or buffered bus. Whenever current is flowing out of Sx, into an I2C chip driving the I2C bus low, its amplifier will sink ten times that current into Lx to drive the buffered bus low (see Figure 2). To minimize interference and ensure stability, the current rise and fall times of the Lx drive amplifier are internally controlled. The P82B715 does not amplify signal currents flowing into Sx on the I2C bus, driven by currents flowing out of Lx on the buffered side. A buffered bus logic low signal at Lx passes via the internal 30 resistor to drive the I2C bus low. This signal current amplification, dependent on its direction, preserves the multi-master, bi-directional, open-collector/open-drain, characteristic of any connected I2C bus lines and the new low impedance bus. Bus logic signal voltage levels will be clamped at (Vcc + 0.7 V) but otherwise are independent of the supply voltage Vcc.
The P82B715 will operate with a supply voltage from 3 V to 12.5 V but the logic signal levels at Sx/Lx are independent of the chip's supply. They remain at the levels presented to the chip by the attached ICs. The maximum static I2C bus sink current, 3 mA, flowing in either direction in the internal current sense resistor, causes a difference less than 100 mV in the bus logic low levels at Sx and Lx. This makes P82B715 fully compatible with all logic signal drivers, including TTL. The P82B715 cannot modify the bus logic signal voltage levels but it contains internal diodes connected between Lx/Sx and Vcc that will conduct and limit the logic signal swing if the applied logic levels would have exceeded the supply voltage by more than 0.7 V. In normal applications external pull-up resistors will pull the connected buses up to the desired voltage high level. Usually this will be the chip supply, Vcc, but for very low logic voltages it is necessary to use a Vcc of at least 3.3 V and preferably higher. Note that full performance over temperature is only guaranteed from 4.5 V. Specification de-ratings that apply when its supply voltage is reduced below 4.5 V are given in Appendix 3 of AN255-02 I2C and SMBus Repeaters, Hubs and Expanders Application Note. The absolute minimum Vcc is 3 V.
I2C Systems
As in standard I2C systems, pull-up resistors are required to provide the logic high levels on the buffered bus. (The standard open-collector configuration is retained). The size and number of pull-up resistors depends on the system. If P82B715 ICs are to be permanently connected into a system, the circuit may be configured with only one pull-up resistor on the buffered bus and none on the I2C buses, but the system design will be simplified and performance improved by fitting separate pull-ups on each section of the bus. When a sub-system using P82B715 may be optionally connected to an existing I2C system that already has a pull-up then the effects of the sub-system pull-ups acting in parallel with the existing I2C bus pull-up must be considered.
APPLICATION NOTES
By using two (or more) P82B715 ICs, a sub-system can be built that retains the interface characteristics of a normal I2C device so that the sub-system may be included in, or added onto, any I2C or related system. The sub-system features a low impedance or buffered bus, capable of driving large wiring capacitance (see Figure 3).
82B715
VCC LDA VCC LONG CABLE LCL
82B715 SDA I2C DEVICE 1/2 SCL
SDA
1/2
1/2
SCL
1/2
STANDARD I2C BUS
SPECIAL BUFFERED BUS
SPECIAL BUFFERED BUS
STANDARD I2C BUS SU00293
Figure 3. Minimum Sub-System with P82B715 Pull-Up Resistance Calculation When calculating the pull-up resistance values the gain of the buffer introduces scaling factors which must be applied to the system components. In practical systems the pull-up resistance value is calculated to meet the rise time limit for I2C systems. As an approximation, this limit will be satisfied in a 100 kHz system if the time constant of the total system (product of the net resistance and net capacitance) is set to 1 microsecond or less. In systems using the P82B715 it is convenient to set the total system time constant by considering each bus node separately (i.e., the I2C nodes and the buffered bus node)and selecting a
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Philips Semiconductors
Product data
I2C bus extender
P82B715
separate pull-up resistor for each node to provide time constants of less than 1 microsecond. If each node complies then the system requirement is also met. This arrangement, using multiple pull-ups as in Fig 4, provides the best system performance and allows stand-alone operation of individual I2C buses if parts of the extended system are disconnected or re-connected. For each bus section the pull-up resistor is calculated as follows: 1ms R+ C device ) C wiring Where: C device = sum of any connected device capacitances, and C wiring = total wiring and stray capacitance on the bus section. [The 1 s is an approximation, with a safety factor, to the theoretical time-constant necessary to meet the specified 1 s bus rise-time specification in a system with variable logic thresholds where the CMOS limits of 30% and 70% of Vcc apply. The calculated value is 1.18 s.]
VCC = 5 V R1 SDA Sx Lx R2 BUFFERED BUS
If these capacitances cannot be measured or calculated then an approximation can be made by assuming that each device presents 10 pF of load capacitance and 10 pF of trace capacitance and that cables range from 50 to 100 pF per metre. If only a single pull-up must be used then it must be placed on the buffered bus (as R2 in Fig 4) and the associated total system capacitance calculated by combining the individual bus capacitances into an equivalent capacitive loading on the buffered bus. This equivalent capacitance is the sum of the capacitance on the buffered bus plus 10 times the sum of the capacitances on all the connected I2C nodes. The calculated value should not exceed 4 nF. The single buffered bus pull-up resistor is then calculated to achieve the 1 s risetime and it then provides the pull-up for the buffered bus and for all other connected I2C bus nodes included in the calculation.
R3 SDA Lx Sx
I2C 2
SCL
SCL Sy Ly Ly Sy VCC = 5 V R4
SDA Lx Sx SCL Ly Sy SU01733
I2C 3
Figure 4. Single Pull-up Buffered Bus Calculating bus drive currents Figure 4 shows three P82B715s connected to a common buffered bus. The associated bus capacitances are omitted for clarity but assume the resistors have been selected to give R-C products of less than 1 s so the bus rise time requirement is satisfied. An I2C chip connected at I2C 1 and holding the SDA bus low must sink the current flowing in its local pull-up R1 plus, with assistance from the P82B715, the currents in R2, R3 and R4. Because the resistors R3 and R4 act to pull the bus nodes I2C 2 and I2C 3, and their corresponding Sx pins, to a voltage higher than the voltage at the Lx pins their buffer amplifiers will be inactive. The SDA at Sx of I2C 2 and I2C 3 is pulled low by the low at Lx via the internal 30 ohm resistor that links Lx to Sx. So the effective current that must be sunk by the P82B715 buffer on I2C 1, at its Lx pin, is the sum of the currents in R2, R3 and R4. The Sx current that must be sunk by an I2C chip at I2C 1, due to the buffer gain action, is 1/10 of the Lx current. So the effective pull-up, determining the current to be sunk by an I2C chip at I2C 1, is R1 in parallel with resistors 10 times the values of R2, R3 and R4. If R1 = R3 = R4 = 10k, and R2 = 1k, the effective pull-up load at I2C 1 is 10k||10k||100k||100k = 4.55 k ohms The same calculation applies for I2C 2 or I2C 3. To calculate the current sunk by the Lx pin of the buffer at I2C 1 note that the current in R1 is sunk directly by the IC at I2C 1. The buffer therefore sinks only the currents flowing in R2, R3, and R4 so the effective pull-up is R2 in parallel with R3 and R4. In this example that's 1k||10k||10k = 833 ohms. For a 5.5 V supply and 0.4 V low that means the buffer is sinking 16.3 mA. The P82B715 has a static sink rating of 30 mA at Lx. The requirement is that the pull-up on the buffered bus, in parallel with all other pull-ups that it is indirectly pulling low on Sx pins of other P82B715 ICs, will not cause this 30 mA limit to be exceeded. The minimum pull-up resistance in a 5 V +/-10% system is 170 ohms. The general requirement is: V CC max * 0.4 t 30 mA RP Where: Rp = parallel combination of all pull-up resistors driven by the Lx pin of the P82B715. Figure 5 shows calculations for an expanded I2C bus with 3 nF of cable capacitance.
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Philips Semiconductors
Product data
I2C bus extender
P82B715
LOCAL BUS VCC
PROPOSED BUS EXPANSION 5V
I2C
SDA
R1
R2
R3
Sx I2C
Lx
LDA
Lx
Sx
SDA
I2C
SDA
3 nF = CABLE WIRING CAPACITANCE
GND
0V
EFFECTIVE CAPACITANCE LOCAL BUS I2C DEVICES 2 x I2C Devices Strays P82B715 TOTAL CAP. 20 pF 20 pF 10 pF ----50 pF
EFFECTIVE CAPACITANCE BUFFERED LINE Wiring Cap. TOTAL CAP. 3000 pF ----3000 pF
EFFECTIVE CAPACITANCE REMOTE I2C DEVICES 1 x I2C Devices Strays P82B715 TOTAL CAP. 10 pF 10 pF 10 pF ----30 pF
LOCAL I2C PULL-UP R1 + 1 m sec + 20 kW 50 pF
BUFFERED BUS PULL-UP R2 + 1 m sec + 330 W 3000 pF
REMOTE I2C PULL-UP R3 + 1 m sec + 33 kW 30 pF
SU00294
Figure 5. Typical Loading Calculation: Adding An Extension Bus with P82B715
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134). Voltages with respect to pin GND (DIL-8 pin 4). LIMITS SYMBOL VCC to GND Vbus Vbuff I Ptot Tstg Tamb Supply voltage range VCC Voltage range I2C Bus, SCL or SDA Voltage range Buffered Bus DC current (any pin) Power dissipation Storage temperature range Operating ambient temperature range PARAMETER MIN. -0.3 0 0 -- -- -55 -40 MAX. +12 VCC VCC 60 300 +125 +85 UNIT V V V mA mW C C
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Philips Semiconductors
Product data
I2C bus extender
P82B715
CHARACTERISTICS
At Tamb = +25 C and VCC = 5 Volts, unless otherwise specified. LIMITS SYMBOL Power Supply VCC ICC ICC ICC Drive Currents ISx, ISy Output sink on I2C bus VSx, VSy LOW = 0.4 V VLx, VLy LOW on Buffered bus = 0.3 V Output sink on Buffered bus VLx, VLy LOW = 0.4 V VSx, VSy LOW on I2C bus = 0.3 V Input current from I2C bus when ILx, ILy sink on Buffered bus = 30 mA Input current from Buffered bus when ISx, ISy sink on I2C bus = 3 mA Leakage current on Buffered bus VLx, VLy = VCC, and VSx, VSy = VCC Input/Output impedance 3 -- -- mA Supply voltage (operating) Supply current Supply current at VCC = 12 V Supply current, both I2C inputs LOW, both buffered outputs sinking 30 mA. 4.5 -- -- -- -- 16 22 28 12 -- -- -- V mA mA mA PARAMETER MIN. TYP. MAX. UNIT
ILx, ILy
30
--
--
mA
Input Currents ISx, ISy ILx, ILy ILx, ILy -- -- -- -- -- -- 3 3 200 mA mA A
Impedance Transformation Zin/Zout 8 10 13
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7
Philips Semiconductors
Product data
I2C bus extender
P82B715
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
2003 Feb 20
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Philips Semiconductors
Product data
I2C bus extender
P82B715
DIP8: plastic dual in-line package; 8 leads (300 mil)
SOT97-1
2003 Feb 20
9
Philips Semiconductors
Product data
I2C bus extender
P82B715
REVISION HISTORY Rev Date _5 20030220
Description Product data (9397 750 11094); ECN 853-2240 29410 of 22 January 2003; supersedes data of 2001 Mar 06 (9397 750 08163). Modifications: * Pin capacitance added Product data (9397 750 08163); ECN 853-2240 25757 of 2001 Mar 06.
_4
20010306
2003 Feb 20
10
Philips Semiconductors
Product data
I2C bus extender
P82B715
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011.
Data sheet status
Level
I
Data sheet status[1]
Objective data
Product status[2] [3]
Development
Definitions
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data
Qualification
III
Product data
Production
[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products--including circuits, standard cells, and/or software--described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
Koninklijke Philips Electronics N.V. 2003 All rights reserved. Printed in U.S.A. Date of release: 02-03
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Document order number:
9397 750 11094
Philips Semiconductors
2003 Feb 20 11

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