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MC74F544 OCTAL REGISTERED TRANSCEIVER, INVERTING, 3-STATE
The MC74F544 Octal Registered Transceivers contain two sets of D-Type latches for temporary storage of data flowing in either direction. Separate Latch Enable (LEAB, LEBA) and Enable (OEAB, OEBA) inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow. The MC74F544 has an inverting data path. The A outputs are guaranteed to sink 24 mA while the B outputs are rated for 64 mA.
OCTAL REGISTERED TRANSCEIVER, INVERTING, 3-STATE
FASTTM SCHOTTKY TTL
* * * * * * * * * * *
Combines 74F245 and 74F373 Type Functions in One Chip 8-Bit Octal Transceiver Inverting Back-to-Back Registers for Storage Separate Controls for Data Flow in Each Direction Glitchless Outputs During 3-State Power Up or Power Down Operation High Impedance Outputs in Power Off State A Outputs Sink 24 mA and Source 3.0 mA B Outputs Sink 64 mA and Source 15 mA See F543 for Noninverting Version ESD Protection > 4000 Volts
24 1
N SUFFIX PLASTIC CASE 724-03
24 1
DW SUFFIX SOIC CASE 751E-03
PIN ASSIGNMENT
VCC EBA 24 23 B0 22 B1 21 B2 20 B3 19 B4 18 B5 17 B6 16 B7 LEAB OEAB 15 14 13
ORDERING INFORMATION
MC74FXXXN Plastic MC74FXXXDW SOIC
1
2
3
4 A1
5 A2
6 A3
7 A4
8 A5
9 A6
10 A7
11
12
LEBA OEBA A0
EAB GND
GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL DC Supply Voltage Operating Ambient Temperature Range Output Current -- High Output Current -- Low Parameter 74 74 74 74 Min 4.5 0 -- -- Typ 5.0 25 -- -- Max 5.5 70 - 3.0 / - 15 24 / 64 Unit V C mA mA
FAST AND LS TTL DATA 4-216
MC74F544
FUNCTION TABLE
Inputs OEXX H X L L L L L L L EXX X H L L L L L LEXX X X L L L L H Data X X l h l h L H X Outputs Z Z Z Z H L H L NC Status Outputs disabled Outputs disabled Outputs disabled Data latched Data latched Transparent Hold
H = HIGH voltage level: h = HIGH state must be present one set-up time before the LOW-to-HIGH transition of LEXX or EXX (XX = AB or BA): L = LOW voltage level: l = LOW state must be present one set-up time before the LOW-to-HIGH transition of LEXX or EXX (XX = AB or BA): X = Don't care: Z = HIGH impedance state: NC = No Change.
FUNCTIONAL DESCRIPTION The MC74F544 contains two sets of eight D-type latches, with separate input and controls for each set. For data flow from A to B, for example, the A-to-B Enable (EAB) input must be LOW in order to enter data from A0 - A7 or take data from B0 - B7, as indicated in the Function Table. With EAB LOW, a LOW signal on the A-to-B latch enable (LEAB) input makes the A-to-B latches transparent; a subsequent LOW-to-HIGH
transition of the LEAB signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With EAB and OEAB both LOW, the 3-State B output buffers are active and reflect the inverted data present at the output of the A latches. Control of data flow from B to A is similar, but using the EBA, LEBA, and OEBA inputs.
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK VOH Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage A0 - A7 B0 - B7 VOL Output LOW Voltage A0 - A7 B0 - B7 74 74 74 74 I/O Pins IIH Input HIGH Current Control Pins Control Pins I/O Pins IIL IOZH IOZL IOS Input LOW Current Off-State Output Current Off-State Output Current, Low-Level Voltage Applied Output Short Circuit Current (Note 2) An Outputs Bn Outputs ICCH ICCL ICCZ EAB, EBA Other Inputs Parameter Min 2.0 -- -- 2.4 2.7 2.0 -- -- -- -- -- -- -- -- -- -- - 60 - 100 -- -- -- Typ -- -- - 0.73 -- 3.4 -- 0.35 0.4 -- -- -- -- -- -- -- -- -- -- 70 95 95 Max -- 0.8 - 1.2 -- -- -- 0.5 0.55 1.0 100 20 70 - 1.2 - 0.6 70 - 600 -150 -225 105 130 125 mA VCC = MAX Unit V V V V V V V mA A A A mA A A mA Test Conditions (Note 1) Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage VCC = MIN, IIN = - 18 mA VCC = 4.5 V IOH = - 3.0 mA VCC = 4.75 V IOH = - 15 mA IOL = 24 mA VCC = 4.5 V
VCC = MIN IOL = 64 mA VCC = MAX, VIN = 5.5 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 0.5 V VCC = MAX, VOUT = 2.7 V VCC = MAX, VOUT = 0.5 V VCC = MAX, VOUT = 0 V
ICC
Total Supply Current
NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type. 2. Not more than one output should be shorted at a time, nor for more than 1 second.
FAST AND LS TTL DATA 4-217
MC74F544
AC ELECTRICAL CHARACTERISTICS
74F TA = + 25C VCC = + 5.0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation Delay Transparent Mode An to Bn or Bn to An Propagation Delay LEBA to An Propagation Delay LEAB to Bn Output Enable Time OEBA or OEAB to An or Bn EBA or EAB to An or Bn Output Disable Time OEBA or OEAB to An or Bn EBA or EAB to An or Bn Parameter Min 2.0 2.0 6.0 4.0 6.0 4.0 3.0 4.0 1.5 1.5 Typ -- -- -- -- -- -- -- -- -- -- Max 9.5 6.5 13 9.5 13 9.5 9.0 10.5 8.0 7.5 74F TA = 0 C to + 70C VCC = + 5.0 V 10% CL = 50 pF Min 2.0 2.0 6.0 4.0 6.0 4.0 3.0 4.0 1.5 1.5 Max 10.5 7.5 14.5 10.5 14.5 10.5 10 12 9.0 8.5 Unit ns
ns ns
ns
ns
AC OPERATING REQUIREMENTS
74F TA = + 25C VCC = + 5.0 V CL = 50 pF Symbol ts(H) ts(L) th(H) th(L) tw(L) Parameter Setup Time, HIGH or LOW An or Bn to LEBA or LEAB Hold Time, HIGH or LOW An to Bn to LEBA or LEAB Latch Enable, B to A Pulse Width, LOW Min 3.0 3.0 3.0 3.0 6.0 Typ -- -- -- -- -- Max -- -- -- -- -- 74F TA = 0C to + 70C VCC = + 5.0 V 10% CL = 50 pF Min 3.0 3.0 3.0 3.0 7.5 Typ -- -- -- -- -- Max -- -- -- -- -- Unit ns ns ns
FAST AND LS TTL DATA 4-218
MC74F544
LOGIC DIAGRAM
DQ LE A0 DETAIL A D Q LE B0
A1 A2 A3 A4 A5 A6 A7 DETAIL A X 7
B1 B2 B3 B4 B5 B6 B7
OEBA OEAB EBA EAB LEBA LEAB
NOTE: Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
FAST AND LS TTL DATA 4-219

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