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NJU6682
160-common x 132-segment 4-level Gray Scale BITMAP LCD DRIVER
s GENERAL DESCRIPTION The NJU6682 is a 160-common x 132-segment 4-level gray scale bit map LCD driver to display graphics or characters. It contains 84,480-bit display data RAM, microprocessor interface circuits, instruction decoder, and common and segment drivers. An image data from CPU through the serial or 8-bit/16-bit parallel interface are stored into the 84,480 bits internal display data RAM and are displayed on the LCD panel through the commons and segments drivers. The NJU6682 features 4-level gray scale display function creating 4 types of gray scale (white / light gray / dark gray / black) and black & white display function. The NJU6682 contains a built-in OSC circuit for reducing external components. And it features Partial Display Function containing selectable active display block(s) (two blocks max.) and optimizing the duty cycle ratio. This function dramatically reduces the operating current, setting the optimum boosted voltage combined with a programmable voltage booster circuit and an electrical variable resister. As result, it reduces the operating current. The operating voltage from 2.4V to 3.3V and low operating current are suitable for small size battery operation items. s PACKAGE OUTLINE
NJU6682CJ
s FEATURES q Direct Correspondence of Display Data RAM to LCD Pixel q Display Method - 4 level Gray Scale / Black & White q Display Data RAM - 84,480 bits ;( 160-Com x 132-Seg) x 2 (double of the display size) x 2bit q LCD drivers - 160-common and 132-segment q Direct connection to 8-bit / 16-bit Microprocessor interface for both of 68 and 80 type MPU q Serial Interface (SI, SCL, A0, CS) q Partial Display Function (Two limited active display blocks setting. Duty ratio set automatically.) q Variable RAM Mapping - The display screen can be composed from the RAM area in a maximum of 8 blocks discontinuity. q Easy Vertical Scroll by setting the start line address of over size display data RAM (This function doesn't work in Variable RAM Mapping mode ) q Programmable Bias ratio selection ; 1/4, 1/5, 1/6, 1/7, 1/8, 1/9, 1/10, 1/11, 1/12, 1/13, 1/14 bias q Common Driver Order Assignment by mask option Version C0 to C159 (Pin Name) NJU6682A COM0 to COM159 NJU6682B COM159 to COM0 q Useful Instruction Sets Display ON/OFF, Display Start Line-Address Set, Column-Address Set, Row-Address Set, Status Read, Display Data Read/Write, Normal or Reverse Display, Whole display/Normal display, Partial Display, n-Line Inverse Set, EVR Resister Set, Variable RAM Mapping Mode, Gray Scale Level Select, Bias Select, Booster Select (7-times maximum), Read Modify Write, Reset, Power Supply selection, Driver Outputs ON/OFF, Power Save, ADC Select, Display Mode Select, 8-bit / 16-bit Buss Select. q Power Supply Circuit for LCD; Programmable Booster Circuits (7 times maximum, Voltage boosting polarity : Negative Voltage (VDD Common), Voltage Adjust Circuit, Voltage Follower (x 4)) q Precision Electrical Variable Resistance (201 Step) q Low Operating Current T.B.D ( typ. ) q Operating Voltage 2.4 to 3.3 V q LCD Driving Voltage 6.0 to 18.0V q Package Outline Bumped Chip q C-MOS Technology ( Substrate : N )
NJU6682
s PAD LOCATION
S81 S80 C158 C159 S131 S130 C80 C81
S79 S78
C79 C78
Y
X
S1 S0
C1 C0
VDD V1 V2 V3 V4 V5 VR VDD C1+ C1+ C2 C2C3C4C5C6VOUT VSS D15 D14 D13 D12 D11 D10 D9 D8 D7(SI) D6(SCL) D5 D4 D3 D2 D1 D0 RD WR A0 CS OSC2 OSC1 VSS RES SEL68 PS0 PS1
Chip Center :X=0um,Y=0um Chip Size :X=8.27m,Y=5.67mm Chip Thickness :675um +/- 30um Bump Size :45um x 83um Pad Pitch :60um (min) Bump Height :17.5um (typ) Bump Material :Au Voltage boosting polarity : Negative Voltage (VDD Common) Substrate : N
DUMMY2 DUMMY1 DUMMY0 VDD
NJU6682
s PAD Coordinates PAD No. Terminal 1 VDD 2 DUMMY0 3 DUMMY1 4 DUMMY2 5 PS1 6 PS0 7 SEL68 8 RES 9 VSS 10 OSC1 11 OSC2 12 CS 13 A0 14 WR 15 RD 16 D0 17 D1 18 D2 19 D3 20 D4 21 D5 22 D6(SCL) 23 D7(SI) 24 D8 25 D9 26 D10 27 D11 28 D12 29 D13 30 D14 31 D15 32 VSS 33 VOUT 34 C6 35 C5 36 C4 37 C3 38 C2 + 39 C2 40 C1 + 41 C1 42 VDD 43 VR 44 V5 45 V4 46 V3 47 V2 48 V1 49 VDD 50 C0 X(um) -3933 -3863 -3793 -3723 -3562 -3325 -3105 -2869 -2712 -2555 -2319 -2098 -1862 -1641 -1405 -1168 -948 -727 -507 -287 -66 153 374 594 814 1035 1255 1476 1696 1916 2137 2298 2368 2464 2613 2683 2832 2902 3050 3120 3269 3339 3519 3589 3659 3729 3799 3869 3939 3975 Chip Size Y(um) -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2675 -2186 8.27x5.67mm(Chip Center PAD No. Terminal 51 C1 52 C2 53 C3 54 C4 55 C5 56 C6 57 C7 58 C8 59 C9 60 C10 61 C11 62 C12 63 C13 64 C14 65 C15 66 C16 67 C17 68 C18 69 C19 70 C20 71 C21 72 C22 73 C23 74 C24 75 C25 76 C26 77 C27 78 C28 79 C29 80 C30 81 C31 82 C32 83 C33 84 C34 85 C35 86 C36 87 C37 88 C38 89 C39 90 C40 91 C41 92 C42 93 C43 94 C44 95 C45 96 C46 97 C47 98 C48 99 C49 100 C50 X=0m, Y=0m) X(um) Y(um) 3975 -2126 3975 -2066 3975 -2006 3975 -1946 3975 -1886 3975 -1826 3975 -1766 3975 -1706 3975 -1646 3975 -1586 3975 -1526 3975 -1466 3975 -1406 3975 -1346 3975 -1286 3975 -1226 3975 -1166 3975 -1106 3975 -1046 3975 -986 3975 -926 3975 -866 3975 -806 3975 -746 3975 -686 3975 -626 3975 -566 3975 -506 3975 -446 3975 -386 3975 -326 3975 -266 3975 -206 3975 -146 3975 -86 3975 -26 3975 34 3975 94 3975 154 3975 214 3975 274 3975 334 3975 394 3975 454 3975 514 3975 574 3975 634 3975 694 3975 754 3975 814
NJU6682
PAD No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150
Terminal C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 C65 C66 C67 C68 C69 C70 C71 C72 C73 C74 C75 C76 C77 C78 C79 C80 C81 C82 C83 C84 C85 C86 C87 C88 C89 C90 C91 C92 C93 C94 C95 C96 C97 C98 C99 C100
X(um) 3975 3975 3975 3975 3975 3975 3975 3975 3975 3975 3975 3975 3975 3975 3975 3975 3975 3975 3975 3975 3975 3975 3975 3975 3975 3975 3975 3975 3975 3930 3870 3810 3750 3690 3630 3570 3510 3450 3390 3330 3270 3210 3150 3090 3030 2970 2910 2850 2790 2730
Y(um) 874 934 994 1054 1114 1174 1234 1294 1354 1414 1474 1534 1594 1654 1714 1774 1834 1894 1954 2014 2074 2134 2194 2254 2314 2374 2434 2494 2554 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675
PAD No. 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200
Terminal C101 C102 C103 C104 C105 C106 C107 C108 C109 C110 C111 C112 C113 C114 C115 C116 C117 C118 C119 C120 C121 C122 C123 C124 C125 C126 C127 C128 C129 C130 C131 C132 C133 C134 C135 C136 C137 C138 C139 C140 C141 C142 C143 C144 C145 C146 C147 C148 C149 C150
X(um) 2670 2610 2550 2490 2430 2370 2310 2250 2190 2130 2070 2010 1950 1890 1830 1770 1710 1650 1590 1530 1470 1410 1350 1290 1230 1170 1110 1050 990 930 870 810 750 690 630 570 510 450 390 330 270 210 150 90 30 -30 -90 -150 -210 -270
Y(um) 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675
NJU6682
PAD No. 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250
Terminal C151 C152 C153 C154 C155 C156 C157 C158 C159 S131 S130 S129 S128 S127 S126 S125 S124 S123 S122 S121 S120 S119 S118 S117 S116 S115 S114 S113 S112 S111 S110 S109 S108 S107 S106 S105 S104 S103 S102 S101 S100 S99 S98 S97 S96 S95 S94 S93 S92 S91
X(um) -330 -390 -450 -510 -570 -630 -690 -750 -810 -870 -930 -990 -1050 -1110 -1170 -1230 -1290 -1350 -1410 -1470 -1530 -1590 -1650 -1710 -1770 -1830 -1890 -1950 -2010 -2070 -2130 -2190 -2250 -2310 -2370 -2430 -2490 -2550 -2610 -2670 -2730 -2790 -2850 -2910 -2970 -3030 -3090 -3150 -3210 -3270
Y(um) 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675
PAD No. 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300
Terminal S90 S89 S88 S87 S86 S85 S84 S83 S82 S81 S80 S79 S78 S77 S76 S75 S74 S73 S72 S71 S70 S69 S68 S67 S66 S65 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41
X(um) -3330 -3390 -3450 -3510 -3570 -3630 -3690 -3750 -3810 -3870 -3930 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975
Y(um) 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2675 2517 2457 2397 2337 2277 2217 2157 2097 2037 1977 1917 1857 1797 1737 1677 1617 1557 1497 1437 1377 1317 1257 1197 1137 1077 1017 957 897 837 777 717 657 597 537 477 417 357 297 237
NJU6682
PAD No. 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341
Terminal S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
X(um) -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975 -3975
Y(um) 177 117 57 -2 -62 -122 -182 -242 -302 -362 -422 -482 -542 -602 -662 -722 -782 -842 -902 -962 -1022 -1082 -1142 -1202 -1262 -1322 -1382 -1442 -1502 -1562 -1622 -1682 -1742 -1802 -1862 -1922 -1982 -2042 -2102 -2162 -2222
NJU6682
s BLOCK DIAGRAM
S0 Vss VDD V1 to V5 5 C1 C1 C2 C2 C3 C4 C5 C6
+ -
S131 C0
C159
SEG Driver
COM Driver
132
Shift Register
Voltage Generator
+ -
Common Timing Generator
Output Assignment Register
Gray Scale/Black & White Control
132 x 2
Display Data Latch Line Address Decoder Row Address Decoder Start Line Register FRC/PWM Controller Display Timing Generator
Display Data RAM 132 x 2 x 160 x 2
VR
Row Address Register
I/O Buffer
Column Address Decoder Column Address Counter Column Address Register Multiplex 6bit 6bit OSC OSC1 OSC2
I/O Buffer
Status Instruction Decoder Internal Bus
BF
Bus Holder
Reset
MPU Interface
Line Counter
RES
CS
A0
RD
WR SEL68 PS0
PS1
D0 to D5 D6(SCL) D7(SI)
D8 toD15
NJU6682
s TERMINAL DESCRIPTION Symbol I/O DUMMY0 - DUMMY2 Power 1,42,49 VDD 9,32 VSS GND Power V1 48 47 V2 46 V3 45 V4 44 V5 No. 2-4 Function Dummy Terminals
These are open terminals electrically. Power Supply Terminal (+2.4V - +3.3V) Ground terminal (0V) LCD Driving Voltage Supplying Terminals. In case of the external power supply operation without internal power supply operation, each level of LCD driving voltage is supplied from outside fitting with following relation. In case of the internal power supply, LCD driving voltages V1-V4 depending on the Bias selection are supplied as shown in follows; Bias V1 V2 V3 V4 1/4Bias V5+3/4VLCD V5+2/4VLCD V5+2/4VLCD V5+1/4VLCD 1/5Bias V5+4/5VLCD V5+3/5VLCD V5+2/5VLCD V5+1/5VLCD 1/6Bias V5+5/6VLCD V5+4/6VLCD V5+2/6VLCD V5+1/6VLCD 1/7Bias V5+6/7VLCD V5+5/7VLCD V5+2/7VLCD V5+1/7VLCD 1/8Bias V5+7/8VLCD V5+6/8VLCD V5+2/8VLCD V5+1/8VLCD 1/9Bias V5+8/9VLCD V5+7/9VLCD V5+2/9VLCD V5+1/9VLCD 1/10Bias V5+9/10VLCD V5+8/10VLCD V5+2/10VLCD V5+1/10VLCD 1/11Bias V5+10/11VLCD V5+9/11VLCD V5+2/11VLCD V5+1/11VLCD 1/12Bias V5+11/12VLCD V5+10/12VLCD V5+2/12VLCD V5+1/12VLCD 1/13Bias V5+12/13VLCD V5+11/13VLCD V5+2/13VLCD V5+1/13VLCD 1/14Bias V5+13/14VLCD V5+12/14VLCD V5+2/14VLCD V5+1/14VLCD
VDDV1V2V3V4V5VOUT
41 40 39 38 37 36 35 34 33 43 16 - 23 (22,23)
C1 C1 + C2 C2 C3 C4 C5 C6 VOUT VR D0 - D7 (SCL, SI)
+
(VLCD=VDD-V5) O
Capacitor connecting terminals for Internal Voltage Booster. Boosting time is programmed by instruction (2 to 7 times )
O I I/O
Boosted voltage output terminal. Connects the capacitor between VOUT terminal and VSS. VLCD voltage adjustment terminal. The gain of VLCD setup circuit for V5 level is adjusted by external resistors.
Data Input/Output terminals. In Pararel Interface Mode (PS1="H", PS0="H"/"L") *8-bit bus mode*1: I/O terminals of 8-bit bus. 1 *16-bit bus mode* : I/O terminals of lower 8-bit of 16-bit bus * 8-bit or 16-bit bus is set by the "8-bit / 16-bit Bus Select" instruction In Serial Interface Mode(PS1="L", PS0="H"/"L") *D7: Input terminal of serial data ( SI ). *D6: Input terminal of serial data clock ( SCL ).
D0 to D5 terminals are Hi-impedance When CS="H", D0 to D7 terminals are Hi-impedance.
1
24 - 30
D8 - D15
I/O
Data Input/Output terminals
In 16-bit Bus interface Mode (PS1="H", PS0="H"/"L")
*I/O terminals of upper 8-bit of 16-bit bus.
In 8-bit Bus or Serial interface Mode * D8 to D15 terminals are Hi-impedance
NJU6682
No. 13
Symbol A0
I/O I
Description
Data discremination signal input terminal. The signal from MPU discreminates transmoitted data between Display data and Instruction.
A0 Distin. 8 12 15 RES CS RD I I I
Reset terminal.
H Display Data
L Instruction
When the RES terminal goes to "L", the initialization is performed.
Reset operation is executing during "L" state of RES. Chip select signal input terminal. Data Input/Output are available during CS="L". RD(80 type) or E(68 type) signal input terminal. *In 80 type MPU mode ( PS1="H", SEL68="L" ) RD signal from 80 type MPU input terminal. Active "L". D0 to D7 terminals are output during "L" level. *In 68 type MPU mode ( PS1="H", SEL68="H" ) Enable signal from 68 type MPU input terminal. Active "H". WR(80 type) or R/W(68 type) signal input terminal *In 80 type MPU mode ( PS1="H", SEL68="L" ) WR signal from 80 type MPU input terminal. Active "L". The data transmitted during WR="L" are fetched at the rising edge of WR. *In 68 type MPU mode ( PS1="H", SEL68="H" ) R/W signal from 68 type MPU input terminal.
(E)
I
14
WR
I
(R/W)
R/W State 7 SEL68 I SEL68 State
H Read H 68 Type
L Write
This terminal must connect to VDD or VSS.
MPU interface type selection terminal.
L 80 Type
6 5
PS0 PS1
I
Parallel or Serial interface selection signal input terminal.
PS1 PS0 Interface Chip Select H L/H H L L
Parallel Serial 4-wire Serial 3-wire
Data/ Instruction
Data D0D7, D8D15 SI(D7) SI(D7)
Read/ Write
Serial Clock SCL(D6) SCL(D6)
CS CS CS
A0 A0
Every 17th data of Serial data is recognized as A0.
RD,WR -
10 11
OSC1 OSC2
I/O
In case of serial interface( PS1="L",PS0="H/L" ), RD and WR terminals must fix to "H" or "L". D0 to D5 and D8 to D15 terminals are Hi-impedance. External clock input terminal. In Internal oscillation operation, OSC1 and OSC2 terminals should be Open. In External clock operation, the external clock input to OSC1 terminal.
NJU6682
No. 50 - 209 Symbol C0 - C159 I/O O Function
LCD driving signal output terminal. *Common output terminal: C0 to C159 *Segment output terminal: S0 to S131 *Common output terminal Following output voltage is selected by the combination of alternating (FR) signal and Common scanning data.
341 - 210
S0 - S131
O
Scanning Data H L
Altern ating (FR) H L H L
Common terminal Output Voltage V5 VDD V1 V4
*Segment output terminal Following output voltage is selected by the combination of alternating (FR) signal and display data in the DD RAM.
Scanning Data H L
Altern ating (FR) H L H L
Segment terminal Output Voltage Normal Display VDD V5 V2 V3 Reverse Display V2 V3 VDD V5
NJU6682
s Functional Description (1) Description of each blocks (1-1) Busy Flag (BF) The Busy Flag (BF) is set to logical "1" in busy of internal execution by an instruction, and any instruction excepting for the "Status Read" is disable at this time. Busy Flag is outputted through D7 terminal by "Status Read" instruction. Although another instructions should be inputted after check of Busy Flag, no need to check Busy flag if the system cycle time (tCYC) as shown in "AC Characteristics" is secured completely. (1-2) Display Start Line Register The Display Start Line Register is a register to set a display data RAM address corresponding to the COM0 display line (the top line normally) for the vertical scroll on the LCD, Row address change and so forth. The Display Start Line Address set instruction sets the 9-bit display start address into this register. (1-3) Line Counter Line Counter is reset when the internal FR signal is switched and outputs the line address of the display data RAM by count up operation synchronizing with common cycle of NJU6682. (1-4) Column Address Counter Column Address Counter is the 6-bit preset-able counter to point the column address of the display data RAM (DD RAM) as shown in Figure 1-1 and 1-2. The counter is incremented automatically after the display data read/write instructions execution. When the column address counter reaches to the maximum existing address by the increment operations, the count up operation (increment) is frozen. However, when new address is set to the column address counter again, it restarts the count up operation from a set address. The operation of Column Address Counter is independent against Row Address Register. By the address inverse instruction (ADC select) as shown in Figure 1-1 and 1-2, Column Address Decoder reverses the correspondence between Column address and Segment output of display data RAM. (1-5) Row Address Register Row Address Register assigns the row address of the display data RAM as shown in Figure 1-1 and 1-2. In case of accessing from the MPU with changing the row address, Row Address Set instruction is required. (1-6) Display data RAM (DD RAM) The Display data RAM (DD RAM) is the bit map RAM consisting of 84,480 bits to store the display data corresponding to the LCD pixel on LCD panel. Each LCD pixel corresponds to two bits in the display data RAM in gray scale mode and to one bit in black & white mode, display data respectively. The DD RAM data : "00" = Gray Scale Level 0 ( Set by the "Gray Scale Level Select" instruction) The DD RAM data : "01" = Gray Scale Level 1 ( " ) The DD RAM data : "10" = Gray Scale Level 2 ( " ) The DD RAM data : "11" = Gray Scale Level 3 ( " ) The DD RAM data and the state of the LCD in Black & White Mode: In Normal Display : "1"=Turn-On Display, "0" =Turn-Off Display In Reveres Display : "1"=Turn-Off Display, "0" =Turn-On Display The bus length accessing to the DD RAM is chosen 8-bit access or 16-bit by the 8-bit/16-bit Bus Select instruction. In case of the 16-bit bus length is selected in the gray scale display mode, only upper 8 bits of column address are valid and lower 8 bits (D7-D0) are ignored (Fig. 1-1) because of 8-bit addressing RAM area of column address=10H. When the 16-bit bus length in the Black & White display mode is selected, only upper 4 bits of column address are valid and lower 12 bit (D11-D0) is ignored because of 4-bit RAM area of column address=08H(Layer0) or column address=28H(Layer1) When the 8-bit bus length in the Black & White display mode is selected, the DD RAM is addressed by only upper 4 bits of column address thus lower 4 bits are also ignored. DD RAM output 132 x 2 bits parallel data addressed by Line counter then the data latched in the display data latch. Asynchronous data access to the DD RAM is available due to the access to the DD RAM from the MPU and latch to the display data latch operation are done independently.
Row Address
Column Address
ADC=1 ADC=0
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12
138 139 13A 13B 13C 13D 13E 13F
Segment Output 10H (010000) 00H (000000)
D8 D9 D10 D11 D12 D13 D14 D15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
1
2
3
4
5
6
0FH (001111)
7
Fig.1-1 DD RAM addressing (Gray scale mode)
0FH (001111)
124
125
126
127
00H (000000)
128
129
10H (010000)
130
NJU6682
131
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8
Row Address
Segment Output
Column Address
ADC=1 08H
(001000)
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12
138 139 13A 13B 13C 13D 13E 13F
ADC=0
0 1 2 3 4 5 6 7
00H (000000)
07H (000111)
D12 D13 D14 D15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Layer 0
00H (000000)
07H (000111) 08H
124 125 126 127 128 129 130 131
(001000)
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12
28H
(101000)
Fig.1-2 DD RAM addressing (Black & White mode)
D12 D13 D14 D15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
0 1 2 3 4 5 6 7
20H (100000)
27H (100111)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Layer 1
27H (100111)
20H (100000)
NJU6682
124 125 126 127 128 129 130
28H
(101000)
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12
NJU6682
(1-7) Output Assignment Register This circuit determines the scanning direction of the common output. Table 1 Scanning direction of the common output Common Output Terminal PAD No. 50 209 Terminal C0 C159 Name Ver.A COM0 COM159 Ver.B COM159 COM0 * The Mask fixes the common scanning direction between version A and B that can not be changed by the instruction. (1-8) Reset Circuit When the input signal to RES terminal goes to "L", the reset circuit executes initialization as below; -The Initialization state (default) 1. Display mode: 4 level Gray Scale Display Mode. 2. Display off 3. Normal Display (not inverse) 4. ADC selects: Normal 5. Read Modify Write off 6. Voltage Booster off, Voltage Regulator off, Voltage follower off 7. Whole Display / Normal Display 8. Driver output off 9. Clear the data of serial interface register 10. Set the Column Address Counter to 00H 11. Set the Row Address Register to 00H 12. Set the Start Line Address to 00H 13. Set the Gray Scale Level to default value (Refer to (2-1)Descriptions of the Instruction Codes (n)Select Gray Scale Level) 14. The continuous addressing of DDRAM (Variable RAM Mapping Mode off) 15. Set the EVR register to FFH 16. Set the Duty Ratio to 1/160 17. Bias select D3, D2, D1, D0 = "1,0,1,0" (1/14 Bias) 18. Voltage Booster Select D2, D1, D0 = "1,0,1" (7 times) 19. Set n-line inverse register to 0H 20. Set to 8-bit bus interface mode The RES terminal connects to the reset terminal of the MPU synchronization with the MPU initialization as shown in " the MPU interface " in the Application Circuit section. The "L" level input signal as reset signal must keep the period over than 10us as shown in DC Characteristics. The NJU6682 takes 1us for the reset operation after the rising edge of the RES signal. The reset operation by RES ="L" initializes each resister setting as above reset status, but the internal oscillation circuit and output terminals (D0 to D15) are not affected. To avoid the lock-up, the reset operation by the RES terminal must be required every time when power terns on. Note1) The reset operation by the reset instruction, function 9 to 20 operations mentioned above is performed. Note2) The noise into the RES terminal should be eliminated to avoid the error on the application with the careful design. Note3) The RES terminal must be keep "L" level when the power terns on in not use of the built-in LCD power supply circuit for no affect to the internal execution.
NJU6682
(1-9) LCD Driving Circuit (a) LCD driver LCD driver is 292 sets of multiplexer consisting of 160 commons and 132 segments drivers to output the 4-level of LCD driving voltage. The common driver outputs the common scan signals formed with the shift register. The segment driver outputs the segment driving signal determined by a combination of display data in the DD RAM, common timing, FR signal, and alternating signal for LCD. The output wave forms of segment/common are shown in "LCD Driving Wave Form".
(b) Display Data Latch Circuit Display Data Latch Circuit latches the 132 x 2-bit display data outputted from the DD RAM addressed by the Line address counter to LCD driver at every common signal cycle temporarily. The original data in the DD RAM is not changed because of the Normal/Reverse display in Black & White display mode, Display On/Off, Whole Display / Normal Display instruction processes only stored data in this Display Data Latch Circuit. (c) Gray Scale / Black & White Control Circuit The Gray Scale control circuit selects the gray scale level data pointed by instruction out of 264 bits display data of the gray scale level signal in Display Data Latch Circuit and outputs to LCD driver Sn. The Black & White display control circuit selects a layer set by the instruction out of the 264 bits Black & White data latched in Display Data Latch Circuit and outputs to the LCD driver Sn. (d) Signal forming to Line Counter and Display Data Latch Circuit The count clock to Line Counter and the latch clock to Display Data Latch Circuit are formed using the internal display clock (CL). The display data of 132 x 2 bits from Display Data RAM pointed by the line address synchronizing with the internal display clock are latched into the Display Data Latch Circuit and are outputted to Gray Scale Control Circuit / Black & White Control Circuit. The display data read out operation from DD RAM to the LCD Driver Circuit is completely independent operation with an access to the display data RAM from MPU. (e) Display Timing Generation Circuit The display timing generation circuit generates the internal timing of the display system by the master clock and the internal FR signal. As for it, the internal FR signal and the LCD alternating signal generate the wave form of 2-frame alternating drive wave form or the n-line inverse drive method for the LCD Driving circuit. (f) FRC / PWM Control Circuit The FRC/PWM Control Circuit operates functions of Frame Rate Control (FRC) and Pulse Width Modulation (PWM) for the 4-level gray scale display.
NJU6682
(g) Common Timing Generator The Common Timing Generator generates the common timing signal from the internal display clock (CL ). Figure 2 shows display timing in Black & White mode.
159 160 CL
1
2
3
4
5
6
7
8
158 159 160
1
2
3
4
5
6
7
FR
VDD V1
C0
V4 V5 VDD V1
C1
V4 V5
RAM
DATA
VDD V2
Sn
V3 V5
Fig.2-1 2-frame alternating drive mode (line inverting register sets to 0)
159 160 CL
1
2
3
4
5
6
7
8
158 159 160
1
2
3
4
5
6
7
FR
VDD V1
C0
V4 V5 VDD V1
C1
V4 V5
RAM
DATA
VDD V2
Sn
V3 V5
Fig.2-2 n-line inverse drive mode (n=7, line inverting register sets to 6)
NJU6682
(h) Oscillation Circuits The Oscillation Circuit is a low power type CR oscillator using an internal resistor and capacitor. The oscillator output is using for the display timing clock and for the voltage booster circuit. And the display clock(CL) is generated from this oscillator output frequency by dividing. Table 2 Relationship between Duty ratio and Dividing Duty Divide Duty Divide Duty Divide
1/4 1/1200 1/8 1/600 1/12 1/405 1/16 1/300 1/20 1/240 1/24 1/195 1/28 1/165 1/32 1/150 1/36 1/135 1/40 1/120 1/44, 1/48 1/105 1/52, 1/56 1/90
1/60, 1/64, 1/68 1/75
1/72, 1/76, 1/80, 1/84, 1/88 1/60
1/92, 1/96, 1/100, 1/104, 1/108, 1/112, 1/116, 1/120 1/45
1/124, 1/128, 1/132, 1/136, 1/140, 1/144, 1/148, 1/152, 1/156, 1/160 1/30
(i) Power Supply Circuits The internal power supply circuit generates the voltage for driving LCD. 2 times to 7 times), voltage adjust circuits, and voltage followers.
It consists of voltage booster circuits (from
The internal power supply Circuits is designed specially for a small-size LCD like as normal cellular phone size LCD panel. When NJU6682 apply to the large size LCD panel application (large capacitive load), external power supply is required to keep good display condition.. To keep good display condition, external component of the capacitors connecting to the V1 to V5 terminals and voltage booster circuits and the feedback resistors for the V5 operational amplifier must fix each optimized constant after checking various display patterns on LCD panel actually in the application. The Internal Power Supply Circuits operation is controlled by Internal Power Supply Control Instruction.
A0 0
RD 1
WR 0
D15 0
D14 0
D13 0
D12 1
D11 0
D10 0
D9 0
D8 1
D7 *
D6 *
D5 *
D4 *
D3 *
D2 DC
D1 D0 VR VF *:Don't Care
DC : Voltage Booster Circuit DC = 1 : Booster Circuit ON + + DC = 0 : Booster Circuit OFF (In this time , terminals C1 ,C1 ,C2 ,C2 ,C3 ,C4 ,C5 and C6 should be open and LCD driving voltage should be supplied to VOUT terminal from outside) VR : Voltage Adjust Circuit VR = 1 : Adjust Circuit ON VR = 0 : Adjust Circuit OFF (In this time, terminal VR should be open, and V5 should be supplied from outside) VF : Voltage Follower VF = 1 : Voltage Follower ON VF = 0 : Voltage Follower OFF (In this time, LCD bias voltage V1 to V5 should be supplied to terminals V1 to V5 from outside. )
NJU6682
!Power Supply Circuits example (1) Internal Power Supply Example All of the Internal Booster, Voltage Adjust Circuit, Voltage Follower using. (DC, VR, VF) = (1, 1, 1)
VDD
(2) External Power Supply Example Only VOUT Supply from outside, Int. Voltage Adjust Circuit, Voltage Follower using. (DC, VR, VF) = (0, 1, 1)
VDD
NJU6682
NJU6682
C1+ C1C2+ C2C3C4C5C6+ + + + + + + + + + + V1 V2 V3 V4 V5 VOUT VSS VDD
+ + + + + +
V1 V2 V3 V4 V5 VOUT VSS VDD
VR
V5
VR
V5
(3) External Power Supply Example VOUT and V5 supply from outside, Internal Voltage Follower using. (DC, VR, VF) =
VDD
(4) External Power Supply Example All of V1 to V5 and VOUT supply from outside. (DC, VR, VF)
VDD
(0, 0, 1)
=
(0, 0, 0)
NJU6682
NJU6682
+ + + +
V1 V2 V3 V4 V5 VOUT VSS
V1 V2 V3 V4 V5 VOUT VSS
(Note)
: These switches should be open or external power supply stops in power-save mode.
NJU6682
(2) Instructions The NJU6682 distinguishes the data on the data bus D0 to D15 as an instruction by combination of A0, RD, and WR signals. The decoding of the instruction and exection performes with only high speed internal timing without relation to the external clock. In case of the serial interface, the data input as MSB(D15) first serially. Table.3 shows the instruction codes of the NJU6682 Table 3. Instruction Codes (*:Don't Care)
Code
Instruction
(a) Display ON/OFF (b) Display Start Line Address Set
A0 RD WR D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2
D1
D0
Description
LCD Display ON/OFF D0=0:OFF, D0=1:ON Determine the Line Address of DD RAM to the COM0 Set the Column Address of DD RAM Set the Row Address of DD RAM Read out the internal status Write the data into the DD RAM Read out the data from the DD RAM
0 0 0 0 0 1 1 0 0 0 0
1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0
0 0 0 0
0 1 1 1
0 0 0 0 Status
0 1 0 1
0 0 0 0
0 1 0 0
0
* Line Address
0/1
(c) Column Address Set (d) Row Address Set (e) Status Read (f) Write Display Data (g) Read Display Data (h) (i) Normal or Inverse Display Whole Display/ Normal Display
0
*
*
Column Address Row Address
0 Write Data Read Data
Status
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0
0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0
0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
0 1 0 0 1 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
1 0 0 1 0 1 0 1 0 * * * * *
* *
0/1 0/1
Normal or Inverse Display D0=0:Normal, D0=1:Inverse Whole Display Turns ON
D0=0:Normal, D0=1:Whole Display ON Set the Display Start Unit of Block1
Start Unit of 1st Block
Number of unit in 1st Block Set the Number of Display Unit in Block1 Start Unit of 2nd Block
nd
(j) Partial Display
0 0 0
Set the Display Start Unit of Block2
Number of unit in 2 Block Set the Number of Display Unit in Block2 * The Number of n-line Inverse EVR Register Data 0 Execute the Partial Display Set the n-line inverse number Set the V5 output level to the EVR register
Set the Row address of 1st Display block Set the line number of 1st Display block Set the Row address of 2nd Display block Set the line number of 2nd Display block Set the Row address of 3rd Display block Set the line number of 3rd Display block Set the Row address of 4th Display block Set the line number of 4th Display block Set the Row address of 5th Display block Set the line number of 5th Display block Set the Row address of 6th Display block Set the line number of 6th Display block Set the Row address of 7th Display block Set the line number of 7th Display block Set the Row address of 8th Display block Set the line number of 8th Display block
(k)
n-Line Inverse Register Set
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
(l) EVR Register Set
Row Address of 1st Display Block 0 0 * Line Number of 1 Block
st
Row Address of 2nd Display Block * Line Number of 2nd Block Row Address of 3rd Display Block 0 * Line Number of 3rd Block Row Address of 4th Display Block * Line Number of 4 Block Row Address of 5th Display Block 0 * Line Number of 5th Block 0 0 0 0 Row Address of 6 Display Block * Line Number of 6th Block Row Address of 7th Display Block * * Line Number of 7th Block
th th
0
th
Variable RAM (m) Mapping Mode
Row Address of 8 Display Block Line Number of 8th Block * 0/1
Variable RAM Mapping Mode D0=0:ON, D0=1:OFF
NJU6682
Code
Instruction
A0 RD WR D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 1 0 1 0 1 1 0 0 1 PWM Data (1st Frame) PWM Data (3rd Frame) PWM Data (1st Frame) PWM Data (3rd Frame) PWM Data (1st Frame) PWM Data (3rd Frame) PWM Data (1st Frame) PWM Data (3rd Frame) * * * * PWM Data (2nd Frame) PWM Data (4th Frame) PWM Data (2nd Frame) PWM Data (4th Frame) PWM Data (2nd Frame) PWM Data (4th Frame) PWM Data (2nd Frame) PWM Data (4th Frame) Bias
Description
Gray Scale Level 0: Set the Data for 1st and 2nd Frames Gray Scale Level 0: Set the Data for 3rd and 4th Frames Gray Scale Level 1: Set the Data for 1st and 2nd Frames Gray Scale Level 1: Set the Data for 3rd and 4th Frames Gray Scale Level 2: Set the Data for 1st and 2nd Frames Gray Scale Level 2: Set the Data for 3rd and 4th Frames Gray Scale Level 3: Set the Data for 1st and 2nd Frames Gray Scale Level 3: Set the Data for 3rd and 4th Frames Select the Bias (11 types) PWM PWM PWM PWM PWM PWM PWM PWM
Select (n) Gray Scale Level
0 0 0 0 0
(o) Bias Select (p) Boost level Select Read Modify Write (q) /End (r) Reset
0 0 0 0
Boost stage Set the Boost stage :2 to 7 times
Increase Column Address Counter +1 when
0/1 writing and no-change when reading D0=0:ON, D0=1:END 1 Initialize the internal circuits DC=1: Voltage Booster ON DC=0: Voltage Booster OFF VR=1: Voltage Regurator ON DC VR VF VR=0: Voltage Regurator OFF VF=1: Voltage Follower ON VF=0: Voltage Follower OFF LCD Driving wave form outputs ON/OFF 0/1 D0=0: LCD Driver Outputs OFF D0=1: LCD Driver Outputs ON Set the Power Save mode 0/1 (Display OFF + Static Drive ON) 0/1 Output the Display RAM address Sn D0=0:Normal, D0=1:Inverse
(s)
Internal Power Supply setting
0
1
0
0
0
0
1
0
0
1
0
*
(t)
LCD Driver Outputs ON/OFF Power Save (complex instruction)
0 0 0 0
1 1 1 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
1 0 0 1
0 0 0 1
0 0 0 0
1 0 1 0
1 0 0 0
*
(u)
* *
(v) ADC Select
(w) Display Mode Select
0
1
0
0
0
0
1
1
0
0
1
*
Set Display mode GB=1: Gray scale mode GB=0: Black and white mode GS L1 L0 L1=1: Select layer 1 L1=0: Not select layer 1 L0=1: Select layer 0 L0=0: Not select layer 0 * D8=0: Set 8-bit bus interface D8=1: Set 16-bit bus interface
(x)
8-/16-bit Bus Interface Select
0
1
0
0
0
0
1
1
0
1
0/1
(*:Don't Care)
NJU6682
(2-1) Descriptions of the Instruction Codes (a) Display ON/OFF Control It executes the ON/OFF control of the whole display without relation to the DD RAM or any internal conditions. A0 0 RD 1 D WR 0 D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 * D6 * D5 * D4 * D3 * D2 * D1 D0 * D *:Don't Care
0: Display OFF 1: Display ON
(b) Display Start Line Address Set (Refer to "Functional Description Fig. 1-1,1-2 DD RAM addressing") It sets the DD RAM line address corresponding to the COM0 terminal (normally assigned to the top display line). In this instruction execution, the display area is automatically set by the lines that correspond to the display duty ratio to the upward direction of the line address. Changing the line address by this instruction performs smooth scrolling to a vertical direction. In this time, the DD RAM data are unchanged. When variable RAM mapping mode is selected, this variable RAM mapping setting takes precedence over the line address setting and Line address Set instruction is ignored. A0 0 RD 1 WR 0 A8 0 0 D15 0 A7 0 0 D14 0 A6 0 0 D13 1 A5 0 0 D12 0 A4 0 0 : : : 1 1 D11 1 A3 0 0 D10 0 A2 0 0 D9 1 A1 0 0 D8 A8 A0 0 1 D7 A7 D6 A6 D5 A5 D4 A4 D3 A3 D2 A2 D1 A1 D0 A0
1 1
0 0
0 0
1 1
1 1
1 1
1 1
0 1
Start Line Address (HEX) 000 001 : : : 13E 13F
NJU6682
(c) Column Address Set (Refer to "Functional Description Fig. 1-1,1-2 DD RAM addressing") When MPU access to the DD RAM, a column address is set by Column Address Set instruction before writing the data. The DD RAM becomes accessible by setting both of column address and row address. (Note: the change of row address is not affected to the display.) The range of column address is determined by the display mode. In gray scale mode, the range of column address is 00H to 10H. In black & white mode, 00H to 08H(layer 0) and 20H to 28H(layer 1). Over range of column address setting is ignored. When the MPU access to the DD RAM continuously, the column address increments automatically from the set address after each data access. Therefore, the MPU can transmit only the Data continuously without setting the column address at every transmission time. The increment of column address is stopped at the maximum column address plus 1 limited by each display mode. When the column address count up is stopped, the row address is not changed. A0 0 RD 1 WR 0 D15 0 D14 0 D13 1 D12 0 D11 0 D10 0 D9 0 D8 0 D7 * D6 * D5 A5 D4 A4 D3 A3 D2 A2 D1 D0 A1 A0 *:Don't Care
A5 0 0 0 0 0 0 0
A4 0 0 0 0 0 0 1
A3 0 0 0 : : 1 : : 1 1 0 : : : :
A2 0 0 0 0 1 1 0
A1 0 0 1 0 1 1 0
A0 0 1 0 0 0 1 0
Column Address (HEX) Gray Scale Mode Black & White Mode 00 00 01 01 02 02 : : : : : 08 0E 0F 10 Layer 0
Address Set is Invalid
Address Set is Invalid 1 1 0 0 0 1 : : : 1 0 1 0 1 0
Layer 1
1 1
0 0
0 0
0 0
0 0
0 1
20 21 : : 27 28
Address Set is Invalid
NJU6682
(d) Row Address Set (Refer to "Functional Description Fig. 1-1,1-2 DD RAM addressing") When MPU accesses to the DD RAM , the row address set by Row Address Set instruction is required with the (c) Column Address Set before writing the data. A0 0 RD 1 WR 0 A8 0 0 1 1 D15 0 A7 0 0 0 0 D14 0 A6 0 0 0 0 D13 1 A5 0 0 1 1 D12 0 A4 0 0 : : 1 1 D11 1 A3 0 0 1 1 D10 0 A2 0 0 1 1 D9 0 A1 0 0 1 1 D8 A8 A0 0 1 0 1 D7 A7 D6 A6 D5 A5 D4 A4 D3 A3 D2 A2 D1 A1 D0 A0
Row Address (HEX) 000 001 : : 13E 13F
(e) Status Read This instruction reads out the intenal status of "BUSY", "ADC", "Display ON/OFF", "RESET", "GB", and "LY" described as follows. Even if 8-bit bus interface mode is selected, the status read instruction completes within one cycle only. A0 0 RD 0 WR D15 D14 1 BUSY ADC D13 D12 D11 GB D10 LY1 D9 LY0 D8 D7 D6 0 BUSY ADC D5 D4 D3 GB D2 LY1 D1 LY0 D0 0
ON/OFF RESET
ON/OFF RESET
BUSY
: BUSY=1 indicates internal circuits is operating or the Reset cycle. All instructions can be input after the BUSY status change to "0". : Indidates the correspondence of Column Address and Segment Driver. 0: Counterclockwise output (Inverse) Column Address 131-n <--->Segment Driver n 1: Clockwise output (Normal) Column Address n <--->Segment Driver n (Note) The data "0=Inverse" and "1=Normal" of ADC status is inverted with the ADC Select instruction of "1=Inverse" and "0=Normal".
ADC
ON/OFF : Indicates the display ON/OFF status. 0: Display "ON" 1: Display "OFF" (Note) The data "0=ON" and "1=OFF" of Display ON/OFF status is inverted with the Display ON/OFF instruction of "1=ON" and "0=OFF". RESET : Indicates the initializing period by RES terminal signal or Reset instruction. 0: Not Reset status 1: In the Reset status GB : Indicates the current Display Mode. 0: Black & White Mode 1: Gray Scale Mode : Indicates the status of Layer 1 when the Black & White Display Mode is selected. 0: Layer 1 is not selected 1: Layer 1 is selected : Indicates the status of Layer 0 when the Black & White Display Mode is selected. 0: Layer 0 is not selected 1: Layer 0 is selected
LY1
LY0
NJU6682
(f) Write Display Data It writes the data on the data bus into the DD RAM. Column Address increments automatically after data writing, therefore, the MPU can write the data into the DD RAM continuously without the address setting at every writing time once the starting address is set. A0 1 RD 1 WR 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 Write Data D6 D5 D4 D3 D2 D1 D0
(g) Read Display Data This instruction reads out the 16-bit data from DD RAM addressed by the row and the column Address. The column address automatically increments after the 16-bit data read out, therefore, the MPU can read the data from the DD RAM continuously without the address setting at every reading time once the starting address is set. Note that the dummy read is required just after setting the column address (see "(5-4) Access to the DD RAM and the Internal Register"). In the serial interface mode, the display data is unable to read out. A0 1 RD 0 WR 1 D15 D14 D13 D12 D11 D10 D9 D8 D7 Read Data D6 D5 D4 D3 D2 D1 D0
(h) Normal / Inverse Display It changes the display condition of normal or inverse for entire display area. The execution of this instruction does not change the display data in the DD RAM. A0 0 RD 1 WR 0 D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 1 D7 * D6 * D5 * D4 * D3 * D2 * D1 D0 * D *:Don't Care
Black & White Mode: D DD RAM="1" 0 (Normal) LCD ON 1 (Inverse) LCD OFF Gray Scale Mode: D DD RAM="00" 0 (Normal) Gray Scale Level 0 1 (Inverse) Gray Scale Level 3
DD RAM="0" LCD OFF LCD ON
DD RAM="01" Gray Scale Level 1 Gray Scale Level 2
DD RAM="10" Gray Scale Level 2 Gray Scale Level 1
DD RAM="11" Gray Scale Level 3 Gray Scale Level 0
NJU6682
(i) Whole Display / Normal Display This instruction turns all the pixels ON regardless the data stored in the DD RAM. In this time, the data in DD RAM are remained and unchanged. This instruction is executed prior to the "Normal or Inverse Display" Instruction. A0 0 RD 1 D WR 0 D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 1 D8 0 D7 * D6 * D5 * D4 * D3 * D2 * D1 D0 * D *:Don't Care
0: Normal Display 1: Whole Display Turns ON
When the "Static Drive ON" instruction is executed at Display OFF status, the NJU6682 operates in Power Save Mode. (Refer " Power Save Mode ") (j) Partial Display It selects two active display areas on the LCD Panel partially. The display area is divided to 40 units with four commons each and selected two display blocks by setting Unit number and number of Unit required (not overlap, not over than 40 units) to display on the LCD panel. These two display blocks are assigned optionally on the LCD panel. Duty selects an adapted ratio number corresponding to the total number of two display blocks automatically. Partial Display function adjusts the LCD driving voltage, Voltage boosting times and E.V.R level by the instruction to generate the optimum LCD driving voltage for display quality. As result, the operating current is reduced. - Display Unit Structure UNIT 0 UNIT 1 UNIT 2 UNIT 3 : : : UNIT 36 UNIT 37 UNIT 38 UNIT 39 132-segment - Partial Display instruction When Partial Display functions, both of Top Unit Number of display area (the Start Unit) and the number of the effective continuous unit (Display Unit) from the Start Unit for the first display block and the second. Attention that the first display block and the second definition must not be overlap of display area and not be over than 40 units in total. In case of whole display (1/160 duty), the first display block defines Start Unit=0 (0,0,0,0,0,0) and Display Unit = 40 (1,0,1,0,0,0) for all of display area selection. In this time, the definition of the second display block is ignored. In case of only the first block display, the second display block defines Start Unit=0 (0,0,0,0,0,0) and Display Unit = 0 (0,0,0,0,0,0) for no display area.
4-common x 40-unit = 160-common maximum
NJU6682
(1) Set the Start Unit of the 1st partial display block A0 0 RD 1 WR 0 D15 0 D14 0 D13 1 D12 1 D11 0 D10 0 D9 0 D8 0 D7 * D6 * D5 D D4 D D3 D D2 D D1 D D0 D
(2) Set the Display Unit Number of the 1st partial display block A0 0 RD 1 WR 0 D15 0 D14 0 D13 1 D12 1 D11 0 D10 0 D9 0 D8 1 D7 * D6 * D5 D D4 D D3 D D2 D D1 D D0 D
(3) Set the Start Unit of the 2nd partial display block A0 0 RD 1 WR 0 D15 0 D14 0 D13 1 D12 1 D11 0 D10 0 D9 1 D8 0 D7 * D6 * D5 D D4 D D3 D D2 D D1 D D0 D
(4) Set the Display Unit Number of the 2nd partial display block A0 0 RD 1 D WR 0 D15 0 D14 0 D13 1 D12 1 D11 0 D10 0 D9 1 D8 1 D7 * D6 * D5 D D4 D D3 D D2 D D1 D0 D D *:Don't Care
: The Start Unit (D:000000-100111), or the Display Unit Number(000000-101000)
By input following instruction, the duty ratio is changed automatically and executes the partial display function.
A0 0
RD 1
WR 0
D15 0
D14 0
D13 1
D12 1
D11 0
D10 1
D9 0
D8 0
D7 *
D6 *
D5 *
D4 *
D3 *
D2 *
D1 D0 * 0 *:Don't Care
(Notes) Attention followings due to prevent from mulfunction. - The input order of Partial Display instructions must follow above. - Prohibits the overlap of the 1st partial display block and the 2nd. - The Start Unit of the 1st partial display block must not be over 39. - The total Display Unit Number (the sum of the 1st and 2nd partial display block Unit Number) must not be over 40. - On the LCD panel, no active display area inserts between the 1st display block and the 2nd . However, the display data of the 1st display block and the 2nd must store continuously in the display data RAM.
NJU6682
Example of the Partial Display setting.
UNIT UNIT :
0 1
the 1st Block
UNIT 14 UNIT 15 : UNIT 28 UNIT 29 :
Display Area the 2nd Block
The above partial display condition is set as follows: (1) Set the Start Unit of the 1st partial display block to "0". A0 0 RD 1 WR 0 D15 0 D14 0 D13 1 D12 1 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0
(2) Set the Display Unit Number of the 1st partial display block to "2". A0 0 RD 1 WR 0 D15 0 D14 0 D13 1 D12 1 D11 0 D10 0 D9 0 D8 1 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 1 D0 0
(3) Set the Start Unit of the 2nd partial display block to "14". A0 0 RD 1 WR 0 D15 0 D14 0 D13 1 D12 1 D11 0 D10 0 D9 1 D8 0 D7 0 D6 0 D5 0 D4 0 D3 1 D2 1 D1 1 D0 0
(4) Set the Display Unit Number of the 2nd partial display block to "16". A0 0 RD 1 WR 0 D15 0 D14 0 D13 1 D12 1 D11 0 D10 0 D9 1 D8 1 D7 0 D6 0 D5 0 D4 1 D3 0 D2 0 D1 0 D0 0
(5) Execute the Partial Display. D8 A0 RD WR D15 D14 D13 D12 D11 D10 D9 0 1 0 0 0 1 1 0 1 0 0 The Duty is changed to 1/72 automatically. ( Duty = 1/UNIT x 4 ) D7 0 D6 0 D5 0 D4 1 D3 0 D2 0 D1 0 D0 0
Duty is changed automatically when Partial Display execution. But LCD Driving Voltage, Bias, Driving form like as 2-frame alternating driving or n-line inverse are not changed. Therefore, LCD Driver Output Off should operate before Partial Display execution for prevention of unexpected display, and Voltage Booster Select instruction, E.V.R Register Set, Bias Select and n-line Inverse Driving Set should set optimum conditions for good display in the mean time of Partial Display instruction execution. The optimum conditions should fix refering the result of actual display eveluation.
NJU6682
The Sequence about the Partial Display function
Driver Output OFF
Set a Start Unit of the first display unit
Set a number of Display Unit of the first
Partial Display Instruction
Set a Start Unit of the Second display unit
Set a number of Display Unit of the Second
Executes Partial Display Function
n-Line Inverse Set EVR Resister Set Bias Select Voltage Boosting
(Waiting Time)
Driver Outputs ON
(k) n-Line Inverse Resister Set (refer s Functional Description Fig.2-2 n-line Inverse alternative driving wave form) It sets a line number to inverse the polarity lof common driver and segment. Set a n-Line Inverse Resister A0 0 RD 1 WR 0 D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 1 D8 1 D7 * D6 * D5 A5 D4 A4 D3 A3 D2 A2 D1 D0 A1 A0 *:Don't Care
Inverse Line -(*) 2 3 : : : : 1 1 1 1 1 0 63 1 1 1 1 1 1 64 *When A5 to A0 are "000000", it set to 2-frame alternating drive mode.
A5 0 0 0
A4 0 0 0
A3 0 0 0
A2 0 0 0
A1 0 0 1
A0 0 1 0
(*) 2-frame alternating drive mode.
NJU6682
(l) EVR Resister Set It controls the voltage regulator circuit of the internal LCD power supply to adjust the LCD display contrast by changing the LCD driving voltage "V5". By data setting into the EVR register, the LCD driving voltage "V5" selects out of 201 steps of regulated voltage. The voltage adjustable range of "V5" is fixed by the external resistors. For details, refer the section "4-2) Voltage Adjust Circuit". A0 0 RD 1 WR 0 A7 0 1 1 D15 0 A6 0 D14 0 A5 1 D13 0 A4 1 : : 1 1 1 1 1 1 0 1 1 1 1 1 1 1 VLCD=VDD-V5 Set the EVR Register to FFH (1,1,1,1,1,1,1,1), if not use the EVR. D12 0 A3 0 D11 1 A2 1 D10 0 A1 1 D9 0 A0 1 D8 0 D7 A7 D6 A6 D5 A5 D4 A4 D3 A3 D2 A2 D1 A1 D0 A0
VLCD Low : : : High
NJU6682
(m) Variable RAM Mapping Mode In the variable RAM mapping mode, independent 8 blocks can be defined in the DD RAM. The variable RAM mapping functions to assign the RAM data unconsecutively selectable out of the above 8 blocks (at the maximum); therefore, replacing one part of the display data to another becomes easier (see Figure 3-1, 3-2, 4-1 and 4-2). it is possible to define the RAM area in a maximum of 8-blocks not to continue to display the screen. Therefore, it is easy to replace a part of the Display Data each other(Fig.3-1,3-2, 4-1,4-2). In the variable RAM mapping mode, Display Start Line Address determined by "2-1 (b) Start Line Address Set instruction" instruction becomes invalid, thus the vertical scroll function also becomes invalid with changing a Line Address will be unable. The number of the display line for each block is assignable from "1" to "63"; "0" is invalid in this command. And, it is available to define the Display Line Number of each blocks as, but it must not define as "0". If the total number of the display line exceeds the duty, the line data in excess of its duty is not displayed. The initialized state of the resistor regarding the variable RAM mapping is indefinite after reset.
1st Block Row Address
A
2nd Block Row Address 3rd Block Row Address 4th Block Row Address
1st Block Display Line Number
A B
B C D
2nd Block Display Line Number 3rd Block Display Line Number 4th Block Display Line Number 5th Block Display Line Number 6th Block Display Line Number 7th Block Display Line Number
C D E F G
5th Block Row Address 6th Block Row Address
E F
7th Block Row Address
H
G
8th Block Row Address
H
8th Block Display Line Number
Fig.3-1 Setup the Variable RAM Mapping Mode, and Address Map in the DD RAM
Fig.3-2 Actual Display Image
NJU6682
The Example of Variable RAM Mapping Mode
1st Block Row Address
A
1st Block Display Line Number
3rd Block Row Address
B
2nd Block Row Address=80H Row Address=100H
3rd Block Display Line Number
C D
Fig.4-1 The setup of Variable RAM Mapping Mode, and the Address Map
A C
A D
A C
B
B
B
Fig.4-2 The actual Display image when the 2nd Block Row-Address is changed like the sequence of "80"H -> "100"H -> "80"H
NJU6682
(1) Set the Row Address of the 1st Display Block A0 0 RD 1 WR 0 D15 0 D14 1 D13 0 D12 0 D11 0 D10 0 D9 0 D8 A D7 A D6 A D5 A D4 A D3 A D2 A D1 A D0 A
A: the Row Address of the 1st Display Block (0 to 319) (2) Set the Display Line Number of the 1st Display Block A0 0 RD 1 WR 0 D15 0 D14 1 D13 0 D12 0 D11 0 D10 0 D9 1 D8 0 D7 * D6 * D5 D D4 D D3 D D2 D D1 D0 D D *:Don't Care
D: the Display Line Number of the 1st Display Block (1 to 63) (3) Set the Row Address of the 2nd Display Block A0 0 RD 1 WR 0 D15 0 D14 1 D13 0 D12 0 D11 0 D10 1 D9 0 D8 A D7 A D6 A D5 A D4 A D3 A D2 A D1 A D0 A
A: the Row Address of the 2nd Display Block (0 to 319) (4) Set the Display Line Number of the 2nd Display Block A0 0 RD 1 WR 0 D15 0 D14 1 D13 0 D12 0 D11 0 D10 1 D9 1 D8 0 D7 * D6 * D5 D D4 D D3 D D2 D D1 D0 D D *:Don't Care
D: the Display Line Number of the 2nd Display Block (1 to 63) (5) Set the Row Address of the 3rd Display Block A0 0 RD 1 WR 0 D15 0 D14 1 D13 0 D12 0 D11 1 D10 0 D9 0 D8 A D7 A D6 A D5 A D4 A D3 A D2 A D1 A D0 A
A: the Row Address of the 3rd Display Block (0 to 319) (6) Set the Display Line Number of the 3rd Display Block A0 0 RD 1 WR 0 D15 0 D14 1 D13 0 D12 0 D11 1 D10 0 D9 1 D8 0 D7 * D6 * D5 D D4 D D3 D D2 D D1 D0 D D *:Don't Care
D: the Display Line Number of the 3rd Display Block (1 to 63) (7) Set the Row Address of the 4th Display Block A0 0 RD 1 WR 0 D15 0 D14 1 D13 0 D12 0 D11 1 D10 1 D9 0 D8 A D7 A D6 A D5 A D4 A D3 A D2 A D1 A D0 A
A: the Row Address of the 4th Display Block (0 to 319) (8) Set the Display Line Number of the 4th Display Block A0 0 RD 1 WR 0 D15 0 D14 1 D13 0 D12 0 D11 1 D10 1 D9 1 D8 0 D7 * D6 * D5 D D4 D D3 D D2 D D1 D0 D D *:Don't Care
D: the Display Line Number of the 4th Display Block (1 to 63)
NJU6682
(9) Set the Row Address of the 5th Display Block A0 0 RD 1 WR 0 D15 0 D14 1 D13 0 D12 1 D11 0 D10 0 D9 0 D8 A D7 A D6 A D5 A D4 A D3 A D2 A D1 A D0 A
A: the Row Address of the 5th Display Block (0 to 319) (10) Set the Display Line Number of the 5th Display Block A0 0 RD 1 WR 0 D15 0 D14 1 D13 0 D12 1 D11 0 D10 0 D9 1 D8 0 D7 * D6 * D5 D D4 D D3 D D2 D D1 D0 D D *:Don't Care
D5: the Display Line Number of the 5th Display Block (1 to 63) (11) Set the Row Address of the 6th Display Block A0 0 RD 1 WR 0 D15 0 D14 1 D13 0 D12 1 D11 0 D10 1 D9 0 D8 A D7 A D6 A D5 A D4 A D3 A D2 A D1 A D0 A
A: the Row Address of the 6th Display Block (0 to 319) (12) Set the Display Line Number of the 6th Display Block A0 0 RD 1 WR 0 D15 0 D14 1 D13 0 D12 1 D11 0 D10 1 D9 1 D8 0 D7 * D6 * D5 D D4 D D3 D D2 D D1 D0 D D *:Don't Care
D: the Display Line Number of the 6th Display Block (1 to 63) (13) Set the Row Address of the 7th Display Block A0 0 RD 1 WR 0 D15 0 D14 1 D13 0 D12 1 D11 1 D10 0 D9 0 D8 A D7 A D6 A D5 A D4 A D3 A D2 A D1 A D0 A
A: the Row Address of the 7th Display Block (0 to 319) (14) Set the Display Line Number of the 7th Display Block A0 0 RD 1 WR 0 D15 0 D14 1 D13 0 D12 1 D11 1 D10 0 D9 1 D8 0 D7 * D6 * D5 D D4 D D3 D D2 D D1 D0 D D *:Don't Care
D: the Display Line Number of the 7th Display Block (1 to 63) (15) Set the Row Address of the 8th Display Block A0 0 RD 1 WR 0 D15 0 D14 1 D13 0 D12 1 D11 1 D10 1 D9 0 D8 A D7 A D6 A D5 A D4 A D3 A D2 A D1 A D0 A
A: the Row Address of the 8th Display Block (0 to 319) (16) Set the Display Line Number of the 8th Display Block A0 0 RD 1 WR 0 D15 0 D14 1 D13 0 D12 1 D11 1 D10 1 D9 1 D8 0 D7 * D6 * D5 D D4 D D3 D D2 D D1 D0 D D *:Don't Care
D: the Display Line Number of the 8th Display Block (1 to 63)
NJU6682
Execute the Variable RAM Mapping Mode, by the following instruction.
A0 0
D1 D0 * 0 *:Don't Care Return to the normal display status from Variable RAM Mapping Mode by the following instruction execution. RD 1 WR 0 D15 0 RD 1 WR 0 D15 0 D14 1 D13 1 D12 0 D11 0 D10 0 D9 0 D8 0 D7 * D6 * D5 * D4 * D3 * D2 * D1 D0 * 1 *:Don't Care
D14 1
D13 1
D12 0
D11 0
D10 0
D9 0
D8 0
D7 *
D6 *
D5 *
D4 *
D3 *
D2 *
A0 0
NJU6682
(n) Gray Scale Level Select This instruction sets the 4 levels of the gray scale. The setting of each gray scale level is executed by writing the PWM data (0 to FH) to the four registers for the 1st to 4th frame. The glay scale level 0 corresponds to the data (0,0) of the DD RAM, the level 1 is the data (0,1), the level 2 is the data (1,0), and the level 3 is the data (1,1), respectively. After reset, 4 registers of each level of the gray scale, 16 registers totality, are initialized as follows. See the table below. PWM Data 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 HEX 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F Gray Scale Level 0/15 (initialized value of level 0) 1/15 2/15 3/15 4/15 5/15 (initialized value of level 1) 6/15 7/15 8/15 9/15 10/15 (initialized value of level 2) 11/15 12/15 13/15 14/15 15/15 (initialized value of level 3)
(1) Set the 1st and 2nd frame PWM Data for the Gray Scale Level 0. A0 0 RD 1 WR 0 D15 0 D14 1 D13 1 D12 1 D11 0 D10 0 D9 0 D8 0 D7 D1 D6 D1 D5 D1 D4 D1 D3 D2 D2 D2 D1 D2 D0 D2
D1: the PWM Data for the 1st Frame D2: the PWM Data for the 2nd Frame (2) Set the 3rd and 4th frame PWM Data for the Gray Scale Level 0. A0 0 RD 1 WR 0 D15 0 D14 1 D13 1 D12 1 D11 0 D10 0 D9 0 D8 1 D7 D3 D6 D3 D5 D3 D4 D3 D3 D4 D2 D4 D1 D4 D0 D4
D3: the PWM Data for the 3rd Frame D4: the PWM Data for the 4th Frame
NJU6682
(3) Set the 1st and 2nd frame PWM Data for the Gray Scale Level 1. A0 0 RD 1 WR 0 D15 0 D14 1 D13 1 D12 1 D11 0 D10 0 D9 1 D8 0 D7 D1 D6 D1 D5 D1 D4 D1 D3 D2 D2 D2 D1 D2 D0 D2
D1: the PWM Data for the 1st Frame D2: the PWM Data for the 2nd Frame (4) Set the 3rd and 4th frame PWM Data for the Gray Scale Level 1. A0 0 RD 1 WR 0 D15 0 D14 1 D13 1 D12 1 D11 0 D10 0 D9 1 D8 1 D7 D3 D6 D3 D5 D3 D4 D3 D3 D4 D2 D4 D1 D4 D0 D4
D3: the PWM Data for the 3rd Frame D4: the PWM Data for the 4th Frame (5) Set the 1st and 2nd frame PWM Data for the Gray Scale Level 2. A0 0 RD 1 WR 0 D15 0 D14 1 D13 1 D12 1 D11 0 D10 1 D9 0 D8 0 D7 D1 D6 D1 D5 D1 D4 D1 D3 D2 D2 D2 D1 D2 D0 D2
D1: the PWM Data for the 1st Frame D2: the PWM Data for the 2nd Frame (6) Set the 3rd and 4th frame PWM Data for the Gray Scale Level 2. A0 0 RD 1 WR 0 D15 0 D14 1 D13 1 D12 1 D11 0 D10 1 D9 0 D8 1 D7 D3 D6 D3 D5 D3 D4 D3 D3 D4 D2 D4 D1 D4 D0 D4
D3: the PWM Data for the 3rd Frame D4: the PWM Data for the 4th Frame (7) Set the 1st and 2nd frame PWM Data for the Gray Scale Level 3. A0 0 RD 1 WR 0 D15 0 D14 1 D13 1 D12 1 D11 0 D10 1 D9 1 D8 0 D7 D1 D6 D1 D5 D1 D4 D1 D3 D2 D2 D2 D1 D2 D0 D2
D1: the PWM Data for the 1st Frame D2: the PWM Data for the 2nd Frame (8) Set the 3rd and 4th frame PWM Data for the Gray Scale Level 3. A0 0 RD 1 WR 0 D15 0 D14 1 D13 1 D12 1 D11 0 D10 1 D9 1 D8 1 D7 D3 D6 D3 D5 D3 D4 D3 D3 D4 D2 D4 D1 D4 D0 D4
D3: the PWM Data for the 3rd Frame D4: the PWM Data for the 4th Frame
NJU6682
(o) Bias Select This instruction sets the bias voltage. ( 1/4 to 1/14 Bias ) A0 0 RD 1 WR 0 D15 0 D14 0 D13 0 D12 0 D11 1 D10 0 D9 0 D8 1 D7 * D6 * D5 * D4 * D3 A3 D2 A2 D1 D0 A1 A0 *:Don't Care
A3 0 0 0 0 0 0 0 0 1 1 1
A2 0 0 0 0 1 1 1 1 0 0 *
A1 0 0 1 1 0 0 1 1 0 0 1
A0 0 1 0 1 0 1 0 1 0 1 * * : Don't Care
Bias 1/4 1/5 1/6 1/7 1/8 1/9 1/10 1/11 1/12 1/13 1/14
(p) Boost Level Select This instruction sets the boost level (2 to 7 times). When "Partial Display Instruction" execution, the "Boost Level Select" also must be executed. If the external capasitors are connected as the lower than 6 times boost level, don't set the boost level by the instruction over than the boost level by conecting capasitors. If set the boost level over than it, the device will make malfunction. A0 0 RD 1 WR 0 D15 0 D14 0 D13 0 D12 0 D11 1 D10 0 D9 1 D8 0 D7 * D6 * D5 * D4 * D3 D2 D1 * A2 A1 *:Don't Care D0 A0
A2 0 0 0 0 1 1
A1 0 0 1 1 0 *
A0 0 1 0 1 0 1
Boost Level 2-times 3-times 4-times 5-times 6-times 7-times * : Don't Care
(q) Read Modify Write / End This instruction sets the Read Modify Write/End controlling the page address increment. In this mode, the Column Address only increments when execute the display data "Write" instruction; but no change when the display data "Read" Instruction. This status is continued until the End instruction execution. When the End instruction is executed, the Column Adddress goes back to the start address before the execution of this "Read Modify Write" instruction. This function reduces the load of MPU for repeating display data change of the fixed area (ex. cursor blink). A0 0 RD 1 WR 0 D15 0 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 * D6 * D5 * D4 * D3 * D2 D1 * * * : Don't Care D0 D
D=0: Read Modify Write ON D=1: End (Note) In this "Read Modify Write" mode, out of display dara "Read"/"Write", any instructions except "Row Address Set" can be executed.
NJU6682
The Example of Read Modify Write Sequence Executed Instructions Display Contents
(In 8-bit bus mode, indicates the column Address)
Executed Instructions
Row Address Set Column Address Set
Set the Start Address of the Cursor Display *1
N
N+1
N+2
N+3
Start the Read Mdify Read Modify Write Write The data is ignored
Dummy Read
Column Counter does't increase Data Read Column Counter does't increase Data Write Column Counter increase Dummy Read Data Read Data Write
N N+1 N+2 N+3
Read out the data The data is inversed at MPU Write back the data Repeat the same sequence
N
N+1
N+2
N+3
Column Counter doesn't increase
Column Counter doesn't increase Column Counter increase Column Counter doesn't increase Column Counter doesn't increase Column Counter increase Column Counter doesn't increase Column Counter doesn't increase Column Counter increase
Dummy Read Data Read Data Write
N
N+1
N+2
N+3
N+4
Dummy Read Data Read Data Write
N
N+1
N+2
N+3
N+4
End the Read Modify Write End No Column Counter reset to the value of *1
N
N+1
N+2
N+3
N+4
Finish ? Yes
NJU6682
(r) Reset This instruction executes the following initialization The reset by the reset signal input to the RES terminal (hardware reset) is required when power turns on. This reset instruction does not use instead of this hardware reset when power turns on. Initialization 1: Clear the data in the Selial Interface register. 2: Set the Column Address Counter to 00H. 3: Set the Row Address Resister to 000H. 4: Set the Line Address Counter to 000H 5: Set the Gray Scale Level ( refer to "(n)) 6: Normal RAM Address Mapping (Variable RAM Mapping Mode OFF). 7: Set the EVR Resister to FFH. 8: Set the Duty ratio to "1/160"(All ON). 9: Set the Bias ratio to "1/14". 10: Set the Booster Level to 7 times. 11: Set the n-Line Inverse Register to 0H. 12: Set the 8-bit Bus length for the interface The DD RAM is not affected in this Initialization. A0 0 RD 1 WR 0 D15 0 D14 0 D13 0 D12 1 D11 0 D10 0 D9 0 D8 1 D7 * D6 * D5 * D4 * D3 * D2 D1 * * * : Don't Care D0 D
The DD RAM is not affected in this instruction
(s) Internal Power Supply This instruction control ON and OFF for the internal Voltage Converter, Voltage Regulator and Voltage Follower circuits. For the Booster circuits operation, the oscillation circuits must be in operation. A0 0 RD 1 WR 0 D15 0 D14 0 D13 0 D12 1 D11 0 D10 0 D9 1 D8 0 D7 * D6 * D5 * D4 * D3 * D2 D1 D0 DC VR VF * : Don't Care
DC=1: Booster ON DC=0: Booster OFF*1) VR=1: Voltage Regulator ON VR=0: Voltage Regulator OFF*2) VF=1: Voltage Follower ON VF=0: Voltage Follower OFF*3) *1) At this time, terminals C1 ,C1 ,C2 ,C3 ,C4 ,C5 and C6 should be open, and supply the VOUT from outside. *2) At this time, terminal VR should be open, and supply the V5 from outside. *3) At this time, bias voltage of V1 to V5 should be supplied from outside. *The Internal Power Supply rise time is depending on the condition of the Supply Voltage, VLCD=VDD-V5, External Capacitor of Booster, and External Capacitor connected to V1 to V5. To know the rise time correctly, test by using the actual LCD module.
+ + -
NJU6682
(t) Driver Outputs ON/OFF This instruction controlls ON/OFF of the LCD Driver Outputs. A0 0 RD 1 WR 0 D15 0 D14 0 D13 0 D12 1 D11 0 D10 0 D2 D1 * * * : Don't Care D=0: Driver Outputs OFF(Signai is VDD level) D=1: Driver Outputs ON (Signal is output) D9 1 D8 1 D7 * D6 * D5 * D4 * D3 * D0 D
The NJU6682 implements low power LCD driving voltage generator circuit and requires the following Power Supply ON/OFF sequence. * LCD Driving Power Supply ON/OFF Sequences The sequences below are required when the power supply turns ON/OFF. For the power supply turning on operation after the power-save mode, refer the (u) "power save release sequence" mentioned after. Turn ON Sequence Turn OFF Sequence
Display OFF Static Drive ON Internal Power Supply ON
EVR Resister Set
Internal Power Supply OFF or External Power Supply OFF
(Wait Time)*1 Driver Outputs ON
Driver Outputs OFF NJU6682 Power OFF
*1 The Internal Power Supply rise time is depending on the condition of the Supply Voltage, VLCD=VDD-V5, External Capacitor of Booster, and External Capacitor connected to V1 to V5. To know the rise time correctly, test by using the actual LCD module.
NJU6682
(u) Power Save (complex comand) When Whole Display ON at the Display OFF status (inverse order also same), the internal circuits goes to the Power Save Mode and the operating current is dramatically reduced, almost same as the standby current. The internal status in the Power Save Mode is shown as follows; 1: The Oscillation Circuits and the Internal Power Supply Circuits stop the operation. 2: LCD driving is stopped. Segment and Common drivers output VDD level voltage. 3: The display data and the internal operating condition are remained and kept as just before enter the Power Save Mode. 4: All the LCD driving bias voltage (V1 to V5) is fixed to the VDD level.
Power Save Sequence *1
Display OFF
Power Save Release Sequence *2
Whole Display OFF Display ON (Wait Time)*3 Driver Outputs ON
Whole Display ON
Driver Outputs OFF
*4
*1 In the Power Save sequence, the Power Save Mode starts after the Static Drive ON command is executed. *2 In the Power Save Release sequence, the Power Save Mode releases just after the Static Drive OFF instruction execution. The Display ON instruction is allowed to execute at any time after the Static Drive OFF instruction is completed. *3 The Internal Power Supply rise time is depending on the condition of the Supply Voltage, VLCD=VDD-V5, External Capacitor of Booster, and External Capacitor connected to V1 to V5. To know the rise time correctly, test by using the actual LCD module *4 LCD driving waveform is output after the exection of the Driver Outputs ON instruction execution. *5 In case of the external power supply operation, the external power supply should be turned off before the Power Save Mode and connected to the VDD for fixing the voltage of Vout terminal.. In this time, VOUT terminal also should be made codition like as connection to the VSS terminal.
(v) ADC Select This instruction determines the correspondence of Column Address of the DD RAM with the Segment Driver Outputs.( refer to Fig.1-1 DD RAM addressing) Segment Driver Output order is inverse when this instruction executes, therefore, the placement the NJU6682 against the LCD panel becomes easy.
A0 0
RD 1
WR 0
D15 0
D14 0
D13 0
D12 1
D11 1
D10 0
D9 0
D8 0
D7 *
D6 *
D5 *
D4 *
D3 *
D2 D1 D0 * * D *:Don't Care
D=0: Clockwise Output (Normal) D=1: Counterclockwise Output (Inverting)
NJU6682
(w) Display Mode Select This instruction selects the Display Mode.
A0 0
RD 1
WR 0
D15 0
D14 0
D13 0
D12 1
D11 1
D10 0
D9 0
D8 1
D7 *
D6 *
D5 *
D4 *
D3 *
D2 D1 D0 GS L1 L0 *:Don't Care
GS=1: Gray Scale Mode GS=0: Black & White Mode * When GS=0(Black & White Mode), the following L1 and L0 bit are valid. L1=1: Select the Layer 1 L1=0: Not select the Layer 1 L0=1: Select the Layer 0 L0=0: Not select the Layer 0 If L1=L0=0, the display data becomes 0 And if L1=L0=1, the display data becomes logical OR of the Layer 0 and Layer 1. GS=1: Gray Scale Mode
(x) 8-/16-bit Bus Interface Select This instruction selects the 8-bit or 16-bit bus interface length. A0 0 RD 1 WR 0 D15 0 D14 0 D13 0 D12 1 D11 1 D10 0 D9 1 D8 D D7 * D6 * D5 * D4 * D3 * D2 D1 D0 * * * *:Don't Care
D=0: Select 8-bit bus interface length (D7 to D0). D=1: Select 16-bit bus interface length (D15 to D0)
NJU6682
(4) Internal Power Supply (4-1) 7-Time Voltage Booster circuits The 7-time voltage booster circuit outputs the negative Voltage(VDD Common) boosted 7 times of VDD-VSS from the + + + + + VOUT terminal with connecting the seven capacitors between C1 and C1 , C2 and C2 , C1 and C3 , C2 and C4 , C1 and + C5 , C2 and C6 ,and VSS and VOUT. The boosting time is selected out of 2 times to 7 by the combination of changing the external capacitors connection and "Boost Level Select" instruction. (refer to (2)Instruction (q)Voltage Boost time select) Voltage Booster circuits requires the clock signals from internal oscillation circuit or the external clock signal. therefore, the internal oscillation circuits or the external clock supplier must be operating when the voltage booster is in operation. The boosted voltage of VDD-VOUT must be 18V or less. The boost voltage and the capacitor connection are shown below.
VDD=+3V VSS=0V VOUT=-VDD=-3V VOUT=-2VDD=-6V VOUT=-3VDD=-9V VOUT=-4VDD=-12V VOUT=-5VDD=-15V VOUT=-6VDD=-15V VDD=+2.5V
2-Times
3-Times
4-Times
5-Times
6-Times
7-Times
; VDD=+2.5V for voltage limitation
7-Times Voltage
VSS C1+ C1C2+ C2C3C4C5C6VOUT + + + + + + +
6-Times Voltage
VSS C1+ C1C2+ C2C3+ C4C5C6VOUT + + +
5-Times Voltage
VSS C1+ C1C2+ +
+
C2+ C3C4C5C6VOUT
+ + +
+
4-Times Voltage
VSS C1+ C1C2+ C2C3C4C5C6VOUT +
3-Times Voltage
VSS C1+ C1C2+ + + + C2C3C4C5C6VOUT
2-Times Voltage
VSS C1+ C1+ C2+ + C2C3C4C5C6VOUT + +
+
NJU6682
(4-2)Voltage Adjust Circuit The boosted voltage of VOUT outputs V5 for LCD driving through the voltage adjust circuits. The output voltage of V5 is adjusted by Ra and Rb within the range of |V5| < |VOUT|. The output is calculated by the following formula(1). VLCD=VDD-V5=(1+Rb/Ra)*VREG ------------------------------------------(1)
The VREG voltage is a reference voltage generated by the built-in bleeder registance. VREG is adjustable by EVR functions (see section 4-3). For minor adjustment of V5, it is recommended that the Ra and Rb is composed of R2 as variable resistor and R1 and R3 as fixed resistors, constant should be connected to VDD terminal,VR and V5 ,as shown below. (refer to Fig.5)
VDD VREG Ra R1 VR R2 R3
+
VOUT
V5
Rb Fig.5 Voltage Adjust Circuit < Design example for R1, R2 and R3 /Reference > *R1+R2+R3=5M (Determind by the current between VDD-V5) *Variable voltage range by the R2. -7V to -11V (VLCD=VDD-V5 : 10V to 12V) (Determind by the LCD electrical characteristics) *VREG=3V (In case of VDD=3V and EVR=FFH) R1,R2 and R3 are calculated by above conditions and the fomula of(1) to below; R1=1.5M R2=0.3M R3=4.2M Note) V5 voltage is generated referencing with VREG voltage beased on the supply voltage (VDD and VSS) as shown in above Figure 5. Therefore, VLCD (VDD-V5) is affected including the gain (Rb/Ra) by the fluctuation of VREG voltage based on the supply voltage. The power supply voltage should be stabilized for V5 stable operation.
NJU6682
(4-3)Contrast adjustment by the EVR function The EVR selects the VREG voltage out of the following 201 conditions by setting 8-bit data into the EVR register. With the EVR function, VREG is controlled, and the LCD display contrast is adjusted. The EVR controls the voltage of VREG by instruction and changes the voltage of V5. A step with EVR is set like table shown below. * If keeping 3% precision set EVR over 4FH.
EVR register 37H 38H 39H : : : : FDH FEH FFH VREG (100/300) x (VDD-VSS) (101/300) x (VDD-VSS) (102/300) x (VDD-VSS) : : : : (298/300) x (VDD-VSS) (299/300) x (VDD-VSS) (300/300) x (VDD-VSS)
In use of the EVR function, the voltage adjustment circuit must turn on by the power supply instruction. q Adjustable range of the LCD driving voltage by EVR function The adjustable range is decided by the power supply voltage VDD and the ratio of external resistors Ra and Rb. < Design Example : NJU6682 > Condition:VDD=3.0V Ra=1M, Rb=4M (Ra:Rb=1:4) The adjustable range and step voltage are calculated as follows in the above condition. In case of setting 4FH in the EVR register, VLCD=(1+Rb/Ra) x VREG =(1+4) x (124/300) x 3.0 =6.2V In case of setting FF(H) in the EVR register, VLCD=(1+Rb/Ra) x VREG =(1+4) x (300/300) x 3.0 =15.0V
Adjusutment Renge ( VLCD) Step Voltage ( VLCD ) * In case of VDD=3V
(min.)4FH 6.2 50
(max.)FFH 15.0 [ V ] [ mV ]
NJU6682
(4-4)LCD Driving Voltage Generation Circuit The LCD driving bias voltage of V1,V2,V3,V4 are generated by dividing the VLCD(VLCD=VDD-V5) voltage with the internal bleeder resistance and is supplied to the LCD driving circuits after the impedence conversion by the voltage follower. As shown in Figure 6, five external capacitors are required to connect to each LCD driving voltage terminal for voltage stabilization. The value of capacitors (C7 to C11) should be determined after the actual LCD panel display evaluation. In case of Internal Power Supply
VSS + C1 C2 + C1+ C1C2+ C2-
In case of using External Power Supply
VSS C1+ C1C2+ C2-
+ Cout
C3 + +
C3C3C4C4C5C6NJU6682 Vout V5
C4
C5 + C6 +
C5-
C6Vout R3 V5
*2 NJU6682
*1
R2
VR
VR
R1 VDD VDD
+ + + + +
C7 C8 C9 C10 C11
V1 V2 External V3 V4 V5 Power Supply
V1 V2 V3 V4 V5
Fig.6 LCD Driving Voltage Generation Circuit Reference set up value VLCD=VDD-V59.0 to 10.5V *1 Short wiring or sealed wiring to the VR terminal is COUT to 1.0uF required due to the high impedance of VR Terminal. *2 Following connection of VOUT is required when external C1 to C6 to 1.0uF power supply using. C7 to C11 0.1 to 0.47 uF When VSS>V5 --- VOUT=V5 R1 2M When VSSV5 --- VOUT=VSS R2 500K
R3 2.5M
NJU6682
(5)MPU Interface (5-1) Interface type selection Two MPU interface types are available in the NJU6682: by 1) 8/16-bit bi-directional data bus (D15 to D0), 2) serial data input (SI:D7). The interface type (the 8/16 bit parallel or serial interface) is determined by the condition of the PS1 and PS0 terminals connecting to "H" or "L" level as shown in Table 5. In case of the parallel interface, the external bus line selection is set by the "8-bit/16-bit Bus Select" instruction. In case of the serial interface, neither the status read-out nor the RAM data read-out operation is allowed. Table 5
PS1 H PS0 * Parallel 16-bit Bus L H L Serial (4-wire) Serial (3-wire) Type 8-bit Bus CS CS CS CS A0 A0 A0 A0 * RD RD RD * WR WR WR * SEL68 SEL68 SEL68 * D15-D8 Hi-Z D15-D8 Hi-Z D7 D7 D7 SI D6 D6 D6 SCL D5-D0 D5-D0 D5-D0 Hi-Z
*:Don't care (5-2)Parallel interface(PS1="H") The NJU6682 interfaces the 68- or 80-type MPU directly if the parallel interface (PS1="H") is selected. The 68-type or 80-type MPU is selected by connecting the SEL68 terminal to "H" or "L" as shown in table 6. Table 6 CS RD WR SEL68 Type A0 D15-D8 D7-D0 CS H 68 type MPU A0 E R/W D7-D0 D15-D8 L 80 type MPU CS RD WR A0 D7-D0 D15-D8 - Interface operation with MPU The NJU6682 can be connected to MPU with the 8/16-bit interface: transferring data twice by 8-bit ,or Once by 16-bit. When the 8-bit bus interface is selected, data is transferred only through the D0-D7; the D8-D15 lines are not used with this interface. Then, the 8-bit data transmission is performed twice to complete the data transmission.. The data transmisson is executed through the upper 8 bits(D15-D8) and through the lower 8 bits(D7-D0), respectively. If checking the Busy Flag(status read) is required, it should be performed after the 2nd data transmission. In this case, the status read is completed only once. When 16-bit bus interface is selected, D0-D15 lines as 16-bit bus are used once to complete the data transmission.
(a) Interface with 8 bit MPU (8 bit BUS Interface Mode)
A0 Terminal WR Terminal RD Terminal D7 to D0 Terminal
Write Instruction BUSY Flag Check (Status read) Write Display Data Dummy Read Read Display Data
D15 to D8
D7 to D0
Status
D15toD8
D7 to D0
D15 to D8
D7 to D0
D15 to D8
D7 to D0
NJU6682
(b) Interface with 16 bit MPU (16 bit BUS Interface Mode)
A0 Terminal WR Terminal RD Terminal D15 to D8 Terminal D7 to D0 Terminal
Write Instruction BUSY Flag Check (Status read) Write Display Data Dummy Read Read Display Data
D15 to D8 D7 to D0
Status Status
D15 to D8 D7 to D0
D15 to D8 D7 to D0
D15 to D8 D7 to D0
(5-3) Serial Data Input (PS1="L") The serial interface of the NJU6682 consists of the 16-bit shift register and 4-bit counter. In case the chip is selected (CS=L), the input to D7(SI) and D6(SCL) becomes available, and in case that the chip isn't selected, the shift register and the counter are reset to the initial condition. The data input from the terminal(SI) is MSB first like as the order of D15, D14, *** D0 by a serial interface, it is entered into with rise edge of serial clock(SCL). The data converted into parallel data of 16-bit with the rise edge of 16th serial clock and processed. The serial interface of the NJU6682 can be selected out of the 3-wire or 4-wire type according to the PS0 terminal. In chosen PS0 terminal to "H", it becomes 4-wire interface and discriminates display data or instructions by A0 input terminal. A0 is read with rise edge of (16 X n)th of serial clock (SCL), it is recognized display data by A0=H" and instruction by A0="L". A0 input is read in the rise edge of (16 X n)th of serial clock (SCL) after chip select and distinguished. However,in case of RES="L" or CS="H" with trasfered data does not fill 16 bit, attention is necessary because it will processed as there was command input. Always, input the data of (16 X n) style. In chosen PS0 terminal to "L",it becomes 3-wire interface and discleminate data after the serial data of 16-bit as the A0 data. Note) The SCL signal must be careful of the termination reflection by the wiring length and the external noise and confirmation by the actual machine is recommended by it.
NJU6682
(a) 4-wired Serial Interface
CS First transfer data Next transfer data
SI
D15
D14
D13
D12
D1
D0
D15
D14
SCL
1
A0
2
3
4
15
16
17
18
Fig 7-1 4-wired Serial Interface (b) 3-wire Serial Interface CS
First transfer data
A0="H": Display Data A0="L": Instruction
Next transfer data
SI
D15
D14
D13
D12
D1
D0
A0
D15
SCL 1 2 3 4 15 16 17 18
Fig 7-2 3-wire Serial Interface
A0="1":Display Data A0="0":Instruction
(5-4)Display Data RAM , Access of Internal Register The NJU6682 transfers data to the CPU through the bus holder with the internal data bus. In case of reading out the display data contents in the DD RAM, the data which was read in the first data read cycle (= the dummy read ) is memorized in the bus holder. Then the data is read out to the system bus from the bus holder in the next data read cycle. Also, In case that the MPU writes into DD RAM, the data is temporarily stored in the bus holder and is then written into DD RAM by the next data write cycle. Therefore, the limitation of the access to NJU6682 from MPU side is not access time (tACC,tDS) of Display Data RAM and the cycle time becomes dominant. With this, speed-up of the data transfer with the MPU becomes possible. In case of cycle time isn't met, the MPU inserts NOP operation only and becomes an equivalent to an execution of wait operation on the sutisfy condition in MPU. When setting an address, the data of the specified address isn't output immediately by the read operation after setting an address, and the data of the specified address is output at the the 2nd data read operation. Therefore, the dummy read is always necessary once after the address set and the write cycle. (See Fig. 8) The exsample of Read Modify Write operaion is mentioned in (2-1) Description of the Instruction codesInstruction (q) " Read Modify Write / End" . )
NJU6682
q Write Operation
MPU
8bit bus Interface 16bit bus Interface
WR DATA (D7-D0) WR DATA (D15-D0) Bus-holder WR N N+1 N+2 N+3
N(High) N(Low) N+1(High) N+1(Low) N+2(High) N+2(Low) N+3(High) N+3(Low)
Internal Timing
N
N+1
N+2
N+3
q Read Operation
MPU WR RD DATA (D7-D0)
N(High) N(Low) N(High) N(Low) n(High) n(Low) n+1(High) n+1(Low)
8bit bus Interface
Address set (n)
Dummy read
Data Read (n)
Data Read (n+1)
WR
16bit bus Interface
RD DATA (D15-D0) N Address set (n) N Dummy read n Data Read (n) n+1 Data Read (n+1)
Internal Timing
WR RD X Address Bus-holder N N n N+1 n+1 N+2 n+2
Fig.8 Relation of Display Read/Write and Internal Timing
(5-5) Chip Select CS is the Chip Select terminal. In case of CS="L", the interface with MPU is available. In case of CS="H" (Chip is not selected), the terminals of D0 to D15 are high impedance and A0, RD, WR, D7(SI) and D6(SCL) inputs are ignored. If the serial interface is selected when CS="H", the shift register and the counter for the serial interface are reset. However, the reset signal is always input and executed in any conditions of CS.
NJU6682
sABSOLUTE MAXIMUM RATING PARAMETER Supply Voltage(1) Supply Voltage(2) Supply Voltage(3) Input Voltage Operating Temperature Strage Temperature TCP Chip SYMBOL VDD V5 , VOUT V1,V2,V3,V4 VIN TOPR TSTG RATINGS -0.3 to +5.0 VDD-20.0 to VDD+0.3 V5 to VDD+0.3 -0.3 to VDD+0.3 -30 to +80 -55 to +100 -55 to +125 UNIT V V V V C C
VDD VSS
VDD
V5
(* 1) Voltage value is specified as VSS=0V. (* 2) The relation of VDDV1V2V3V4V5VOUT ; VDD>VSSVOUT must be maintained. In case of inputting external LCD driving voltage , the LCD drive voltage should start supplying to NJU6682 at the mean time of turning on VDD power supply or after turned on VDD . In use of the voltage boost circuit, the condition that the supply voltage: 18.0VVDD-VOUT is necessary. (* 3) If the LSI are used on condition beyond the absolute maximum rating, the LSI may be destroyed. Using LSI within electrical characteristics is strongly recommended for normal operation. Use beyond the erectric characteristics conditions will cause malfunction and poor reliability. (* 4) Decoupling capacitor should be connected between VDD and VSS due to stabilized operation, especially for the Voltage Converter.
NJU6682
sELECTRICAL CHARACTERISTICS PARAMETER
Operating voltage(1) SYMBOL
CONDITIONS
VDD V5 Operating Voltage(2) V1,V2 V3,V4 Input High Level VIHC1 Voltage Low Level VILC1 Output High Level VHC11 Voltage Low Level VOLC11 Input Leagage Current ILI0
VLCD=VDD-V5 A0,D0-D15,RD,WR,RES,CS Exclude P/S, SEL68,OSC1 terminal D0toD1 IOH=-0.5mA Terminal IOL= 0.5mA All input terminal, D0 to D15 Terminal in High Z Ta=25C VLCD=15V During Power Save Mode Display VLCD=16V Access fCYC=200KHz Ta=25C VDD= 3.0V, Ta=25C RES terminal
(VDD=2.4 to 3.3V, VSS=0V, Ta=-30 to +80C) MIN TYP MAX UNIT NOTE 2.4 3.3 V 5 VDD-18.0V VDD-6.0V V 6 VDD-0.5VLCD VDD V5 VDD - 0.5VLCD 0.8VDD VDD V VSS 0.2VDD 0.8VDD VDD V VSS 0.2VDD -1.0 2.0 T.B.D T.B.D T.B.D 10 T.B.D 1.0 10 1.0 3.0 T.B.D T.B.D TBD A k A A A pF kHz S S 11 12 7 8 8 9 10
Driver On-resistance RON Stand-by Current Operating Current
In use external Power supply
IDDQ IDD01 IDD02 CIN fOSC tR tRW
Input Terminal Capacitance Oscillation Frequency Reset Time Reset "L" level pulse Width Voltage boost output voltage Voltage boost On-resistance Adjustment range of LCD driving Voltage Voltage Follower Operating Current
In use internal power supply
VOUT1 RTRI VOUT2 V5 IOUT1 VREG%
7-times boost, VDD=2.5V 7-times boost, VDD=2.5V,Cout=4.7F Voltage boost operation off Voltage adjustment circuit "OFF"
Display VDD=3V,VLCD=16V, 6-time boost COn/Sn are Open , non-access , Display Checkerd pattern
VDD-17.5V
VDD-17.0V 3.0
V k V V A % 14 13
VDD - 8.0V VDD - 18.0V 300
VDD - 6.0V VDD - 6.0V T.B.D T.B.D
Voltage Regulator
VDD=3.0V, Ta=25C
*5:Although the NJU6682 can operate in wide range of the operating voltage, it shall not be guaranteed in a sudden voltage fluctuation during the access with MPU. *6:The operating voltage when using external power supply. *7:RON is the resistance values in supplying 0.1V voltage-difference beteen power supply terminals (V1,V2,V3,V4) and each output terminals (common/ segment). This is specified within the range of Operating Voltage(2). *8,9:Refers to the current consumption of the IC itself; external power supply is used for the LCD driving. In case of not use internal power supply circuit,meaning current of IC's. LCD driving power supply are external power supply. *8,9:The value of after Driver Output On instruction execution. *8:Applicable in case of not accessing to the MPU. *9:The operating current when writing a vertical stripe pattern on the tcyc. Current consumption during the access is approximately proportional to the access frequency. When not accessed, it consumpts only IDD01. *10:Apply to A0,D0-D15,RD,WR,CS,RES,SEL68,PS0,PS1 terminals *11:tR ( Reset Time ) refers to the reset completion time of the internal circuits from the rise edge of the RES signal. *12:Apply minimum pulse width of the RES signal. To reset, the "L" pulse over tRW shall be input. . *13:The voltage adjustment circuit controls V5 within the range of the voltage follower operating voltage.
NJU6682
*14:Each operating current shall be defined as being measured in the following condition. POWER SUPPLY SET INSTRUCTION DC VR VF Internal Oscillator OPERATING CONDITION V/F Circuit Validity EXTERNAL VOLTAGE SUPPLY
(INPUT TERMINAL)
SYMBOL
Voltage Voltage Booster Adjustment Validity IDD1 1 1 1 Validity Validity (6-time boost) *LCD output terminals are open (No connection). *Display on,Display checkered pattern,No access from MPU *Set VLCD=16V *Set to R1+R2+R3=2M
Unuse
Measurement Block Diagram :IOUT1
R1 VR VDD R2 R2 V5
NJU6682 A
VSS C1C1+ C3C5C2C2+ C4C6VOUT
+
+
+
+ +
NJU6682
sBUS TIMING CHARACTERISTICS *Read/Write operation sequence(80 type MPU) tCYC8 A0 tr tAW8 WR,RD (CS) D0-D8 D0-D15 (16 bit BUS Mode) (Write) D0-D8 D0-D15 (16 bit BUS Mode) (Read) tACC8 tOH8 tCCL tDH8 tDS8 tf tAH8 tCCH
PARAMETER Address Hold Time Address Set up Time System Cycle Time (WRITE) System Cycle Time (READ)
SIGNAL A0,CS WR RD
SYMBOL tAH8 tAW8 tCYC8(W) tCYC8(R) tCCL(W) tCCL(R)
(VDD=2.4V to 3.3V, Ta=-30 to 80C) Measurement MIN TYP MAX UNIT Condition 0 0 160 360 50 250 110 30 5 CL=100pF 240 0 50 15 ns
Control Pulse Width (WR) Control Pulse Width (RD) Control "H" Pulse Width Data Set Up Time Data Hold Time Rdaccess Time Output Disable Time Rise Time / FallTime WR,RD D0 to D7 D8 to D15
tCCH tDS8 tDH8 tACC8 tOH8
CS,WR,RD tr, tf
*15 All timing based on 20% and 80% of VDD voltage level.
NJU6682
*System BUS Sequence (Read / Write) (68-type MPU) tCYC6 E tr tEWH R/W tAW6 A0,CS tAH6 tf tEWL
D0-D7, D8-D15 (16 bit BUS Mode) (Write) tACC6 D0-D7, D8-D15 (16 bit BUS Mode) (Read)
tDS6
tDH6
tOH6
PARAMETER Address Hold Time Address Set Up time System Cycle Time (WRITE) System Cycle Time (READ) Enable "H" Pulse Width READ WRITE
SIGNAL A0,CS R/W
SYMBOL tAH6 tAW6 tCYC6(W) tCYC6(R)
(VDD=2.4V to 3.3V, Ta=-30 to 80C) Measurement MIN TYP MAX UNIT Condition 0 0 160 360 250 50 110 30 5 CL=100pF 240 0 50 15 ns
E
tEWH tEWL
Enable "L" PilseWidth (READ/WRITE) Data Set Up Time Data Hold Time Access Time Output Disable Time Rise Time / Fall Time tr, tf
tDS6 tDH6 D0 to D7, D8 to D15 tACC6 tOH6 E
*16 All timing are based on 20% and 80% of VDD voltage level. *17 tCYC6 shows the cycle of the E signal in active CS.
NJU6682
*Serial Interfave tCSS CS tCSH
A0
tSAS
tSAH
SCL
tSCYC1 tSLW tSHW
SI
tf tSDS
tr tSDH
(VDD=2.4V to 3.3V, Ta=-30 to 80C) PARAMETER Instruction Input 19) Instruction Time* SCL"H" Pulse Width Serial Clock Cycle SCL"L" Pilse Width Address Set Up Time Address Hold Time Data Set Up Time Data Hold Time CS-SCLTime Rise Time / Fall Time SIGNAL SYMBOL tSCYC1 tSCYC2 tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH tf, tr Measurement Condition MIN 60 200 30 30 15 15 15 15 30 30 15 TYP MAX UNIT
SCL
A0 SI CS SCL
ns
*18 All timing are based on 20% and 80% of VDD voltage level. *19 When inputting an instruction continuously, keep 200nS as the cycle of SCL between the instructions as follows SCL 16 Clock(4-wire) th SCL 17 Clock(3-wire)
th
SCL 1 Clock
st
SCL tSCYC2 (200nS) SCL"L"Pulse Width (Instruction Time)
Instruction (n th)
Instruction (n+1 th)
NJU6682
sLCD Driving Wave Form (Black & White Mode)
VDD VSS VDD V1 V2 V3 V4 V5 VDD V1 V2 V3 V4 V5 VDD V1 V2 V3 V4 V5 VDD V1 V2 V3 V4 V5 VDD V1 V2 V3 V4 V5 V5 V4 V3 V2 V1 VDD -V1 -V2 -V3 -V4 -V5 V5 V4 V3 V2 V1 VDD -V1 -V2 -V3 -V4 -V5
FR
C0 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C12 C11 C13 C14 C15 S4 S3 S2 S1 S0 S1 C0-S0 C0-S1
C1
C2
S0
NJU6682
sAPPLICATION CIRCUIT MPU Interface Example NJU6682 can direct connection with 80 type MPU and 68 type MPU. Moreover, with to use a serial interface, it is possible to control by the signal line with the more small being. *SEL68 terminal should be connect VDD or VSS
q80 type MPU
VCC
A0 A1 - A15
A0
VDD SEL68
Decoder
CS NJU6682 D0 - D7 D8 - D15 RD WR RES VSS PS1 VDD
CPU
IORQ D0 - D7 D8 - D15 RD WR GND RES RESET
PS0
q68 type MPU
VDD SEL68
VCC
A0 A1 - A15
A0
VDD
CPU
VMA D0 - D7 D8 - D15 E R/W GND RES
Decoder
CS NJU6682 D0 - D7 D8 - D15 E R/W RES VSS PS1 VDD
PS0
RESET
qSerial Interface (4-Wire)
VDD SEL68
VCC
A0 A1 - A7
A0
VDD
CPU
Port 1 Port 2
Decoder
CS NJU6682 D7(SI) D6(SCL) PS1 VDD
PS0 GND RES RESET RES VSS
NJU6682 MEMO
[CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.

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