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| Datasheet File OCR Text: |
| SEG61 SEG62 SEG63 SEG64 V5 V2 V3 VSS VDD IOB2 SHL1 SHL2 SEG32 SEG31 SEG30 SEG29 ! PIN CONFIGURATION SEG60 SEG61 SEG62 SEG63 SEG64 V5 V2 V3 VSS VDD IOB2 SHL1 SHL2 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 64 65 80 1 60 61 80 1 NJU6417CFG1 NJU6417CFC1 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 41 40 21 20 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 25 24 41 40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 LM LP SCL IOA1 IOB1 NC NC IOA2 SEG1 SEG2 SEG3 SEG4 SEG5 SEG36 SEG35 SEG34 SEG33 LM LP SCL IOA1 IOB1 NC NC IOA2 SEG1 SEG2 SEG3 SEG4 NJU6417C NJU6417C ! TERMINAL DESCRIPTION No. FC1 128 3768 7780 29 33 32 74 FG1 125 3465 7480 26 30 29 71 SYMBOL SEG1SEG64 IOA2 IOA1 IOB1 IOB2 FUNCTION LCD segment driving terminal. Each terminal corresponds to each bit of shift register. Data input/output terminals for 1 to 32 bits shift register. Display data is input (output) synchronized with clock pulse. Input or output is selected by SHL1 terminal. rd th Data input/output terminals for 33 to 64 bits shift register. Display data is input (output) synchronized with clock pulse. Input or output is selected by SHL2 terminal. Shift register clock pulse input terminal. The data is shifted in the shift register by the falling edge of the clock pulse. A data setup time and hold time are required between data input and SCL. Clock pulse rising time (TRS) and falling time (TFS) should be set less than 50ns respectively. Latch pulse input terminal. The data in the shift register is latched to the latch by this signal. "H" : Data writing, "L" : Data latch Alternate signal input for LCD driving. LCD driving power source terminals. VDD V2 V3 V5, VDD VSS V5 Power supply terminal (connect to the controller's VSS terminal) Power supply terminal (connect to the controller's VDD terminal) Shift direction and input/output control terminal (Pull-up R) st nd "H" or Open : Shift direction is from 1 bit to 32 bit. nd st "L" : Shift direction is from 32 bit to 1 bit. Shift direction and input/output control terminal (Pull-up R) rd th "H" or Open : Shift direction is from 33 bit to 64 bit. th rd "L" : Shift direction is from 64 bit to 33 bit. Non connection. st nd 34 31 SCL 35 36 69,70, 71 72 73 75 32 33 66,67, 68 69 70 72 LP LM V5, V2, V3 VSS VDD SHL1 76 30,31 73 27,28 SHL2 NC NJU6417C MEMO [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. |
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