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NCP800 Lithium Battery Protection Circuit for One Cell Battery Packs
The NCP800 resides in a lithium battery pack where the battery cell continuously powers it. In order to maintain cell operation within specified limits, this protection circuit senses cell voltage and discharge current, and correspondingly controls the state of two, N-channel, MOSFET switches. These switches reside in series with the negative terminal of the cell and the negative terminal of the battery pack. During a fault condition, the NCP800 open circuits the pack by turning off one of these MOSFET switches, which disconnects the current path.
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2 1
3 4
5
6
TSOP-6 SN SUFFIX CASE 318G
BAEyw
* * * * *
Internally Trimmed Precision Charge and Discharge Voltage Limits Discharge Current Limit Detection Automatic Reset from Discharge Current Faults Low Current Standby State when Cells are Discharged Available in a Low Profile Surface Mount Package
y = Year w = Week
PIN CONNECTIONS
DO 1 P- 2 CO 3 (Top View) 6 Gnd 5 Vcell 4 Ct
5
ORDERING INFORMATION
Device NCP800 NCP800SN1T1 Package TSOP-6 Shipping 3000 Units/Rail
6 4
1
3
2
Figure 1. Typical One Cell Smart Battery Pack This device contains 169 transistors.
(c) Semiconductor Components Industries, LLC, 2001
1
April, 2001 - Rev. 4
Publication Order Number: NCP800/D
NCP800
Vcell 5
Ct 4 VD1 VD2 VD3
Level Shift VD1 10 kOhm
Standby/Reset
Delay VD2
Short Circuit Detector
VD3
Rshort
6 Gnd
1 Do
3 Co
2 P-
Figure 1. Detailed Block Diagram
PIN FUNCTION DESCRIPTION
Pin 1 2 Symbol DO P- Description This output connects to the gate of the discharge MOSFET allowing it to enable or disable battery pack discharging.
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This pin monitors cell discharge current. The excess current detector sets when the combined voltage drop of the charge MOSFET and the discharge MOSFET exceeds the discharge current limit threshold voltage, V(DET3). The short circuit detector activates when V(P-) is pulled within typically 0.85 V of the Vcell voltage. The CO driver is level shifted to the voltage at this pin. This output connects to the gate of the charge MOSFET switch Q1 allowing it to enable or disable battery pack charging. This pin connects to the external capacitor for setting the output delay of the overvoltage detector (VD1). 3 4 5 6 CO Ct Vcell Gnd This input connects to the positive terminal of the cell for voltage monitoring and provides operating bias for the integrated circuit. This is the ground pin of the IC.
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MAXIMUM RATINGS
Ratings Supply Voltage (Pin 5 to Pin 6) Symbol VDD VP- VCt Value -0.3 to 12 Unit V V
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Input Voltage Charge Gate Drive Common/Current Limit (Pin 5 to Pin 2) Overvoltage Delay Capacitor (Pin 4 to Pin 6) Output Voltage CO Pin Voltage (Pin 3 to Pin 2) DO Pin Voltage (Pin 1 to Pin 6) V(pin5) + 0.3 to V(pin 5) - 8 0.3 to 12 V(pin5) + 0.3 to V(pin 5) - 8 -0.3 to 12 250 V VCO VDO Thermal Resistance, Junction-to-Air SN Suffix, TSOP-6 Plastic Package, Case 318G Operating Junction Temperature Storage Temperature RJA TJ C/W C C -40 to 85 Tstg -55 to 125 1. This device contains ESD protection: Human Body Model 2000 V. Machine Model Method 200 V.
ELECTRICAL CHARACTERISTICS (TA = 25C, unless otherwise noted.)
Characteristic VOLTAGE SENSING Overvoltage Threshold, VDD Increasing (Note 2.) Overvoltage Hysteresis VDD Decreasing Overvoltage Delay Time Ct = 560 pF Ct = 0.01 F Undervoltage Threshold, VDD Decreasing Undervoltage Delay Time (VDD = 3.6 V to 2.4 V) VDET2 tDET2 VDET1 VHYS1 tDET1 2 - 2.437 7.0 4 75 2.5 11 6 - 2.563 13 V ms 4.30 150 4.35 200 4.40 250 V mV ms Symbol Min Typ Max Unit
CURRENT SENSING
Excess Current Threshold (Detect rising edge of P- pin voltage) (Note 3.) Short Protection Voltage (VDD = 3.0 V)
VDET3
170
200
230
mV V
VSHORT tDET3 tSHORT
VDD - 1.1 9.0 - 50
VDD - 0.85 14 10 100
VDD - 0.5 17 - 150
Current Limit Delay Time (VDD = 3.0 V) Reset Resistance OUTPUTS
ms s kW
RSHORT
Charge Gate Drive Output Low (Pin 3 to Pin 2) (VDD = 4.4 V, Io = 50 A)
Vol1
-
0.16 3.8 0.1 3.8
0.5 - 0.5 -
V V V V
Charge Gate Drive Output High (Pin 5 to Pin 3) (VDD = 3.9 V, Io = -50 A) Discharge Gate Drive Output Low (Pin 1 to Pin 6) (VDD = 2.4 V, Io = 50 A) Discharge Gate Drive Output High (Pin 5 to Pin 1) (VDD = 3.9 V, Io = -50 A)
Voh1 Vol2 Voh2
3.4 - 3.4
TOTAL DEVICE
Supply Current Operating (VDD = 3.9 V, VP- = 0 V) Standby (VDD = 2.0 V) Operating Voltage
Icell
2.0 - 1.5
4.0 0.3 -
6.0 0.6 10
A A V
VDD
2. Consult factory about other Overvoltage Threshold Options. 3. Consult factory about other Excess Current Threshold Options.
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UNDERVOLTAGE THRESHOLD VDET2 (V) 10 20 30 40 50 60 70 80 90 OVERVOLTAGE THRESHOLD VDET1 (V) 4.40 4.39 4.38 4.37 4.36 4.35 4.34 4.33 4.32 4.31 4.30 -40 -30 -20 -10 0 2.55 2.54 2.53 2.52 2.51 2.50 2.49 2.48 2.47 2.46 2.45 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
TA, AMBIENT TEMPERATURE (C)
TA, AMBIENT TEMPERATURE (C)
Figure 2. Overvoltage Threshold vs. Temperature
SHORT PROTECTION THRESHOLD VShort (V) EXCESS CURRENT THRESHOLD VDET3 (V)
Figure 3. Undervoltage Threshold vs. Temperature
0.230 0.225 0.220 0.215 0.210 0.205 0.200 0.195 0.190 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 VDD = 3.0 V
2.20 VDD = 3.0 V 2.15
2.10
2.05
2.00 -40 -30 -20 -10 0
10 20 30 40 50 60 70 80 90
TA, AMBIENT TEMPERATURE (C)
TA, AMBIENT TEMPERATURE (C)
Figure 4. Excess Current Threshold vs. Temperature
120 110 100 90 80 70 60 50 40 30 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 C3 = 0.01 F VDD = 3.6 V to 4.5 V OUTPUT DELAY OF UNDERVOLTAGE tDET2 (ms) OUTPUT DELAY OF OVERVOLTAGE tDET1 (ms) 13
Figure 5. Short Protection Threshold vs. Temperature
12
VDD = 3.6 V to 2.4 V
11
10
9 -40 -30 -20 -10 0
10 20 30 40 50 60 70 80 90
TA, AMBIENT TEMPERATURE (C)
TA, AMBIENT TEMPERATURE (C)
Figure 6. Output Delay of Overvoltage vs. Temperature
Figure 7. Output Delay of Undervoltage vs. Temperature
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OUTPUT DELAY OF EXCESS CURRENT tVDET3 (ms) 17 100 90 80 70 60 50 40 30 20 10 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 C2 not used C2 = 0.22 F
16 15 14 13 VDD = 3.0 V VP- = 0 V to 0.24 V
12 11
10 9 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
OUTPUT DELAY OF SHORT CIRCUIT DETECTOR tSHORT (s)
TA, AMBIENT TEMPERATURE (C)
TA, AMBIENT TEMPERATURE (C)
OVERVOLTAGE THRESHOLD HYSTERESIS VHYS1 (V)
Figure 8. Output Delay of Excess Current vs. Temperature
Figure 9. Output Delay of Short Circuit Detector vs. Temperature
0.25 OPERATING CURRENT Icell (A) 0.24 0.23 0.22 0.21 0.20 0.19 0.18 0.17 0.16 0.15 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
6 5.5 5 4.5 4 3.5 3 -40 -30 -20 -10 0 VDD = 3.9 V VP- = 0 V
10 20 30 40 50 60 70 80 90
TA, AMBIENT TEMPERATURE (C)
TA, AMBIENT TEMPERATURE (C)
Figure 10. Overvoltage Threshold Hysteresis vs. Temperature
0.40 STANDBY CURRENT Icell (A) Cout Nch DRIVER ON VOLTAGE (VOL1 (V)) 0.20 0.19 0.18 0.17 0.16 0.15 0.14 0.13 0.12 0.11 0.10 -40
Figure 11. Operating Current vs. Temperature
0.35
VDD = 2.0 V
IOL = 50 A VDD = 4.4 V
0.30
0.25
0.20
0.15 -40 -30 -20 -10 0
10 20 30 40 50 60 70 80 90
-20
0
20
40
60
80
TA, AMBIENT TEMPERATURE (C)
TA, AMBIENT TEMPERATURE (C)
Figure 12. Standby Current vs. Temperature
Figure 13. Cout Nch Driver On Voltage vs. Temperature
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Dout Nch DRIVER ON VOLTAGE (VOL2 (V)) 0.12 0.11 0.10 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0.00 -40 -30 -20 -10 0 IOL = 50 A VDD = 2.4 V Cout Pch DRIVER ON VOLTAGE (VOH1 (V)) 3.90 3.88 3.86 3.84 3.82 3.80 3.78 3.76 3.74 3.72 3.70 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 IOH = -50 A VDD = 3.9 V
10 20 30 40 50 60 70 80 90
TA, AMBIENT TEMPERATURE (C)
TA, AMBIENT TEMPERATURE (C)
OUTPUT DELAY OF SHORT PROTECTION tSHORT (s)
Figure 14. Dout Nch Driver On Voltage vs. Temperature
Figure 15. Cout Pch Driver On Voltage vs. Temperature
Dout Pch DRIVER ON VOLTAGE (VOH2 (V))
3.90 3.88 3.86 3.84 3.82 3.80 3.78 3.76 3.74 3.72 3.70 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 IOH = -50 A VDD = 3.9 V
200 180 160 140 120 100 80 60 40 20 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 CAPACITANCE C2 (F)
TA, AMBIENT TEMPERATURE (C)
Figure 16. Dout Pch Driver On Voltage vs. Temperature
OUTPUT DELAY OF EXCESS CURRENT tDET3 (ms) 22 20 18 16 14 12 10 8 6 4 2 0 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 EXCESS CURRENT THRESHOLD VDET3 (V) 0.210 0.209 0.208 0.207 0.206 0.205 0.204 0.203 0
Figure 17. Short Protection Delay Time vs. Capacitance C2
500
1000
1500
2000
2500
3000
SUPPLY VOLTAGE VDD (V)
EXTERNAL RESISTANCE R1 ()
Figure 18. Excess Current Delay Time vs. VDD
Figure 19. Excess Current Threshold vs. External Resistance R2
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NCP800
OVERVOLTAGE THRESHOLD VDET1 (V) 4.343 4.342 4.341 4.340 4.339 4.338 4.337 4.336 4.335 100 200 300 400 500 600 700 800 900 1000 C1 = 0.22 F C1 = 0.01 F C1 = 0.1 F
EXTERNAL RESISTANCE R1 ()
Figure 20. Overvoltage Threshold vs. External Resistance R1
OPERATING DESCRIPTION
VD1 / Over-Charge Detector
VD1 monitors the voltage at the VCELL pin (VDD). When it exceeds the over-charge detector threshold, VDET1. VD1 senses an over-charging condition, the CO pin goes to a "Low" level, and the external charge control, Nch-MOSFET turns off. Resetting VD1 allows resumption of the charging process. VD1 resets under two conditions, thus, making the CO pin level "High." The first case occurs when the cell voltage drops below "VDET1-VHYS1." (VHYS1 is typically 200 mV). In the second case, disconnecting the charger from the battery pack can reset VD1 after VDD drops between "VDET1" and "VDET1-VHYS1". After detecting over-charge, connecting a load to the battery pack allows load current to flow through the parasitic diode of the external charge control FET. The CO level goes "High" when the cell voltage drops below VDET1 due to load current draw through the parasitic diode. An external capacitor connected between the Gnd pin and Ct pin sets the output delay time for over-charge detection. The external capacitor sets up a delay time from the moment of over-charge detection to the time CO outputs a signal, which enables the charge control FET to turn off. If the voltage fault occurs within the time delay window. CO will not turn off the charge control FET. The output delay time can be calculated as follows:
t [sec] + (Ct[F] DET1 (VDD[V] * 0.7) (0.48 10 *6)
Nch MOSFET turns off. The IC enters a low current standby mode after detection of an over-discharged voltage by VD2. Supply current then reduces to approximately 0.3 A. During standby mode, only the charger detector operates. VD2 can only reset after connecting the pack to a charger. While VDD remains under the over-discharge detector threshold, VDET2, discharge current can flow through the parasitic diode of the external discharge control FET. The DO level goes "High" when the cell voltage rises above VDET2 due to the charging current through the parasitic diode. Connecting a charger to the battery pack will instantly set DO "High" if this causes VDD to rise above VDET2. Output delay time for the over-discharge detection (tDET2) is fixed internally. If the voltage fault occurs within the time delay window, DO will not turn off the discharge control FET. A CMOS buffer sets the output of the DO pin to a "High" level of VDD and a "Low" level of Gnd.
VD3 / Excess Current Detector, Short Circuit Detector
A level shifter incorporated in a buffer driver for the CO pin drives the "Low" level of CO pin to the P- pin voltage. A CMOS buffer sets the "High" level of CO pin to VDD.
VD2 / Over-Discharge Detector
VD2 monitors the voltage at the VCELL pin (VDD). When it drops below the over-discharge detector threshold, VDET2, VD2 senses an over-discharge condition, the DO pin goes to a "Low" level, and the external discharge control
Both the excess current detector and the short circuit detector can work when the two control FET's are on. When the voltage at the P- pin rises to a value between the short circuit protection voltage, VSHORT, and the excess current threshold, VDET3, the excess current detector operates. Increasing V(P-) higher than VSHORT enables the short circuit detector. The DO pin then goes to a "Low" level, and the external discharge control Nch MOSFET turns off. Output delay time for excess current detection (tDET3) is fixed internally. If the excess current fault occurs within the time delay window, DO will not turn off the discharge control FET. However, when the short circuit protector is enabled, DO can turn off the discharge control FET. Its delay time is approximately 10 s. The P-pin has a built-in pull down resistor, typically 100 kW, which connects to the Gnd pin. Once an excess current or short circuit fault is removed, the internal resistor
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NCP800
pulls V(P-) to the Gnd pin potential. Therefore, the voltage from P- to Gnd drops below the current detection thresholds and DO turns the external MOSFET back on. NOTE: If VDD voltage is higher than the over-discharge voltage threshold, VDET2, when excess current is detected the IC will not enter a standby mode. However, if VDD is below VDET2 when excess current is detected, the IC will enter a standby mode. This will not occur when the short circuit detector activates.
Figure 21. Timing Diagram / Operational Description
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+ R1 100 W
C1 0.1 F 4 C3 0.01 F
5
NCP800
2
6
1
3
C2 0.22 F
R2 1 kW -
Figure 22. Typical Application Circuit Technical Notes
R1 and C1 will stabilize a supply voltage to the NCP800. A recommended R1 value is less than 1 kW. A larger value of R1 leads to higher detection voltage because of shoot through current into the IC. R2 and C2 stabilize P- pin voltage. Larger R2 values could possibly disable reset from over-discharge by connecting a charger. Recommended values are less than 1 kW. After an over-charge detection even connecting a battery pack to a system could probably not allow a system to draw load current if one uses a larger R2C2 time constant. The recommended C2 value is less than 1 F. R1 and R2 can operate as a current limiter against setting cell reverse direction or for applying excess charging voltage to the IC and battery pack. Smaller R1 and R2 values may cause excessive power consumption over the specified power dissipation rating. Therefore R1 + R2 should be more than 1 kW. The time constants R1C1 and R2C2 must have a relation as follows: R1C1 R2C2 If the R1C1 time constant for the Vcell pin is larger than the R2C2 time constant for the P- pin, the IC might enter a standby mode after detecting excess current. This was noted in the operating description of the current detectors.
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Notes
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Notes
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PACKAGE DIMENSIONS
TSOP-6 SN SUFFIX CASE 318G-02 ISSUE G
A L
6 5 1 2 4 3 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. DIM A B C D G H J K L M S MILLIMETERS MIN MAX 2.90 3.10 1.30 1.70 0.90 1.10 0.25 0.50 0.85 1.05 0.013 0.100 0.10 0.26 0.20 0.60 1.25 1.55 0_ 10 _ 2.50 3.00 INCHES MIN MAX 0.1142 0.1220 0.0512 0.0669 0.0354 0.0433 0.0098 0.0197 0.0335 0.0413 0.0005 0.0040 0.0040 0.0102 0.0079 0.0236 0.0493 0.0610 0_ 10 _ 0.0985 0.1181
S
B
D G M 0.05 (0.002) H C K J
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PUBLICATION ORDERING INFORMATION
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NCP800/D

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