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MSP430xW42x MIXED SIGNAL MICROCONTROLLER
SLAS383A - OCTOBER 2003 - REVISED AUGUST 2004
D Low Supply-Voltage Range, 1.8 V to 3.6 V D Ultralow-Power Consumption:
- Active Mode: 200 A at 1 MHz, 2.2 V - Standby Mode: 0.7 A - Off Mode (RAM Retention): 0.1 A Five Power-Saving Modes Wake-Up From Standby Mode in less than 6 s Frequency-Locked Loop, FLL+ 16-Bit RISC Architecture, 125-ns Instruction Cycle Time Scan IF for Background Water, Heat, and Gas Volume Measurement 16-Bit Timer_A With Three Capture/Compare Registers 16-Bit Timer_A With Five Capture/Compare Registers Integrated LCD Driver for Up to 96 Segments On-Chip Comparator
D Serial Onboard Programming,
No External Programming Voltage Needed Programmable Code Protection by Security Fuse Brownout Detector Supply Voltage Supervisor/Monitor With Programmable Level Detection Bootstrap Loader in Flash Devices Family Members Include: - MSP430FW423: 8KB + 256B Flash Memory, 256B RAM - MSP430FW425: 16KB + 256B Flash Memory, 512B RAM - MSP430FW427: 32KB + 256B Flash Memory, 1KB RAM Available in 64-Pin Quad Flat Pack (QFP) For Complete Module Descriptions, Refer to the MSP430x4xx Family User's Guide, Literature Number SLAU056
D D D D D D D D D
D D D D
D D
description
The Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low power modes is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6s. The MSP430xW42x series are microcontroller configurations with two built-in 16-bit timers, a comparator, 96 LCD segment drive capability, a scan interface, and 48 I/O pins. Typical applications include sensor systems that capture analog signals, convert them to digital values, and process the data and transmit them to a host system. The comparator and timers make the configurations ideal for gas, heat, and water meters, industrial meters, counter applications, handheld meters, etc.
AVAILABLE OPTIONS PACKAGED DEVICES TA PLASTIC 64-PIN QFP (PM) MSP430FW423IPM MSP430FW425IPM MSP430FW427IPM
-40C to 85C
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2003 - 2004, Texas Instruments Incorporated
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pin designation, MSP430xW42x
AVCC DVSS AVSS P6.2/SIFCH2 P6.1/SIFCH1 P6.0/SIFCH0 RST/NMI TCK TMS TDI/TCLK TDO/TDI P1.0/TA0.0 P1.1/TA0.0/MCLK P1.2/TA0.1 P1.3/TA1.0/SVSOUT P1.4/TA1.0 DVCC P6.3/SIFCH3/SIFCAOUT P6.4/SIFCI0 P6.5/SIFCI1 P6.6/SIFCI2/SIFDACOUT P6.7/SIFCI3/SVSIN SIFCI XIN XOUT SIFVSS SIFCOM P5.1/S0 P5.0/S1 P4.7/S2 P4.6/S3 P4.5/S4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MSP430xW42x 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P1.5/TA0CLK/ACLK P1.6/CA0 P1.7/CA1 P2.0/TA0.2 P2.1/TA1.1 P5.7/R33 P5.6/R23 P5.5/R13 R03 P5.4/COM3 P5.3/COM2 P5.2/COM1 COM0 P2.2/TA1.2/S23 P2.3/TA1.3/S22 P2.4/TA1.4/S21
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P4.4/S5 P4.3/S6 P4.2/S7 P4.1/S8 P4.0/S9 P3.7/S10 P3.6/S11 P3.5/S12 P3.4/S13 P3.3/S14 P3.2/S15 P3.1/S16 P3.0/S17 P2.7/SIFCLKG/S18 P2.6/CAOUT/S19 P2.5/TA1CLK/S20
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functional block diagram
XIN XOUT DVCC DVSS AVCC AVSS RST/NMI P1 P2 P3 P4 P5 P6
8 Oscillator FLL+ ACLK 8KB Flash 256B RAM 512B RAM 1KB RAM Scan IF
8
8 I/O Port 3/4 16 I/Os
8
8
8
SMCLK 16KB Flash 32KB Flash
I/O Port 1/2 16 I/Os, with Interrupt Capability
I/O Port 5/6 16 I/Os
MCLK MAB, 4 Bit MCB Emulation Module
Test JTAG CPU Incl. 16 Reg.
MAB,MAB, 16-Bit 16 Bit
MDB, 16-Bit MDB, 16 Bit
Bus Conv
MDB, 8 Bit
4 TMS TCK TDI/TCLK TDO/TDI Watchdog Timer 15/16-Bit Timer0_A3 3 CC Reg Timer1_A5 5 CC Reg POR/ Multilevel SVS/ Brownout Comparator A Basic Timer 1 1 Interrupt Vector LCD 96 Segments 1,2,3,4 MUX fLCD
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Terminal Functions MSP430xW42x
TERMINAL NAME AVCC AVSS DVCC DVSS SIFVSS P1.0/TA0.0 P1.1/TA0.0/MCLK P1.2/TA0.1 P1.3/TA1.0/ SVSOUT P1.4/TA1.0 P1.5/TA0CLK/ ACLK P1.6/CA0 P1.7/CA1 P2.0/TA0.2 P2.1/TA1.1 P2.2/TA1.2/S23 P2.3/TA1.3/S22 P2.4/TA1.4/S21 P2.5/TA1CLK/S20 P2.6/CAOUT/S19 P2.7/SIFCLKG/ S18 P3.0/S17 P3.1/S16 P3.2/S15 P3.3/S14 P3.4/S13 P3.5/S12 P3.6/S11 P3.7/S10 NOTE: NO. 64 62 1 63 10 53 52 51 50 49 48 47 46 45 44 35 34 33 32 31 30 29 28 27 26 25 24 23 22 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O DESCRIPTION Analog supply voltage, positive terminal. Supplies SVS, brownout, oscillator, FLL+, comparator_A, scan IF AFE, port 6, and LCD resistive divider circuitry; must not power up prior to DVCC. Analog supply voltage, negative terminal. Supplies SVS, brownout, oscillator, FLL+, comparator_A, scan IF AFE. and port 6. Must be externally connected to DVSS. Internally connected to DVSS. Digital supply voltage, positive terminal. Digital supply voltage, negative terminal. Scan IF AFE reference supply voltage. General-purpose digital I/O/Timer0_A. Capture: CCI0A input, compare: Out0 output/BSL transmit General-purpose digital I/O/Timer0_A. Capture: CCI0B input/MCLK output/BSL receive Note: TA0.0 is only an input on this pin. General-purpose digital I/O/Timer0_A, capture: CCI1A input, compare: Out1 output General-purpose digital I/O/Timer1_A, capture: CCI0B input/SVS: output of SVS comparator Note: TA1.0 is only an input on this pin. General-purpose digital I/O/Timer1_A, capture: CCI0A input, compare: Out0 output General-purpose digital I/O/input of Timer0_A clock/output of ACLK General-purpose digital I/O/Comparator_A input General-purpose digital I/O/Comparator_A input General-purpose digital I/O/Timer0_A, capture: CCI2A input, compare: Out2 output General-purpose digital I/O/Timer0_A, capture: CCI1A input, compare: Out1 output General-purpose digital I/O/Timer1_A, capture: CCI2A input, compare: Out2 output/LCD segment output 23 (see Note) General-purpose digital I/O/Timer1_A, capture: CCI3A input, compare: Out3 output/LCD segment output 22 (see Note) General-purpose digital I/O/Timer1_A, capture: CCI4A input, compare: Out4 output/LCD segment output 21 (see Note) General-purpose digital I/O/input of Timer1_A clock/LCD segment output 20 (see Note) General-purpose digital I/O/Comparator_A output/LCD segment output 19 (see Note) General-purpose digital I/O/Scan IF, signal SIFCLKG from internal clock generator/LCD segment output 18 (see Note) General-purpose digital I/O/ LCD segment output 17 (see Note) General-purpose digital I/O/ LCD segment output 16 (see Note) General-purpose digital I/O/ LCD segment output 15 (see Note) General-purpose digital I/O/ LCD segment output 14 (see Note) General-purpose digital I/O/LCD segment output 13 (see Note) General-purpose digital I/O/LCD segment output 12 (see Note) General-purpose digital I/O/LCD segment output 11 (see Note) General-purpose digital I/O/LCD segment output 10 (see Note)
LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits.
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Terminal Functions (Continued) MSP430xW42x
TERMINAL NAME P4.0/S9 P4.1/S8 P4.2/S7 P4.3/S6 P4.4/S5 P4.5/S4 P4.6/S3 P4.7/S2 P5.0/S1 P5.1/S0 COM0 P5.2/COM1 P5.3/COM2 P5.4/COM3 R03 P5.5/R13 P5.6/R23 P5.7/R33 P6.0/SIFCH0 P6.1/SIFCH1 P6.2/SIFCH2 P6.3/SIFCH3/ SIFCAOUT P6.4/SIFCI0 P6.5/SIFCI1 P6.6/SIFCI2/ SIFDACOUT P6.7/ SIFCI3/SVSIN SIFCI SIFCOM RST/NMI TCK TDI/TCLK TDO/TDI TMS XIN XOUT NOTE: NO. 21 20 19 18 17 16 15 14 13 12 36 37 38 39 40 41 42 43 59 60 61 2 3 4 5 6 7 11 58 57 55 54 56 8 9 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I O I I I I/O I I O DESCRIPTION General-purpose digital I/O/LCD segment output 9 (see Note) General-purpose digital I/O/LCD segment output 8 (see Note) General-purpose digital I/O/LCD segment output 7 (see Note) General-purpose digital I/O/LCD segment output 6 (see Note) General-purpose digital I/O/LCD segment output 5 (see Note) General-purpose digital I/O/LCD segment output 4 (see Note) General-purpose digital I/O/LCD segment output 3 (see Note) General-purpose digital I/O/LCD segment output 2 (see Note) General-purpose digital I/O/LCD segment output 1 (see Note) General-purpose digital I/O/LCD segment output 0 (see Note) Common output. COM0-3 are used for LCD backplanes General-purpose digital I/O/common output. COM0-3 are used for LCD backplanes General-purpose digital I/O/common output. COM0-3 are used for LCD backplanes General-purpose digital I/O/common output. COM0-3 are used for LCD backplanes Input port of fourth positive (lowest) analog LCD level (V5) General-purpose digital I/O/input port of third most positive analog LCD level (V4 or V3) General-purpose digital I/O/input port of second most positive analog LCD level (V2) General-purpose digital I/O/output port of most positive analog LCD level (V1) General-purpose digital I/O/Scan IF, channel 0 sensor excitation output and signal input General-purpose digital I/O/Scan IF, channel 1 sensor excitation output and signal input General-purpose digital I/O/Scan IF, channel 2 sensor excitation output and signal input General-purpose digital I/O/Scan IF, channel 3 sensor excitation output and signal input/Scan IF comparator output General-purpose digital I/O/Scan IF, channel 0 signal input to comparator General-purpose digital I/O/Scan IF, channel 1 signal input to comparator General-purpose digital I/O/Scan IF, channel 2 signal input to comparator/10-bit DAC output General-purpose digital I/O/Scan IF, channel 3 signal input to comparator/SVS, analog input Scan IF input to Comparator. Common termination for Scan IF sensors. Reset input or nonmaskable interrupt input port. Test clock. TCK is the clock input port for device programming and test. Test data input or test clock input. The device protection fuse is connected to TDI/TCLK. Test data output port. TDO/TDI data output or programming data input terminal. Test mode select. TMS is used as an input port for device programming and test. Input port for crystal oscillator XT1. Standard or watch crystals can be connected. Output terminal of crystal oscillator XT1.
LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits.
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short-form description
CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. The remaining registers are general-purpose registers. Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions. instruction set The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 1 shows examples of the three types of instruction formats; the address modes are listed in Table 2.
Program Counter Stack Pointer Status Register Constant Generator General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register PC/R0 SP/R1 SR/CG1/R2 CG2/R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
Table 1. Instruction Word Formats
Dual operands, source-destination Single operands, destination only Relative jump, un/conditional e.g. ADD R4,R5 e.g. CALL e.g. JNE R8 R4 + R5 ---> R5 PC -->(TOS), R8--> PC Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE Register Indexed Symbolic (PC relative) Absolute Indirect Indirect autoincrement Immediate NOTE: S = source SD D D D D D D D D = destination D D D D SYNTAX MOV Rs,Rd MOV X(Rn),Y(Rm) MOV EDE,TONI MOV &MEM,&TCDAT MOV @Rn,Y(Rm) MOV @Rn+,Rm MOV #X,TONI MOV @R10,Tab(R6) MOV @R10+,R11 MOV #45,TONI EXAMPLE MOV R10,R11 MOV 2(R5),6(R6) OPERATION R10 --> R11 M(2+R5)--> M(6+R6) M(EDE) --> M(TONI) M(MEM) --> M(TCDAT) M(R10) --> M(Tab+R6) M(R10) --> R11 R10 + 2--> R10 #45 --> M(TONI)
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operating modes The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software:
D Active mode AM;
- All clocks are active
D Low-power mode 0 (LPM0);
- CPU is disabled ACLK and SMCLK remain active, MCLK is available to modules FLL+ Loop control remains active
D Low-power mode 1 (LPM1);
- CPU is disabled ACLK and SMCLK remain active, MCLK is available to modules FLL+ Loop control is disabled
D Low-power mode 2 (LPM2);
- CPU is disabled MCLK and FLL+ loop control and DCOCLK are disabled DCO's dc-generator remains enabled ACLK remains active
D Low-power mode 3 (LPM3);
- CPU is disabled MCLK, FLL+ loop control, and DCOCLK are disabled DCO's dc-generator is disabled ACLK remains active
D Low-power mode 4 (LPM4);
- CPU is disabled ACLK is disabled MCLK, FLL+ loop control, and DCOCLK are disabled DCO's dc-generator is disabled Crystal oscillator is stopped
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interrupt vector addresses The interrupt vectors and the power-up starting address are located in the address range 0FFFFh - 0FFE0h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
INTERRUPT SOURCE Power-up External Reset Watchdog Flash memory NMI Oscillator Fault Flash memory access violation Timer1_A5 Timer1_A5 Comparator_A Watchdog Timer Scan IF INTERRUPT FLAG WDTIFG KEYV (see Note 1) NMIIFG OFIFG ACCVIFG (see Notes 1 & 3) TA1CCR0 CCIFG (see Note 2) TA1CCR1 CCIFG to TA1CCR4 CCIFG, TA1CTL TAIFG (see Notes 1 & 2) CMPAIFG WDTIFG SIFIFG0 to SIFIFG6 (See Note 1) SYSTEM INTERRUPT Reset WORD ADDRESS 0FFFEh PRIORITY 15, highest
(Non)maskable (Non)maskable (Non)maskable Maskable Maskable Maskable Maskable Maskable
0FFFCh 0FFFAh 0FFF8h 0FFF6h 0FFF4h 0FFF2h 0FFF0h 0FFEEh
14 13 12 11 10 9 8 7 6 5
Timer0_A3 Timer0_A3 I/O port P1 (eight flags)
TA0CCR0 CCIFG (see Note 2) TA0CCR1 CCIFG, TA0CCR2 CCIFG, TA0CTL TAIFG (see Notes 1 & 2) P1IFG.0 to P1IFG.7 (see Notes 1 & 2)
Maskable Maskable
0FFECh 0FFEAh
Maskable
0FFE8h 0FFE6h 0FFE4h
4 3 2 1 0, lowest
I/O port P2 (eight flags) Basic Timer1
P2IFG.0 to P2IFG.7 (see Notes 1 & 2) BTIFG
Maskable Maskable
0FFE2h 0FFE0h
NOTES: 1. Multiple source flags 2. Interrupt flags are located in the module. 3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt-enable cannot.
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special function registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits that are not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement.
interrupt enable 1 and 2
Address 00h 7 6 5 ACCVIE rw-0 Address 01h 7 BTIE rw-0 6 5 4 NMIIE rw-0 4 3 2 3 2 1 OFIE rw-0 1 0 WDTIE rw-0 0
WDTIE: OFIE: NMIIE: ACCVIE: BTIE:
Watchdog-timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval timer mode. Oscillator-fault-interrupt enable Nonmaskable-interrupt enable Flash access violation interrupt enable Basic Timer1 interrupt enable
interrupt flag register 1 and 2
Address 02h 7 6 5 4 NMIIFG rw-0 Address 03h 7 BTIFG rw-0 6 5 4 3 2 3 2 1 OFIFG rw-1 1 0 WDTIFG rw-(0) 0
WDTIFG: OFIFG: NMIIFG: BTIFG:
Set on watchdog-timer overflow (in watchdog mode) or security key violation. Reset with VCC power-up, or a reset condition at the RST/NMI pin in reset mode. Flag set on oscillator fault Set via RST/NMI pin Basic Timer1 interrupt flag
module enable registers 1 and 2
Address 04h/05h Legend: rw: rw-0,1: rw-(0,1): Bit Can Be Read and Written Bit Can Be Read and Written. It Is Reset or Set by PUC. Bit Can Be Read and Written. It Is Reset or Set by POR. SFR Bit Not Present in Device 7 6 5 4 3 2 1 0
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memory organization
MSP430FW423 Memory Interrupt vector Code memory Information memory Boot memory RAM Peripherals Size Flash Flash Size Size Size 16-bit 8-bit 8-bit SFR 8KB 0FFFFh - 0FFE0h 0FFFFh - 0E000h 256 Byte 010FFh - 01000h 1KB 0FFFh - 0C00h 256 Byte 02FFh - 0200h 01FFh - 0100h 0FFh - 010h 0Fh - 00h MSP430FW425 16KB 0FFFFh - 0FFE0h 0FFFFh - 0C000h 256 Byte 010FFh - 01000h 1KB 0FFFh - 0C00h 512 Byte 03FFh - 0200h 01FFh - 0100h 0FFh - 010h 0Fh - 00h MSP430FW427 32KB 0FFFFh - 0FFE0h 0FFFFh - 08000h 256 Byte 010FFh - 01000h 1KB 0FFFh - 0C00h 1KB 05FFh - 0200h 01FFh - 0100h 0FFh - 010h 0Fh - 00h
bootstrap loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the Application report Features of the MSP430 Bootstrap Loader, Literature Number SLAA089.
BSL Function Data Transmit Data Receive PM Package Pins 53 - P1.0 52 - P1.1
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D Flash memory has n segments of main memory and two segments of information memory (A and B) of 128
bytes each. Each segment in main memory is 512 bytes in size.
D Segments 0 to n may be erased in one step, or each segment may be individually erased. D Segments A and B can be erased individually, or as a group with segments 0-n.
Segments A and B are also called information memory.
D New devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.
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flash memory (continued)
8KB 16KB 32KB 0FFFFh Segment 0 With Interrupt Vectors Segment 1 0FC00h 0FC00h 0FC00h 0FBFFh 0FBFFh 0FBFFh Segment 2 0FA00h 0F9FFh 0FA00h 0F9FFh 0FA00h 0F9FFh
0FFFFh 0FFFFh
0FE00h 0FE00h 0FE00h 0FDFFh 0FDFFh 0FDFFh
Main Memory
0E400h 0C400h 0E3FFh 0C3FFh 0E200h 0C200h 0E1FFh 0C1FFh 0E000h 010FFh 01080h 0107Fh 01000h 0C000h 010FFh 01080h 0107Fh 01000h
08400h 083FFh 08200h 081FFh Segment n 08000h 010FFh Segment A 01080h 0107Fh Segment B 01000h Information Memory Segment n-1
peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, refer to the MSP430x4xx Family User's Guide, literature number SLAU056.
oscillator and system clock
The clock system in the MSP430xW42x family of devices is supported by the FLL+ module that includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system cost and low-power consumption. The FLL+ features a digital frequency locked loop (FLL) hardware which in conjunction with a digital modulator stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 s. The FLL+ module provides the following clock signals:
D D D D
Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal. Main clock (MCLK), the system clock used by the CPU. Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules. ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8.
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brownout, supply voltage supervisor
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the device is not automatically reset). The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not have ramped to VCC(min) at that time. The user must insure the default FLL+ settings are not changed until VCC reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).
digital I/O
There are six 8-bit I/O ports implemented--ports P1 through P6:
D D D D
All individual I/O bits are independently programmable. Any combination of input, output, and interrupt conditions is possible. Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2. Read/write access to port-control registers is supported by all instructions.
Basic Timer1
The Basic Timer1 has two independent 8-bit timers which can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. The Basic Timer1 can be used to generate periodic interrupts and clock for the LCD module.
LCD drive
The LCD driver generates the segment and common signals required to drive an LCD display. The LCD controller has dedicated data memory to hold segment drive information. Common and segment signals are generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral.
watchdog timer
The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.
comparator_A
The primary function of the comparator_A module is to support precision slope analog-to-digital conversions, battery-voltage supervision, and monitoring of external analog signals.
scan IF
The scan interface is used to measure linear or rotational motion and supports LC and resistive sensors such as GMR sensors. The scan IF incorporates a VCC/2 generator, a comparator, and a 10-bit DAC and supports up to four sensors.
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timer0_A3
Timer0_A3 is a 16-bit timer/counter with three capture/compare registers. Timer0_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer0_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
Timer0_A3 Signal Connections Input Pin Number 48 - P1.5 Device Input Signal TA0CLK ACLK SMCLK 48 - P1.5 53 - P1.0 52 - P1.1 TA0CLK TA0.0 TA0.0 DVSS DVCC 51 - P1.2 TA0.1 CAOUT (internal) DVSS DVCC 45 - P2.0 TA0.2 ACLK (internal) DVSS DVCC Module Input Name TACLK ACLK SMCLK INCLK CCI0A CCI0B GND VCC CCI1A CCI1B GND VCC CCI2A CCI2B GND VCC CCR2 TA0.2 CCR1 TA0.1 CCR0 TA0.0 53 - P1.0 Timer NA Module Block Module Output Signal Output Pin Number
51 - P1.2
45 - P2.0
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timer1_A5
Timer1_A5 is a 16-bit timer/counter with five capture/compare registers. Timer1_A5 can support multiple capture/compares, PWM outputs, and interval timing. Timer1_A5 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
Timer1_A5 Signal Connections Input Pin Number 32 - P2.5 Device Input Signal TA1CLK ACLK SMCLK 32 - P2.5 49 - P1.4 50 - P1.3 TA1CLK TA1.0 TA1.0 DVSS DVCC 44 - P2.1 TA1.1 CAOUT (internal) DVSS DVCC 35 - P2.2 TA1.2 SIFO0sig (internal) DVSS DVCC 34 - P2.3 TA1.3 SIFO1sig (internal) DVSS DVCC 33 - P2.4 TA1.4 SIFO2sig (internal) DVSS DVCC Module Input Name TACLK ACLK SMCLK INCLK CCI0A CCI0B GND VCC CCI1A CCI1B GND VCC CCI2A CCI2B GND VCC CCI3A CCI3B GND VCC CCI4A CCI4B GND VCC CCR4 TA1.4 CCR3 TA1.3 CCR2 TA1.2 CCR1 TA1.1 CCR0 TA1.0 49 - P1.4 Timer NA Module Block Module Output Signal Output Pin Number
44 - P2.1
35 - P2.2
34 - P2.3
33 - P2.4
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peripheral file map
PERIPHERALS WITH WORD ACCESS Watchdog Timer1_A5 Watchdog Timer control Timer1_A interrupt vector Timer1_A control Capture/compare control 0 Capture/compare control 1 Capture/compare control 2 Capture/compare control 3 Capture/compare control 4 Reserved Reserved Timer1_A register Capture/compare register 0 Capture/compare register 1 Capture/compare register 2 Capture/compare register 3 Capture/compare register 4 Reserved Reserved Timer0_A3 Timer0_A interrupt vector Timer0_A control Capture/compare control 0 Capture/compare control 1 Capture/compare control 2 Reserved Reserved Reserved Reserved Timer0_A register Capture/compare register 0 Capture/compare register 1 Capture/compare register 2 Reserved Reserved Reserved Reserved Flash Flash control 3 Flash control 2 Flash control 1 FCTL3 FCTL2 FCTL1 TA0R TA0CCR0 TA0CCR1 TA0CCR2 TA0IV TA0CTL0 TA0CCTL0 TA0CCTL1 TA0CCTL2 TA1R TA1CCR0 TA1CCR1 TA1CCR2 TA1CCR3 TA1CCR4 WDTCTL TA1IV TA1CTL TA1CCTL0 TA1CCTL1 TA1CCTL2 TA1CCTL3 TA1CCTL4 0120h 011Eh 0180h 0182h 0184h 0186h 0188h 018Ah 018Ch 018Eh 0190h 0192h 0194h 0196h 0198h 019Ah 019Ch 019Eh 012Eh 0160h 0162h 0164h 0166h 0168h 016Ah 016Ch 016Eh 0170h 0172h 0174h 0176h 0178h 017Ah 017Ch 017Eh 012Ch 012Ah 0128h
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PERIPHERALS WITH WORD ACCESS (CONTINUED) Scan IF SIF timing state machine 23 : SIF timing state machine 0 SIF DAC register 7 : SIF DAC register 0 SIF control register 5 SIF control register 4 SIF control register 3 SIF control register 2 SIF control register 1 SIF processing state machine vector SIF counter CNT1/2 Reserved PERIPHERALS WITH BYTE ACCESS LCD LCD memory 20 : LCD memory 16 LCD memory 15 : LCD memory 1 LCD control and mode Comparator_A Comparator_A port disable Comparator_A control 2 Comparator_A control 1 Brownout, SVS FLL+ Clock SVS control register FLL+ Control 1 FLL+ Control 0 System clock frequency control System clock frequency integrator System clock frequency integrator Basic Timer1 BT counter 2 BT counter 1 BT control LCDM20 : LCDM16 LCDM15 : LCDM1 LCDCTL CAPD CACTL2 CACTL1 SVSCTL FLL_CTL1 FLL_CTL0 SCFQCTL SCFI1 SCFI0 BTCNT2 BTCNT1 BTCTL 0A4h : 0A0h 09Fh : 091h 090h 05Bh 05Ah 059h 056h 054h 053h 052h 051h 050h 047h 046h 040h SIFTSM23 : SIFTSM0 SIFDACR7 : SIFDACR0 SIFCTL5 SIFCTL4 SIFCTL3 SIFCTL2 SIFCTL1 SIFPSMV SIFCNT SIFDEBUG 01FEh : 01D0h 01CEh : 01C0h 01BEh 01BCh 01BAh 01B8h 01B6h 01B4h 01B2h 01B0h
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peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED) Port P6 Port P6 selection Port P6 direction Port P6 output Port P6 input Port P5 Port P5 selection Port P5 direction Port P5 output Port P5 input Port P4 Port P4 selection Port P4 direction Port P4 output Port P4 input Port P3 Port P3 selection Port P3 direction Port P3 output Port P3 input Port P2 Port P2 selection Port P2 interrupt enable Port P2 interrupt-edge select Port P2 interrupt flag Port P2 direction Port P2 output Port P2 input Port P1 Port P1 selection Port P1 interrupt enable Port P1 interrupt-edge select Port P1 interrupt flag Port P1 direction Port P1 output Port P1 input Special Functions SFR module enable 2 SFR module enable 1 SFR interrupt flag 2 SFR interrupt flag 1 SFR interrupt enable 2 SFR interrupt enable 1 P6SEL P6DIR P6OUT P6IN P5SEL P5DIR P5OUT P5IN P4SEL P4DIR P4OUT P4IN P3SEL P3DIR P3OUT P3IN P2SEL P2IE P2IES P2IFG P2DIR P2OUT P2IN P1SEL P1IE P1IES P1IFG P1DIR P1OUT P1IN ME2 ME1 IFG2 IFG1 IE2 IE1 037h 036h 035h 034h 033h 032h 031h 030h 01Fh 01Eh 01Dh 01Ch 01Bh 01Ah 019h 018h 02Eh 02Dh 02Ch 02Bh 02Ah 029h 028h 026h 025h 024h 023h 022h 021h 020h 005h 004h 003h 002h 001h 000h
absolute maximum ratings
Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to + 4.1 V Voltage applied to any pin (see Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VCC + 0.3 V Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 mA Storage temperature (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to 150C Storage temperature (programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE: All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied to the TDI/TCLK pin when blowing the JTAG fuse.
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recommended operating conditions
PARAMETER Supply voltage during program execution, SVS disabled VCC (AVCC = DVCC = VCC) Supply voltage during program execution, SVS enabled (see Note 1), VCC (AVCC = DVCC = VCC) Supply voltage during programming flash memory, VCC (AVCC = DVCC = VCC) Supply voltage, VSS (AVSS = DVSS = VSS) Operating free-air temperature range, TA LF selected, XTS_FLL=0 LFXT1 crystal frequency, f(LFXT1) (see Note 2) XT1 selected, XTS_FLL=1 XT1 selected, XTS_FLL=1 Processor frequency (signal MCLK), f(System) MSP430xW42x Watch crystal Ceramic resonator Crystal VCC = 1.8 V VCC = 3.6 V 450 1000 DC DC MSP430xW42x MSP430xW42x MSP430FW42x MIN 1.8 2.2 2.7 0 -40 32768 8000 8000 4.15 8 MHz NOM MAX 3.6 3.6 3.6 0 85 UNITS V V V V C Hz kHz kHz
NOTES: 1. The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing supply voltage. POR is going inactive when the supply voltage is raised above minimum supply voltage plus the hysteresis of the SVS circuitry. 2. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal.
f(System) - Maximum Processor Frequency - MHz
f (MHz)
Supply Voltage Range During Programming of the Flash Memory
8 MHz
Supply Voltage Range During Program Execution
4.15 MHz
1.8 V
2.7 V
VCC - Supply Voltage - V
Figure 1. Maximum Frequency vs Supply Voltage
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IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII IIIIII
3V
3.6 V
MSP430xW42x MIXED SIGNAL MICROCONTROLLER
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electrical characteristics over recommended operating free-air temperature (unless otherwise noted)
supply current into AVCC + DVCC excluding external current, (see Note 1)
PARAMETER Active mode, f(MCLK) = f(SMCLK) = 1 MHz, f(ACLK) = 32,768 Hz, XTS_FLL = 0 (FW42x: Program executes in flash) Low-power mode, (LPM0) f(MCLK) = f(SMCLK) = 1 MHz, f(ACLK) = 32,768 Hz, XTS_FLL = 0 FN_8=FN_4=FN_3=FN_2=0 Low-power mode, (LPM2) TEST CONDITIONS VCC = 2.2 V TA = -40C to 85C VCC = 3 V VCC = 2.2 V TA = -40C to 85C VCC = 3 V TA = -40C to 85C TA = -40C TA = -10C TA = 25C TA = 60C I(LPM3) Low-power mode, (LPM3) (see Note 2) TA = 85C TA = -40C TA = -10C TA = 25C TA = 60C TA = 85C I(LPM4) Low-power mode, (LPM4) TA = -40C TA = 25C VCC = 3 V VCC = 2.2 V VCC = 2.2 V VCC = 3 V 92 11 17 0.95 0.8 0.7 0.95 1.6 1.1 1.0 0.9 1.1 2.0 0.1 100 14 22 1.4 1.3 1.2 1.4 2.3 1.7 1.6 1.5 1.7 2.6 0.5 A A A A 300 57 350 70 A A MIN NOM 200 MAX 250 A A UNIT
I(AM)
I(LPM0)
I(LPM2)
0.1 0.5 VCC = 2.2 V/3 V A TA = 85C 0.8 2.5 NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current. The current consumption is measured with active Basic Timer1 and LCD (ACLK selected). The current consumption of the Comparator_A and the SVS module are specified in the respective sections. 2. The LPM3 currents are characterized with a KDS Daishinku DT-38 (6 pF) crystal.
current consumption of active mode versus system frequency, F version
I(AM) = I(AM) [1 MHz] x f(System) [MHz]
current consumption of active mode versus supply voltage, F version
I(AM) = I(AM) [3 V] + 140 A/V x (VCC - 3 V)
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electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
Schmitt-trigger inputs - Ports P1, P2, P3, P4, P5, and P6; RST/NMI; JTAG: TCK, TMS, TDI/TCLK
PARAMETER VIT+ VIT- Vhys Positive-going input threshold voltage Negative-going input threshold voltage Input voltage hysteresis (VIT+ - VIT-) TEST CONDITIONS VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V MIN 1.1 1.5 0.4 0.9 0.3 0.45 TYP MAX 1.5 1.9 0.9 1.3 1.1 1 V V V UNIT
inputs Px.x, TAx.x
PARAMETER TEST CONDITIONS Port P1, P2: P1.x to P2.x, External trigger signal for the interrupt flag, (see Note 1) VCC 2.2 V/3 V 2.2 V 3V 2.2 V t(cap) f(TAext) f(TAint) Timer_A, capture timing Timer_A clock frequency externally applied to pin Timer_A clock frequency TAx.x 3V 2.2 V 3V 2.2 V SMCLK or ACLK signal selected 3V MIN 1.5 62 50 62 50 8 10 8 10 MHz ns ns TYP MAX UNIT cycle
t(int)
External interrupt timing
TAxCLK, INCLK t(H) = t(L)
MHz
NOTES: 1. The external signal sets the interrupt flag every time the minimum t(int) cycle and time parameters are met. It may be set even with trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in MCLK cycles.
leakage current (see Note 1)
PARAMETER Ilkg(P1.x) Ilkg(P6.x) Leakage current Leakage current Port P1 Port P6 TEST CONDITIONS Port 1: V(P1.x) (see Note 2) Port 6: V(P6.x) (see Note 2) VCC = 2.2 V/3 V VCC = 2.2 V/3 V MIN NOM MAX 50 50 UNIT nA nA
NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. 2. The port pin must be selected as an input.
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electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
outputs - Ports P1, P2, P3, P4, P5, and P6
PARAMETER TEST CONDITIONS IOH(max) = -1.5 mA, IOH(max) = -6 mA, IOH(max) = -1.5 mA, IOH(max) = -6 mA, IOL(max) = 1.5 mA, IOL(max) = 6 mA, IOL(max) = 1.5 mA, IOL(max) = 6 mA, VCC = 2.2 V, VCC = 2.2 V, VCC = 3 V, VCC = 3 V, VCC = 2.2 V, VCC = 2.2 V, VCC = 3 V, VCC = 3 V, See Note 1 See Note 2 See Note 1 See Note 2 See Note 1 See Note 2 See Note 1 See Note 2 MIN VCC-0.25 VCC-0.6 VCC-0.25 VCC-0.6 VSS VSS VSS VSS TYP MAX VCC VCC VCC VCC VSS+0.25 VSS+0.6 VSS+0.25 VSS+0.6 UNIT
VOH
High-level output voltage
V
VOL
Low-level output voltage
V
NOTES: 1. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed 12 mA to satisfy the maximum specified voltage drop. 2. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed 24 mA to satisfy the maximum specified voltage drop.
output frequency
PARAMETER fPx.y fACLK, fMCLK, fSMCLK (1 x 6, 0 y 7) P1.1/TA0.0/MCLK, P1.5/TA0CLK/ACLK CL = 20 pF, IL = 1.5mA CL = 20 pF P1.5/TA0CLK/ACLK, CL = 20 pF VCC = 2.2 V / 3 V tXdc Duty cycle of output frequency P1.1/TA0.0/MCLK, CL = 20 pF, VCC = 2.2 V / 3 V TEST CONDITIONS VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V fACLK = fLFXT1 = fXT1 fACLK = fLFXT1 = fLF fACLK = fLFXT1/n fMCLK = fLFXT1/n fMCLK = fDCOCLK 50%- 15 ns 50%- 15 ns 40% 30% 50% 50% 50% 50%+ 15 ns 50%+ 15 ns MIN DC DC TYP MAX 10 12 8 MHz 12 60% 70% MHz UNIT
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electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
outputs - Ports P1, P2, P3, P4, P5, and P6 (continued)
TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE
25 IOL - Typical Low-Level Output Current - mA IOL - Typical Low-Level Output Current - mA VCC = 2.2 V P2.4 20 TA = 85C 15 TA = 25C 40 35 30 25 20 15 10 5 0 0.0 VCC = 3 V P2.4 TA = 25C TA = 85C
TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE
10
5
d
0 0.0
0.5
1.0
1.5
2.0
2.5
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOL - Low-Level Output Voltage - V
VOL - Low-Level Output Voltage - V
Figure 2
TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE
0 IOH - Typical High-Level Output Current - mA IOH - Typical High-Level Output Current - mA VCC = 2.2 V P2.4 -5 0 -5 -10 -15 -20 -25 -30 -35 TA = 85C -40 -45 VCC = 3 V P2.4
Figure 3
TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE
-10
-15
-20
TA = 85C
-25 0.0
TA = 25C 0.5 1.0 1.5 2.0 2.5 VOH - High-Level Output Voltage - V
TA = 25C -50 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VOH - High-Level Output Voltage - V
Figure 4
NOTE: One output loaded at a time
Figure 5
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electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
wake-up LPM3
PARAMETER TEST CONDITIONS f = 1 MHz td(LPM3) Delay time f = 2 MHz f = 3 MHz VCC = 2.2 V/3 V MIN TYP MAX 6 6 6 s UNIT
RAM (see Note 1)
PARAMETER VRAMh TEST CONDITIONS CPU halted (see Note 1) MIN 1.6 TYP MAX UNIT V
NOTES: 1. This parameter defines the minimum supply voltage when the data in the program memory RAM remain unchanged. No program execution should take place during this supply voltage condition.
LCD
PARAMETER V(33) V(23) V(13) V(33) - V(03) I(R03) I(R13) I(R23) V(Sxx0) V(Sxx1) V(Sxx2) V(Sxx3) Segment line voltage Input leakage TEST CONDITIONS Voltage at P5.7/R33 Voltage at P5.6/R23 Analog voltage Voltage at P5.5/R13 Voltage at R33/R03 R03 = VSS P5.5/R13 = VCC/3 P5.6/R23 = 2 x VCC/3 No load at all segment and common lines, VCC = 3 V V(03) V(13) V(23) V(33) VCC = 3 V 2.5 MIN 2.5 TYP MAX VCC +0.2 (V33-V03) x 2/3 + V03 (V(33)-V(03)) x 1/3 + V(03) VCC +0.2 20 20 20 V(03) - 0.1 V(13) - 0.1 V(23) - 0.1 V(33) + 0.1 nA V UNIT
I(Sxx) = -3 A, A,
VCC = 3 V
V
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electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
Comparator_A (see Note 1)
PARAMETER I(CC) TEST CONDITIONS CAON = 1, CARSEL = 0, CAREF = 0 CAON = 1, CARSEL = 0, CAREF = 1/2/3, No load at P1.6/CA0 and P1.7/CA1 VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V / 3 V 0.23 MIN TYP 25 45 30 45 0.24 MAX 40 60 50 71 0.25 A A UNIT A A
I(Refladder/RefDiode)
V(Ref025)
Voltage @ 0.25 V CC node PCA0 = 1, CARSEL = 1, CAREF = 1, No load at P1.6/CA0 and P1.7/CA1 V CC Voltage @ 0.5 V CC node V CC (See Figure 6 and Figure 7) Common-mode input voltage range Offset voltage Input hysteresis PCA0 = 1, CARSEL = 1, CAREF = 2, No load at P1.6/CA0 and P1.7/CA1 PCA0 = 1, CARSEL = 1, CAREF = 3, No load at P1.6/CA0 and P1.7/CA1; TA = 85C CAON = 1 See Note 2 CAON = 1 TA = 25C, 25 C, Overdrive 10 mV, without filter: CAF = 0
V(Ref050)
VCC = 2.2V / 3 V VCC = 2.2 V VCC = 3.0 V VCC = 2. 2V/3 V VCC = 2.2 V/3 V VCC = 2.2 V / 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V VCC = 3 V VCC = 2.2 V
0.47 390 400 0 -30 0 130 80 1.4 0.9 130 80 1.4
0.48 480 490
0.50 540 mV 550 VCC-1.0 30 V mV mV ns s s ns
V(RefVT) V(IC) V(offset) Vhys
0.7 210 150 1.9 1.5 210 150 1.9
1.4 300 240 3.4 2.6 300 240 3.4
t(response LH)
TA = 25C 25 C Overdrive 10 mV, with filter: CAF = 1 TA = 25C 25 C Overdrive 10 mV, without filter: CAF = 0
t(response HL)
s s VCC = 3.0 V 0.9 1.5 2.6 NOTES: 1. The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification. 2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements. The two successive measurements are then summed together.
TA = 25C, 25 C, Overdrive 10 mV, with filter: CAF = 1
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electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
REFERENCE VOLTAGE vs FREE-AIR TEMPERATURE
650 VCC = 3 V V(RefVT) - Reference Voltage - mV V(RefVT) - Reference Voltage - mV 600 Typical 550 600 650
REFERENCE VOLTAGE vs FREE-AIR TEMPERATURE
VCC = 2.2 V
Typical 550
500
500
450
450
400 -45
-25
-5
15
35
55
75
95
400 -45
-25
-5
15
35
55
75
95
TA - Free-Air Temperature - C
TA - Free-Air Temperature - C
Figure 6
0 V VCC 0 1 CAON Low Pass Filter + _ 0 1 0 1 CAF
Figure 7
To Internal Modules
V+ V-
CAOUT Set CAIFG Flag 2 s
Figure 8. Block Diagram of Comparator_A Module
Overdrive V-
VCAOUT
400 mV V+ t(response)
Figure 9. Overdrive Definition
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electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
POR brownout, reset (see Notes 1 and 2)
PARAMETER td(BOR) VCC(start) V(B_IT-) Vhys(B_IT-) t(reset) Brownout TEST CONDITIONS dVCC/dt 3 V/s (see Figure 10) dVCC/dt 3 V/s (see Figure 10, Figure 11, Figure 12) dVCC/dt 3 V/s (see Figure 10) 70 MIN TYP 0.7 x V(B_IT-) 1.71 130 180 MAX 2000 UNIT s V V mV
Pulse length needed at RST/NMI pin to accepted reset internally, 2 s VCC = 2.2 V/3 V NOTES: 1. The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT-) + Vhys(B_IT-) is 1.8 V. 2. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT-) + Vhys(B_IT-). The default FLL+ settings must not be changed until VCC VCC(min), where VCC(min) is the minimum supply voltage for the desired operating frequency. See the MSP430x4xx Family User's Guide (SLAU056) for more information on the brownout/SVS circuit.
VCC Vhys(B_IT-) V(B_IT-) VCC(start)
1
0 td(BOR)
Figure 10. POR/Brownout Reset (BOR) vs Supply Voltage
2 V cc = 3 V Typical Conditions VCC (min) - V 1.5 1 0.5 0 0.001 VCC(min) VCC 3V tpw
1 tpw - Pulse Width - s
1000 1 ns 1 ns tpw - Pulse Width - s
Figure 11. VCC(min) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
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electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
VCC 2 1.5 1 0.5 0 0.001 VCC(min) tf = tr 1 tpw - Pulse Width - s 1000 tf tr tpw - Pulse Width - s V cc = 3 V Typical Conditions 3V tpw
VCC (min) - V
Figure 12. VCC(min) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal SVS (supply voltage supervisor/monitor) (See Notes 1 and 2)
PARAMETER td(SVSR) td(SVSon) tsettle V(SVSstart) TEST CONDITIONS dVCC/dt > 30 V/ms (see Figure 13) dVCC/dt 30 V/ms SVSon, switch from VLD=0 to VLD 0, VCC = 3 V VLD 0 VLD 0, VCC/dt 3 V/s (see Figure 13) VLD = 1 VCC/dt 3 V/s (see Figure 13) Vhys(SVS_IT-) VCC/dt 3 V/s (see Figure 13), external voltage applied on SVSIN VLD = 2 .. 14 VLD = 15 VLD = 1 VLD = 2 VLD = 3 VLD = 4 VLD = 5 VLD = 6 VCC/dt 3 V/s (see Figure 13) V(SVS_IT-) VLD = 7 VLD = 8 VLD = 9 VLD = 10 VLD = 11 VLD = 12 VLD = 13 VLD = 14 VCC/dt 3 V/s (see Figure 13), external voltage applied on SVSIN VLD = 15 70 V(SVS_IT-) x 0.004 4.4 1.8 1.94 2.05 2.14 2.24 2.33 2.46 2.58 2.69 2.83 2.94 3.11 3.24 3.43 1.1 1.9 2.1 2.2 2.3 2.4 2.5 2.65 2.8 2.9 3.05 3.2 3.35 3.5 3.7 1.2 MIN 5 20 1.55 120 NOM MAX 150 2000 150 12 1.7 155 V(SVS_IT-) x 0.008 10.4 2.05 2.25 2.37 2.48 2.6 2.71 2.86 3 3.13 3.29 3.42 3.61 3.76 3.99 1.3 V mV UNIT s s s s V mV
ICC(SVS) VLD 0, VCC = 2.2 V/3 V 10 15 A (see Note 1) The recommended operating voltage range is limited to 3.6 V. tsettle is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD 0 to a different VLD value somewhere between 2 and 15. The overdrive is assumed to be > 50 mV. NOTES: 1. The current consumption of the SVS module is not included in the ICC current consumption data. 2. The SVS is not active at power up.
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electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
Software Sets VLD>0:SVS is Active VCC V (SVS_IT-) V(SVSstart) V(B_IT-) VCC(start)
Brownout Region Brownout
Vhys(SVS_IT-)
Vhys(B_IT-)
Brownout 1 0 SVS out 1 0 Set POR 1
Region
td(BOR)
SVS Circuit is Active From VLD > to VCC < V(B_IT-)
td(BOR)
td(SVSon) td(SVSR) Undefined
0
Figure 13. SVS Reset (SVSR) vs Supply Voltage
VCC 3V 2 Rectangular Drop 1.5 VCC(min) - V tpw
Triangular Drop
VCC(min)
1 1 ns 0.5 VCC 3V 1 10 100 1000 tpw 1 ns
0 tpw - Pulse Width - s VCC(min) tf = tr tf tr t - Pulse Width - s
Figure 14. VCC(min) With a Square Voltage Drop and a Triangle Voltage Drop to Generate an SVS Signal
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electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
DCO
PARAMETER f(DCOCLK) f(DCO2) f(DCO27) f(DCO2) f(DCO27) f(DCO2) f(DCO27) f(DCO2) f(DCO27) f(DCO2) f(DCO27) Sn Dt DV TEST CONDITIONS N(DCO)=01E0h, FN_8=FN_4=FN_3=FN_2=0, D = 2, DCOPLUS= 0 FN_8=FN_4=FN_3=FN_2=0 , DCOPLUS = 1 FN_8=FN_4=FN_3=FN_2=0, DCOPLUS = 1, (see Note 1) FN_8=FN_4=FN_3=0, FN_2=1; DCOPLUS = 1 FN_8=FN_4=FN_3=0, FN_2=1; DCOPLUS = 1, (see Note 1) FN_8=FN_4=0, FN_3= 1, FN_2=x; DCOPLUS = 1 FN_8=FN_4=0, FN_3= 1, FN_2=x;, DCOPLUS = 1, (see Note 1) FN_8=0, FN_4= 1, FN_3= FN_2=x; DCOPLUS = 1 FN_8=0, FN_4=1, FN_3= FN_2=x; DCOPLUS = 1, (see Note 1) FN_8=1, FN_4=FN_3=FN_2=x; DCOPLUS = 1 FN_8=1,FN_4=FN_3=FN_2=x,DCOPLUS = 1, (see Note 1) Step size between adjacent DCO taps: Sn = fDCO(Tap n+1) / fDCO(Tap n), (see Figure 16 for taps 21 to 27) Temperature drift, N(DCO) = 01E0h, FN_8=FN_4=FN_3=FN_2=0 D = 2, DCOPLUS = 0, (see Note 2) Drift with VCC variation, N(DCO) = 01E0h, FN_8=FN_4=FN_3=FN_2=0 D = 2, DCOPLUS = 0 (see Note 2) VCC 2.2 V/3 V 2.2 V 3V 2.2 V 3V 2.2 V 3V 2.2 V 3V 2.2 V 3V 2.2 V 3V 2.2 V 3V 2.2 V 3V 2.2 V 3V 2.2 V 3V 1 < TAP 20 TAP = 27 2.2 V 3V 2.2 V/3 V MIN 0.3 0.3 2.5 2.7 0.7 0.8 5.7 6.5 1.2 1.3 9 10.3 1.8 2.1 13.5 16 2.8 4.2 21 30 1.06 1.07 -0.2 -0.2 0 -0.3 -0.3 5 TYP 1 0.65 0.7 5.6 6.1 1.3 1.5 10.8 12.1 2 2.2 15.5 17.9 2.8 3.4 21.5 26.6 4.2 6.3 32 46 1.25 1.3 10.5 11.3 2.3 2.5 18 20 3 3.5 25 28.5 4.2 5.2 33 41 6.2 9.2 46 70 1.11 1.17 -0.4 -0.4 15 %/_C %/V MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MAX UNIT MHz
NOTES: 1. Do not exceed the maximum system frequency. 2. This parameter is not production tested. f f (DCO) f f (DCO)
(DCO3V)
(DCO205C)
1.0
1.0
0
1.8
2.4
3.0
3.6 VCC - V
-40
-20
0
20
40
60
85 TA - C
Figure 15. DCO Frequency vs Supply Voltage VCC and vs Ambient Temperature
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electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
Sn - Stepsize Ratio between DCO Taps
1.17
1.11
1.07 1.06
Figure 16. DCO Tap Step Size
f(DCO)
FN_2=0 FN_3=0 FN_4=0 FN_8=0
FN_2=1 FN_3=0 FN_4=0 FN_8=0
FN_2=x FN_3=1 FN_4=0 FN_8=0
Figure 17. Five Overlapping DCO Ranges Controlled by FN_x Bits
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Max Min 1 20 27 DCO Tap Legend Tolerance at Tap 27 DCO Frequency Adjusted by Bits 29 to 25 in SCFI1 {N{DCO}} Tolerance at Tap 2 Overlapping DCO Ranges: Uninterrupted Frequency Range FN_2=x FN_3=x FN_4=1 FN_8=0 FN_2=x FN_3=x FN_4=x FN_8=1
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crystal oscillator, LFXT1 oscillator (see Notes 1 and 2)
PARAMETER TEST CONDITIONS OSCCAPx = 0h OSCCAPx = 1h CXIN Integrated load capacitance OSCCAPx = 2h OSCCAPx = 3h OSCCAPx = 0h OSCCAPx = 1h CXOUT Integrated load capacitance OSCCAPx = 2h OSCCAPx = 3h VIL VIH Input levels at XIN see Note 3 VCC 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V VSS 0.8xVCC MIN TYP 0 10 14 18 0 10 14 18 0.2xVCC VCC V pF pF MAX UNIT
NOTES: 1. The parasitic capacitance from the package and board may be estimated to be 2pF. The effective load capacitor for the crystal is (CXIN x CXOUT) / (CXIN + CXOUT). It is independent of XTS_FLL. 2. To improve EMI on the low-power LFXT1 oscillator, particularly in the LF mode (32 kHz), the following guidelines must be observe: * Keep as short a trace as possible between the 'xW42x and the crystal. * Design a good ground plane around oscillator pins. * Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. * Avoid running PCB traces underneath or adjacent to XIN an XOUT pins. * Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins. * If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins. * Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter. 3. Applies only when using an external logic-level clock source. XTS_FLL must be set. Not applicable when using a crystal or resonator. 4. External capacitance is recommended for precision real-time clock applications; OSCCAPx = 0h.
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electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
Scan IF, port drive, port timing
PARAMETER Voltage drop due to excitation transistor's on-resistance. (see Figure 18) Voltage drop due to damping transistor's on-resistance. (see Figure 18) TEST CONDITIONS VCC 3V MIN TYP MAX UNIT
VOL(SIFCHx)
I(SIFCHx) = 2.0 mA, SIFTEN = 1
0.3
V
VOH(SIFCHx) (see Note 1) VOL(SIFCOM) ISIFCHx(tri-state) tdSIFCH : twEx(tsm)-twSIFCH (see Note 2 and Figure 18)
I(SIFCHx) = -200 A, SIFTEN = 1 I(SIFCOM) = 3 mA, SIFSH = 1 V(SIFCHx) = 0 V to AVCC, port function disabled, SIFSH = 1
3V
0.1
V
2.2 V/3 V 3V
0 -50
0.1 50
V nA
Change of pulse width of internal signal SIFEX(tsm) to pulse width at pin SIFCHx
I(SIFCHx) = 3 mA, tEx(SIFCHx) = 500 ns 20%
2.2 V/3 V
-20
20
ns
NOTES: 1. SIFCOM=1.5V , supplied externally. (See Figure 19). 2. Not production tested. tEx(SIFCHx)
SIFEX(tsm)
P6.x/SIFCH.x tSIFCH(x)
Figure 18. P6.x/SIFCHx timing, SIFCHx function selected
SIFCOM
VOH(SIFCHx) I(SIFCHx) P6.x/SIFCH.x VOL(SIFCHx)
Damping Transistor
Excitation Transistor
Figure 19. Voltage drop due to on-resistance
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electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
Scan IF, sample capacitor/Ri timing (See Note 1)
PARAMETER CSHC(SIFCHx) Ri(SIFCHx) tHold (See Notes 1 and 2) Sample capacitance at SIFCHx pin Serial input resistance at the SIFCHx pin Maximum hold time TEST CONDITIONS SIFEx(tsm) = 1, SIFSH = 1 SIFEx(tsm) = 1, SIFSH = 1 Vsample < 3 mV VCC 2.2 V/3 V 2.2 V/3 V 62 MIN TYP 5 1.5 MAX 7 3 UNIT pF k s
NOTES: 1. Values are not production tested. 2. The sampled voltage at the sample capacitance varies less than 3 mV (Vsample) during the hold time tHold. If the voltage is sampled after tHold, the sampled voltage may be any other value. 3. The minimum sampling time (7.6 x tau for 1/2 LSB accuracy) with maximum CSHC(SIFCHx) and Ri(SIFCHx) and Ri(source) is tsample(min) ~ 7.6 x CSHC(SIFCHx) x (Ri(SIFCHx) + Ri(source)) with Ri(source) estimated at 3 k, tsample(min) = 319 ns.
Scan IF, VCC/2 generator
PARAMETER AVCC Analog supply voltage Scan IF VCC/2 generator operating supply current into AVCC terminal VCC/2 refresh frequency Output voltage at pin SIFCOM SIFCOM source current (see Note 2 and Figure 20) SIFCOM sink current (see Note 2 and Figure 20) Time to recover from Voltage Drop on Load Time to reach 98% after VCC/2 is switched on Settling time to VCC/512 (2 LSB) after AVCC voltage change ILoad1 = ILOAD3 = 0 mA ILoad2 = 3 mA, tload(on) = 500nS, CL at SIFCOM pin = 470 nF 20% CL at SIFCOM pin = 470 nF 20% frefresh(SIFCOM) = 32768 Hz SIFEN =1, SIFVCC2 =1, SIFSH =0, AVCC = AVCC -100 mV frefresh(SIFCOM) = 32768 Hz AVCC = AVCC + 100mV frefresh(SIFCOM) = 32768 Hz TEST CONDITIONS AVCC = DVCC (connected together) AVSS = DVSS (connected together) CL at SIFCOM pin = 470 nF 20%, frefresh(SIFCOM) =32768 Hz 2.2 V 3V 2.2 V/3 V Source clock = ACLK CL at SIFCOM pin = 470 nF 20%, I_Load = 1A 2.2 V 3V 2.2 V 3V 2.2 V/3 V 2.2 V/3 V 1.7 6 ms 30 AVCC/2 - .05 -500 -900 150 nA 180 30 s s A A 32.768 AVCC/2 + .05 kHz VCC MIN 2.2 250 370 TYP MAX 3.6 350 nA 450 UNIT V
AICC
frefresh(SIFCOM) V(SIFCOM)
AVCC/2
V
Isource(SIFCOM)
Isink(SIFCOM)
trecovery(SIFCOM)
ton(SIFCOM)
tVccSettle(SIFCOM) (See Note 1)
2.2 V/3 V
80 ms
2.2 V/3 V
3
NOTES: 1. The settling time after an AVCC voltage change is the time to for the voltage at pin SIFCOM to settle to AVCC/2 2LSB. 2. The sink and source currents are a function of the voltage at the pin SIFCOM. The maximum currents are reached if SIFCOM is shorted to GND or VCC. Due to the topology of the output section (refer to Figure 20) the VCC/2 generator can source relatively large currents but can sink only small currents.
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electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
VCC
VCC/2 ISource(SIFCOM) SIFCOM ISink(SIFCOM)
Figure 20. P6.x/SIFCHx timing, SIFCHx function selected Scan IF, 10-bit DAC (See Note 1)
PARAMETER AVCC Analog supply voltage Scan IF 10-bit DAC operating supply current into AVCC terminal RL = 1000 M, CL = 20 pF RL = 1000 M, CL = 20 pF Zero Scale Error Gain Error Output resistance On time after AVCC of SIFDAC is switched on V+SIFCA - VSIFDAC = 6 mV SIFDAC code = 1C0h 240h VSIFDAC(240h) - V+SIFCA = +6 mV SIFDAC code = 240h 1C0h, VSIFDAC(1C0h) - V+SIFCA = -6 mV 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V TEST CONDITIONS AVCC = DVCC (connected together) AVSS = DVSS (connected together) CL at SIFCOM pin = 470 nF 20%, frefresh(SIFCOM) = 32768 Hz 2.2 V 3V VCC MIN 2.2 23 33 10 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 25 2 5 1 10 0.6 50 2.0 2.0 2.0 TYP MAX 3.6 45 A A 60 bit LSB LSB mV % k s s s UNIT V
AICC Resolution INL DNL EZS EG RO ton(SIFDAC)
tSettle(SIFDAC)
Settling time
NOTES: 1. The SIFDAC operates from AVCC and SIFVSS. All parameters are based on these references.
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electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
Scan IF, Comparator
PARAMETER AVCC Analog supply voltage Scan IF comparator operating supply current into AVCC terminal Common Mode Input Voltage Range Input Offset Voltage Temperature coefficient of VOffset VOffset supply voltage (VCC) sensitivity Input Voltage Hysteresis On time after SIFCA is switched on Settle time V+terminal = V-terminal = 0.5 x VCC V+SIFCA - VSIFDAC = +6 mV V+SIFCA = 0.5 x AVCC V+SIFCA - VSIFDAC= -12 mV 6 mV V+SIFCA = 0.5 x AVCC TEST CONDITIONS AVCC = DVCC (connected together) AVSS = DVSS (connected together) 2.2 V 3V (see Note 1) 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2 V/3 V 2.2V 3.0V 2.2 V/3 V 0 0 10 0.3 5.0 6.0 2.0 0.9 VCC MIN 2.2 25 35 TYP MAX 3.6 35 50 AVCC - 0.5 30 A A UNIT V
AICC
VIC VOffset dVOffset/dT dVOffset/dVCC Vhys ton(SIFCA)
V mV V/_C mV/V mV us
tSettle(SIFCA)
2.2 V/3 V
2.0
us
NOTES: 1. The comparator output is reliable when at least one of the input signals is within the common mode input voltage range.
Scan IF, SIFCLK Oscillator
PARAMETER AVCC Analog supply voltage Scan IF oscillator operating supply current into AVCC terminal Scan IF oscillator at minimum setting Scan IF oscillator at nominal setting Scan IF oscillator at maximum setting Settling time to full operation after VCC is switched on Frequency Change per 1 SIFCLKFQ(SIFCTL5) step Temperature Coefficient Frequency vs. supply voltage VCC variation S(SIFCLK) = f(SIFCLKFQ + 1) / f(SIFCLKFQ) SIFCLKFQ(SIFCTL5) = 8 SIFCLKFQ(SIFCTL5) = 8 TA=25C, SIFCLKFQ=0000 TA=25C, SIFCLKFQ=0000 TA=25C, SIFCLKFQ=0000 TEST CONDITIONS AVCC = DVCC (connected together) AVSS = DVSS (connected together) 2.2 V 3V SIFNOM = 0 SIFNOM = 1 SIFNOM = 0 SIFNOM = 1 SIFNOM = 0 SIFNOM = 1 2.2 V/3 V 4.48 1.12 150 1.8 0.45 4 1 6.8 1.7 500 ns MHz VCC MIN 2.2 TYP MAX 3.6 75 90 3.2 0.8 A A UNIT V
AICC
fSIFCLKG = 0 fSIFCLKG = 8 fSIFCLKG = 15
ton(SIFCLKG)
S(SIFCLK) Dt DV
2.2 V/3 V 2.2 V/3 V 2.2 V/3 V
1.01
1.05
1.18 0.35 2
Hz/Hz %/_C %/V
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electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)
Flash Memory
PARAMETER VCC(PGM/ ERASE) fFTG IPGM IERASE tCPT tCMErase tRetention tWord tBlock, 0 tBlock, 1-63 tBlock, End tMass Erase tSeg Erase TEST CONDITIONS VCC MIN NOM MAX UNIT
Program and Erase supply voltage Flash Timing Generator frequency Supply current from DVCC during program Supply current from DVCC during erase Cumulative program time Cumulative mass erase time Program/Erase endurance Data retention duration Word or byte program time Block program time for 1st byte or word Block program time for each additional byte or word Block program end-sequence wait time Mass erase time Segment erase time see Note 3 TJ = 25C see Note 1 see Note 2 2.7 V/ 3.6 V 2.7 V/ 3.6 V 2.7 V/ 3.6 V 2.7 V/ 3.6 V
2.7 257 3 3 200 104 100 35 30 21 6 5297 4819
3.6 476 5 7 4 105
V kHz mA mA ms ms cycles years
tFTG
NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming methods: individual word/byte write and block write modes. 2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/fFTG,max = 5297x1/476kHz). To achieve the required cumulative mass erase time the Flash Controller's mass erase operation can be repeated until this time is met. (A worst case minimum of 19 cycles are required). 3. These values are hardwired into the Flash Controller's state machine (tFTG = 1/fFTG).
JTAG Interface
PARAMETER fTCK RInternal TCK input frequency Internal pull-up resistance on TMS, TCK, TDI/TCLK TEST CONDITIONS see Note 1 see Note 2 VCC 2.2 V 3V 2.2 V/ 3 V MIN 0 0 25 60 NOM MAX 5 10 90 UNIT MHz MHz k
NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected. 2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.
JTAG Fuse (see Note 1)
PARAMETER VCC(FB) VFB IFB tFB Supply voltage during fuse-blow condition Voltage level on TDI/TCLK for fuse-blow Supply current into TDI/TCLK during fuse blow Time to blow fuse TEST CONDITIONS TA = 25C VCC MIN 2.5 6 7 100 1 NOM MAX UNIT V V mA ms
NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched to bypass mode.
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APPLICATION INFORMATION input/output schematic
Port P1, P1.0 to P1.5, input/output with Schmitt-trigger
Pad Logic
CAPD.x P1SEL.x P1DIR.x Direction Control From Module P1OUT.x Module X OUT 0 1 0 1 Bus keeper P1.0/TA0.0 P1.1/TA0.0/MCLK P1.2/TA0.1 P1.3/TA1.0/SVSOUT P1.4/TA1.0 P1.5/TA0CLK/ACLK 0: Input 1: Output
P1IN.x EN Module X IN D P1IE.x P1IFG.x Q
P1IRQ.x
EN Set
Interrupt Edge Select P1IES.x P1SEL.x
NOTE: 0 x 5. Port Function is Active if CAPD.x = 0
PnSEL.x P1SEL.0 P1SEL.1 P1SEL.2 P1SEL.3 P1SEL.4 P1SEL.5 PnDIR.x P1DIR.0 P1DIR.1 P1DIR.2 P1DIR.3 P1DIR.4 P1DIR.5 Direction Control From Module P1DIR.0 P1DIR.1 P1DIR.2 P1DIR.3 P1DIR.4 P1DIR.5 PnOUT.x P1OUT.0 P1OUT.1 P1OUT.2 P1OUT.3 P1OUT.4 P1OUT.5 Module X OUT Out0 Sig. MCLK Out1 Sig. SVSOUT Out0 Sig. ACLK PnIN.x P1IN.0 P1IN.1 P1IN.2 P1IN.3 P1IN.4 P1IN.5 Module X IN CCI0A CCI0B CCI1A CCI0B CCI0A T0ACLK PnIE.x P1IE.0 P1IE.1 P1IE.2 P1IE.3 P1IE.4 P1IE.5 PnIFG.x P1IFG.0 P1IFG.1 P1IFG.2 P1IFG.3 P1IFG.4 P1IFG.5 PnIES.x P1IES.0 P1IES.1 P1IES.2 P1IES.3 P1IES.4 P1IES.5
Timer0_A Timer1_A
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APPLICATION INFORMATION input/output schematic (continued)
Port P1, P1.6, P1.7 input/output with Schmitt-trigger
Pad Logic Note: Port Function Is Active if CAPD.6 = 0 CAPD.6 P1SEL.6 0 P1DIR.6 P1DIR.6 P1OUT.6 DVSS P1IN.6 EN unused D P1IE.7 P1IRQ.07 Q P1IFG.7 Set EN Interrupt Edge Select 1 Bus Keeper 1 0 0: Input 1: Output P1.6/ CA0
P1IES.x
P1SEL.x
Comparator_A AVcc CAREF
P2CA CAEX CA0
CAF CCI1B to Timer_Ax + CA1 -
2 CAREF Reference Block
Pad Logic
Note: Port Function Is Active if CAPD.7 = 0 CAPD.7 P1SEL.7 P1DIR.7 P1DIR.7 0 P1OUT.7 DVSS P1IN.7 EN unused D 1 Bus Keeper 0 1 0: Input 1: Output P1.7/ CA1
P1IE.7 P1IRQ.07 Q P1IFG.7 Set EN Interrupt Edge Select
P1IES.7
P1SEL.7
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APPLICATION INFORMATION
input/output schematic (continued) port P2, P2.0 to P2.7, input/output with Schmitt-trigger
P2.0, P2.1 LCDM.5 LCDM.6 P2.2 to P2.5 LCDM.7 P2.6, P2.7 0: Port Active 1: Segment xx Function Active Segment xx Pad Logic
P2SEL.x P2DIR.x Direction Control From Module P2OUT.x Module X OUT 0 1 0 1 Bus keeper
0: Input 1: Output P2.x P2.0/TA0.2 P2.1/TA1.1 P2.2/TA1.2/S23 P2.3/TA1.3/S22 P2.4/TA1.4/S21 P2.5/TA1CLK/S20 P2.6/CAOUT/S19 P2.7/SIFCLKG/S18
P2IN.x EN Module X IN D P2IE.x P2IFG.x NOTE: 0 x 7
Direction Control From Module P2DIR.0 P2DIR.1 P2DIR.2 P2DIR.3 P2DIR.4 P2DIR.5 P2DIR.6 P2DIR.7
P2IRQ.x
Q
EN Set
Interrupt Edge Select P2IES.x P2SEL.x
PnIN.x P2IN.0 P2IN.1 P2IN.2 P2IN.3 P2IN.4 P2IN.5 P2IN.6 P2IN.7 Module X IN CCI2A CCI1A CCI2A CCI3A CCI4A TA1CLK1 Unused Unused PnIE.x P2IE.0 P2IE.1 P2IE.2 P2IE.3 P2IE.4 P2IE.5 P2IE.6 P2IE.7 PnIFG.x P2IFG.0 P2IFG.1 P2IFG.2 P2IFG.3 P2IFG.4 P2IFG.5 P2IFG.6 P2IFG.7 PnIES.x P2IES.0 P2IES.1 P2IES.2 P2IES.3 P2IES.4 P2IES.5 P2IES.6 P2IES.7
PnSEL.x P2SEL.0 P2SEL.1 P2SEL.2 P2SEL.3 P2SEL.4 P2SEL.5 P2SEL.6 P2SEL.7
PnDIR.x P2DIR.0 P2DIR.1 P2DIR.2 P2DIR.3 P2DIR.4 P2DIR.5 P2DIR.6 P2DIR.7
PnOUT.x P2OUT.0 P2OUT.1 P2OUT.2 P2OUT.3 P2OUT.4 P2OUT.5 P2OUT.6 P2OUT.7
Module X OUT Out2 Sig. Out1 Sig. Out2 Sig. Out3 Sig. Out4 Sig. DVSS CAOUT SIFCLKG
Timer0_A Timer1_A Scan IF
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MSP430xW42x MIXED SIGNAL MICROCONTROLLER
SLAS383A - OCTOBER 2003 - REVISED AUGUST 2004
APPLICATION INFORMATION
input/output schematic (continued) port P3, P3.0, P3.7, input/output with Schmitt-trigger
LCDM.5 LCDM.6 LCDM.7
P3.2 to P3.7
P3.0, P3.1 0: Port Active 1: Segment xx Function Active Segment xx Pad Logic
P3SEL.x P3DIR.x Direction Control From Module P3OUT.x Module X OUT 0 1 0 1
0: Input 1: Output P3.x Bus keeper P3.0/S17 P3.1/S16 P3.2/S15 P3.3/S14 P3.4/S13 P3.5/S12 P3.6/S11 P3.7/S10
P3IN.x EN Module X IN D
NOTE: 0 x 7
Direction Control From Module P3DIR.0 P3DIR.1 P3DIR.2 P3DIR.3 P3DIR.4 P3DIR.5 P3DIR.6 P3DIR.7 Module X OUT DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS
PnSEL.x P3SEL.0 P3SEL.1 P3SEL.2 P3SEL.3 P3SEL.4 P3SEL.5 P3SEL.6 P3SEL.7
PnDIR.x P3DIR.0 P3DIR.1 P3DIR.2 P3DIR.3 P3DIR.4 P3DIR.5 P3DIR.6 P3DIR.7
PnOUT.x P3OUT.0 P3OUT.1 P3OUT.2 P3OUT.3 P3OUT.4 P3OUT.5 P3OUT.6 P3OUT.7
PnIN.x P3IN.0 P3IN.1 P3IN.2 P3IN.3 P3IN.4 P3IN.5 P3IN.6 P3IN.7
Module X IN Unused Unused Unused Unused Unused Unused Unused Unused
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MSP430xW42x MIXED SIGNAL MICROCONTROLLER
SLAS383A - OCTOBER 2003 - REVISED AUGUST 2004
APPLICATION INFORMATION
input/output schematic (continued) port P4, P4.0 to P4.7, input/output with Schmitt-trigger
LCDM.5 LCDM.6 LCDM.7 Segment xx 0: Port Active 1: Segment xx Function Active
Pad Logic
P4SEL.x P4DIR.x Direction Control From Module P4OUT.x Module X OUT 0 1 0 1
0: Input 1: Output P4.x Bus keeper P4.0/S9 P4.1/S8 P4.2/S7 P4.3/S6 P4.4/S5 P4.5/S4 P4.6/S3 P4.7/S2
P4IN.x EN Module X IN D
NOTE: 0 x 7
Direction Control From Module P4DIR.0 P4DIR.1 P4DIR.2 P4DIR.3 P4DIR.4 P4DIR.5 P4DIR.6 P4DIR.7 Module X OUT DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS
PnSEL.x P4SEL.0 P4SEL.1 P4SEL.2 P4SEL.3 P4SEL.4 P4SEL.5 P4SEL.6 P4SEL.7
PnDIR.x P4DIR.0 P4DIR.1 P4DIR.2 P4DIR.3 P4DIR.4 P4DIR.5 P4DIR.6 P4DIR.7
PnOUT.x P4OUT.0 P4OUT.1 P4OUT.2 P4OUT.3 P4OUT.4 P4OUT.5 P4OUT.6 P4OUT.7
PnIN.x P4IN.0 P4IN.1 P4IN.2 P4IN.3 P4IN.4 P4IN.5 P4IN.6 P4IN.7
Module X IN Unused Unused Unused Unused Unused Unused Unused Unused
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41
MSP430xW42x MIXED SIGNAL MICROCONTROLLER
SLAS383A - OCTOBER 2003 - REVISED AUGUST 2004
APPLICATION INFORMATION
input/output schematic (continued) port P5, P5.0, P5.1, input/output with Schmitt-trigger
LCDM.5 LCDM.6 LCDM.7 Segment xx or COMx or Rxx P5SEL.x P5DIR.x Direction Control From Module P5OUT.x Module X OUT 0 1 0 1 P5.x Bus keeper P5.0/S1 P5.1/S0 0: Port Active 1: Segment Function Active
Pad Logic
0: Input 1: Output
P5IN.x EN Module X IN D
NOTE: x = 0, 1
Direction Control From Module P5DIR.0 P5DIR.1
PnSEL.x P5SEL.0 P5SEL.1
PnDIR.x P5DIR.0 P5DIR.1
PnOUT.x P5OUT.0 P5OUT.1
Module X OUT DVSS DVSS
PnIN.x P5IN.0 P5IN.1
Module X IN Unused Unused
Segment S1 S0
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MSP430xW42x MIXED SIGNAL MICROCONTROLLER
SLAS383A - OCTOBER 2003 - REVISED AUGUST 2004
APPLICATION INFORMATION
input/output schematic (continued) port P5, P5.2, P5.4, input/output with Schmitt-trigger
0: Port Active 1: COMx Function Active COMx
Pad Logic
P5SEL.x P5DIR.x Direction Control From Module P5OUT.x Module X OUT 0 1 0 1
0: Input 1: Output P5.x Bus keeper P5.2/COM1 P5.3/COM2 P5.4/COM3
P5IN.x EN Module X IN D
NOTE: 2 x 4
Direction Control From Module P5DIR.2 P5DIR.3 P5DIR.4 Module X OUT DVSS DVSS DVSS
PnSEL.x P5SEL.2 P5SEL.3 P5SEL.4
PnDIR.x P5DIR.2 P5DIR.3 P5DIR.4
PnOUT.x P5OUT.2 P5OUT.3 P5OUT.4
PnIN.x P5IN.2 P5IN.3 P5IN.4
Module X IN Unused Unused Unused
COMx COM1 COM2 COM3
NOTE: The direction control bits P5SEL.2, P5SEL.3, and P5SEL.4 are used to distinguish between port and common functions. Note that a 4MUX LCD requires all common signals COM3 to COM0, a 3MUX LCD requires COM2 to COM0, 2MUX LCD requires COM1 to COM0, and a static LCD requires only COM0.
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43
MSP430xW42x MIXED SIGNAL MICROCONTROLLER
SLAS383A - OCTOBER 2003 - REVISED AUGUST 2004
APPLICATION INFORMATION
input/output schematic (continued) port P5, P5.5 to P5.7, input/output with Schmitt-trigger
0: Port Active 1: Rxx Function Active Rxx
Pad Logic
P5SEL.x P5DIR.x Direction Control From Module P5OUT.x Module X OUT 0 1 0 1
0: Input 1: Output P5.x Bus keeper P5.5/R13 P5.6/R23 P5.7/R33
P5IN.x EN Module X IN D
NOTE: 5 x 7
Direction Control From Module P5DIR.5 P5DIR.6 P5DIR.7 Module X OUT DVSS DVSS DVSS
PnSEL.x P5SEL.5 P5SEL.6 P5SEL.7
PnDIR.x P5DIR.5 P5DIR.6 P5DIR.7
PnOUT.x P5OUT.5 P5OUT.6 P5OUT.7
PnIN.x P5IN.5 P5IN.6 P5IN.7
Module X IN Unused Unused Unused
Rxx R13 R23 R33
NOTE: The direction control bits P5SEL.5, P5SEL.6, and P5SEL.7 are used to distinguish between port and LCD analog level functions. Note that 4MUX and 3MUX LCDs require all Rxx signals R33 to R03, a 2MUX LCD requires R33, R13, and R03, and a static LCD requires only R33 and R03.
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MSP430xW42x MIXED SIGNAL MICROCONTROLLER
SLAS383A - OCTOBER 2003 - REVISED AUGUST 2004
APPLICATION INFORMATION
input/output schematic (continued) port P6, P6.0, P6.1, P6.2, P6.4, P6.5, input/output with Schmitt-trigger
P6SEL.x P6DIR.x Direction Control From Module 0 1 0 1 P6.0/SIFCH0 P6.1/SIFCH1 P6.2/SIFCH2 P6.4/SIFCI0 P6.5/SIFCI1 Bus Keeper P6IN.x EN Module X IN D 0: Input 1: Output Pad Logic
P6OUT.x Module X OUT
P6.X
To/From Scan I/F P6SEL.x must be set if the corresponding pins are used by the Scan IF.
x: Bit Identifier = 0, 1, 2, 4, or 5 NOTE: Analog signals applied to digital gates can cause current flow from the positive to the negative terminal. The throughput current flows if the analog signal is in the range of transitions 01 or 10. The value of the throughput current depends on the driving capability of the gate. For MSP430, it is approximately 100 A. Use P6SEL.x=1 to prevent throughput current. P6SEL.x should be set, if an analog signal is applied to the pin. PnSEL.x P6Sel.0 P6Sel.1 P6Sel.2 P6Sel.4 P6Sel.5 PnDIR.x P6DIR.0 P6DIR.1 P6DIR.2 P6DIR.4 P6DIR.5 Dir. Control From Module P6DIR.0 P6DIR.1 P6DIR.2 P6DIR.4 P6DIR.5 PnOUT.x P6OUT.0 P6OUT.1 P6OUT.2 P6OUT.4 P6OUT.5 Module X OUT DVSS DVSS DVSS DVSS DVSS PnIN.x P6IN.0 P6IN.1 P6IN.2 P6IN.4 P6IN.5 Module X IN unused unused unused unused unused
NOTE: The signal at pins P6.x/SIFCHx and P6.x/SIFCIx are shared by Port P6 and the San IF module. P6SEL.x must be set if the corresponding pins are used by the Scan IF.
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45
MSP430xW42x MIXED SIGNAL MICROCONTROLLER
SLAS383A - OCTOBER 2003 - REVISED AUGUST 2004
APPLICATION INFORMATION
input/output schematic (continued) port P6, P6.3 input/output with Schmitt-trigger
P6SEL.3 P6DIR.3 0 1 0 1 0: Input 1: Output Pad Logic P6OUT.x SIFCAOUT P6.3/SIFCH3/SIFCAOUT
Bus Keeper P6IN.3 EN Module X IN D
To/From Scan I/F P6SEL.x must be set if the corresponding pins are used by the Scan IF. NOTE: Analog signals applied to digital gates can cause current flow from the positive to the negative terminal. The throughput current flows if the analog signal is in the range of transitions 01 or 10. The value of the throughput current depends on the driving capability of the gate. For MSP430, it is approximately 100 A. Use P6SEL.x=1 to prevent throughput current. P6SEL.x should be set, if an analog signal is applied to the pin. P6SEL.3 0 0 1 1 P6DIR.3 0 1 0 1 Port Function P6.3 Input P6.3 Output SIFCH3 (Scan IF channel 3 excitation output and comparator input) SIFCAOUT (Comparator output)
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MSP430xW42x MIXED SIGNAL MICROCONTROLLER
SLAS383A - OCTOBER 2003 - REVISED AUGUST 2004
APPLICATION INFORMATION
input/output schematic (continued) port P6, P6.6 input/output with Schmitt-trigger
P6SEL.6 P6DIR.6 0 1 0 1 0: Input 1: Output Pad Logic P6.6/SIFCI2/DACOUT
P6OUT.6 DVss
Bus Keeper P6IN.6 EN Module X IN D
From Scan I/F DAC To Scan I/F comparator input mux P6SEL.x must be set if the corresponding pins are used by the Scan IF.
1
NOTE: Analog signals applied to digital gates can cause current flow from the positive to the negative terminal. The throughput current flows if the analog signal is in the range of transitions 01 or 10. The value of the throughput current depends on the driving capability of the gate. For MSP430, it is approximately 100 A. Use P6SEL.x=1 to prevent throughput current. P6SEL.x should be set, if an analog signal is applied to the pin. P6SEL.6 0 0 1 1 P6DIR.6 0 1 0 1 Port Function P6.6 Input P6.6 Output SIFCI2 (Scan IF channel 2 comparator input) SIFDAOUT (Scan IF DAC output)
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47
MSP430xW42x MIXED SIGNAL MICROCONTROLLER
SLAS383A - OCTOBER 2003 - REVISED AUGUST 2004
APPLICATION INFORMATION
input/output schematic (continued) port P6, P6.7 input/output with Schmitt-trigger
SVS VLDx=15 P6SEL.7 P6DIR.7 0 1 0 1 0: Input 1: Output Pad Logic P6.7/SIFCI3/SVSIN
P6OUT.7 DVss
Bus Keeper P6IN.7 EN Module X IN D
SVS VLDx=15 To SVS To Scan I/F comparator (+) terminal P6SEL.x must be set if the corresponding pins are used by the Scan IF. NOTE: Analog signals applied to digital gates can cause current flow from the positive to the negative terminal. The throughput current flows if the analog signal is in the range of transitions 01 or 10. The value of the throughput current depends on the driving capability of the gate. For MSP430, it is approximately 100 A. Use P6SEL.x=1 to prevent throughput current. P6SEL.x should be set, if an analog signal is applied to the pin. SVS VLDx = 15 0 0 0 1 P6SEL.7 0 0 1 X P6DIR.7 0 1 X X Port Function P6.7 Input P6.7 Output SIFCI3 (Scan IF channel 3 comparator input) SVSIN 1
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MSP430xW42x MIXED SIGNAL MICROCONTROLLER
SLAS383A - OCTOBER 2003 - REVISED AUGUST 2004
APPLICATION INFORMATION JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt-trigger or output
TDO Controlled by JTAG Controlled by JTAG JTAG Controlled by JTAG TDI DVCC TDO/TDI
Burn and Test Fuse TDI/TCLK Test and Emulation Module TMS DVCC TCK TCK RST/NMI TMS DVCC
Tau ~ 50 ns Brownout G D U S D U S
TCK
G
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MSP430xW42x MIXED SIGNAL MICROCONTROLLER
SLAS383A - OCTOBER 2003 - REVISED AUGUST 2004
APPLICATION INFORMATION JTAG fuse check mode
MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current, ITF , of 1.8 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned. Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption. Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse check mode has the potential to be activated. The fuse check current only flows when the fuse check mode is active and the TMS pin is in a low state (see Figure 21). Therefore, the additional current flow can be prevented by holding the TMS pin high (default condition). The JTAG pins are terminated internally, and therefore do not require external termination.
Time TMS Goes Low After POR TMS
ITDI/TCLK
ITF
Figure 21. Fuse Check Mode Current, MSP430FW42x
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MECHANICAL DATA
MTQF008A - JANUARY 1995 - REVISED DECEMBER 1996
PM (S-PQFP-G64)
0,27 0,17 48 33
PLASTIC QUAD FLATPACK
0,50
0,08 M
49
32
64
17 0,13 NOM
1 7,50 TYP 10,20 SQ 9,80 12,20 SQ 11,80 1,45 1,35
16 Gage Plane
0,25 0,05 MIN 0- 7
0,75 0,45
Seating Plane 1,60 MAX 0,08 4040152 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Falls within JEDEC MS-026 May also be thermally enhanced plastic with leads connected to the die pads.
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1
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