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MK1574-01
3.3 VOLT FRAME RATE COMMUNICATIONS PLL
Description
The MK1574-01 is a Phase-Locked Loop (PLL) based clock synthesizer, which accepts an 8 kHz clock input as a reference, and generates many popular communications frequencies. All outputs are frequency locked together and to the input. This allows for the generation of locked clocks to the 8 kHz backplane clock, simplifying clock generation and distribution in communications systems. ICS manufactures the largest variety of clock generators and buffers, and can customize this device for a variety of frequencies.
Features
* * * * *
3.3 volt operation Packaged in 16-pin SOIC Accepts 8 kHz input clock Output clock rates include T1, E1, T2, E2 Available in commercial (0 to + 70C) or industrial (-40 to +85C) temperature ranges
* For jitter attenuation, use the MK2049 * For 5.0 V operation, use the MK1574-01A
Block Diagram
VDD GND
2
2
CLK1
FS0-3
4
8 kHz input clock
Input Buffer
PLL Clock Synthesis and Control Circuitry
CLK2 CLK3 8 kHz (recovered)
CAP1
CAP2
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MK1574-01 3.3 VOLT FRAME RATE COMMUNICATIONS PLL
Pin Assignment
ICLK VDD VDD CAP1 GND CAP2 GND FS0 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 FS3 NC FS2 FS1 CLK3 CLK2 CLK1 8KOUT
Output Clocks Decoding Table
Decode FS3:0
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Address (Hex)
0 1 2 3 4 5 6 7 8 9 A B C D E F
ICLK pin1
Reserved Reserved Reserved Reserved 8.00 kHz 8.00 kHz 8.00 kHz 8.00 kHz 8.00 kHz 8.00 kHz 8.00 kHz 8.00 kHz 8.00 kHz 8.00 kHz 8.00 kHz 8.00 kHz
Multiplier On-chip
Reserved Reserved Reserved Reserved 2940 1960 2760 2640 1920 6480 2112 1578 8192 6176 1024 772
CLK1 pin 10
Reserved Reserved Reserved Reserved 23.52 15.68 22.08 21.12 15.36 51.84 16.896 12.624 65.536 49.408 8.192 60176
CLK2 pin 11
Reserved Reserved Reserved Reserved 11.76 7.84 11.04 10.56 7.68 25.92 8.448 6.312 32.768 24.704 4.096 3.088
CLK3 pin 12
Reserved Reserved Reserved Reserved 5.88 3.92 5.52 5.28 3.84 12.96 4.224 3.156 16.384 12.352 2.048 1.544
0 = connect directly to ground, 1 = connect directly to VDD.
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MK1574-01 3.3 VOLT FRAME RATE COMMUNICATIONS PLL
Pin Descriptions
Pin Number
1 2 3 4
Pin Name
ICLK VDD VDD CAP1
Pin Type
Input Power Power Input Connect to 3.3 V. Connect to 3.3 V.
Pin Description
Clock input. Connect to an 8 kHz clock input.
Connect to a ceramic capacitor and a resistor in series between this pin and CAP2. Refer to the section "Loop Bandwidth and Loop Filter Component Selection". Connect to ground. Connect to a ceramic capacitor and a resistor in series between this pin and CAP1. Refer to the section "Loop Bandwidth and Loop Filter Component Selection". Connect to ground. Frequency select 0. Determines CLK outputs per table above.
5 6
GND CAP2
Power Power
7 8 9 10 11 12 13 14 15 16
GND FS0 8KOUT CLK1 CLK2 CLK3 FS1 FS2 NC FS3
Power Input
Output Recovered 8 kHz output clock. Can be low jitter, better duty cycle than clock input. Output Clock 1 determined by status of FS3:0 per table above. Output Clock 2 determined by status of FS3:0 per table above. Output Clock 3 determined by status of FS3:0 per table above. Input Input -- Input Frequency select 1. Determines CLK outputs per table above. Frequency select 2. Determines CLK outputs per table above. No connect. Do not connect anything to this pin. Frequency select 3. Determines CLK outputs per table above.
External Components
The MK1574-01 requires a minimum number of external components for proper operation. An RC network (see the section "Loop Bandwidth and Loop Filter Component Selection") should be connected between CAP1 and CAP2 as close tot he device as possible. Decoupling capacitors of 0.01F should be connected between VDD and GND on pins 2, 3, 5 and 7, as close to the device as possible. A series termination resistor of 33 may be used close to each clock output pin to reduce reflections.
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MK1574-01 3.3 VOLT FRAME RATE COMMUNICATIONS PLL
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK1574-01. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD (referenced to GND) All Inputs and Outputs Ambient Operating Temperature (commercial) Ambient Operating Temperature (industrial) Storage Temperature Junction Temperature Soldering Temperature -0.5 V to 7 V
Rating
-0.5 V to VDD+0.5 V 0 to +70C -40 to +85C -65 to +150C 150C 260C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature (commercial) Ambient Operating Temperature (industrial) Power Supply Voltage (measured in respect to GND)
Min.
0 -40 +3.13
Typ.
Max.
+70 +85 +5.5
Units
C C
V
DC Electrical Characteristics
VDD = 5 V, Ambient temperature 0 to +70C, unless stated otherwise
Parameter
Operating Voltage Input High Voltage Input Low Voltage Output High Voltage Output High Voltage Output Low Voltage Operating Supply Current Short Circuit Current Input Capacitance
Symbol
VDD VIH VIL VOH VOH VOL IDD IOS CIN
Conditions
Min.
3.0 2
Typ.
Max.
3.6 0.8
Units
V V V V V
IOH = -4 mA IOH = -25 mA IOL = 25 mA No Load Each output
VDD-0.4 2.4 0.4 13 100 7
V mA mA pF
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MK1574-01 3.3 VOLT FRAME RATE COMMUNICATIONS PLL
AC Electrical Characteristics
VDD = 5 V, Ambient Temperature 0 to +70C, unless stated otherwise
Parameter
Input Frequency Output Clock Rise Time Output Clock Fall Time Output Clock Duty Cycle, High time Absolute Clock Period Jitter Actual Mean Frequency Error Versus Target (note 1)
Symbol
fIN tOR tOF tDC
Conditions
0.8 to 2.0 V 2.0 to 0.8 V At VDD/2
Min.
Typ.
8.000
Max. Units
kHz 1.5 1.5 ns ns % ns
40 1
49 to 51
60
Any clock selection
0
0
ppm
Note 1: All multipliers as shown in the table on page two are exact, and are stored in ROM on the chip.
Thermal Characteristics
Parameter
Thermal Resistance Junction to Ambient
Symbol
JA JA JA JC
Conditions
Still air 1 m/s air flow 3 m/s air flow
Min.
Typ.
120 115 105 58
Max. Units
C/W C/W C/W C/W
Thermal Resistance Junction to Case
Loop Bandwidth and Loop Filter Component Selection
The series-connected capacitor and resistor between CAP1 and CAP2 (pins 4 and 6) determine the dynamic characteristics of the phase-locked loop. The capacitor must have very low leakage, therefore a high quality ceramic capacitor is recommended. DO NOT use any type of polarized or electrolytic capacitor. The series connected capacitor and resistor between CAP1 and CAP2 (pins 4 and 6) determine the dynamic characteristics of the phase-locked loop. The capacitor must have very low leakage, therefore a high quality ceramic capacitor is recommended. DO NOT use any type of polarized or electrolytic capacitor. Ceramic capacitors should have C0G or NP0 dielectric. Avoid high-K dielectrics like Z5U and X7R; these and other ceramics which have piezoelectric properties allow mechanical vibration in the system to increase the output jitter because the mechanical energy is converted directly to voltage noise on the VCO input. The values of the RC network determine the bandwidth of the PLL. The values of the loop filter components are calculated using the constants K1 and K2 from the Loop Filter Constants table (page 7). The loop bandwidth is set by the capacitor C and the constant K1 using the formula: BW (Hz) = K1 C Equation 1
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MK1574-01 3.3 VOLT FRAME RATE COMMUNICATIONS PLL
The loop damping is set by the resistor R, the capacitor C, and the constant K2 using the formula:: R=
* K2
Equation 2; (zeta) is the damping factor
C
For example, to design the loop filter whewn generating 8.192 MHz from 8 kHz: 1. From the Output Clock Decoding table (page 2), the address is E. The Loop Filter Constants table (page 7) shows the constants K1 = 0.0516 and K2 = 6.2. 2. A good value for the loop bandwidth is 1/20 the input frequency; where 8 kHz/20 = 400 Hz. Using equation 1, 400 = K1 C
Therefore, C= ( 0.0516 ) 2 = 16.6 nF (16 nF nearest standard value 400
3. A good value for the damping factor is 0.707. From equation 2, R= 0.707 * 6.2 16E-9 = 34.7 k (36 k nearest standard value)
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MK1574-01 3.3 VOLT FRAME RATE COMMUNICATIONS PLL
Loop Filter Constants
This table shows the constants K1 and K2 that are used with the equations on page 6 to calculate the external loop filter components.
Loop Filter Contstants for MK1574-01 Decode FS3:0
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Address (Hex)
0 1 2 3 4 5 6 7 8 9 A B C D E F
Loop Filter Constants K1
Reserved Reserved Reserved Reserved 0.0430 0.0527 0.0444 0.0454 0.0533 0.0410 0.0508 0.0587 0.0365 0.0420 0.0516 0.0594
K2
Reserved Reserved Reserved Reserved 7.4 6.0 7.2 7.0 6.0 7.8 6.3 5.4 8.7 7.6 6.2 5.4
PC Board Layout
A proper board layout is critical to the successful use of the MK1574-01. In particular, the CAP1 and CAP2 pins are very sensitive to noise and leakage (CAP1 at pin 4 is the most sensitive). Traces must be as short as possible and the capacitor and resistor must be mounted next to the device as shown to the right. The capacitor connected between pins 3 and 5 is the power supply decoupling capacitor. The high frequency output clocks on may benefit from a series 33 resistor connected close to the pin (not shown).
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MK1574-01 3.3 VOLT FRAME RATE COMMUNICATIONS PLL Clock Multipliers/Accuracies
In the table on page 2 are the actual multipliers stored in the MK1574-01 ROM, which yield the exact values shown for the output clocks.
Package Outline and Package Dimensions (16-pin SOIC, 150 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
16
Millimeters Symbol
E INDEX AREA H
Inches Min Max
Min
Max
12 D
A A1 B C D E e H h L
h x 45
1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 9.80 10.00 3.80 4.00 1.27 BASIC 5.80 6.20 0.25 0.50 0.40 1.27 0 8
.0532 .0688 .0040 .0098 .013 .020 .0075 .0098 .3859 .3937 .1497 .1574 0.050 BASIC .2284 .2440 .010 .020 .016 .050 0 8
A A1
C
-Ce
B SEATING PLANE L
.10 (.004)
C
Ordering Information
Part / Order Number
MK1574-01S MK1574-01STR MK1574-01SI MK1574-01SITR
Marking
MK1574-01S MK1574-01S MK1574-01SI MK1574-01SI
Shipping Packaging
Tubes Tape and Reel Tubes Tape and Reel
Package
16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC
Temperature
0 to +70 C 0 to +70 C -40 to +85 C -40 to +85 C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 1574-01 E Integrated Ci rcu it Systems
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