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| Features * High Speed - 180 ps Gate Delay - 2 Input NAND, FO = 2 (nominal) * Up to 1.198M Used Gates and 512 Pads with 3.3V, 3V and 2.5V Libraries when Tested to Space Quality Grades * Up to 1.6M Used Gates and 596 Pads with 3.3V, 3V and 2.5V Libraries when Tested to Military Quality Grades * System Level Integration Technology Cores on Request: - Memory: SRAMs and TPRAMs; Gate Level or Embedded, with EDACS * I/O Interfaces: - 5V Tolerant/Compliant (S) or 3V (R) Matrix Options - CMOS, LVTTL, LVDS, PCI, USB, etc. - Output Currents Programmable from 2 to 24 mA, by Step of 2 mA - Cold Sparing Buffers (2 A Max. Leakage Current at 3.6V Worst Case Mil Temp.) 250 MHz PLL (on request), 220 MHz LVDS and 800 MHz Max. Toggle Frequency at 3.3V Deep Submicron CAD Flow Latch-up Immune, 200K rads Total Dose Capability, SEU Free Cells and 4000V ESD Protection QML Q and V with SMD 5962-01B01 * * * * Rad Hard 1.6M Used Gates 0.35 m CMOS Sea of Gates/ Embedded Array Description The MH1RT Series Gate Array and Embedded Array families from Atmel are fabricated on a radiation tolerant 0.35 micron CMOS process, with up to 4 levels of metal for interconnect. This family features arrays with up to 1.6 million routable gates and 596 pads. The high density and high pin count capabilities of the MH1RT family, coupled with the ability to embed cores or memory on the same silicon, makes the MH1RT series of arrays an ideal choice for System Level Integration. The MH1RT series is supported by an advanced software environment based on industry standards linking proprietary and commercial tools. Verilog(R), DFT(R), Synopsys(R) and Vital are the reference front end tools. The Cadence(R) `Logic Design Planner' floor planning associated with timing driven layout provides an efficient back end cycle. The MH1RT series comes as a dual use of the MH1 series, adding: - through process changes, the 100 MeV latch-up immunity and the 200K rads+ total dose capability as required by most space programs - through cells relayout, an SEU immunity allowing to SEU harden only where it is necessary with respect to function requirements With a background of 15 years experience, the MH1RT series comes as the Atmel 7th generation of ASIC series designed for radiation hardened applications. MH1RT Rev. 4110F-AERO-06/02 1 Table 1. MH1RT Array Organization Device Number MH1099E MH1156E MH1242E MH1332E(2) Notes: Max. Sites Count 921,000 1,452,000 2,275,000 3,105,000 4 LM Routable Gates (Typ) 519,000 764,000 1,198,000 1,634,000 Max. Pad Count 332 412 512 596 Max. I/O Count 324 404 504 588 Gate Speed(1) 180 ps 180 ps 180 ps 180 ps 1. Nominal 2 Input NAND Gate FO = 2 at 3.3V. 2. Available only when tested to mil quality grades. Design Design Systems Supported Atmel supports several major software systems for design with complete macro cell libraries, as well as utilities for checking the netlist and estimated pre-route delay simulations. The following design systems are supported: Table 2. Supported design systems System Available/Planned Tools Pearl(R) - Static Path Verilog-XL(R) - Verilog Simulator Logic Design PlannerTM - Floorplanner BuildGates(R) - Synthesis (Ambit) Modelsim Verilog and VHDL (VITAL) Simulator Leonardo SpectrumTM - Synthesis Velocity - Static Path DFT- Scan insertion and ATPG, BIST Design CompilerTM - Synthesis Test CompilerTM - Scan Insertion and ATPG TestGenTM - Scan Insertion and ATPG Primetime(R) - Static Path Cadence Mentor/Model Tech Synopsys(R) 2 MH1RT 4110F-AERO-06/02 MH1RT Design Flow and Tools Atmel's design flow for Gate Arrays/Embedded Arrays is structured to allow the designer to consolidate the greatest number of system components possible onto the same silicon chip, using available third party design tools. Atmel's cell library reflects silicon performance over extremes of temperature, voltage, and process, and includes the effects of metal loading, inter-level capacitance, and edge rise and fall times. The Design Flow includes clock tree synthesis to customer specified skew and latency goals. RC extraction is performed on final design database and incorporated into the timing analysis. The Typical Gate Array/Embedded Array Design Flow, shown on page 4, provides a pictorial description of the typical interaction between Atmel's Gate Array/Embedded Array design staff and the customer. Atmel will deliver design kits to support the customer's synthesis, verification, floorplanning, and SCAN insertion activities. Tools such as Synopsys, Cadence, Verilog-HDL and CTgenTM are used, and many others are available. Should a design include embedded memory or an embedded core, Atmel will support a design review with the customer. The purpose of the design review is to permit Atmel to understand the partition of the Gate Array/Embedded Array, and define the location of the memory blocks and/or cores so that an underlayer layout model can be created. Following a Preliminary Design Review, the design is routed, and post-route RC data is extracted. Following post-route verification and a Final Design Review, the design is taped out for fabrication. 3 4110F-AERO-06/02 Figure 1. Typical Gate Array/Embedded Array Design Flow Atmel Atmel Atmel Tape Out Underlayer Logic Atmel Atmel Atmel Atmel Atmel Joint Atmel Customer Rev.1.5 - 03/2001 4 MH1RT 4110F-AERO-06/02 MH1RT Pin Definition Requirements The corner pads are reserved for Power and Ground only. All other pads are fully programmable as Input, Output, Bidirectional, Power or Ground. When implementing a design with 5V tolerant buffers, one buffer site must be reserved for the VDD5 pin, which is used to distribute power to the buffers. Figure 2. Gate Array Figure 3. Embedded Array SRAM Standard Gate Array Architecture Core Core I/O Site: Pad and SubSections The I/O sites are configurable as input, output, 3-state output and bidirectional buffers, each with pullup or pulldown capability, if required, by utilizing their corresponding subsection. Bidirectionnal buffers are the result of an input and output buffers placed in adjacent sub-sections in the same I/O site. Special buffers may require multiple I/O sites. Oscillators require 2 I/O sites, each power and ground pin utilizes one I/O site. PCI compatible input and output buffers are available for each bias voltage, 3 and 5V. Each LVDS buffer uses 2 I/O sites. LVDS drivers are specific for each bias voltage and require one external current bias resistor per chip; LVDS receiver is the same for all bias voltages and requires 1 external line matching 100 k resistor per receiver. PCI Buffers LVDS Buffers Cold Sparring It is the use of twice the same chip, A1 and A2, A1 ON and A2 OFF, with all signal pins/pads connected by pairs, A1I1 with A2I1, A101 with A201,... 5 4110F-AERO-06/02 During this mode operation: - - the chip OFF must survive and operate when turned ON without functional, AC, DC or reliability impact, the current pulled by the OFF chip must be limited to a low value: Atmel specification for their dedicated cold sparring buffers is 2 A worst case by signal pins/pads. For any other operation mode, refer to maximum ratings. Memory Blocks Memory blocks can be either synthesized on gates (when smaller than 8 bits) or compiled and embedded in the array itself; various combinations of Through Flow or Bus Watch EDACs, 4, 8, 16 and 32 wide, can be used to alleviate the effect of SEU induced errors. Design Options ASIC Design Translation Atmel has successfully translated existing designs from most major ASIC vendors (LSI Logic(R), Motorola(R), SMOS(R), Oki(R), NEC(R), Fujitsu(R), AMI(R) and others) into the gate arrays. These designs have been optimized for speed and gate count and modified to add logic or memory, or replicated for a pin-for-pin compatible, drop-in replacement. Design entry is performed by the customer using an Atmel provided macro cell library. A complete netlist and vector set must then be provided to Atmel. Upon acceptance of this data set, Atmel continues with the standard design flow. Atmel has successfully translated existing FPGA/PLD designs from most major vendors (Xilinx(R), Actel(R), Altera(R), AMD(R) and Atmel) into the gate arrays. There are four primary reasons to convert from an FPGA/PLD to a gate array. Conversion of high volume devices for a single or combined design is cost effective. Performance can often be optimized for speed or low power consumption. Several FPGA/PLDs can be combined onto a single chip to minimize cost while reducing on-board space requirements. Finally, in situations where an FPGA/PLD was used for fast cycle time prototyping, a gate array may provide a lower cost answer for long-term volume production. Design Entry FPGA and PLD Conversions 6 MH1RT 4110F-AERO-06/02 MH1RT Cell Library Atmel's MH1RT Series gate arrays make use of an extensive library of macro cell structures, including logic cells, buffers and inverters, multiplexers, decoders, and I/O options. Soft macros are also available. The MH1RT Series PLL operates at frequencies of up to 250 MHz with minimal phase error and jitter, making it ideal for frequency synthesis of high speed on-chip clocks and chip to chip synchronization. These cells are well characterized by use of SPICE modeling at the transistor level, with performance verified on manufactured test arrays. Characterization is performed over the rated temperature and voltage ranges to ensure that the simulation accurately predicts the performance of the finished product. Table 3. Cell Index Cell Name ADD3X AND2 AND2H AND3 AND3H AND4 AND4H AND5 AOI22 AOI22H AOI222 AOI222H AOI2223 AOI2223H AOI23 BUF1 BUF2 BUF2T BUF2Z BUF3 BUF4 BUF4T CLA7X DEC4 Description 1 bit full adder with buffered outputs 2 input AND 2 input AND - high drive 3 input AND 3 input AND - high drive 4 input AND 4 input AND - high drive 5 input AND 2 input AND into 2 input NOR 2 input AND into 2 input NOR - high drive Two, 2 input ANDs into 2 input NOR Two, 2 input ANDs into 2 input NOR - high drive Three, 2 input ANDs into 3 input NOR Three, 2 input ANDs into 3 input NOR - high drive 2 input AND into 3 input NOR 1x buffer 2x buffer 2x Tri State bus driver with active high enable 2x Tri State bus driver with active low enable 3x buffer 4x buffer 4x Tri-State bus driver with active high enable 7 input carry lookahead 2:4 decoder Gate Count 10 2 3 3 4 3 4 5 2 4 2 4 4 8 3 2 2 4 4 3 3 6 5 8 7 4110F-AERO-06/02 Table 3. Cell Index (Continued) Cell Name DEC4N DEC8N DFF DFFBCPX DFFBSRX DFFC DFFR DFFS DFFSR DLY1 DLY2 DLY3 DPLG DSS DSSBCPY DSSBR DSSBS DSSR DSSS DSSSR INV1 INV2 INV2T INV3 INV4 JKF JKFBCPX JKFC LAT LATB Description 2:4 decoder with active low enable 3:8 decoder with active low enable D flip-flop D flip-flop with asynchronous clear and preset with complementary outputs D flip-flop with asynchronous set and reset with complementary outputs D flip flop with asynchronous clear D flip-flop with asynchronous reset D flip-flop with asynchronous set D flip-flop with asynchronous set and reset Delay buffer 1.0 ns Delay buffer 1.5 ns Delay buffer 2.0 ns Dual Port cell (for Genesys) Set scan flip-flop Set scan flip-flop with clear and preset Set scan flip-flop with reset Set scan flip-flop with set Set scan D flip-flop with reset Set scan D flip-flop with set Set scan D flip-flop with set and reset 1x inverter 2x inverter 2x Tri State inverter with active high enable 3x inverter 4x inverter JK flip-flop Clear preset JK flip-flop with asynchronous clear and preset and complementary outputs JK flip-flop with asynchronous clear Latch Latch with complementary outputs Gate Count 10 22 8 16 16 9 10 9 11 6 9 11 - 12 16 14 14 12 14 16 1 1 3 2 2 10 16 12 6 6 8 MH1RT 4110F-AERO-06/02 MH1RT Table 3. Cell Index (Continued) Cell Name LATBG LATBH LATIQ LATR LATS LATSR MUX2 MUX2H MUX2N MUX4 MUX5H MUX8 MUX8N NAN2 NAN2H NAN3 NAN3H NAN4 NAN4H NAN5 NAN5H NAN6 NAN6H NAN8 NAN8H NOR2 NOR2H NOR3 NOR3H NOR4 NOR4H NOR5 Description Latch with complementary outputs and inverted gate signal Latch with high drive complementary outputs Quad Latch Latch with reset Latch with set Latch with set and reset 2:1 MUX 2:1 MUX - high drive 2:1 MUX with active low enable 4:1 MUX 5:1 MUX - high drive 8:1 MUX 8:1 MUX with active low enable 2 input NAND 2 input NAND - high drive 3 input NAND 3 input NAND - high drive 4 input NAND 4 input NAND - high drive 5 input NAND 5 input NAND - high drive 6 input NAND 6 input NAND - high drive 8 input NAND 8 input NAND - high drive 2 input NOR 2 input NOR - high drive 3 input NOR 3 input NOR - high drive 4 input NOR 4 input NOR - high drive 5 input NOR Gate Count 6 7 20 5 6 8 4 5 5 10 14 20 20 2 2 2 3 3 4 5 6 6 7 7 8 2 2 2 3 3 5 5 9 4110F-AERO-06/02 Table 3. Cell Index (Continued) Cell Name NOR8 OAI22 OAI22H OAI222 OAI222H OAI22224 OAI23 ORR2 ORR2H ORR3 ORR3H ORR4 ORR4H ORR5 XNR2 XNR2H XOR2 XOR2H Description 8 input NOR 2 input OR into 2 input NAND 2 input OR into 2 input NAND - high drive Two, 2 input ORs into 2 input NAND Two, 2 input ORs into 2 input NAND - high drive Four, 2 input ORs into 4 input NAND 2 input OR into 3 input NAND 2 input OR 2 input OR - high drive 3 input OR 3 input OR - high drive 4 input OR 4 input OR - high drive 5 input OR 2 input exclusive NOR 2 input exclusive NOR - high drive 2 input exclusive OR 2 input exclusive OR - high drive Gate Count 7 2 4 3 6 8 3 2 3 3 4 3 4 5 4 4 4 4 Table 4. I/O Buffer Cell Index Buffer PESD PIC PICH PICI PICS PICSI PICSV PICSV5 PICV I/O order X, P AI, P AI, P AI, P AI, P AI, P AI, P AI, P, VCC AI, P Description Hard connection into array with ESD protection CMOS input buffer, TTL compatible at 3.0V CMOS input buffer, TTL compatible at 3.0V, high drive CMOS input buffer, TTL compatible at 3.0V, inverted output CMOS input buffer with Schmitt trigger, TTL compatible at 3.0V CMOS input buffer with Schmitt trigger, TTL compatible at 3.0V, inverted output CMOS input buffer with Schmitt trigger, TTL compatible at 3.0V, 5V tolerant CMOS input buffer with Schmitt trigger, TTL compatible at 3.0V, 5V compliant CMOS input buffer, TTL compatible at 3.0V, 5V tolerant 10 MH1RT 4110F-AERO-06/02 MH1RT Table 4. I/O Buffer Cell Index (Continued) Buffer PICV5 PID PICV PICV5 I/O order AI, P, VCC AI, P, REF, EN AI, P AI, P LCK, OSCCLKOUT, PLF, PVCOBIAS, CLKIN, CPA, CPB, EN, REFCLK, RSTN, TESTCLK, TESTEN, VDDPLL, VSSPLL LCK, OSCCLKOUT, PLF, PVCOBIAS, CLKIN, CPA, CPB, EN, REFCLK, RSTN, TESTCLK, TESTEN, VDDPLL, VSSPLL P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 Description CMOS input buffer, TTL compatible at 3V, 5V compliant Differential input buffer CMOS inout buffer, TTL compatible at 3V, 5V tolerant CMOS inout buffer, TTL compatible at 3V, 5V compliant PLL5-125 125 MHz Max. PLL PLL5-250 PO11 PO11F PO11S PO11V PO11V5 PO11VF PO11VS PO22 PO22F PO22I PO22S PO22V PO22V5 PO22VF PO22VS PO33 PO33F PO33S 250 MHz Max. PLL Tristate output buffer, 2 mA drive Tristate output buffer, 2 mA drive, fast slew rate control Tristate output buffer, 2 mA drive, slow slew rate control Tristate output buffer, 2 mA drive, 5V tolerant Tristate output buffer, 2 mA drive, 5V compliant Tristate output buffer, 2 mA drive, fast slew rate control, 5V tolerant Tristate output buffer, 2 mA drive, slow slew rate control, 5V tolerant Tristate output buffer, 4 mA drive Tristate output buffer, 4 mA drive, fast slew rate control Tristate output buffer, 4 mA drive, inverted output Tristate output buffer, 4 mA drive, slow slew rate control Tristate output buffer, 4 mA drive, 5V tolerant Tristate output buffer, 4 mA drive, 5V compliant Tristate output buffer, 4 mA drive, fast slew rate control, 5V tolerant Tristate output buffer, 4 mA drive, slow slew rate control, 5V tolerant Tristate output buffer, 6 mA drive Tristate output buffer, 6 mA drive, fast slew rate control Tristate output buffer, 6 mA drive, slow slew rate control 11 4110F-AERO-06/02 Table 4. I/O Buffer Cell Index (Continued) Buffer PO33V PO33VF PO33VS PO44 PO44F PO44S PO44V PO44V5 PO44VF PO44VS PO55 PO55F PO55S PO55V PO55VF PO55VS PO66 PO66F PO66S PO66V PO66VF PO66VS PO77 PO77F PO77S PO77V PO77VF I/O order P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO,E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 Description Tristate output buffer, 6 mA drive, 5V tolerant Tristate output buffer, 6 mA drive, fast slew rate control, 5V tolerant Tristate output buffer, 6 mA drive, slow slew rate control, 5V tolerant Tristate output buffer, 8 mA drive Tristate output buffer, 8 mA drive, fast slew rate control Tristate output buffer, 8 mA drive, slow slew rate control Tristate output buffer, 8 mA drive, 5V tolerant Tristate output buffer, 8 mA drive, 5V compliant Tristate output buffer, 8 mA drive, fast slew rate control, 5V tolerant Tristate output buffer, 8 mA drive, slow slew rate control, 5V tolerant Tristate output buffer, 10 mA drive Tristate output buffer, 10 mA drive, fast slew rate control Tristate output buffer, 10 mA drive, slow slew rate control Tristate output buffer, 10 mA drive, 5V tolerant Tristate output buffer, 10 mA drive, fast slew rate control, 5V tolerant Tristate output buffer, 10 mA drive, slow slew rate control, 5V tolerant Tristate output buffer, 12 mA drive Tristate output buffer, 12 mA drive, fast slew rate control Tristate output buffer, 12 mA drive, slow slew rate control Tristate output buffer, 12 mA drive, 5V tolerant Tristate output buffer, 12 mA drive, fast slew rate control, 5V tolerant Tristate output buffer, 12 mA drive, slow slew rate control, 5V tolerant Tristate output buffer, 14 mA drive Tristate output buffer, 14 mA drive, fast slew rate control Tristate output buffer, 14 mA drive, slow slew rate control Tristate output buffer, 14 mA drive, 5V tolerant Tristate output buffer, 14 mA drive, fast slew rate control, 5V tolerant 12 MH1RT 4110F-AERO-06/02 MH1RT Table 4. I/O Buffer Cell Index (Continued) Buffer PO77VS PO88 PO88F PO88S PO88V PO88VF PO88VS PO99 PO99F PO99S PO99V PO99VF PO99VS POAA POAAF POAAS POAAV POAAVF POAAVS POBB POBBF POBBS POBBV POBBVF POBBVS POCC POCCF I/O order P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 P, AO, E0 Description Tristate output buffer, 14 mA drive, slow slew rate control, 5V tolerant Tristate output buffer, 16 mA drive Tristate output buffer, 16 mA drive, fast slew rate control Tristate output buffer, 16 mA drive, slow slew rate control Tristate output buffer, 16 mA drive, 5V tolerant Tristate output buffer, 16 mA drive, fast slew rate control, 5V tolerant Tristate output buffer, 16 mA drive, slow slew rate control, 5V tolerant Tristate output buffer, 18 mA drive Tristate output buffer, 18 mA drive, fast slew rate control Tristate output buffer, 18 mA drive, slow slew rate control Tristate output buffer, 18 mA drive, 5V tolerant Tristate output buffer, 18 mA drive, fast slew rate control, 5V tolerant Tristate output buffer, 18 mA drive, slow slew rate control, 5V tolerant Tristate output buffer, 20 mA drive Tristate output buffer, 20 mA drive, fast slew rate control Tristate output buffer, 20 mA drive, slow slew rate control Tristate output buffer, 20 mA drive, 5V tolerant Tristate output buffer, 20 mA drive, fast slew rate control, 5V tolerant Tristate output buffer, 20 mA drive, slow slew rate control, 5V tolerant Tristate output buffer, 22 mA drive Tristate output buffer, 22 mA drive, fast slew rate control Tristate output buffer, 22 mA drive, slow slew rate control Tristate output buffer, 22 mA drive, 5V tolerant Tristate output buffer, 22 mA drive, fast slew rate control, 5V tolerant Tristate output buffer, 22 mA drive, slow slew rate control, 5V tolerant Tristate output buffer, 24 mA drive Tristate output buffer, 24 mA drive, fast slew rate control 13 4110F-AERO-06/02 Table 4. I/O Buffer Cell Index (Continued) Buffer POCCS POCV5 PRD1 PRD10 PRD10V5 PRD11 PRD11V5 PRD12 PRD12V5 PRD13 PRD13V5 PRD14 PRD14V5 PRD15 PRD15V5 PRD16 PRD16V5 PRD17 PRD17V5 PRD18 PRD18V5 PRD19 PRD19V5 PRD1V5 PRD2 PRD20 PRD20V5 PRD21 PRD21V5 PRD22 PRD22V5 PRD23 I/O order P, AO, E0 P, AO, EO P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P Description Tristate output buffer, 24 mA drive, slow slew rate control Tristate output buffer, 16.8 mA drive, 5V compliant 20 k pull-down terminator 200 k pull-down terminator 200 k pull-down terminator, 5V compliant 220 k pull-down terminator 220 k pull-down terminator, 5V compliant 240 k pull-down terminator 240 k pull-down terminator, 5V compliant 260 k pull-down terminator 260 k pull-down terminator, 5V compliant 280 k pull-down terminator 280 k pull-down terminator, 5V compliant 300 k pull-down terminator 300 k pull-down terminator, 5V compliant 320 k pull-down terminator 320 k pull-down terminator, 5V compliant 340 k pull-down terminator 340 k pull-down terminator, 5V compliant 360 k pull-down terminator 360 k pull-down terminator, 5V compliant 380 k pull-down terminator 380 k pull-down terminator, 5V compliant 20 k pull-down terminator, 5V compliant 40 k pull-down terminator 400 k pull-down terminator 400 k pull-down terminator, 5V compliant 420 k pull-down terminator 420 k pull-down terminator, 5V compliant 440 k pull-down terminator 440 k pull-down terminator, 5V compliant 460 k pull-down terminator 14 MH1RT 4110F-AERO-06/02 MH1RT Table 4. I/O Buffer Cell Index (Continued) Buffer PRD23V5 PRD24 PRD24V5 PRD25 PRD25V5 PRD26 PRD26V5 PRD27 PRD27V5 PRD28 PRD28V5 PRD29 PRD29V5 PRD2V5 PRD3 PRD30 PRD30V5 PRD31 PRD31V5 PRD3V5 PRD4 PRD4V5 PRD5 PRD5V5 PRD6 PRD6V5 PRD7 PRD7V5 PRD8 PRD8V5 PRD9 PRD9V5 I/O order P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P Description 460 k pull-down terminator, 5V compliant 480 k pull-down terminator 480 k pull-down terminator, 5V compliant 500 k pull-down terminator 500 k pull-down terminator, 5V compliant 520 k pull-down terminator 520 k pull-down terminator, 5V compliant 540 k pull-down terminator 540 k pull-down terminator, 5V compliant 560 k pull-down terminator 560 k pull-down terminator, 5V compliant 580 k pull-down terminator 580 k pull-down terminator, 5V compliant 40 k pull-down terminator, 5V compliant 60 k pull-down terminator 600 k pull-down terminator 600 k pull-down terminator, 5V compliant 620 k pull-down terminator 620 k pull-down terminator, 5V compliant 60 k pull-down terminator, 5V compliant 80 k pull-down terminator 80 k pull-down terminator, 5V compliant 100 k pull-down terminator 100 k pull-down terminator, 5V compliant 120 k pull-down terminator 120 k pull-down terminator, 5V compliant 140 k pull-down terminator 140 k pull-down terminator, 5V compliant 160 k pull-down terminator 160 k pull-down terminator, 5V compliant 180 k pull-down terminator 180 k pull-down terminator, 5V compliant 15 4110F-AERO-06/02 Table 4. I/O Buffer Cell Index (Continued) Buffer PRU1 PRU10 PRU10V5 PRU11 PRU11V5 PRU12 PRU12V5 PRU13 PRU13V5 PRU14 PRU14V5 PRU15 PRU15V5 PRU16 PRU16V5 PRU17 PRU17V5 PRU18 PRU18V5 PRU19 PRU19V5 PRU1V5 PRU2 PRU20 PRU20V5 PRU21 PRU21V5 PRU22 PRU22V5 PRU23 PRU23V5 PRU24 I/O order P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P Description 20 k pull-up terminator 200 k pull-up terminator 200 k pull-up terminator, 5V compliant 220 k pull-up terminator 220 k pull-up terminator, 5V compliant 240 k pull-up terminator 240 k pull-up terminator, 5V compliant 260 k pull-up terminator 260 k pull-up terminator, 5V compliant 280 k pull-up terminator 280 k pull-up terminator, 5V compliant 300 k pull-up terminator 300 k pull-up terminator, 5V compliant 320 k pull-up terminator 320 k pull-up terminator, 5V compliant 340 k pull-up terminator 340 k pull-up terminator, 5V compliant 360 k pull-up terminator 360 k pull-up terminator, 5V compliant 380 k pull-up terminator 380 k pull-up terminator, 5V compliant 20 k pull-up terminator, 5V compliant 20 k pull-up terminator 400 k pull-up terminator 400 k pull-up terminator, 5V compliant 420 k pull-up terminator 420 k pull-up terminator, 5V compliant 440 k pull-up terminator 440 k pull-up terminator, 5V compliant 460 k pull-up terminator 460 k pull-up terminator, 5V compliant 480 k pull-up terminator 16 MH1RT 4110F-AERO-06/02 MH1RT Table 4. I/O Buffer Cell Index (Continued) Buffer PRU24V5 PRU25 PRU25V5 PRU26 PRU26V5 PRU27 PRU27V5 PRU28 PRU28V5 PRU29 PRU29V5 PRU2V5 PRU3 PRU30 PRU30V5 PRU31 PRU31V5 PRU3V5 PRU4 PRU4V5 PRU5 PRU5V5 PRU6 PRU6V5 PRU7 PRU7V5 PRU8 PRU8V5 PRU9 PRU9V5 PVCCB PVDDA I/O order P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P VCC, P Description 480 k pull-up terminator, 5V compliant 500 k pull-up terminator 500 k pull-up terminator, 5V compliant 520 k pull-up terminator 520 k pull-up terminator, 5V compliant 540 k pull-up terminator 540 k pull-up terminator, 5V compliant 560 k pull-up terminator 560 k pull-up terminator, 5V compliant 580 k pull-up terminator 580 k pull-up terminator, 5V compliant 40 k pull-up terminator, 5V compliant 60 k pull-up terminator 600 k pull-up terminator 600 k pull-up terminator, 5V compliant 620 k pull-up terminator 620 k pull-up terminator, 5V compliant 60 k pull-up terminator, 5V compliant 80 k pull-up terminator 80 k pull-up terminator, 5V compliant 100 k pull-up terminator 100 k pull-up terminator, 5V compliant 120 k pull-up terminator 120 k pull-up terminator, 5V compliant 140 k pull-up terminator 140 k pull-up terminator, 5V compliant 160 k pull-up terminator 160 k pull-up terminator, 5V compliant 180 k pull-up terminator 180 k pull-up terminator, 5V compliant Buffer VCC supply pad Array VDD supply pad 17 4110F-AERO-06/02 Table 4. I/O Buffer Cell Index (Continued) Buffer PVDDB PVDDV3B PVDDVB PVSSA PVSSB I/O order P P P VSS, P P Description Buffer VDD supply pad for standard buffers Buffer VDD supply pad for 5V compliant buffers Buffer VDD supply pad for 5V tolerant buffers Array VSS supply pad Buffer VSS supply pad Table 5. Cold Sparing Buffers Cell Name PO11VZ PO11Z PO22VZ PO22Z PO33VZ PO33Z PO44VZ PO44Z PO55VZ PO55Z PO66VZ PO66Z PO77VZ PO77Z PO88VZ PO88Z PO99VZ PO99Z POAAVZ POAAZ POBBVZ POBBZ POCCVZ POCCZ I/O order P, AO, EO P, AO, EO P, AO, EO P, AO, EO P, AO, EO P, AO, EO P, AO, EO P, AO, EO P, AO, EO P, AO, EO P, AO, EO P, AO, EO P, AO, EO P, AO, EO P, AO, EO P, AO, EO P, AO, EO P, AO, EO P, AO, EO P, AO, EO P, AO, EO P, AO, EO P, AO, EO P, AO, EO Description Tristate output buffer, 1.4 mA drive, for cold sparing, 5V tolerant Tristate output buffer, 2 mA drive, for cold sparing Tristate output buffer, 2.8 mA drive, for cold sparing, 5V tolerant Tristate output buffer, 4 mA drive, for cold sparing Tristate output buffer, 4.2 mA drive, for cold sparing, 5V tolerant Tristate output buffer, 6 mA drive, for cold sparing Tristate output buffer, 5.6 mA drive, for cold sparing, 5V tolerant Tristate output buffer, 8 mA drive, for cold sparing Tristate output buffer, 7 mA drive, for cold sparing, 5V tolerant Tristate output buffer, 10 mA drive, for cold sparing Tristate output buffer, 8.4 mA drive, for cold sparing, 5V tolerant Tristate output buffer, 12 mA drive, for cold sparing Tristate output buffer, 9.8 mA drive, for cold sparing, 5V tolerant Tristate output buffer, 14 mA drive, for cold sparing Tristate output buffer, 11.2 mA drive, for cold sparing, 5V tolerant Tristate output buffer, 16 mA drive, for cold sparing Tristate output buffer, 12.6 mA drive, for cold sparing, 5V tolerant Tristate output buffer, 18 mA drive, for cold sparing Tristate output buffer, 14 mA drive, for cold sparing, 5V tolerant Tristate output buffer, 20 mA drive, for cold sparing Tristate output buffer, 15.4 mA drive, for cold sparing, 5V tolerant Tristate output buffer, 22 mA drive, for cold sparing Tristate output buffer, 16.8 mA drive, for cold sparing, 5V tolerant Tristate output buffer, 24 mA drive, for cold sparing 18 MH1RT 4110F-AERO-06/02 MH1RT Table 5. Cold Sparing Buffers (Continued) Cell Name PICVZ PICZ PVDDVZB PVDDZB PRD1Z PRD10Z PRD11Z PRD12Z PRD13Z PRD14Z PRD15Z PRD16Z PRD17Z PRD18Z PRD19Z PRD20Z PRD21Z PRD22Z PRD23Z PRD24Z PRD25Z PRD26Z PRD27Z PRD28Z PRD29Z PRD2Z PRD30Z PRD31Z PRD3Z PRD4Z PRD5Z PRD6Z I/O order AI, P AI, P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P Description Cold sparing CMOS input buffer, TTL compatible at 3V, 5V compliant Cold sparing CMOS input buffer, TTL compatible at 3V Buffer VDD supply pad for tolerant cold sparing buffers Buffer VDD supply pad for standard cold sparing buffers 20 k cold sparing pull-down terminator 200 k cold sparing pull-down terminator 220 k cold sparing pull-down terminator 240 k cold sparing pull-down terminator 260 k cold sparing pull-down terminator 280 k cold sparing pull-down terminator 300 k cold sparing pull-down terminator 320 k cold sparing pull-down terminator 340 k cold sparing pull-down terminator 360 k cold sparing pull-down terminator 380 k cold sparing pull-down terminator 400 k cold sparing pull-down terminator 420 k cold sparing pull-down terminator 440 k cold sparing pull-down terminator 460 k cold sparing pull-down terminator 480 k cold sparing pull-down terminator 500 k cold sparing pull-down terminator 520 k cold sparing pull-down terminator 540 k cold sparing pull-down terminator 560 k cold sparing pull-down terminator 580 k cold sparing pull-down terminator 40 k cold sparing pull-down terminator 600 k cold sparing pull-down terminator 620 k cold sparing pull-down terminator 60 k cold sparing pull-down terminator 80 k cold sparing pull-down terminator 100 k cold sparing pull-down terminator 120 k cold sparing pull-down terminator 19 4110F-AERO-06/02 Table 5. Cold Sparing Buffers (Continued) Cell Name PRD7Z PRD8Z PRD9Z I/O order P P P Description 140 k cold sparing pull-down terminator 160 k cold sparing pull-down terminator 180 k cold sparing pull-down terminator Table 6. SEU Hardened Cells Cell Name HDS HDSR HDSP HDF HDFR HDFP HLT HLTR HTLP Description SEU hardened set scan D flip-flop SEU hardened set scan D flip-flop with async. reset SEU hardened set scan D flip-flop with async. preset SEU hardened D flip-flop SEU hardened D flip-flop with async. reset SEU hardened D flip-flop with async. preset SEU hardened latch SEU hardened latch with async. reset SEU hardened latch with async. preset Table 7. Specific Buffer Cells Cell Name PFILVDS PFOLVDS25 PFOLVDS30 PFOLVDS33 I/O Order AI, AIB, P, PN, EO P, PB, AO, EO, IREF P, PB, AO, EO, IREF P, PB, AO, EO, IREF Description LVDS compatible input buffer 2.5V VDD range LVDS compatible output buffer 3V VDD range LVDS compatible output buffer 3.3V VDD range LVDS compatible output buffer IREF buffer for LVDS outputs PCI compatible 3V input buffer PCI compatible 5V input buffer PCI compatible 3V output buffer PCI compatible 5V output buffer PFOLVDSREF AI, P PFIPCI PFIPCIV POPCI POPCIV5 AI, P AI, P P, AO, EO P, AO, EO 20 MH1RT 4110F-AERO-06/02 MH1RT Electrical Characteristics Absolute Maximum Ratings Operating Ambient Temperature .........-55C to +125C Storage Temperature........................... -65C to +150C Maximum Input Voltage VDD ...+0.5V and VCC + 0.5V Maximum 3.3V Operating Voltage................. 4V (VDD) Maximum 5V Operating Voltage.................... 6V (VCC) *NOTE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics Applicable over recommended operating temperature and voltage range unless otherwise noted. Table 8. 2.5V DC Characteristics Symbol TA VDD Parameter Operating Temperature Supply Voltage Low-level Input Current Pull-up resistors PRU1 (1) Pull down resistor PRD1 Buffer All All Test Condition - - Min. -55 2.3 -1 70 -5 -1 -5 70 Typ 25 2.5 - - - - Max. 125 2.7 1 230 5 1 5 540 Units C V A IIL CMOS VIN = VSS IIH High level Input Current Pull-up resistors PRU1 Pull down resistor PRD1 (2) CMOS A VIN = VDD ( Max.) Vin = Vdd or Vss, Vdd = Vdd (Max.) No pull resistor - - - - - - Vdd = Vss = 0V Vin = 0 to 3.3V Vdd = Vss = 0V Vin = 0 to 3.3V Iocs = 100 A IOL = 0.8 mA, Vdd = Vdd (Min.) Ioh = -0.6 mA, Vdd = Vdd (Min.) Ioz High impedance state output current -1 - 1 A All CMOS CMOS Schmitt level CMOS - - - 0.7 Vdd 1.56 - -2 - - 0.3Vdd V 0.62 Vil Low level Input voltage - - - 0.42 - V - - -2 V A A Vih Delta V High level Input voltage CMOS Hysterisis CMOS Schmitt level Iics Cold sparing leakage input current PICZ Cold sparing leakage output current Supply threshold of cold sparing buffers Iocs Vcsth (3) VOL Voh POxxZ POxxZ -2 -2 - - 2 0.5 - - - 0.4 - V V V Low-level Output Voltage (4) PO11 High level output voltage (5) PO11 21 4110F-AERO-06/02 Table 8. 2.5V DC Characteristics (Continued) Symbol Parameter Output short circuit current Iosn Iosp Leakage current per cell Dynamic current per gate Buffer Test Condition Vdd = Vdd (Max.), Vout = Vdd Vouy = Vss Vdd = Vdd (Max.) Vdd = Vdd (Max.) Min. Typ Max. Units Ios Iccsb Iccop 1. 2. 3. 4. PO11 PO11 - - 15 8 4 0.3 mA - - 0.27 nA W/MHz For standard pull-ups: PRU (#), # = {1-31} index for Ron: Ron = # x RO where RO = 19 k typ, 30 k Max., 12 k Min. For standard pull-downs: PRD (#), # = {1-31} index for Ron: Ron = # x RO where RO = 11 k typ, 30 k Max., 5 k Min. Guaranteed not tested For output buffers PO (1-C) (1-C): 1-C: hex value: convert hex to decimal x IO = p and n-channel output drive IO = 0.8 mA for standard buffers (including cold sparing) measured at Vol = 0.4V 5. For output buffers PO (1-C) (1-C): 1-C: hex value: convert hex to decimal x IO = p and n-channel output drive IO = -0.6 mA for standard buffers (including cold sparing) measured at Voh = 2V Applicable over recommended operating temperature and voltage range unless otherwise noted. 22 MH1RT 4110F-AERO-06/02 MH1RT . Table 9. 3V DC Characteristics Symbol TA VDD Parameter Operating Temperature Supply Voltage Low-level Input Current Pull-up resistors PRU1 (1) Pull down resistor PRD1 High level Input Current Pull-up resistors PRU1 Pull down resistor PRD1 High impedance state output current Buffer All All Test Condition - - Min. -55 2.3 -1 108 -5 -1 -5 108 -1 - - 2 1.89 - -2 -2 - - PO11 (5) Typ 25 2.5 - - - - Max. 125 2.7 1 330 5 1 5 825 1 0.8 Units C V A IIL CMOS VIN = VSS A IIH (2) CMOS VIN = VDD( Max.) Vin = Vdd or Vss, Vdd = Vdd (Max.) No pull resistor - - - - - Vdd = Vss = 0V Vin = 0 to 3.3V Vdd = Vss = 0V Vin = 0 to 3.3V Iocs = 100 A - - - - - 0.53 - - 0.5 - A Ioz All CMOS Vil Low level Input voltage CMOS Schmitt level CMOS V 0.72 - V - - -2 -2 - V A A Vih Delta V Iics Iocs Vcsth (3) High level Input voltage CMOS Hysterisis CMOS Schmitt level - Cold sparing leakage input current PICZ Cold sparing leakage output current Supply threshold of cold sparing buffers Low-level Output Voltage POxxZ POxxZ V VOL Voh (4) 0.4 IOL = 1 mA, Vdd = Vdd(Min.) Ioh = -0.8 mA, Vdd = Vdd(Min.) Vdd = Vdd(Max.), Vout = Vdd Vouy = Vss Vdd = Vdd(Max.) Vdd = Vdd(Max.) - 2.4 - - - - - - 0.6 - - 21 12 5 0.5 PO11 PO11 PO11 - - V V mA nA W/MHz High level output voltage Ios Iccsb Iccop 1. 2. 3. 4. Output short circuit current Iosn Iosp Leakage current per cell Dynamic current per gate 5. For standard pull-ups: PRU (#), # = {1-31} index for Ron: Ron = # x RO where RO = 15 k typ, 25 k Max., 10 k Min. For standard pull-downs: PRD (#), # = {1-31} index for Ron: Ron = # x RO where RO = 9 k typ, 25 k Max., 4 k Min. Guaranteed not tested. For output buffers PO (1-C) (1-C): 1-C: hex value: convert hex to decimal x IO = p and n-channel output drive IO = 1 mA for standard buffers (including cold sparing) measured at Vol = 0.4V For output buffers PO (1-C) (1-C):1-C: hex value: convert hex to decimal x IO = p and n-channel output drive IO = -0.8 mA for standard buffers (including cold sparing) measured at Voh = 2.4V 23 4110F-AERO-06/02 Table 10. 3.3V DC Characteristics Symbol TA VDD Parameter Operating Temperature Supply Voltage Low-level Input Current Pull-up resistors PRU1 (1) Pull down resistor PRD1 High level Input Current Pull-up resistors PRU1 Pull down resistor PRD1 High impedance state output current Buffer All All Test Condition - - Min. -55 2.3 -1 120 -5 -1 -5 150 -1 - - 2 2 - -2 -2 - - - PO11 (5) Typ 25 2.5 - Max. 125 2.7 1 400 5 1 5 900 1 0.8 Units C V A IIL CMOS VIN = VSS - A IIH (2) CMOS VIN = VDD( Max.) Vin = Vdd or Vss, Vdd = Vdd(Max.) No pull resistor - - - - - Vdd = Vss = 0V Vin = 0 to 3.3V Vdd = Vss = 0V Vin = 0 to 3.3V Iocs = 100 A - - - - - 0.61 - - 0.5 A Ioz All CMOS Vil Low level Input voltage CMOS Schmitt level CMOS V 0.8 - V - - -2 -2 - V A A Vih Delta V Iics Iocs Vcsth (3) High level Input voltage CMOS Hysterisis CMOS Schmitt level - Cold sparing leakage input current PICZ Cold sparing leakage output current Supply threshold of cold sparing buffers Low-level Output Voltage POxxZ POxxZ V VOL Voh (4) 0.4 - 23 13 5 0.63 V V mA nA W/MHz IOL = 2 mA, Vdd = Vdd(Min.) Ioh = -1.8 mA, Vdd = Vdd(Min.) Vdd = Vdd(Max.), Vout = Vdd Vouy = Vss Vdd = Vdd(Max.) Vdd = Vdd(Max.) - 2.4 - - - - - 0.7 - High level output voltage PO11 PO11 PO11 - - Ios Iccsb Iccop 1. 2. 3. 4. Output short circuit current Iosn Iosp Leakage current per cell Dynamic current per gate 5. For standard pull-ups: PRU(#), # = {1-31} index for Ron: Ron = # x RO where RO = 14 k typ, 25 k Max., 9 k Min. For standard pull-downs:PRD(#), # = {1-31} index for Ron: Ron = # x RO where RO = 8k typ, 20 k Max., 4 k Min. Guaranteed not tested. For output buffers PO (1-C) (1-C): 1-C: hex value: convert hex to k x IO = p and n-channel output drive IO = 2 mA for standard buffers (including cold sparing) measured at Vol = 0.4V For output buffers PO (1-C) (1-C): 1-C: hex value: convert hex to k x IO = p and n-channel output drive IO = -1.8 mA for standard buffers (including cold sparing) measured at Voh = 2.4V 24 MH1RT 4110F-AERO-06/02 MH1RT Applicable over recommended operating temperature and voltage range unless otherwise noted. Table 11. 5V DC Characteristics Symbol TA VDD Parameter Operating Temperature Supply Voltage Low-level Input Current Pull-up resistors PRU1 (1) Pull down resistor PRD1 Buffer All All Test Condition - - Min. -55 2.3 -1 180 -5 -1 -5 30 Typ 25 2.5 - - - - Max. 125 2.7 1 690 5 1 5 400 Units C V A IIL CMOS VIN = VSS IIH High level Input Current Pull-up resistors PRU1 Pull down resistor PRD1 (2) CMOS A VIN = VDD( Max.) Vin = Vdd or Vss, Vdd = Vdd(Max.) No pull resistor - - - - Vdd = Vss = 0V Vin = 0 to 3.3V Vdd = Vss = 0V Vin = 0 to 3.3V Iocs = 100 A Iol = 0.5 mA Iol = 0.6 mA Iol = 1.2 mA Iol = 1.1 mA Iol = 1.3 mA Iol = 1.5 mA Ioh = 0.5 mA Ioh = 0.6 mA Ioh = 1.2 mA Ioh = 1.1 mA Ioh = 1.3 mA Ioh = 1.5 mA Vdd = Vdd(Max.), Vout = Vdd Vouy = Vss Ioz High impedance state output current -1 - 1 A All PICV, PICV5 - - 2 2 - - - - 0.8 V 0.8 - V - Vil Low level Input voltage CMOS Schmitt level PICV, PICV5 Vih High level Input voltage CMOS Schmitt level Iics Cold sparing leakage input current PICZ Cold sparing leakage output current Supply threshold of cold sparing buffers Low Voltage/2.5V range Low Voltage/3.0V range Low Voltage/3.3V range Low Voltage/2.5V range Low Voltage/3.0V range Low Voltage/3.3V range Low Voltage/2.5V range Low Voltage/3.0V range Low Voltage/3.3V range Low Voltage/2.5V range Low Voltage/3.0V range Low Voltage/3.3V range Output short circuit current Iosn Iosp -2 - -2 A A Iocs Vcsth (3) POxxZ POxxZ PO11V PO11V PO11V PO11V5 PO11V5 PO11V5 PO11V PO11V PO11V PO11V5 PO11V5 PO11V5 -2 - -2 - 0.5 - V - - 0.4 V VOL (4) Voh (5) 2 2.4 2.4 2.4 2.4 2.4 - - V Ios PO11V PO11V - - 28 17 mA 25 4110F-AERO-06/02 1. 2. 3. 4. 5. For 5V tolerant/compliant pull-ups: PRU(#), # = {1-31} index for Ron: Ron = # x RO where RO = 14 k typ, 25 k Max., 8 k Min. For 5V tolerant/compliant pull-downs: PRD(#), # = {1-31} index for Ron: Ron = # x RO where: RO = 19 k typ, 45 k Max., 9 k Min. in 3.3V range, RO = 23 k typ, 55 k Max., 11 k Min. in 3V range, RO = 36 k typ, 80 k Max., 17 k Min. in 2.5V range, Guaranteed not tested. For output buffers PO (1-C) (1-C): 1-C: hex value: convert hex to k x IO = p and n-channel output drive IO = 1.5 mA for compliant buffers (including cold sparing) in 3.3V range (Vcc = 4.5V ) measured at Vol = 0.4V IO = 1.3 mA for compliant buffers (including cold sparing) in 3.0V range (Vcc = 4.5V ) measured at Vol = 0.4V IO = 1.1 mA for compliant buffers (including cold sparing) in 2.5V range (Vcc = 4.5V ) measured at Vol = 0.4V For output buffers PO (1-C) (1-C): 1-C: hex value: convert hex to k x IO = p and n-channel output drive IO = 1.5 mA for compliant buffers (including cold sparing) in 3.3V range (Vcc = 4.5V ) measured at Vol = 2.4V IO = 1.3 mA for compliant buffers (including cold sparing) in 3.0V range (Vcc = 4.5V ) measured at Vol = 2.4V IO = 1.1 mA for compliant buffers (including cold sparing) in 2.5V range (Vcc = 4.5V ) measured at Vol = 2.0V Applicable over recommended operating temperature and voltage range unless otherwise noted. Table 12. 2.5V LVDS Driver DC/ AC Characteristics Symbol TA VDD |VOD| Vol Voh VOS |Delta VOD| |Delta VOS| ISA, ISB ISAB Rbias Ibias F Max. Clock Tfall Trise Tp Tsk1 Tsk2 Parameter Operating Temperature Supply Voltage Output differential voltage Output voltage low Output voltage high Output offset voltage Test Condition - - Rload = 100 Rload = 100 Rload = 100 Rload = 100 Min. -55 2.3 230.7 1224 993 1108 0 0 1.0 2.4 9.8 5.8 - 45 669 670 1270 0 0 Max. 125 2.7 446.5 1817 1406 1610 50 100 6.3 4.8 10.2 11.7 180 55 1178 1167 2660 110 50 Units C V mV mV mV mV mV mV mA mA K mA MHz % ps ps ps ps ps Consumption 14.8 mA - see Figure 4 see Figure 4 see Figure 4 - - Comments - - see Figure 4 see Figure 4 see Figure 4 see Figure 4 - - - - 1 per chip Change in |VOD| between "0" and "1" Rload = 100 Change in |VOS| between "0" and "1" Rload = 100 Output current Output current Bias resistor Bias static current Maximum operating frequency Clock signal duty cycle Fall time 80-20% Rise time 20-80% Propagation delay Duty cycle skew Channel to channel skew (same edge) Drivers shorted to ground or VDD Drivers shorted together - - VDD = 2.5V 0.2V Max. frequency Rload = 100 Rload = 100 Rload = 100 Rload = 100 Rload = 100 26 MH1RT 4110F-AERO-06/02 MH1RT Applicable over recommended operating temperature and voltage range unless otherwise noted. Table 13. 3V LVDS Driver DC/ AC Characteristics Symbol TA VDD |VOD| Vol Voh VOS |Delta VOD| |Delta VOS| ISA, ISB ISAB Rbias Ibias F Max. Clock Tfall Trise Tp Tsk1 Tsk2 Parameter Operating Temperature Supply Voltage Output differential voltage Output voltage low Output voltage high Output offset voltage Test Condition - - Rload = 100 Rload = 100 Rload = 100 Rload = 100 Min. -55 2.7 244 1088 828 958 0 0 1.0 2.6 12.8 6.5 - 45 512 512 1150 0 0 Max. 125 3.3 462 1775 1358 568 50 150 6.3 5 13.2 13.8 200 55 968 970 2300 70 50 Units C V mV mV mV mV mV mV mA mA K mA MHz % ps ps ps ps ps Comments - - see Figure 4 see Figure 4 see Figure 4 see Figure 4 - - - - 1 per chip - Consumption 18.6 mA - see Figure 4 see Figure 4 see Figure 4 - - Change in |VOD| between "0" and "1" Rload = 100 Change in |VOS| between "0" and "1" Rload = 100 Output current Output current Bias resistor Bias static current Maximum operating frequency Clock signal duty cycle Fall time 80-20% Rise time 20-80% Propagation delay Duty cycle skew Channel to channel skew (same edge) Drivers shorted to ground or VDD Drivers shorted together - - VDD = 2.5V 0.2V Max. frequency Rload = 10 Rload = 100 Rload = 100 Rload = 100 Rload = 100 27 4110F-AERO-06/02 Applicable over recommended operating temperature and voltage range unless otherwise noted. Table 14. 3.3V LVDS Driver DC/ AC Characteristics Symbol TA VDD |VOD| Vol Voh VOS |Delta VOD| |Delta VOS| ISA, ISB ISAB Rbias Ibias F Max. Clock Tfall Trise Tp Tsk1 Tsk2 Parameter Operating Temperature Supply Voltage Output differential voltage Output voltage low Output voltage high Output offset voltage Test Condition - - Rload = 100 Rload = 100 Rload = 100 Rload = 100 Min. -55 3 251.4 1071 804 937 0 0 1.0 2.6 16.3 7 - 45 445 445 1120 0 0 Max. 125 3.3 452.2 1731 1323 1527 50 200 6.2 4.8 16.7 14.6 220 55 838 841 2120 80 50 Units C V mV mV mV mV mV mV mA mA k mA MHz % ps ps ps ps ps Comments - - see Figure 4 see Figure 4 see Figure 4 see Figure 4 - - - - 1 per chip - Consumption 14.8 mA - see Figure 4 see Figure 4 see Figure 4 - - Change in |VOD| between "0" and "1" Rload = 100 Change in |VOS| between "0" and "1" Rload = 100 Output current Output current Bias resistor Bias static current Maximum operating frequency Clock signal duty cycle Fall time 80-20% Rise time 20-80% Propagation delay Duty cycle skew Channel to channel skew (same edge) Drivers shorted to ground or VDD Drivers shorted together - - VDD = 2.5V 0.2V Max. frequency Rload = 100 Rload = 100 Rload = 100 Rload = 100 Rload = 100 Figure 4. Test Termination Measurements A VOD B ( VA + VB ) OS = 2 100 k 28 MH1RT 4110F-AERO-06/02 MH1RT Figure 5. Rise and Fall Measurements A 100 k 5 pF B Applicable over recommended operating temperature and voltage range unless otherwise noted. Table 15. LVDS Receiver DC/ AC Characteristics (preliminary) Symbol TA VDD Vi Vidth Parameter Operating Temperature Supply Voltage Input voltage range Input differential voltage Test Condition - - - - Cout = 50 fF, VDD = 2.5V 0.2V Cout = 50 fF, VDD = 3.0V 0.3V Cout = 50 fF, VDD = 3.3V 0.3V Cout = 50 fF Min. -55 2.3 0 -100 0.9 0.7 0.7 - Max. 125 3.6 2400 +100 3.5 2.7 2.4 500 Units C V mV mV Comments - - - - ns - Tp Tskew Propagation delay Duty cycle distortion ps - Table 16. I/O Buffers DC Characteristics Symbol CIN COUT CI/O Parameter Capacitance, Input Buffer (die) Capacitance, Output Buffer (die) Capacitance, Bi-Directional Test Condition 3V 3V 3V Typical 2.4 5.6 6.6 Units pF pF pF 29 4110F-AERO-06/02 Testability Techniques For complex designs, involving blocks of memory and/or cores, careful attention must be given to design-for-test techniques. The sheer size of complex designs and the number of functional vectors that would need to be created to exercise them fully, strongly suggests the use of more efficient techniques. Combinations of SCAN paths, multiplexed access to memory and/or core blocks, and built-in-self-test logic must be employed, in addition to functional test patterns, to provide both the user and Atmel the ability to test the finished product. An example of a highly complex design could include a PLL for clock management or synthesis, a microcontroller or DSP engine or both, SRAM to support the microcontroller or DSP engine, and glue logic to support the interconnectivity of each of these blocks. The design of each of these blocks must take into consideration the fact that the manufactured device will be tested on a high performance digital tester. Combinations of parametric, functional, and structural tests, defined for digital testers, should be employed to create a suite of manufacturing tests. The type of block dictates the type of testability technique to be employed. The PLL will, by construction, provide access to key nodes so that functional and/or parametric testing can be performed. Since a digital tester must control all the clocks during the testing of a Gate Array/Embedded Array, provision must be made for the VCO to be bypassed. Atmel's PLLs include a multiplexing capability for just this purpose. The addition of a few pins will allow other portions of the PLL to be isolated for test, without impinging upon the normal functionality. In a similar vein, access to microcontroller, DSP, and SRAM blocks must be provided so that controllability and observability of the inputs and outputs to the blocks are achieved with the minimum amount of preconditioning. SRAM blocks need to provide access to both address and data ports so that comprehensive memory tests can be performed. Multiplexing I/O pins provides a method for providing this accessibility. The glue logic can be designed using full SCAN techniques to enhance its testability. It should be noted that, in almost all of these cases, the purpose of the testability technique is to provide Atmel a means to assess the structural integrity of a Gate Array/Embedded Array, i.e., sort devices with manufacturing-induced defects. All of the techniques described above should be considered supplemental to a set of patterns which exercise the functionality of the design in its anticipated operating modes. 30 MH1RT 4110F-AERO-06/02 MH1RT Advanced Packaging The MH1RT Series gate arrays are offered in a wide variety of standard ceramic packages, including quad flatpacks (CQFP), multi layers quad flatpacks (MQFP), pin grid arrays (CPGA) and a BGA based on ceramic land grid arrays (CLGA). High volume onshore and offshore contractors can provide assembly and test for commercial or industrial quality grades, when agreed. Custom package designs are also available as required to meet a customer's specific needs, and are supported through Atmel's package design center. When a standard package cannot meet a customer's need, a package can be designed to precisely fit the application and to maintain the performance obtained in silicon. Atmel has delivered custom-designed packages in a wide variety of configurations. Table 17. Packaging Options Package Type PQFP(1) Power Quad(1) L/TQFP(1) PBGA(1) MQFP CLGA(1) Note: Pin Count 44 to 304 144 to 304 32 to 216 121 to 676 84 to 352 349, 472, 564 (1.27 mm pitch) 1. Contact Atmel for availability. 31 4110F-AERO-06/02 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-18-19-60 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France TEL (33) 4-76-58-30-00 FAX (33) 4-76-58-34-80 ASIC/ASSP/Smart Cards Zone Industrielle 13106 Rousset Cedex, France TEL (33) 4-42-53-60-00 FAX (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland TEL (44) 1355-803-000 FAX (44) 1355-242-743 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 literature@atmel.com Web Site http://www.atmel.com (c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R), is a registered trademark of Atmel. Cadence, Verilog, and Pearl are registered trademarks of Cadence Design Systems. Leonardo Spectrum and Model Technology are trademarks of Mentor Graphics. Synopsis and Primetime are registered trademarks of Synopsis Inc.. Xilinx is a registered trademark of Xilinx Inc.. Actel is a registered trademark of Actel Corporation. Altera is a registered trademark of Altera Corporation. AMD is a registered trademark of Advanced Micro Devices Inc.. Buildgates is a registered trademark of Ambit Design Systems Inc.. CTGen and MEC are registered trademarks of NEC Corporation. LSI Logic is a registered trademark of LSI Logic Corporation. Motorola is a registered trademark of Motorola Inc.. SMOS is a registered trademark of SMOS Systems Inc.. Oki is a registered trademark of Oki Electric Industry Co. Ltd.. Fujistu is a registered trademark of Fujitsu Ltd.. AMI is a trademark of American Megatrends. Other terms and product names may be the trademarks of others. 4110F-AERO-06/02 /0M Printed on recycled paper. |
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