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MG1RT
Radiation Tolerant 0.6 Micron Sea of Gates
Description
The MG1RT series is a 0.6 micron 3 metal layers, array based, CMOS product family offering a new frontier in integration and speed. Several arrays up to 500k cells cover all system integration needs. The MG1RT is manufactured using SCMOS 2/2 RT, a 0.6 micron drawn, radiation tolerant, 3 metal layers CMOS process. The advanced feature size of the MG1RT translates into high performance with gate delays of 250 ps and toggle frequency of 350 MHz. Both 3V and 5V operation are possible for optimum speed/power trade off. The MG1RT series base cell architecture provides high routability of logic with extremely dense compiled memories : ROM, RAM and DPRAM. For instance, the largest array is capable of integrating 128K bits of DPRAM with 128K bits of ROM and over 200,000 random gates. Accurate control of clock distribution can be achieved by PLL hardware and CTS (Clock Tree Synthesis) software. New noise prevention techniques are applied in the array and in the periphery : three or more independent supplies, internal decoupling, customisation dependent supply routing, noise filtering, skew controlled I/Os, low swing differential I/Os, all contribute to improve the noise immunity and reduce the emission level. The basic library is designed for optimum speed and area efficiency with logic synthesis software; for example, the register element is 25% smaller than in most competitors libraries. The new delay model included in the simulation libraries gives unprecedented accuracy of the pre-layout and post- layout simulations. The high level function libraries include many common peripheral controllers and several complex circuits derived from the Atmel Wireless & Microcontrollers image and network ASSPs offering. The MG1RT is supported by an advanced software environment based on industry standards linking proprietary and commercial tools. Cadence, Mentor, Synopsys and VHDL are the reference front end tools. Floor planning associated with timing driven layout provides a short back end cycle. The MG1RT family continues the Atmel Wireless & Microcontrollers offering in array based for commercial, automotive, industrial, military and space circuits. Design compatibility with previous CMOS and BiCMOS series is assured.
Features
D Full Range of Matrices up to 480k Cells D 0.6 m Drawn CMOS, 3 Metal Layers, Sea of Gates D High Integration Level : 1000k Equivalent Gates in Memory Intensive Applications D RAM, DPRAM, FIFO Compilers D Library Optimised for Synthesis, Floor Plan & Automatic Test Generation (ATG) D High Speed Performances : - 250 ps Typical Gate Delay - 350 MHz Toggle Frequency D High System Frequency Skew Control : - 250 MHz PLL for Clock Generation - Clock Tree Synthesis Software D 3 & 5 Volts Operation; Single or Dual Supply Modes D Low Power Consumption : - 0.9 W/Gate/Mhz @3 V - 2.4 W/Gate/Mhz @5 V D Integrated Power on Reset D Matrices With More than 500 Pads D D D D D D Versatile I/O Cell : Input, Output, I/O, Supply, Oscillator MQFPs packages, up to 352 pins GTL & BTL Backplane Driver & Differential Receiver Configurable Drive Up To 48 mA ESD (4 kV) And Latch-up Protected I/O High Noise & EMC Immunity : - I/O with Slew Rate Control - Internal Decoupling - Signal Filtering between Periphery & Core - Application Dependent Supply Routing & Several Independent Supply Sources Wide Range of Packages Delivery in Die Form Advanced CAD Support : Floor Plan, Proprietary Delay Models, Timing Driven Layout, Power Management Cadence, Mentor & Synopsys Reference Platforms EDIF & VHDL Reference Formats QML Q and V
D D D D D D
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Product Outline
TYPE
MG1000E MG1001E MG1002E MG1004E MG1009E MG1014E* MG1020E MG1033E MG1042E* MG1052E MG1070E MG1090E* MG1120E MG1140E* MG1200E* MG1265E* MG1350E MG1480E*
TOTAL CELLS
798 1 566 2 046 3 608 8 970 13 846 19 879 32 868 41 869 51 958 70 059 88 536 118 472 140 049 196 384 264 375 346 203 480 250
USABLE RANDOM GATES**
600 1 100 1 400 2 500 6 300 9 700 13 900 23 000 29 300 36 400 49 000 62 000 82 900 98 000 137 500 185 100 242 300 336 200
USABLE MEMORY GATES**
1 600 3 100 4 100 7 200 17 900 27 700 39 800 65 700 83 700 103 900 140 100 177 100 236 900 280 000 392 800 528 800 692 400 960 500
MAXIMUM I/O ***
24 32 36 48 72 88 104 130 146 162 188 212 244 264 312 360 412 484
TOTAL PADS ****
43 51 55 67 91 107 123 149 165 181 207 231 263 283 331 379 431 503
* to be used when hermetic packaged ** The maximum number of usable gates is application dependant *** I/O pads may be configured as VDD or VSS supplies according to circuit requirements **** This include I/O pads and dedicated pads for supply, PLL...
WARNING: MG1480E cannot be used for SCC 9000 level B or C, or MIL-STD-883 class S.
Array architecture
Core architecture
The core consists of a continuous array of logic cells without routing channels. Each basic cell can implement a logic function such as a two input NAND gate, a memory element (one bit of RAM or DPRAM or 2 to 4 bits of ROM); a basic cell can also be a part of a more complex function such as a latch. The metallisation pattern of the logic functions mainly uses the first metal layer, this maximises routing resources for interconnections at the second and third levels of metal. The core supply is implemented via a fixed vertical grid using the second metal layer and a layout dependent horizontal grid using the first and third metal layers. The active core is surrounded by three busses : one interconnection bus close to the array core, one supply
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bus powering the core and one interconnection bus close to the periphery. The power bus consists of a VDDA ring using the second metal layer and a VSSA ring using the third metal layer. Integrated decoupling capacitors are located below these buses.
POWER PADS
Pad ring architecture
Each side of the die is filled with versatile I/O buffers. Two corners contains PLLs, one a power on reset and one technological devices. Corner pads can be used for PLL I/O's or buffer supplies. Four power rings run above the buffers. The VSSN and VDDN rings supply the output drivers and the VSSQ and VDDQ rings supply the buffer logic.
Buffer & converter
Buffer & converter
PLL
BUFFER ROW outer bus
LOGO POWER PADS
POWER RING Buffer & converter BUFFER COLUMN inner bus
Buffer & converter BUFFER COLUMN
The array core and buffers can have different supply voltages ; in this case the voltage difference is handled by level shifters located close to each I/O buffer. Buffers on different sides of the array can use different supply voltages.
CORE
Buffer & converter POWER PADS
Buffer & converter
Buffer & converter
Buffer & converter
PLL
POR
POWER PADS
Gate capacity
The gate utilisation is the number of equivalent used gates in a design divided by the total number of cells available in the array. The cell structure is designed to provide a gate utilisation of 70 % on average random logic designs and up to 200 % for dual port RAM. The total number of equivalent gates used in an array is the product of gate utilisation by the total number of available cells. This value is design dependent and is influenced by several factors : complexity, operating speed and design structure. As the cell structure is identical for each matrix of the MG1RT family, a better gate utilisation for the smaller arrays may be achieved. Design structure is the dominant factor on gate utilisation ; indeed, as the array has limited routing resources, a higher connection/cell ration implies a lower gate utilisation. Alternatively, regular structures like memories will allow very high gate utilisation to be achieved. The figure below summarises the relation between gate capacity and design style.
1000 900 800 700 Used 600 Equivalent 500 Gates (k) 400 300 200 100 250 Total Cells (k) Random 500 Memory intensive
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Libraries
The MG1RT cell library has been designed to take full advantage of the features offered by both logic and test synthesis tools. Design testability is assured by the full support of SCAN, JTAG (IEEE 1149) and BIST methodologies. More complex macro functions are available, some of these are listed in the following table.
Cell library
A cell is an optimised simple function having a unique metallisation pattern. Cell layout is mainly done using the first metal layer, thus freeing the second and third layers for supply and circuit interconnections. A statistical study of several hundred designs showed that very few cells are intensively used ; therefore the design effort was focused on the optimisation of these cells rather than increasing the number of cells. The result is a library providing fast and dense designs. Storage elements (Flip-flops and latches) are available in normal and scan versions. 5 and 3 Volt libraries can be delivered.
Communication
M6402 M15530 MI2C M6207 UART Manchester coder Protocol controller DPRAM controller Micro Slice M2901 M2910 ALU slice Sequencer JTAG BIST
P Peripheral
M8251 M8259 M8254 M82288 USART Interrupt controller Timer Bus Controller Testability IEEE 1149 I/O and TAP Autotest for memories
Macros library
Macros are useful to define elements of greater complexity than cells. Macros are composed of cells or simpler macros. A large selection of generic or 7400 functions is available : counters, decoders, adders, comparators, parity checkers... Compatibility with previous MC and MF libraries is assured at this level.
Block Generators
Block generators are used to create a customer specific simulation model and metallisation pattern for regular functions like RAM, DPRAM and FIFO. The basic cell architecture allows one bit per cell for RAM and DPRAM and 2 to 4 bits per cell for ROM. The main characteristics of these generators are summarised below.
Typical characteristics (16 k bits)
Function
RAM DPRAM FIFO
Maximum Size (bits)
36 k 36 k 36 k
bits/word
1-36 1-36 1-36
access time (ns)
12 12 12
consumption (mA/MHz)
1.6 3.3 2.1
Used cells
20 k 23 k 23 k
I/O buffer interfacing
I/O Fexibility
All I/O buffers may be configured as input, output, bi-directional, oscillator or supply. A level translator is located close to each buffer.
Inputs
Input buffers with CMOS or TTL thresholds are non inverting and feature versions with and without hysteresis. The CMOS and TTL input buffers may
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incorporate pull-up or pull down terminators. For special purposes, a buffer allowing direct input to the matrix core is available. A differential input buffer is also available allowing resolution of data values on smal swing busses such as GTL or other proprietary solutions.
Differential input typical characteristics Supply (V)
5 3
Outputs
Several kinds of CMOS and TTL output drivers are offered : fast buffers with 3, 6, 12 and 24 mA drive, low noise buffers with 12 mA drive. GTL and pseudo ECL bus drivers are also available.
Differential voltage (mV)
100 100
Tphl (ns)
2,3 3,7
Tplh (ns)
5,5 5,2
Clock generation & PLL
Clock generation
Atmel Wireless & Microcontrollers offers 4 different types of oscillators : low power 32KHz crystal oscillator, high frequency crystal oscillator and 2 RC oscillators. For all devices, the mark-space ratio is better than 40/60 and the start-up time less than 10 ms; the other characteristics are summarised below :
Frequency (MHz) Minimum
Xtal 32K Xtal 50 M RC 10M RC 32 M 0.03 2 0.02 10
frequency F0 by a factor M and the other divides the internal clock frequency F by N. The internal clock frequency is : F = F0 * M / N Both M and N can take values from 1 to 16.
Typical PLL Usage
Clock Tree Output F*N/M
Maximum
0.034 50 10 32
Typical consumption (A)
50 1 000 600 1 500 Q D
PLL %N %M System clock F
PLL
Two independent PLL devices are located in upper left and lower right corners. Each may be used for the following functions : - Synchronisation of an internal clock on a reference system clock. - Skew control : the internal clock transitions are synchronous with the reference clock whatever the load and the depth of logic in the clock tree. - Frequency synthesis : two frequency dividers are included in each PLL. One divides the reference clock
The maximum frequency at the PLL input after division by M is 70 MHz. The maximum internal clock frequency is 250 MHz at 5 V and 150 MHz at 3 V ; the minimum frequency is 20 MHz. Each PLL corner block has 6 dedicated pads : 2 VDD, 3 VSS and a filtering I/O connected to an RC network.
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Propagation delays
Propagation delays for MG1RT cells and blocks are a function of several factors including fan out, signal slope, interconnection capacitance, supply voltage, junction temperature and processing tolerance and additionaly total irradiation dose for special operating conditions. Propagation delays are provided for MG1RT cells under nominal conditions (Tj = 25C, VDD = 5.0 or 3.0 V, typical process, no irradiation). Worst case values are obtained by applying derating coefficients for temperature, voltage, process and total dose irradiation : KT, KV KP and KD. These coefficients are also design dependent and in the design kits each cell has its individual set of parameters. Worst case propagation delays can however be estimated by using the following formula and tables : Worst case = Typical * KTmax * KVmax * KPmax (* KDmax)
Voltage
4.5 5 5.5
KV
1.1 1 0.93
Process
Best Typical Worst
KP
0.78 1 1.28
Voltage
2.7 3 3.2 3.6
KV
1.14 1 0.93 0.81
Temperature
-55 -40 0 25 90 105 145
KT
0.74 0.79 0.92 1 1.21 1.26 1.38
Dose (krad)
0 50
KD
1 1
Power supply & noise protection
The speed and density of the SCMOS 2/2 RT technology causes large switching current spikes for example either when : 16 high current output buffers switch simultaneously, or 10% of the 500 000 gates are switching within a window of 1ns . Sharp edges and high currents cause some parasitic elements in the packaging to become significant. In this frequency range, the package inductance and series resistance should be taken into account. It is known that an inductor slows down the settling time of the current and causes voltage drops on the power supply lines. These drops can affect the behaviour of the circuit itself or disturb the external application (ground bounce). In order to improve the noise immunity of the MG core matrix, several mechanisms have been implemented inside the MG arrays. Two kinds of protection have been added : one to limit the I/O buffer switching noise and the other to protect the I/O buffers against the switching noise coming from the matrix. generated by the switching current : The power supplies of the input and output buffers are separated. The rise and fall times of the output buffers can be controlled by an internal regulator. A design rule concerning the number of buffers connected on the same power supply line has been imposed.
Matrix switching current protection
This noise disturbance is caused by a large number of gates switching simultaneously. To allow this without impacting the functionality of the circuit, three new features have been added : Some decoupling capacitors are integrated directly on the silicon to reduce the power supply drop. A power supply network has been implemented in the matrix. This solution lessens the parasitic elements such as inductance and resistance and constitutes an artificial VDD and Ground plane. One mesh of the network supplies approximately 150 cells. A low pass filter has been added between the matrix and the input to the output buffer. This limits the transmission of the noise coming from the ground or the VDD supply of the matrix to the external world via the output buffers.
I/O Buffers switching protection
Three features are implemented to limit the noise
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Power consumption
The power consumption of an MG1RT array is due to three factors : leakage (P1), core (P2) and I/O (P3) consumption. P = P1 + P2 + P3 random data and PGATE is the power consumption per cell. PGATE = PCA + PCO CACTIVITY is the fraction of the total number of cells toggling per cycle.
Standby Power Consumption
The consumption due to leakage currents may be defined as : P1 = (VDD - VSS) * ICCSB * NCELL Where ICCSB is the leakage current through a polarised basic gate and NCELL is the number of used cells.
Capacitance Power
PCA = C * (VDD - VSS)2/2 C is the total output capacitance and may be expressed as the sum of the drain capacitance of the driver, the wiring capacitance and the gate capacitance of the inputs. Worst case value : PCA # 1.7 W/gate/MHz @ 5 V
Core Power Consumption
The consumtion due to the switching of cells in the core of the matrix is bounded by : P2 = NCELL * PGATE * CACTIVITY * F Where NCELL is the number of used cells, F the data toggling frequency is equal to half the clock frequency for
Commutation Power
PCO = (VDD - VSS) * Idsohm Where Idsohm is the current flowing into the driver between supply and ground during the commutation. Idsohm is about 15 % of the Pmos saturation currrent. Worst case value : Pco # 0.7 W/gate/MHz @ 5 V
I/O Power Consumption
The power consumption due to the I/Os is : P3 = Ni * CO * (VDD - VSS)2 * Fi/2 With Ni equals to the number of buffers running at Fi and CO is the output capacitance.
Note: If a signal is a clock, Fi = F, if it is a data with random values, Fi = F/4.
Power Consumption Example
Matrix
Used gates (70 %) Voltage Frequency 185 k 5V 40 MHz
MG1RT265
185 k 3V 40 MHz
Standby Power
Iccsb (125C) P1 = (VDD - VSS) * ICCSB * NCELL 10 nA 10 mW 10 nA 6 mW
Core Power
Power Consumption per Cell Cactivity P2 = NCELL * PGATE * Cactivity * F 2.4 W/Gate/MHz 20 % 1776 mW 0.9 W/Gate/MHz 20 % 666 mW
I/O Power
Number of Outputs and I/O Buffers Output Capacitance P3 = Ni * CO * (VDD - VSS)2 * Fi/2 100 50 pF 625 mW 100 50 pF 225 mW
Total Power
P = P1 + P2 + P3 2.41 W 900 mW
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MG1RT
Design flows & tools
Design Flows and modes
A generic design flow for an MG1RT array is sketched on next page. A top down design methodology is proposed which starts with high level system description and is refined in successive design steps. At each step, structural verification is performed which includes the following tasks : - Gate level logic simulation and comparison with high level simulation results. - Design and test rule check. - Power consumption analysis. - Timing analysis (only after floor plan). The main design steps are : - System specification, preferably in VHDL form. - Functional description at RTL level. - Logic synthesis. - Floor planning and bonding diagram generation. - Test insertion, ATG and/or fault simulation. - Physical cell placement, JTAG insertion and clock tree synthesis. - Routing To meet the various requirements of designers, several interface levels between the customer and Atmel Wireless & Microcontrollers are possible. MG1RT Design Flow
System Specifications RTL Simulation Logic synthesis STAR Floor Plan Bonding diagram Scan insertion ATG & Fault Simulation
Placement
JTAG insertion Clock Tree Synthesis
Routing Samples Manufacturing and Test STAR Back Annotation Simulation
For each of the possible design modes a review meeting is required for data transfer from the user to Atmel Wireless & Microcontrollers. In all cases the final routing and verifications are performed by Atmel Wireless & Microcontrollers. The design acceptance is formalised by a design review which authorises Atmel Wireless & Microcontrollers to proceed with sample manufacturing.
Design tool and design kits (DK)
The basic content of a design kit is described in the table on the right. The interface formats to and from Atmel Wireless & Microcontrollers rely on IEEE or industry standard : - VHDL for functional descriptions - VHDL or EDIF for netlists
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- Tabular or .CAP for simulation results - SDF (VITAL format) and SPF for backannotation - LEF and DEF for physical floor plan information The design kit level supported for several commercial tools is outlined in the table below.
Design kit Description
Design Tool or library
Design manual & libraries VHDL library for blocks
Atmel Software Name
Design Kit Support
Cadence Mentor Synopsys Compass Intergraph Viewlogic
VHDL
* * * * * *
Gate
* *
Synthesis library Gate level simulation library Design rules analyser STAR COMET
* Power consumption analyser Floor plan library Timing analyser library Package & bonding software Scan path & JTAG insertion ATG & fault simulation library PIM ASIS/AJIS
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MG1RT
Operating characteristics
Absolute Maximum Ratings
Ambient temperature under bias (TA) Military . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to +125C Junction temperature . . . . . . . . . . . . . . . . . . TJ < TA + 20C Storage temperature . . . . . . . . . . . . . . . . . . . . -65 to +150C TTL/CMOS : Supply voltage VDD . . . . . . . . . . . . . . . . . . . -0.5 V to +7 V I/O voltage . . . . . . . . . . . . . . . . . . . . -0.5 V to VDD + 0.5 V Stresses above those listed may cause permanent damage to the device.
DC Characteristics
Specified at VDD = +5 V +/- 10 %
Symbol
VIL
Parameter
Input LOW voltage CMOS input TTL input Input HIGH voltage CMOS input TTL input Output low voltage CMOS input TTL input Output high voltage CMOS input TTL input Schmitt trigger positive threshold CMOS input TTL input Schmitt trigger negative threshold CMOS input TTL input Input leakage No pull up/down Pull up Pull down 3-State Output Leakage current Output Short circuit current IOSN IOSP Leakage current per cell Operating current per cell
Min
0 0 0.7 VDD 2.2
Typ
Max
0.3 VDD 0.8 VDD VDD 0.1 VDD 0.4
Unit
V
Conditions
VIH
V V IOL = -12, 6, 3 mA *
VOL
VOH
V 3.9 2.4 2.6 1.7 1.3 1.1 1.4 1.2 +/-1 -50 +180 +/-1 +/-5 +450 +/-5 48 36 0.3 0.3 1 0.5 3.2 1.9 V
IOH = -12, 6, 3 mA *
VT+
VT-
V
IL
-250
A A A A mA mA nA A/MHz VOUT = VDD VOUT = VSS
IOZ IOS
ISSDP ISSOP
* For each of the following buffers: Bout12, Bout6, Bout3
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DC Characteristics
Specified at VDD = +3 V +/- 10 %
Symbol
VIL
Parameter
Input LOW voltage CMOS input TTL input Input HIGH voltage CMOS input TTL input Output low voltage CMOS input TTL input Output high voltage TTL input Schmitt trigger positive threshold CMOS input TTL input Schmitt trigger negative threshold CMOS input TTL input Input leakage No pull up/down Pull up Pull down 3-State Output Leakage current Output Short circuit current IOSN IOSP Leakage current per cell Operating current per cell
Min
0 0 0.7 VDD 2.2
Typ
Max
0.3 VDD 0.8 VDD VDD 0.1 VDD 0.4
Unit
V
Conditions
VIH
V V IOL = -6, 3, 1.5 mA *
VOL
VOH VT+
V 2.4 1.8 1.3 0.9 0.9 1.0 1.0 +/-1 -50 -50 -10 20 +100 +/-1 24 12 0.1 0.2 0.3 2.0 1.4 V
IOH = +4, 2, 1 mA *
VT-
V
IL
A A A A mA mA nA A/MHz VOUT = VDD VOUT = VSS
IOZ IOS
ISSDP ISSOP
* For each of the following buffers: Bout12, Bout6, Bout3
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AC Characteristics
TJ = 25C, Process typical (all values in ns)
Load (40 pF) Buffer
BOUT3
Description
Output buffer with 3 mA drive
Transition 5V
Tplh Tphl 5.04 6.16 2.94* 2.99* 3.57* 6.96* 5.15 6.20 3.09* 3.02* 3.68* 7.04*
3V
8.88 9.80 5.10 4.77 6.10 12.10 9.06 9.90 5.31* 4.88* 6.40 12.30
BOUT12
Output buffer with 12 mA drive
Tplh Tphl
BOUTQ
Low noise output buffer with 12 mA drive
Tplh Tphl
B3STA3
3-state output buffer with 3 mA drive
Tplh Tphl
B3STA12
3-state output buffer with 12 mA drive
Tplh Tphl
B3STAQ
Low noise 3-state output buffer with 12 mA drive
Tplh Tphl
* 60 pF
Description
BINCMOS CMOS input buffer
Transition
Tplh Tphl
FO
1.38 15 1.31 1.55 16 1.70 0.91 12 0.45 1.02 51 0.86 1.11 16 0.80 1.10 8 0.33 1.28 8 0.42 1.15 8 0.94 0.50 0.10 1.12 7 0.92 0.78 -0.16 2.11 1.93 2.27 1.89 1.47 0.70 1.73 1.34 1.76 1.24 1.66 0.55 1.83 0.66 1.96 1.59 1.20 0.23 1.92 1.57 1.88 -0.39
BINTTL
TTL input buffer
Tplh Tphl
INV
Inverter
Tplh Tphl
BUF4X
High drive internal buffer
Tplh Tphl
NAND2
2-Input NAND gate
Tplh Tphl
NOR2
2-Input NOR gate
Tplh Tphl
OAI22
4-input OR AND INVERT gate
Tplh Tphl
FDFF
D flip-flop, Clk to Q
Tplh Tphl Ts Th
SFF
D flip-flop with scan input, Clk to Q
Tplh Tphl Ts Th
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Design Offering
Five different ASIC design offerings are available : ULC, Gate Arrays, Composite Arrays, Cell Based and Full Custom, each physical implementation giving an answer to the compromise : flexibility/unit integration/development cost. price and
Design Modes
Three different design modes can be agreed between Customer and Atmel Wireless & Microcontrollers, depending on system and integration skills requirements.
Mode
Customer Design Customer and Atmel Design Atmel Design
Logic Design
Customer Customer Atmel
Physical Layout
Customer Atmel Atmel
Design Tools
Customer tools Atmel supported tools (Netlist and simulation) Atmel supported tools (Netlist and simulation)
Supported tools are currently CADENCE, COMPASS, MENTOR, SYNOPSYS and VHDL/VITAL.
Design Modes versus Design Offering
Customer and Mode Customer Atmel Design Design Atmel Design
j x x x x f j j j
Design Phases and Meetings
The design of a circuit is separated into four main phases, separated by three major meetings between Atmel Wireless & Microcontrollers and the Customer, as shown in Figure 1.
Offering
ULC Gate Array Composite Array Cell Based Full Custom
x : standard offer. f : depending on human and hardware ressources needed and/or available. j : specific development using Atmel Wireless & Microcontrollers own expertise.
The design phases and meetings.
Planning Order Entry Logic Review Design Review
Pre-sale Circuit Feasibility (Customer / Atmel Wireless & Microcontrollers)
Logic Design (Customer / Atmel Wireless & Microcontrollers)
Physical Design (Customer / Atmel Wireless & Microcontrollers)
- Manufacturing - Sample Test and Delivery (Atmel Wireless & Microcontrollers)
Atmel Wireless & Microcontrollers Design
Customer and Atmel Wireless & Microcontrollers Design
Customer Design
The information contained herein is subject to change without notice. No responsibility is assumed by Atmel Wireless & Microcontrollers for using this publication and/or circuits described herein : nor for any possible infringements of patents or other rights of third parties which may result from its use.
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