View M44C588_989340.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

M44C588
MARC4 - 4-bit Microcontroller with 128 Segment LCD
The M44C588 is a member of the TEMIC family of 4-bit single chip microcontrollers. It contains ROM, RAM, up to 32 digital I/O pins, 8-bit synchronous serial I/O, 32 LCD segment drivers, 8 maskable external interrupt sources, 5 maskable internal interrupts, a watchdog timer, 32-kHz oscillator with programmable interval timer, 2 x 8-bit multifunction timer/counter and a versatile on-chip system clock generation module.
Features
Benefits
D 9K x 8-bit application ROM D 512 x 4-bit RAM (256 x 4-bit direct accessible) D Bitwise maskable prioritised interrupts D Up to 8 external and 5 internal interrupt sources D Up to 36 I/O lines - bit or nibblewise I/O D High drive port (4 mA, VDD = 2.2 V) D 2 x 8-bit multifunction timer/counters D 32-kHz on-chip oscillator with 2 programmable
interval timer / prescaler
D 8-bit synchronous serial I/O for 2- /3-wire communication
D 4-MHz crystal, 4-MHz ceramic resonator, external
resistor or fully integrated RC oscillator as options
VEE2 VEE1 C2 VMI VREG S17...S32
(bidir. I/O)
D D D D D D D D D D D D D
Extremely low power consumption Minimal external components Coded reset and watchdog timer option 8 hardware and software interrupt priority levels Power on reset, "brown out" function Power down modes 1.8 V to 6.2 V supply voltage 2 level battery low detect (2.2 V / 2.4 V) Data retention down to 1.8 V in SLEEP mode Efficient, hardware controlled interrupt handling High level programming language in qFORTH Comprehensive library of useful routines PC based development tools
NRST TE SCLIN
C1 OSCIN OSCOUT AVDD VSS VDD
LCD
32 x 4 and
Real time clock
Low voltage detect
Master reset
Test Sleep Timer/ counter Timer 1
System clock
S1...S16
PRAM
256 x 4 bit
ROM
9K x 8 bit
RAM
256 x 4 bit
Prescaler Watch- dog Interval Timer
16 I/O
COM0.. COM3
MARC4
4-bit CPU core I/O bus
I/O
Timer 0
Port 4 (high drive)
I/O
I/O
I/O
Interrupt & reset
I/O
Interrupt
serial
I/O
Buzzer
Port 0
Port 1
Port B
Port 6
96 11556
Figure 1. Block diagram
TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97
1 (44)
Preliminary Information
M44C588
Figure 2. Pin connections Table 1. Pin description
AAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA
COM0 - COM3
Name VDD AVDD VSS BP00 - BP03 BP10 - BP13 BP40-T0OUT0 BP41-T0OUT1 BP42-T1OUT0 BP43-T1OUT1 BPB0 - BPB3 BP60 BP61 BP62 BP63 SCLIN SCLOUT OSCIN OSCOUT TE S01 - S16 S17 - S32 VEE1 VEE2 VREG C1, C2 NRST
Function Power supply voltage +2.2 V to +6.2 V Analogue power supply voltage +2.2 V to +6.2V Circuit ground 4 bidirectional I/O lines of Port 0 - automatic nibblewise configurable I/O 4 bidirectional I/O lines of Port 1 - automatic nibblewise configurable I/O I/O line BP40 of Port 4(*) - configurable I/O or Timer/Counter 0 I/O T0OUT0 I/O line BP41 of Port 4(*) - configurable I/O or Timer/Counter 0 I/O T0OUT1 I/O line BP42 of Port 4(*) - configurable I/O or Timer/Counter 1 I/O T1OUT0 I/O line BP43 of Port 4(*) - configurable I/O or Timer/Counter 1 I/O T1OUT1 4 bidirectional I/O lines of Port B - bitwise configurable I/O I/O line BP60 of Port 6 - configurable I/O or serial clock output or external interrupt source I/O line BP61 of Port 6 - configurable I/O or serial data I/O or external interrupt source I/O line BP62 of Port 6 - configurable I/O or buzzer output BZ or external interrupt source I/O line BP63 of Port 6 - configurable I/O or buzzer output NBZ or external interrupt source 4-MHz quartz crystal/ceramic resonator or trimming resistor pin (mask option dependent) 4-MHz quartz crystal/ceramic resonator pin (mask option dependent) 32-kHz quartz crystal pin (mask option dependent) 32-kHz quartz crystal pin (mask option dependent) Testmode input. This input is used to control the test modes (internal pull-down) LCD backplane outputs LCD segment output lines LCD output lines or bidirectional 2 bitwise configurable digital I/O LCD doubler voltage (2 x VREG) LCD tripler voltage (3 x VREG) Regulated LCD supply voltage LCD tripler capacitor Reset input (/output), a logic low on this pin resets the device. An internal watchdog or coded reset is indicated by a low pulse on this pin.
(*) For mask options please see the ordering information.
2 (44)
Preliminary Information
TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97
M44C588
Table of Contents
1 MARC4 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Components of MARC4 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.1 ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.2 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.4 ALU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.5 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.6 I/O Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.2 Software Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Master Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.1 Clock Trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Addressing Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Bidirectional Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 Port 0, Port 1, Bidirectional Ports Type 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Port B - Bidirectional Port Type 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 Port 6 - Bidirectional Port Type 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-bit Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSI Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.2 Port 4 - Bidirectional Port Type 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.3 Port Monitor Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Interval Timers / Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.1 Interval Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Liquid Crystal Display Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Display Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Display Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 Initializing the LCD Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 LCD operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 Programming the LCD Configuration Register and the Port Configuration . . . . . . 3.2.4 Reduction of LCD Charge Pump and Frame Frequency . . . . . . . . . . . . . . . . . . . . . 3.2.5 LCD Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 LCD Voltage and Timing Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 3:1 Multiplex Drive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 4:1 Multiplex Drive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Extended RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 4 4 5 5 6 8 8 8 8 10 10 10 12 13 13 13 13 16 17 18 18 22 23 27 27 29 29 31 32 32 33 34 34 35 35 35 36 37 39 41 41
2
3
4 5
TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97
3 (44)
Preliminary Information
M44C588
1 MARC4 Architecture
Reset
Reset Clock
System clock
Sleep
1.1
General Description
The MARC4 microcontroller consists of an advanced stack based 4-bit CPU core and on-chip peripherals. The CPU is based on the HARVARD architecture with physically separate program memory (ROM) and data memory (RAM). Three independent buses, the instruction bus, the memory bus and the I/O bus are used for parallel communication between ROM, RAM and peripherals. This enhances program execution speed by allowing both instruction prefetching, and a simultaneous communication to the on-chip peripheral circuitry. The extremely powerful integrated interrupt controller with associated eight prioritized interrupt levels supports fast and efficient processing of hardware events. The MARC4 is designed for the high level programming language qFORTH. The core includes an expression and a return
4 (44)
IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII
MARC4 CORE
PC X Y SP RP
Program memory
RAM
256 x 4-bit
Instruction bus
Instruction decoder Interrupt controller
Memory bus
TOS
CCR
ALU
I/O bus
On-chip peripheral modules
Figure 3. MARC4 core
94 8973
stack. This architecture allows high level language programming without any loss in efficiency or code density.
1.2
Components of MARC4 Core
The core contains ROM, RAM, ALU, program counter, RAM address registers, instruction decoder and interrupt controller. The following sections describe each functional block in more detail:
1.2.1
ROM
The program memory (ROM) is mask programmed with the customer application program during the fabrication of the microcontroller. The ROM is addressed by a 12-bit wide program counter, thus predefining a maximum program bank size of 4 Kbytes which can be addressed directly without bank switching.
Preliminary Information
TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97
M44C588
MARC4 self test routines Bank 3 Bank 2 FFFh 800h 7FFh 1FFh 000h Basebank Zero page Bank 1 Bank 4 SCALL addresses Port D: 11xxb Port D: 10xxb Port D: 01xxb Port D: 00xxb
1F8h 1F0h 1E8h 1E0h
Zero page
020h 018h 010h 008h 000h
1E0h 1C0h 180h 140h 100h 0C0h 080h 040h 008h 000h
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 $RESET $AUTOSLEEP
94 8709
Figure 4. ROM map of M44C588
Test ROM
An additional 1 Kbyte of ROM exists in the 4th ROM bank which is accessible using a ROM bank switch. Of this program space a section is reserved for quality control self-test software, the remainder is available for application program. The lowest ROM address segment is taken up by a 512 byte Zero page which contains predefined start addresses for interrupt service routines and special subroutines accessible with single byte instructions (SCALL). The corresponding memory map is shown in figure 4. Look-up tables of constants can also be held in ROM and are accessed via the MARC4's built-in TABLE instruction. ROM Banking For customers programming with qFORTH the bank switching is fully supported by the compiler. The MARC4 switches from one ROM bank to another by writing the new bank number to the ROM Bank Register (RBR). Conventional program space (power up bank) resides in ROM bank 0. Each ROM bank consists of a 4 Kbyte address space whereby the lowest 2 Kbyte is common to all banks, so that addresses between 000h and 7FFh always accesses the same ROM data (see figure 4). When ROM banking is used, the compiler will, if necessary insert program code to save and restore the condition of the RBR on bank switching.
256 x 4-bit wide and is used for the expression stack, the return stack and data memory for variables and arrays. The internal RAM is addressed by any of the four 8-bit wide RAM address registers SP, RP, X and Y. The additional block of 256 x 4-bit RAM is I/O-mapped and addressed through the peripheral bus. This PRAM should be used for arrays which are accessed seldomly, when doing heavy duty math routines. Expression Stack The 4-bit wide expression stack is addressed with the expression stack pointer (SP). All arithmetic, I/O and memory reference operations take their operands from, and return their result to the expression stack. The MARC4 performs the operations with the top of stack items (TOS and TOS-1). The TOS register contains the top element of the expression stack and works like an accumulator. This stack is also used for passing parameters between subroutines, and as a scratch pad area for temporary storage of data. Return Stack The 12-bit wide return stack is addressed by the return stack pointer (RP). It is used for storing return addresses of subroutines, interrupt routines and for keeping loop index counts. The return stack can also be used as a temporary storage area. The MARC4 instruction set supports the exchange of data between the top elements of the expression stack and the return stack. The two stacks within the RAM have a user definable location and maximum depth.
1.2.2
RAM
The M4C588 contains 512 x 4-bit wide static random access memory (RAM). This RAM area consists of two separate blocks. The MARC4 core internal RAM is
TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97
5 (44)
Preliminary Information
M44C588
(256 x 4-bit) Autosleep FCh
RAM
Expression stack
3 FFh Global variables
X
RAM address register:
TOS-1
11
RP
04h 00h
Return stack Global v 07h variables 03h
Figure 5. RAM map
1.2.3
Registers
The MARC4 controller has seven programmable registers and one condition code register. They are shown in the following programming model. Program Counter (PC) The program counter (PC) is a 12-bit register that contains the address of the next instruction to be fetched from the ROM. Instructions currently being executed are decoded in the instruction decoder to determine the internal micro operations. For linear code (no calls or branches) the program counter is incremented with every instruction cycle. If a branch-, call-, return-instruction or an interrupt is executed the program counter is loaded with a new address. The program counter is also used with the TABLE instruction to fetch 8-bit wide ROM constants. ROM Banking Register (RBR) The ROM banking register is a 4-bit register whereby in the M44C588 only bit 2 and bit 3 are used. These indicate which ROM bank is presently being addressed. The RBR is accessed with a standard peripheral read or write instruction (IN or OUT, port address `D' hex) and is fully supported by the qFORTH compiler. RAM Address Registers The RAM is addressed with the four 8-bit wide RAM address registers: SP, RP, X and Y. These registers allow access to any of the 256 RAM nibbles. Expression Stack Pointer (SP) The stack pointer (SP) contains the address of the next-totop 4-bit item (TOS-1) of the expression stack. The
pointer is automatically pre-incremented if a nibble is moved onto the stack or post-decremented if a nibble is removed from the stack. Every post-decrement operation moves the item (TOS-1) to the TOS register before the SP is decremented. After a reset the stack pointer has to be initialized with " >SP S0 " to allocate the start address of the expression stack area. Return Stack Pointer (RP) The return stack pointer points to the top element of the 12-bit wide return stack. The pointer automatically preincrements if an element is moved onto the stack or it post-decrements if an element is removed from the stack. The return stack pointer increments and decrements in steps of 4. This means that every time a 12-bit element is stacked, a 4-bit RAM location are left unwritten. These location are used by the qFORTH compiler to allocate 4-bit variables. After a reset the return stack pointer has to be initialized with ">RP FCh ". RAM Address Register ( X and Y ) The X and Y registers are used to address any 4-bit item in the RAM. A fetch operation moves the addressed nibble onto the TOS. A store operation moves the TOS to the addressed RAM location. Using either the pre-increment or post-decrement addressing mode arrays in the RAM can be compared, filled or moved. Top Of Stack ( TOS ) The top of stack register is the accumulator of the MARC4. All arithmetic/logic, memory reference and I/O operations use this register. The TOS register receives data from the ALU, ROM, RAM or I/O bus.
6 (44)
Preliminary Information
IIIII IIIII
0 12-bit
SP
IIIII IIIII IIIII IIIIIII I IIIIIII IIIIIII I IIIIIII IIII IIII
Y
Expression stack
Return stack
RP
III
4-bit
0 TOS TOS-1 TOS-2
IIIII
SP
94 8975
TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97
M44C588
Condition Code Register ( CCR ) The 4-bit wide condition code register contains the branch, the carry and the interrupt enable flag. These bits indicates the current state of the CPU. The CCR flags are set or reset by ALU operations. The instructions SET_BCF, TOG_BF, CCR! and DI allow a direct manipulation of the condition code register. Carry/Borrow ( C ) The carry/borrow flag indicates that borrow or carry out of arithmetic logic unit ( ALU ) occurred during the last arithmetic operation. During shift and rotate operations this bit is used as a fifth bit. Boolean operations have no affect on the C flag. Branch ( B ) The branch flag controls the conditional program branching. Should the branch flag have been set by a previous instruction a conditional branch will cause a jump. This flag is affected by arithmetic, logic, shift, and rotate operations. Interrupt Enable ( I ) The interrupt enable flag globally enables or disables the triggering of all interrupt routines with the exception of the non-maskable reset. After a reset or on executing the DI instruction the interrupt enable flag is reset thus disabling all interrupts. The core will not accept any further interrupt requests until the interrupt enable flag has been set again by either executing an EI, RTI or SLEEP instruction.
11
0
PC
0
Program counter RBR
7
bank
-- --
0
ROM bank register Return stack pointer Expression stack pointer
RP
7
0
0
0
SP
7 0
X
7 0
RAM address register (X) RAM address register (Y)
3 0
Y
TOS
3 0
Top of stack register C -- B I Condition code register
Interrupt enable Branch Reserved Carry / borrow
CCR
96 11518
Figure 6. Programming model
TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97
7 (44)
Preliminary Information
M44C588
1.2.4 ALU
The 4-bit ALU performs all the arithmetic, logical, shift and rotate operations with the top two elements of the expression stack (TOS and TOS-1) and returning the result to the TOS. The ALU operations affect the carry/borrow and branch flag in the condition code register (CCR).
1.2.5
Instruction Set
The MARC4 instruction set is optimized for the high level programming language qFORTH. Many MARC4 instructions are qFORTH words. This enables the compiler to generate fast and compact program code. The CPU has an instruction pipeline allowing the controller to prefetch instruction from ROM at the same time as the present instruction is being executed. The MARC4 is a zero address machine, the instructions containing only the operation to be performed and no source or destination address fields. The operations are implicitly performed on the data placed on the stack. There are one and two byte instructions which are executed within 1 to 4 machine cycles. A MARC4 machine cycle is made up of two system clock (SYSCL) cycles. Most of the instructions are only one byte long and are executed in a single machine cycle. For more information see section "MARC4 instruction set overview".
1.2.6
I/O Bus
The I/O ports and the registers of the peripheral modules
8 (44)
IIIII IIII IIIII III IIII IIIII III IIII IIIIIIIII IIII IIII IIIIIIIII IIII IIII III I II IIIIIIIIIIIIII IIII III I I II IIIIIIIIIIIIIIIIII I IIIIIIII I I IIIIIIIIIIIIIIIIII I IIIIIIII IIIII IIII
RAM SP TOS-1 TOS-2 TOS-3 TOS-4 TOS ALU CCR
Figure 7. ALU zero address operations
94 8977
(Timer 0, Timer 1, Watch timer, Watchdog etc.) are I/O mapped. All communication between the core and the onchip peripherals takes place via the I/O bus and the associated I/O control. With the MARC4 IN and OUT instructions the I/O bus allows a direct read or write access to one of the 16 primary I/O addresses. More about the I/O access to the on-chip peripherals is described in the section "Peripheral Modules". The I/O bus is internal and is not accessible by the customer on the final microcontroller device, but it is used as the interface for the MARC4 emulation (see also the section "Emulation").
1.3
Interrupt Structure
The MARC4 can handle interrupts with eight different priority levels. They can be generated from the internal and external interrupt sources or by a software interrupt from the CPU itself. Each interrupt level has a hard-wired priority and an associated vector for the service routine in the ROM (see table 2). The programmer can postpone the processing of interrupts by resetting the interrupt enable flag (I) in the CCR. An interrupt occurrence will still be registered but the interrupt routine only started after the I flag is set. All interrupts can be masked, and the priority individually software configured by programming the appropriate control register of the interrupting module (see section "Peripheral Modules").
Preliminary Information
TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97
M44C588
INT7
7 6 Priority level 5 4 3 2 1 0
Interrupt Processing For processing the eight interrupt levels the MARC4 includes an interrupt controller with two 8-bit wide "interrupt pending" and "interrupt active" registers. The interrupt controller samples all interrupt requests during every non-I/O instruction cycle and latches these in the interrupt pending register. If no higher priority interrupt is present in the interrupt active register it signals the CPU to interrupt the current program execution. If the interrupt enable bit is set the processor enters an interrupt acknowledge cycle. During this cycle a short call (SCALL) instruction to the service routine is executed and the current PC is saved on the return stack. An interrupt service routine is finished with the RTI instruction. This instruction sets the interrupt enable flag, resets the corresponding bits in the interrupt pending/active register and fetches the return address from the return stack to the program counter. When the interrupt enable flag is reset (triggering of interrupt routines are disabled), the execution of new interrupt service routines is inhibited but not
TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97
AAAAA AAAAA AAIIIIII AA AAIIIIII AA AAIIIIIII AA AAIIIIIII AA AAAA AAIIAAAA AA A AIIIII AAAA AAAA AAA AAAA AAA AAAA AAAA AAAA
INT7 active INT5 RTI INT5 active INT3 RTI INT2 INT3 active RTI INT2 pending
SWI0
INT2 active
RTI
INT0 pending
INT0 active
RTI Main / Autosleep
Main / Autosleep
Time
94 8978
Figure 8. Interrupt handling
the logging of the interrupt requests in the interrupt pending register. The execution of the interrupt will be delayed until the interrupt enable flag is set again. Note that interrupts are only lost if an interrupt request occurs while the corresponding bit in the pending register is still set (i.e. the interrupt service routine is not yet finished). It should also be realised that automatic stacking of the RBR is not carried out by the hardware and so if ROM banking is used, the RBR must be stacked on the expression stack by the application program and restored before the RTI. After a master reset (power-on, external or watchdog reset), the interrupt enable flag and the interrupt pending and interrupt active register are all reset. Interrupt Latency The interrupt latency is the time from the occurrence of the interrupt to the interrupt service routine being activated. In the MARC4 this is extremely short taking between 3 to 5 machine cycles depending on the state of the core.
9 (44)
Preliminary Information
M44C588
Table 2. Interrupt priority table
AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAA
C8h (SCALL 040h) D0h (SCALL 080h) D8h (SCALL 0C0h) E8h (SCALL 100h) E8h (SCALL 140h) F0h (SCALL 180h) F8h (SCALL 1C0h) FCh (SCALL 1E0h)
Interrupt INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7
Priority lowest | | | | | highest
ROM Address 040h 080h 0C0h 100h 140h 180h 1C0h 1E0h
Maskable Yes Yes Yes Yes Yes Yes Yes Yes
Interrupt Opcode
1.3.1
Hardware Interrupts
Table 3. Hardware interrupts
AAAAAAAA A A AAA AAAAAA A A A AAA AAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAA AAAAAA AAAAAAAA A A AAA AAAAAA A A A AAA AAAAAA A A A AA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAA AAAAAA A A A AAA AAAAAA A A AAA AAAAAA AA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA A A AAA AAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAA AAAAAA AAAAAAAA A A AAA AAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAA A AAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAA AAAAAA A A A AAA AAAAAA A A AAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA A AAA AAAAAA
X # # * * * * * * * * * * * * * * * * Interval timer INTA * * ITIPR ITIPR T0CR T1CR 0 1 0 0 Interval timer INTB Timer 0 Timer 1 * * * * * * * * * * low level active 1/2 - 2 sec. time out level any inputs any edge, any input any edge, any input any edge, any input SSI receive buffer full, transmit buffer empty 1 of 8 frequencies (1 - 128Hz) 1 of 8 frequencies (8 - 8192Hz) overflow/compare/ end measurement overflow/compare/ end measurement X = hardwired (neither optional or software configurable) # = customer mask option (see "Ordering Information") * = software configurable (see "Peripheral Modules" section for further details) In the M44C588 there are eleven hardware interrupt sources which can be programmed to occupy a variety of priority levels. Each source can be individually masked by mask bits in the corresponding control registers. An overview of the possible hardware configurations is shown in table 3. The software triggered interrupt operates exactly like any hardware triggered interrupt. The SWI instruction takes the top two elements from the expression stack and writes the corresponding bits via the I/O bus to the interrupt pending register. Thus using the SWI instruction, interrupts can be re-prioritised or lower priority processes scheduled for later execution.
Interrupt Source NRST external Watchdog Port B coded reset Port B monitor Port 6 external INTX Port 6 external INTY Serial I/O
0
Possible Interrupt Priorities 1234567
RST
Interrupt Mask Register Bit - - - - - - PBIPR 3 - 0 - 0 SIM0 0
Function
1.3.2
Software Interrupts
The programmer can generate interrupts using the software interrupt instruction (SWI) which is supported in qFORTH by predefined macros named SWI0...SWI7. 10 (44)
1.4
Master Reset
The master reset forces the CPU into a well-defined condition, is unmaskable and is activated independent of TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97
Preliminary Information
M44C588
the current program state. It can be triggered by either initial supply power-up, a short collapse of the power supply, a watchdog time out, activation of the NRST input or the occurrence of a coded reset on Port B (see figure 9). A master reset activation will reset the interrupt enable flag, the interrupt pending register and the interrupt active register. During the reset phase the I/O bus control signals are set to 'reset mode' thereby initializing all on-chip peripherals. Releasing the reset results in a short call instruction (opcode C1h) to the ROM address 008h. This activates the initialization routine $RESET which in turn initialises all necessary RAM variables, stack pointers and peripheral configuration registers. Power-on Reset The fully integrated power-on reset circuit ensures that the core is held in a reset state until the minimum operating supply voltage has been reached. A reset condition will also be generated should the supply voltage drop momentarily below the minimum operating supply. External Reset (NRST) An external reset can be triggered with the NRST pin. To
VDD Pull-up NRST * = Mask option
activate an external reset the pin should be low for a minimum of two machine cycles. Coded Reset (Port B) The coded reset circuit is connected directly to the Port B terminals. Using a mask option, the user can define a hardwired code combination (e.g. all pins low) which, if occurring on the Port B will generate a reset in the same way as the NRST pin. Note that if this option is used, the reset is not maskable and will also trigger if the predefined code is written on to the Port B by the CPU itself. Care should also be taken not to generate an unwanted reset by inadvertently passing through the reset code on input transitions. This applies especially if the pins have a high capacitive loading. Watchdog Reset The watchdog can be activated by using a mask option and triggers a reset with every watchdog counter overflow. To suppress the watchdog reset, the counter must be regularly reset by reading the watchdog register address (WDRES). The CPU reacts in exactly the same manner as a reset stimulus from any of the above sources
CPU reset VSS V DD
Power-on reset
reset code
CODE *
time out Port B I/O
Watchdog * rst
WD reset
Port B
CPU
96 115
Figure 9. Reset configuration
1.5
1.5.1
Clock Generation
Clock Module
The M44C588 contains a clock module with 4 different internal oscillator types: two RC-oscillators, one 4-MHz crystal oscillator and one 32-kHz crystal oscillator. The
pins OSCIN and OSCOUT are the interface to connect a crystal either to the 4-MHz, or to the 32-kHz crystal oscillator. SCLIN can be used as input for external clocks or to connect an external trimming resistor for the RC-oscillator 2. All necessary circuitry except the crystal and the trimming resistor is integrated on-chip. One of
TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97
11 (44)
Preliminary Information
M44C588
these oscillator types or an external input clock can be selected to generate the system clock (SYSCL). In applications that do not require exact timing, it is possible to use the fully integrated RC-oscillator 1 without any external components. The RC-oscillator 2 is more precise whereby the oscillator frequency can be trimmed with an external resistor attached between SCLIN and VDD. In this configuration, the RCoscillator 2 frequency can be maintained stable to within a tolerance of 10% over the full operating temperature and voltage range. The clock module is programmable via software with the clock manage register (CM) and the system configuration register (SC). The required oscillator configuration has to be selected with the OS1[1:0]-bits in the SC-register. A programmable 4-bit divider stage allows the adjustment of the system clock speed. A special feature of the clock management is that an external oscillator may be used and switched on and off via a port pin for the power-down mode. Before the external clock is switched off, the internal RC-oscillator 1 must be selected with the CCSbit and then the SLEEP mode may be activated. In this state an interrupt can wake up the controller with the RCoscillator, and the external oscillator can be activated and selected by software. A synchronization stage avoids too short clock periods if the clock source or the clock speed is changed.
SCLIN
Ext. clock
ExIn ExOut Stop RCOut2 Stop 4Out Stop
RC oscillator 1
IN1
SC: RC[1:0]
SYSCLmax SYSCL to CPU and Timer/ counter
RC oscillator2
OSCIN RTrim
RCOut1 Stop Control
/2 IN2
/2
/2 Divider chain
/2
*
4-MHz oscillator
Oscin Oscout
/8
32-kHz oscillator
OSCOUT Oscin Oscout 32Out Stop SUBCL CM: NSTOP CCS CSS1 CSS0 32 kHz Sleep SYSCLmax/64
*
*
mask option SC: OS1 OS0
13386
Figure 10. Clock module Table 4. Clock modes
Mode 1 2 3 4 OS1 1 0 1 0
A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AAA AA AAAAAAAAAAAAAAAAAA AA A A A AAA AAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AA A A AAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAA
SYSCL max/64 SYSCL max/64 SYSCL max/64 SCLIN / 128 SYSCL max/64 fxtal / 128
Clock Source for SYSCL OS0 CCS = 1 CCS = 0 1 RC-oscillator 1 (intern) External input clock 1 RC-oscillator 1 (intern) RC-oscillator 2 with external trimming resistor 0 RC-oscillator 1 (intern) 4-MHz oscillator 0 RC-oscillator 1 (intern) 32-kHz oscillator
Clock Source for SUBCL CCS = 1 CCS = 0
32 kHz
The clock module generates two output clocks. One is the system clock (SYSCL) and the other the periphery clock (SUBCL). The SYSCL can supply the core and the peripherals and the SUBCL can supply only the peripherals with clocks. The modes for clock sources are programmable with the OS1-bit and OS0-bit in the SC-
register and the CCS-bit in the CM-register.
12 (44)
Preliminary Information
TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97
M44C588
1.5.2 Oscillator Circuits and External Clock Input Stage
configuration, the RC-oscillator 2 frequency can be maintained stable to within a tolerance of 10% over the full operating temperature and voltage range. For example: An SYSCLmax frequency of 2 MHz, can be obtained by connecting a resistor Rext = 136 kW (see figures 13 and 47). The M44C588 clock system consists of four different internal oscillators: two RC-oscillators, one 4-MHz crystal oscillator, one 32-kHz crystal oscillator and an external clock input stage.
RC-Oscillator 1 Fully Integrated
For timing insensitive applications, it is possible to use the fully integrated RC oscillator 1. It operates without any external components and saves additional costs. The RC-oscillator 1 center frequency tolerance is better than 25% over the full temperature and voltage range. The frequency tolerance is better than 10% for a given voltage and temperature (see diagram ). The basic center frequency of the RC-oscillator 1 is programmable with the RC1- and the RC0-bit in the SC register (see page 15).
VDD Rext SCLIN RC oscillator 2 RcOut2 RTrim Stop RcOut2 Osc-Stop
13377
Figure 13. RC-oscillator 2
RC oscillator 1 RcOut1 RC0 Stop Control RcOut1 Osc-Stop
4-MHz Oscillator
The integrated system clock oscillator expects a crystal or ceramic resonator connected to the OSCIN and OSCOUT pins to establish oscillation. All the necessary oscillator circuitry, with the exception of the actual crystal, resonator and the optional C3 and C4 are integrated onchip.
C3 OSCIN Oscin XTAL Cer. Res 4Out 4-MHz oscillator C1 Oscout Stop * * C2 4Out
RC1
13375
Figure 11. RC-oscillator 1
External Input Clock
The SCLIN pin can be driven by an external clock source provided it meets the specified input levels, duty cycle, rise and fall times. The maximum system clock SYSCmax the core operates will therefore be SCLIN/2 (see figure 10).
Osc-Stop
C4 OSCOUT * mask option
Ext. input clock Ext. Clock SCLIN ExIn Stop ExOut
ExOut Osc-Stop
13379
Figure 14. System clock oscillator
13376
32-kHz Oscillator
Some applications require long-term time keeping or low resolution timing. In this case, an on-chip, low power 32-kHz crystal oscillator can be used to generate both the SUBCL and/or the SYSCL. In this mode, power consumption is greatly reduced. The 32-kHz crystal oscillator is still operating (not stopped) during any power-down/SLEEP mode.
Figure 12. External input clock
RC-Oscillator 2 with External Trimming Resistor
The RC-oscillator 2 is a high resolution oscillator whereby the oscillator frequency can be trimmed with an external resistor between SCLIN and VDD. In this TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97
13 (44)
Preliminary Information
M44C588
OSCIN Oscin * XTAL 32 kHz OSCOUT * C2 mask option 13380 C1 * 32Out 32-kHz oscillator Oscout 32Out
Figure 15. 32-kHz crystal oscillator
1.5.3
Clock Management Register (CM)
The clock management register (CM) controls the system clock divider chain, as well as the peripheral clock in the power-down modes. Auxiliary register address: 'E'hex
AAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA AAAAA AAAA AAAAAAAAA A A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAA
CM: Reset value: 1111b NSTOP CCS CSS[1:0] Not STOP peripheral clock NSTOP = 0, stops the peripheral clock (SUBCL) during the core is in SLEEP mode, with the exception of the 32-kHz crystal oscillator SUBCL clock. NSTOP = 1, enables the peripheral clock (SUBCL) during the core in SLEEP mode Core Clock Select CCS = 1, the internal RC-oscillator 1 generates SYSCL CCS = 0, the 4-MHz crystal oscillator, the 32-kHz crystal oscillator, an external clock source or the RC-oscillator 2 (with the external resistor) will generate SYSCL dependent on the setting of OS0 and OS1 in the system configuration register Core Speed Select These two bits control the system clock divider chain Auxiliary register address: 'E'hex CSS1 0 0 1 1 CSS0 0 1 0 1 Divider 16 8 4 2 Note SYSCLmax/8 SYSCLmax/4 SYSCLmax/2 Reset value = SYSCLmax 14 (44)
Bit 3 NSTOP
Bit 2 CCS
Bit 1 CSS1
Bit 0 CSS0
Preliminary Information
TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97
M44C588
System Configuration Register (SC)
Primary register address: 'E'hex Bit 3 RC1 Bit 2 RC0 Bit 1 OS1 Bit 0 OS0
AA A A AAAA AA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAA A AAAAA A A AA AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA A A A A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAA
SC: write Reset value: 1111b RC1, RC0 Internal RC oscillator 1 frequency select (SYSCLmax) RC1 0 0 1 1 RC0 0 1 0 1 SYSCLmax @ 25C, VDD = 5 V 7.5 MHz 3.2 MHz 2.0 MHz 0.8 MHz Note Reset value OS1, OS0 Oscillator selection bits (in conjunction with the CCS-bit) CCS 0 0 0 0 1 OS1 1 0 1 0 x OS0 1 1 0 0 x SUBCL SYSCLmax/64 32 kHz SYSCLmax/64 or 32 kHz System Oscillator Selection External input clock at SCLIN RC-oscillator 2 with Rext 4-MHz crystal oscillator 32-kHz crystal oscillator RC-oscillator 1 If CCS = 0 in the CM-register, the RC-oscillator 1 is stopped.
1.5.4
Power-down Modes
expected average system current consumption, the following formula should be used: Itotal (VDD,fsyscl) = ISleep + (IDD IDD depends on VDD and fsyscl. The M44C588 has various power-down modes. During the sleep mode the clock for the MARC4 core is stopped. With the NSTOP-bit in the clock management register (CM) it is programmable if the clock for the on-chip peripherals is active or stopped during the sleep mode. If the clock for the core and the peripherals is stopped the selected oscillator is switched off. An exception is the 32-kHz oscillator, if it is selected it runs continously independent on the NSTOP-bit. If the oscillator is stopped or the 32 kHz oscillator is selected, power consumption is extremely reduced. Tactive / Ttotal)
The sleep mode is a shut-down condition which is used to reduce the average system power consumption in applications where the C is not fully utilized. In this mode, the system clock is stopped. During the sleep mode the peripheral modules remain active and are able to generate interrupts. The C exits the sleep mode by carrying out any interrupt or a reset condition. The sleep mode can only be kept when none of the interrupt pending or active register bits are set. The application of the $AUTOSLEEP routine ensures the correct function of the sleep mode. The total power consumption is directly proportional to the active time of the C. For a rough estimation of the
Table 5. Power-down modes
Mode
CPU Core
NSTOP
AAAAAAA A A AAA AAAAAAA A A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA A AAA
Active Power-down SLEEP RUN SLEEP SLEEP 1 1 0 RUN RUN RUN Enabled Enabled Disabled TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97 15 (44)
RC-Oscillator 1 RC-Oscillator 2 4-MHz Oscillator RUN RUN STOP
32-kHz Oscillator
External Input Clock at SCLIN
Preliminary Information
M44C588
1.5.5
NRST TE SYSCL clocks BP11 SUBCL clocks
Clock Monitor Mode
BP10
13387
Oscillator supervisory mode
Normal operation
Figure 16. Clock monitoring
For trimming purposes, the M44C588 can be put into a clock monitor mode. The test input (TE) has to be forced high, whereupon the SYSCL clock will appear on BP11 (Port 1, bit 1) and SUBCL clock on Port BP10 (Port 1, bit 0). To put BP10 and BP11 back into normal operation, the TE-pin has to be released again (see figure 17).
2
2.1
Peripheral Modules
Addressing Peripherals
Accessing the peripheral modules takes place via the I/O bus (see figure 12). The IN or OUT instructions allow direct addressing of up to 16 I/O modules. A dual register
addressing scheme has been adopted, with direct addressing of the "primary register". To address the "auxiliary register" the access must be switched with an "auxiliary switching module". Thus a single IN (or OUT) to the module address will read (or write) into the module primary register. Accessing the auxiliary register is performed with the same instruction preceded by writing the module address into the auxiliary switching module. Byte wide registers are access by multiple IN (or OUT) instructions. For more complex peripheral modules, with a larger number of registers, extended addressing is used. In this case a bank of up to 16 subport registers are indirectly addressed with the subport address being initially written into the auxiliary register.
16 (44)
Preliminary Information
TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97
M44C588
Module ASW Module M1
(Address Pointer) Aux. Reg. Bank of Primary Regs. Subport Fh Subport Eh Aux. Reg. 6
Module M2
Module M3
2 Auxiliary Switch Module
Subport 1 Primary Reg. Subport 0 3 1 5 Primary Reg. 4
7
Primary Reg.
I/O bus
to other modules
Indirect Subport Access (Subport Register Write)
1 2
Dual Register Access (Primary Register Write)
4
Single Register Access (Primary Register Write)
7
Addr.(M1) SPort_Data
Addr.(ASW) OUT OUT OUT Addr.(M1)
Prim._Data
Address(M2) OUT
Prim._Data Address(M3) OUT
Addr.(SPort) Addr.(M1)
3
( Auxiliary Register Write ) 5 6 Address(M2) Address(ASW) OUT Aux._Data Address(M2) OUT 7 (Prima ry Register Read) Address(M3) IN
(Subport Register Read) 1 2 3 Addr.(M1) Addr.(ASW) OUT OUT IN
Addr.(SPort) Addr.(M1) Addr.(M1)
(Primary Register Read) 4 Address(M2) (Auxiliary Register Rea d) IN
Example of qFORTH Program Code
(Subport Register Write Byte) 1
2 3
Addr.(M1)
Addr.(ASW) OUT OUT
5
Addr.(SPort) Addr.(M1)
SPort_Data(lo) Addr.(M1) OUT SPort_Data(hi) Addr.(M1) OUT (Subport Register Rea d Byte)
6
Address(M2) Address(ASW) OUT Address(M 2) IN (Auxiliary Register Write Byte)
3
5 6 6
Address(M2) Address(ASW) OUT Aux._Data(lo) Address(M2) OUT Aux._Data(hi) Address(M2) OUT Addr.(ASW) = Auxiliary Switch Module Address Addr.(Mx) = Module Mx Addr ess Addr.(SPort) = Subport Address Prim._Data = data to be written into Primary Register. Aux._Data = data to be written into Auxiliary Register Aux._Data (lo)= data to be written into Auxiliary Register (low nibble) Aux._Data (hi) = da ta to be written into Auxiliary Register(high nibble) SPort_Data(lo) = data to be written into SubP ort (low nibble) SPort_Data(hi) = data to be written into Subport (high nibble)
1 2 3
3
Addr.(M1)
Addr.(ASW) OUT OUT IN IN Addr.(M1) Addr.(M1)
Addr.(SPort) Addr.(M1)
(Auxiliary Register Rea d)
1 2
Address(M1) Address(ASW) OUT Address(M1) IN
Figure 17. Example of I/O addressing
TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97
17 (44)
Preliminary Information
AAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAAAAAAAAA A A AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAAAAAAAAA A A AAAAA AAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAA A A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA A A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAA A AA
Table 6. M44C588 peripheral addresses
M44C588
18 (44) 8 9 7 5 6 4 3 0 1 2
TCM subport addresses 0 1 2 3 4 5 6 7 8
Aux. SSI subport addresses 0
Address
Aux.
Aux.
Aux.
Aux.
Aux
A B
9
1 2 3 4 5 6 7 8
T0MO T0CR T1MO T1CR TCMO TCIO TCCR TCIP T0CP1 T0CA T1CP1 T1CA T0CP2 T1CP2
SISR SIMO SICC SICR P6IOR BZCR P6IPR IRXCR IRYCR RxBUF TxBUF ASW TCM T0SR TCX
P0DAT P1DAT LCD LCR SC CWD CM P4DAT P4DDR - P6DAT P6DDR SSI SIX
Name
Preliminary Information
Write /Read W/R W/R W/R W W R W/R W/R W - W/R W W/R W R W W W W W W W W R W W W/R R W W W W W W W W W W R W R W W
Timer 0 mode register Timer 0 control register Timer 1 mode register Timer 1 control register Timer/counter mode register Timer/counter I/O control register Timer/counter clock control register Timer/counter interrupt priority Timer 0 compare register 1 (byte) Timer 0 capture register (byte) Timer 1 compare register 1 (byte) Timer 1 capture register (byte) Timer 0 compare register 2 (byte) Timer 1 compare register 2 (Byte) Function
Serial interface status register Serial interface mode register Serial interface clock control register Serial interface control register Port 6 (SSI/buzzer) I/O control register Buzzer control register Port 6 (INTX/INTY) interrupt priority register External interrupt X source select External interrupt Y source select Receive buffer (byte) Transmit buffer (byte) Auxiliary Switch register Data to/from subport addressed by TCX Timer 0 interrupt status register Timer/counter subport address pointer
Port 0 - data register/input data Port 1 - data register/input data LCD segment data shadow register port LCD control register System configuration register Watchdog timer reset Clock management register Port 4 - data register/pin data Port 4 - data direction register Reserved Port 6 - data register/pin data Port 6 - data direction register Data to/from subport addressed by SIX Serial interface subport address register
TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97
AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAA
Table 7. Port Data Direction Register (PxDDR)
AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AA A
Value: 1111b means all pins in input mode Port Data Direction Register (PxDDR) All bidirectional ports 0, 1, 4, 6 and B are 4-bits wide. All these ports may be used for data input or output. All inputs are equipped with Schmitt-trigger inputs together with a variety of mask options for open drain, open source, full complementary outputs as well as different kinds of Port Data Register (PxDAT) PxDDR PxDAT * Bit 3 MSB, bit 0 LSB PxDAT3 PxDDR3 Bit 3* Bit 3 PxDAT2 PxDDR2 Bit 2 Bit 2 PxDAT1 PxDDR1 Bit 1 Bit 1 PxDAT0 PxDDR0 Bit 0 Bit 0 Auxiliary register address: 'Port address'hex Primary register address: 'Port address'hex Reset value: 1111b Reset value: 1111b
AAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAA A AA
2.2
C D E A B F
TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97 Code 3210 xxx1 xxx0 xx1x xx0x x1xx x0xx 1xxx 0xxx Address BPx0 input mode BPx0 output mode BPx1 input mode BPx1 output mode BPx2 input mode BPx2 output mode BPx3 input mode BPx3 output mode Aux. Aux. Aux. Aux. C D E F
Bidirectional Ports
T0ICR T1ICR P4ICR P4IOR PBIPR PBICR PBDAT PBDDR - RBR PRAM PRADR ITFSR ITIPR
Name
Preliminary Information
Write /Read W W W W W W W/R W - W W/R W W W Timer 0 interrupt source control register Timer 1 interrupt source control register Port 4 external interrupt control register Port 4 (T0/T1) I/O control register Port B - interrupt priority register Port B - interrupt control register Port B - data register/pin data Port B - data direction register Reserved Rom bank switch register 256 x 4-bit peripheral RAM data access port Peripheral RAM address pointer register (Byte) Interval timer frequency select register Interval timer interrupt priority register pull-up and pull-down transistors. The optional pull-up/ pull-down transistors are only active when the port is in input mode. All Port Data Registers (PxDAT) are I/O mapped to the primary address register of the respective port address and the Port Data Direction Register (PxDDR) to the corresponding auxiliary register. Function Function
M44C588
19 (44)
M44C588
There are four different types of bidirectional ports:
D Type 1 (Ports 0 and 1) - 4-bit wide bidirectional ports
with automatic full bus width direction switching.
D Type 2 (Port B) - 4-bit wide bitwise programmable
bidirectional port with static pull-ups/ -downs.
the port pin following the OUT instruction. After RESET all output latches are set to '1' and the ports are switched to input mode. An IN instruction reads the condition of the associated pins. Note Care must be taken when switching these bidirectional ports from output to input. The capacitive pin loading at this port in conjunction with the high resistance pull-up may cause the CPU to read the contents of the output data register rather than the external input state. To avoid this, one should use either of the following programming techniques:
D Type 3 (Port 6) - 4-bit wide bitwise programmable
bidirectional port with static pull-ups/ -downs and versatile interrupt control logic.
D Type 4 (Port 4) - 4-bit wide bitwise programmable
bidirectional port also provides the I/O interface for Timer 0 and Timer 1.
D Use two IN instructions and DROP the first data
2.2.1 Bidirectional Port 0 and Port 1
In this port type, the data direction register is not independently software programmable, the direction of the complete port being switched automatically when an I/O instruction occurs (see figure 18). The port is switched to output mode with an OUT instruction and to input with an IN instruction. The data written to a port will be stored into the output data latches and appears immediately at nibble. The first IN switches the port from output to input and the DROP removes the first invalid nibble. The second IN reads the valid pin state.
D Use an OUT instruction followed by an IN instruction.
With the OUT instruction the capacitive load is charged or discharged depending on the optional pull-up /pull-down configuration. Write a "1" for pins with pull-up resistors and a "0" for pins with pulldown resistors.
VDD
I/O Bus
*
VDD (Data out) D Q
*
Pull-up
PxDATy R Reset (Direction) OUT S IN R Master reset NQ Q
BPxy * *
*) Mask options Port 1 only Pull-down
96 11523
Figure 18. Bidirectional Ports 0 and 1
20 (44)
Preliminary Information
TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97
M44C588
2.3 Bidirectional Port B
I/O Bus V DD Pull-up V DD Static pull-up
*
VDD (Data out) I/O Bus D Q PBDATy S Master reset I/O Bus S Q D PBDDRy
*
* BPBy *
V DD
*
Pull-down
*
Static pull-down
(Direction)
* Mask options Figure 19. Bidirectional Port B
14010
Port B includes a bitwise programmable Data Direction Register (PBDDR), which allows the individual programming of each port bit as input or output. It also opens up the possibility of reading the pin condition when in output mode. This is a useful feature for self testing and for data bus applications.
driven port scanning without the power consuming task of continuously polling the port inputs. Using the Port Interrupt Control Register (PBICR), each pin can be selected individually. A non-selected pin cannot generate an interrupt. The Port Interrupt Priority Register (PBIPR) allows masking of each interrupt, definition of the interrupt generating signal transition and programming of the interrupt priority level. The Port Interrupt Priority Registers PBIPR is I/O mapped to the primary address registers of the Port Monitor Module addresse 'A'h. The Port Interrupt Control Registers PBICR is mapped to the corresponding auxiliary register.
2.3.1
Port Monitor Module
In addition to the standard I/O functions, Port B (BPB3 - BPB0) is equipped with port monitor module. This module is connected across all four port pins (see figure 20) and generates an interrupt should a preprogrammed transition occur on any of the pins. This allows interrupt
Connected to Port B
PRB1 PRB2
PBICR ENB3 ENB2 ENB1 ENB0
PBIPR
IMB
ITRB
PRB1
PRB2
Decoder
BPB3 BPB2 BPB1 BPB0 INT7 INT5 INT3 INT1
0 0 1 1
0 1 0 1
INT7 INT5 INT3 INT1
96 115
Figure 20. Port B monitor input module
TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97
21 (44)
Preliminary Information
AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA
Bit 0 can generate an interrupt Bit 0 cannot generate an interrupt Bit 1 can generate an interrupt Bit 1 cannot generate an interrupt Bit 2 can generate an interrupt Bit 2 cannot generate an interrupt Bit 3 can generate an interrupt Bit 3 cannot generate an interrupt Function
AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA A A A A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA
Port B Monitor Interrupt Control Register (PBICR)
Table 8. Port B Monitor Interrupt Priority Register (PBIPR)
AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AA A
IMB Port B Monitor Interrupt Priority Register (PBIPR)
Table 9. Port B Monitor Interrupt Control Register (PBICR)
ENB3 ... 0 Port B monitor input ENable code
PRB2..1 - Interrupt Priority code
ITRB
M44C588
22 (44) PBICR PBIPR Code 3210 xxx0 xxx1 xx0x xx1x x0xx x1xx 0xxx 1xxx Code 3210 xx00 xx01 xx10 xx11 x1xx x0xx 0xxx 1xxx - Interrupt Transition - Interrupt Mask Port monitor interrupt priority 7 Port monitor interrupt priority 5 Port monitor interrupt priority 3 Port monitor interrupt priority 1 Port monitor interrupt on rising edge Port monitor interrupt on falling edge Port monitor interrupt enabled Port monitor interrupt masked ENB3 IMB Bit 3 Bit 3 ENB2 ITRB Bit 2 Bit 2 PRB2 ENB1 Bit 1 Bit 1 Function PRB1 ENB0 Bit 0 Bit 0
Preliminary Information
TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97 Auxiliary register address: 'A'hex Primary register address: 'A'hex Reset value: 1111b Reset value: 1111b
M44C588
2.4 Bidirectional Port 6
This 4-bit bidirectional port can be used as bitwise programmable I/O. The port pins can also be used as external interrupt inputs (see figures 21 and 22). Both interrupts can be masked or independently configured to trigger on either edge. The interrupt priority levels are also programmable. The interrupt configuration is controlled by the Port 6 Interrupt Priority Register (P6IPR), the External Interrupt X Source Select Register (IRXCR) and the External Interrupt Y Source Register (IRYCR). The port direction is controlled by the Port 6 Data Direction Register (P6DDR) An additional low resistance pull-up transistor provides an internal static pull-up for serial bus applications (mask option). In output mode (P6DDR bit = 0), the respective Port Data Register (P6DAT) bit will appear on the port pin, driven by an output port driver stage which can be mask programmed as open drain, or full complementary CMOS. With an IN instruction the actual pin state can be read back at any time into the controller without changing the port directional mode. So, for example should the output port be mask configured as an open drain driver, as long as the output transistor is off, the controller is able to receive external data on this pin without switching into input mode. In input mode (P6DDR bit = 1), the output driver stage is deactivated, so that an IN instruction will directly read the pin state which can be driven from an external source. In this case the state of the Port Data Register (P6DAT), although not appearing at the pin itself remains unchanged. High resistance mask selectable pull-up or pull-down transistors are automatically switched onto the port pin in input mode. The Port Data Register is written with an OUT instruction to the respective port address. The Port 6 Data Register (P6DAT) is I/O mapped to the primary address register of address '6'hex and the Port 6 Control Register (P6CR) to the corresponding auxiliary register. The Interrupt Priority Register (P6IPR) and the External Interrupt X/Y Priority Registers IRXCR and IRYCR) are indirectly addressed by using extended addressing mode as descibed in section "Addressing Peripherals" and I/O mapped to the Port 7 subport register addresses '5'hex, '6'hex and '7'hex (see table 6).
V I/O Bus V
DD Pull-up
DD Static pull-up
*
VDD (Data out) I/O Bus D Q P6DATy S Master reset IN enable
*
* BP6y *
V DD
*
Pull-down
*
Static pull-down
14011
* Mask options Figure 21. Bidirectional Port 6
TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97
23 (44)
Preliminary Information
M44C588
IRYCR 0 1 2 3 decode decode
INT6 INT4 INT2 INT0 INT7 INT5 INT3 INT1
INTY
BP60 BP61 BP62 BP63
Mask Mask
Edge Edge
BP60 BP61 INTX BP62 BP63
decode P6ICR 3 2
decode 1 0
decode 0 1
decode 2 3 IRXCR
P6ICR 3 2 INTY INT6 INT4 INT2 INT0 1 0 INTX INT7 INT5 INT3 INT1
IRXCR 0 0 1 1 0 1 0 1 3 0 1 0 1 2 0 0 1 1
INT source
IRYCR 1 0 0 1 1 0 0 1 0 1
INT edge INT masked
0 0 1 1
0 1 0 1
BP60 BP61 BP62 BP63
- -
yes no no yes
96 1152
Figure 22. Port 6 external interrupts
Port 6 Interrupt Priority Register (P6IPR) Auxiliary register address: '5'hex
AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA
AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA A A A A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AA A
Bit 3 Bit 2 Bit 1 Bit 0 P6IPR PRY2 PRY1 PRX2 PRX1 Reset value: 1111b PRY2, PRY1 - Interrupt Y priority code PRX2, PRX1 - Interrupt X priority code
Table 10.Port 6 interrupt priority register (P6IPR)
Code 3210 xx11 xx10 xx01 xx00 11xx 10xx 01xx 00xx
Function Interrupt X = priority 1 Interrupt X = priority 3 Interrupt X = priority 5 Interrupt X = priority 7 Interrupt Y = priority 0 Interrupt Y = priority 2 Interrupt Y = priority 4 Interrupt Y = priority 6
24 (44)
Preliminary Information
TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97
AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAA
Table 12.Interrupt Y control register (IRYCR)
AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A
Table 11.Interrupt X control register (IRXCR)
AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AA A
ISX2, ISX1 Interrupt X Control Register (IRXCR) IRXCR - Interrupt X source code ISX2 Bit 3 ISX1 Bit 2 ITRX Bit 1 IMX Bit 0 Auxiliary register address: '6'hex
TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97 IMY ITRY ISY2, ISY1 IMX ITRX IRYCR Code 3210 xxx0 xxx1 xx0x xx1x 11xx 01xx 10xx 00xx Code 3210 xxx0 xxx1 xx0x xx1x 11xx 01xx 10xx 00xx - Interrupt Y mask - Interrupt X mask ISY2 Bit 3
Interrupt Y Control Register (IRYCR)
Interrupt Y enabled Interrupt Y masked Interrupt Y = rising edge Interrupt Y = falling edge Interrupt source = BP63 Interrupt source = BP62 Interrupt source = BP61 Interrupt source = BP60
Interrupt X enabled Interrupt X masked Interrupt X = rising edge Interrupt X = falling edge Interrupt source = BP63 Interrupt source = BP62 Interrupt source = BP61 Interrupt source = BP60
- Interrupt Y transition
- Interrupt Y source code
- Interrupt X transition
Preliminary Information
ISY1 Bit 2 ITRY Bit 1 Function Function IMY Bit 0 Auxiliary register address: '7'hex
M44C588
Reset value: 1111b
Reset value: 1111b
25 (44)
M44C588
2.5 Bidirectional Port 4
V I/O Bus TIn TOut I/O Bus D S Master reset I/O Bus D (Direction) S Q Q P4DATy (Data out) TCIOy VDD DD Pull-up V DD Static pull-up
*
*
* BP4y *
V DD
*
Pull-down
*
Static pull-down
14012
P4DATy TDir
* Mask options Figure 23. Bidirectional Port 4
The bidirectional Port 4 is both a bitwise configurable I/O port and provides the external pins for both the Timer 0 and the Timer 1. As a normal port, it performs in exactly the same way as bidirectional port type 2 (see figure 14). Two additional multiplexers allow data and port direction control to be passed over to other internal modules (Timer 0 or Timer 1). Each of the four Port 4 pins can be individually switched by the Timer/Counter I/O Register (TCIO). Figure 23 shows the internal interfaces to Port 4.
Frequency Select Register (ITFSR). Buffer registers store the respective frequency select codes and ensure complete programming independence of each interrupt channel. Interrupt masking and programming of the interrupt priority levels is performed with the aid of the Interval Timer Interrupt Priority Register (ITIPR).
2.6.1
Interval Timer Registers
2.6
Interval Timers / Prescaler
The interval timers are based on a frequency divider for generating two independent time base interrupts. It is driven by SUBCL generated by the clock module (see figure 10) and consists of a 15-stage binary divider and two programmable multiplexers for selecting the appropriate interrupt frequencies for each interrupt source (see figure 24). Each multiplexer is completely independent and is controlled by the common Interval Timer
The Interval Timer Frequency Select Register (ITFSR) is I/O mapped to the primary address register of the prescaler/ interval timer address ('F'hex) and the Interval Timer Interrupt Priority Register (ITIPR) to the corresponding auxiliary register. The interrupt masks MIA and MIB enable interrupt masking of INTA and INTB respectively. Each interrupt source can be programmed with PRA and PRB to one of two interrupt priority levels. Disabling both interrupts resets the interval timer and it's divider chain.
26 (44)
Preliminary Information
TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97
M44C588
Interval Timer Interrupt Priority Register (ITIPR)
AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA
AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AA A
Bit 3 Bit 2 Bit 1 Bit 0 ITIPR PRB PRA MIB MIA Reset value: 1111b PRB - Priority select Interval Timer Interrupt INTB PRA - Priority select Interval Timer Interrupt INTA MIB - Mask Interval Timer Interrupt INTB MIA - Mask Interval Timer Interrupt INTA
Table 13.Interval Timer Interrupt Priority Register (ITIPR)
Auxiliary register address (write only): 'F'hex
Code 3210 xxx1 xxx0 xx1x xx0x x1xx x0xx 1xxx 0xxx xx11
Function Mask interrupt A Enable interrupt A Mask interrupt B Enable interrupt B Interrupt A => priority 1 Interrupt A => priority 5 Interrupt B => priority 2 Interrupt B => priority 6 Reset prescaler and halt
ITIPR
PRB
PRA
MIB
MIA
ITFSR
FS3
FS2
FS1
FS0
INT5 INT1
Buffer Buffer
INT6 INT2
Fh Eh Dh INTB Ch 8:1 Bh Mux Ah 9h 8h
8092Hz 2048Hz 4096Hz
8192Hz 4096Hz 2048Hz 1024Hz 256Hz 64Hz 16Hz 8Hz 128Hz
7h 6h 5h INTA 4h 8:1 3h Mux 2h 1h 0h
32Hz 8Hz 16Hz 4Hz
128Hz 64Hz 32Hz 16Hz 8Hz 4Hz 2Hz 1Hz 2Hz 1Hz
1024Hz 256Hz
64Hz
R SUBCL
CK
2 2 2 3 2 4 2 5 2 6 27 2 8 29 210 2 11 212 213 214 2 15
15-stage binary counter Figure 24. Interval timers / prescaler
96 11530
(e.g. SUBCL = 32 kHz)
TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97
27 (44)
Preliminary Information
M44C588
Interval Timer Frequency Select Register (ITFSR)
AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AA A
Bit 3 FS3 Bit 2 FS2 Bit 1 FS1 Bit 0 FS0 ITFSR Reset value: 1111b FS3 ... 0 - Frequency select code
Table 14.Interval Timer Frequency Select Register (ITFSR)
Primary register address (write only): 'F'hex
AAAAAAA A A AA A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAA AAAAAAA A A AA AAAAAAA A A AA A A AAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAA AAAAAAA A A AA A A A AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A AA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AAA
INTA INTB The control bit FS3 determines whether the INTA or the INTB buffer register is loaded with the select code (FS2-FS0). This allows independent programming of interval times for INTA and INTB.
Code 3210 0000 0001 0010 0011 0100 0101 0110 0111
Function
SUBCL divide by 215 214 213 212 211 210 29 28
SUBCL = 32 kHz Select 1 Hz Select 2 Hz Select 4 Hz Select 8 Hz Select 16 Hz Select 32 Hz Select 64 Hz Select 128 Hz
Code 3210 1000 1001 1010 1011 1100 1101 1110 1111
Function
SUBCL divide by 212 211 29 27 25 24 23 22
SUBCL = 32 kHz Select 8 Hz Select 16 Hz Select 64 Hz Select 256 Hz Select 1024 Hz Select 2048 Hz Select 4096 Hz Select 8192 Hz
2.7
Watchdog Timer
NRST

CK R R R R
2
14

2
15

2
16
*
17-stage binary counter
R R R R R R R R R R
*
R R R
*
SUBCL Read WDRES Master Reset
*
Watchdog enable
VDD Figure 25. Watchdog timer
* Mask option
96 11531
The watchdog timer is a 17-stage binary divider clocked by SUBCL generated within the clock module (see figures 10 and 25). It can only be enabled as a mask option whereby it must be periodically reset from the application program. The program cannot disable the watchdog. If the CPU find itself for an extended length of time in SLEEP mode or in a section of program that includes no watchdog reset, then the watchdog will overflow, thus
forcing the NRST pin low. This initiates a master reset. The timeout period can be set to 0.5, 1 or 2 seconds (if SUBCL = 32 kHz) by using a mask option. To reset the watchdog, the program must perform an IN instruction on the address CWD ('3'hex). No relevant data is received. The operation is therefore normally followed by a DROP to flush the data from the stack.
28 (44)
Preliminary Information
TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97
M44C588
2.8 Timer/ Counter Registers
All timer/ counter registers are indirectly addressed using extended addressing as described in section `Addresing Perpherals`. An overview of all register and subport addresses is shown in table 6. The Timer/ Counter auxiliary register (TCX) holds the subport address of the particular register to be accessed. Timer 0 Interrupt Status Register (T0SR)
AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA
AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AA A
Bit 3 Bit 2 Bit 1 Bit 0 T0SR T0EOM T0OFL T0CMP2 T0CMP1 Reset value: 0000b Note: The Timer 0 status register is reset automatically when read and also when Timer 0 is reset. T0CMP1, T0CMP2 - Timer 0 compare 1/ compare 2 interrupt status flag T0OFL - Timer 0 overflow status flag T0EOM - Timer 0 end of measurement status flag
Table 15.Timer 0 interrupt status register (T0SR)
Subport address (read access): '0'hex
Code 3210 0000 xxx1 xx1x x1xx 1xxx
Function No interrupt Timer 0 compare 1 interrupt event (Timer 0 = T0CP1) Timer 0 compare 2 interrupt event (Timer 0 = T0CP2) or external interrupt on BP40 Timer 0 overflow/ underflow interrupt or external interrupt on BP41 Timer 0 measurement completed
Timer 1 Interrupt Status Register (T1SR)
Subport address (read access): '1'hex
AAAAAAAAAAAA A A A A A AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A
Bit 3 Bit 2 Bit 1 Bit 0 T1SR T1EOM T1OFL T1CMP2 T1CMP1 Reset value: 0000b Note: The Timer 1 status register is reset automatically when read and also when Timer 1 is reset. T1CMP1, T1CMP2 - Timer 1 compare 1/ compare 2 interrupt status flag T1OFL - Timer 1 overflow status flag T1EOM - Timer 1 end of measurement status flag
Table 16.Timer 0 interrupt status register (T0SR)
Code 3210 0000 xxx1 xx1x x1xx 1xxx
Function No interrupt Timer 1 compare 1 interrupt event (Timer 1 = T1CP1) Timer 1 compare 2 interrupt event (Timer 1 = T1CP2) or external interrupt on BP42 Timer 1 overflow/ underflow interrupt or external interrupt on BP43 Timer 1 measurement completed
For both interrupt status registers (T0SR and T1SR) the interrupt flag will be set whenever the assiciated condition occurs irrespective of whether the corresponding interrupt is triggered. So, when the interrupt is masked the status flags will still be set if the interrupt condition occurs. To see exactly when the flags are set, see T0MO and T1MO control tables. 29 (44)
TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97
Preliminary Information
M44C588
Timer 0 Compare Register 1 (T0CP1)
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAA A
Bit 3 Bit 7 Bit 2 Bit 6 Bit 1 Bit 5 Bit 0 Bit 4 T0CP1 First write cycle T0CP13 T0CP17 T0CP12 T0CP16 T0CP11 T0CP10 T0CP14 Reset value: xxxxb Reset value: xxxxb Second write cycle T0CP15 T0CP13 ... T0CP10 - Timer 0 compare register 1 data (low nibble) - first write cycle T0CP17 ... T0CP14 - Timer 0 compare register 1 data (high nibble) - second write cycle Timer/ Counter Compare Register (T0CP1) Subport address: `8`hex Timer/ counter subport pointer (TCX) address: `9`hex Timer 0 Compare Register 2 (T0CP2) Subport address (write access): 'A'hex
Subport address (write access): '8'hex
AAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAA AAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAA A
Bit 3 Bit 7 Bit 2 Bit 6 Bit 1 Bit 5 Bit 0 Bit 4 T0CP2 First write cycle T0CP23 T0CP22 T0CP21 T0CP25 T0CP20 T0CP24 Reset value: xxxxb Reset value: xxxxb Second write cycleAAAAT0CP26 T0CP27 T0CP23 ... T0CP20 - Timer 0 compare register 2 data (low nibble) - first write cycle T0CP27 ... T0CP24 - Timer 0 compare register 2 data (high nibble) - second write cycle Timer/ Counter Compare Register (T0CP2) Subport address: `A`hex Timer/ counter subport pointer (TCX) address: `9`hex Timer 1 Compare Register 1 (T1CP1) Subport address (write access): '9'hex
AAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A
Bit 3 Bit 7 Bit 2 Bit 6 Bit 1 Bit 5 Bit 0 Bit 4 T1CP1 First write cycle T1CP13 T1CP17 T1CP12 T1CP16 T1CP11 T1CP10 T1CP14 Reset value: xxxxb Reset value: xxxxb Second write cycle T1CP15 T1CP13 ... T1CP10 - Timer 0 compare register 1 data (low nibble) - first write cycle T1CP17 ... T1CP14 - Timer 0 compare register 1 data (high nibble) - second write cycle Timer/ Counter Compare Register (T1CP1) Subport address: `9`hex Timer/ counter subport pointer (TCX) address: `9`hex 30 (44)
Preliminary Information
TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97
M44C588
Timer 1 Compare Register 2 (T0CP2)
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAA A
Bit 3 Bit 7 Bit 2 Bit 6 Bit 1 Bit 5 Bit 0 Bit 4 T1CP2 First write cycle T1CP23 T1CP27 T1CP22 T1CP26 T1CP21 T1CP25 T1CP20 T1CP24 Reset value: xxxxb Reset value: xxxxb Second write cycle T1CP23 ... T1CP20 - Timer 1 compare register 2 data (low nibble) - first write cycle T1CP27 ... T1CP24 - Timer 1 compare register 2 data (high nibble) - second write cycle Timer/ Counter Compare Register (T1CP2) Subport address: `B`hex Timer/ counter subport pointer (TCX) address: `9`hex The compare registers (T0CP1, T0CP2, T1CP1 and T1CP2) are all 8-bit wide and must accessed as byte wide subports (see section `Addressing Peripherals`). They are writen low nibble first followed by the high nibble. Any time interrupts are suppressed automatically until the complete compare value has been transferred. Timer 0 Capture Register (T0CA)
Subport address (write access): 'B'hex
AAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAA A
Bit 3 Bit 7 Bit 2 Bit 6 Bit 1 Bit 5 Bit 0 Bit 4 T0CA Second read cycle First read cycle T0CA3 T0CA7 T0CA2 T0CA6 T0CA1 T0CA5 T0CA0 T0CA4 Reset value: 0000b Reset value: 0000b T0CA7. .. T0CA4 - Timer 0 capture register data (high nibble) - first read cycle T0CA3 ... T0CA0 - Timer 0 capture register data (low nibble) - second read cycle Timer/ Counter Compare Register (T0CP1) Subport address: `8`hex Timer/ counter subport pointer (TCX) address: `9`hex Timer 1 Capture Register (T1CA) Subport address (indirect read access): '9'hex Bit 0 Bit 4 T1CA0 T1CA4 Reset value: 0000b Reset value: 0000b Bit 3 Bit 7 Bit 2 Bit 6 Bit 1 Bit 5 T1CA Second read cycle First read cycle T1CA3 T1CA7 T1CA2 T1CA6 T1CA1 T1CA5 T1CA7 ... T1CA4 - Timer 1 Capture Register Data (high nibble) - first read cycle T1CA3 ... T1CA0 - Timer 1 Capture Register Data (low nibble) - second read cycle
Subport address (read access): '8'hex
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97 31 (44)
Timer/ Counter Compare Register (T0CP1) Subport address: `9`hex Timer/ counter subport pointer (TCX) address: `9`hex The 8-bit capture registers (T0CA and T1CA) are read as byte wide subports. Note, however, unlike the writing to the compare registers, the high nibble is read first followed by the low nibble. The 8-bit timer state is captured on reading the first nibble and held until the complete byte has been read. During this transfer the timer is free to continue counting.
Preliminary Information
M44C588
Port 4 I/O Control Register (P4IOR)
AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA
AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AA A
Bit 3 Bit 2 Bit 1 Bit 0 P4IOR P4IO3 P4IO2 P4IO1 P4IO0 Reset value: 0000b P4IO3...P4IO0 - Port 4 I/O select
Table 17.Port 4 I/O control register (P4IOR)
Subport address (write access): 'F'hex
Code 3210 xxx0 xxx1 xx0x xx1x x0xx x1xx 0xxx 1xxx
Function
BP40 - Timer 0 clock input (T0IN0) or Timer 0 output (T0OUT0) BP40 - standard port mode BP41 - Timer 0 gate input (T0IN1) or Timer 0 output (T0OUT1) BP41 - standard port mode BP42 - Timer 1 clock input (T1IN0) or Timer 1 output (T1OUT0) BP42 - standard port mode BP43 - Timer 1 gate input (T1IN1) or Timer 1 output (T1OUT1) BP43 - standard port mode
By using the Port 4 I/O control register (P4IOR) the program can configure the respective Port 4 pins as either standard data I/O ports or as external signal ports for the Timer 0 and Timer 1. It should be noted that if a P4IOR bit is set low, then the corresponding port data direction register (P4DDR) bit not longer influences the port direction. The port direction is then controlled by the corresponding Timer 0/1 mode of operation (T0MO, T1MO). Timer/ Counter Control Register (TCCR)
AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AA A
Bit 3 Bit 2 TC8 Bit 1 Bit 0 TCCR T0GS TCIO1 TCIO0 Reset value: 1111b TCIO1, TCIO0 TC8 T0GS - Timer/ counter mode select - Timer/ counter in 8-/ 16-bit mode - Timer 0 gate select
Table 18.Timer/ counter control register (TCCR)
Subport address (write access): '5'hex
Code 3210 xxx0 xxx1 xx0x xx1x x0xx x1xx 0xxx 1xxx
Function Non-inverted output BP41 appears on BP40 (BP40 = BP41) Inverted output BP41 appears on BP40 (BP40 = NOT BP41) Non-inverted output BP43 appears on BP42 (BP42 = BP43) Inverted output BP43 appears on BP42 (BP42 = NOT BP43) 16-bit mode 8-bit mode Timer 0 internal gated by Timer 1 Timer 0 external gated by Port 4
By using the Timer/ counter control register (TCCR) the program can configure the Port 4 pins. With the TCIO0/ TCIO1 bits the Port 4 can programmed as non-inverted or inverted outputs of Timer 0/ Timer 1. In 16-bit mode , Timer 0 and Timer 1 are cascaded thus forming a 16-bit counter (see figure ?? ) whereby irrespective of the state of Timer 0 interrupt mask bit (T0IM), the Timer 1 counts both Timer 0 overflow and compare interrupt events. These are generated according to the state of the Timer 0 mode register as described in the T0MO table. The comparators are also cascaded so that when both Timer 0 and Timer 1 match their respective compare registers, the Timer 1 generates both an output signal and a compare interrupt (if unmasked). 32 (44) TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97
Preliminary Information
AAAAAAAAAAAA A A A A A AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAA
Timer 1 Interrupt Source Control Register (T1ICR)
Table 20.Timer 0 interrupt source control register (T0ICR)
AAAAAAAAAAAA A A A A A AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA
Timer 0 Interrupt Source Control Register (T0ICR)
Table 19.Port 4 external interrupt control register (P4ICR)
AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AA A
ITR3...ITR0 - Interrupt transition on BP40...BP43 Port 4 External Interrupt Control Register (P4ICR) P4ICR ITR3 Bit 3 ITR2 Bit 2 ITR1 Bit 1 ITR0 Bit 0 Subport address (write access): 'E'hex
TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97 T0ICR T0ICR Code 3210 x111 xxx0 0x0x 00xx 1x0x 10xx Code 3210 xxx0 xxx1 xx0x xx1x x0xx x1xx 0xxx 1xxx ITR3 ITR3 Bit 3 Bit 3
ITR3...ITR0 - Interrupt transition on BP40...BP43
ITR3...ITR0 - Interrupt transition on BP40...BP43
No interrupt Compare 1 Compare 2 Overflow or end of measurement External interrupt on BP40/42 External interrupt on BP41/43
Falling edge on BP40 generates an interrupt Rising edge on BP40 generates an interrupt Falling edge on BP41 generates an interrupt Rising edge on BP41 generates an interrupt Falling edge on BP42 generates an interrupt Rising edge on BP42 generates an interrupt Falling edge on BP43 generates an interrupt Rising edge on BP43 generates an interrupt
Preliminary Information
ITR2 ITR2 Bit 2 Bit 2 ITR1 ITR1 Bit 1 Bit 1 Function Function ITR0 ITR0 Bit 0 Bit 0 Subport address (write access): 'D'hex Subport address (write access): 'C'hex
M44C588
Reset value: 1111b
Reset value: 1111b
Reset value: 1111b
33 (44)
AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAA
Table 22.Timer/ counter mode register (TCMO)
AAAAAAAAAAAA A A A A A A AA A AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA
Timer/ Counter Mode Register (TCMO)
Table 21.Timer 1 interrupt source control register (T1ICR)
T0RST T1RST T0N T1N
M44C588
34 (44) TCMO Code 3210 xxx0 xxx1 xx0x xx1x x0xx x1xx 0xxx 1xxx Code 3210 x111 xxx0 0x0x 00xx 1x0x 10xx - Timer 0 reset/ run - Timer 1 reset/ run - Timer 0 normal/ autostop -Timer 1 normal/ autostop Timer 0 running Timer 0 reset and halted Timer 1 running Timer 1 reset and halted Timer 0 autostop Timer 0 normal Timer 1 autostop Timer 1 normal No interrupt Compare 1 Compare 2 Overflow or end of measurement External interrupt on BP40/42 External interrupt on BP41/43 Bit 3 T1N Bit 2 T0N T1RST Bit 1 Function Function T0RST Bit 0
Preliminary Information
Subport address (write access): '4'hex
TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97 Reset value: 1111b
M44C588
3 Liquid Crystal Display Driver
D 16 segment drivers configurable by software as
bidirectional ports (2-bit wise) This chapter describes the function and the programming of the integrated LCD driver. It also includes
D Information about the relationship between a typical
7 segment display, the segment and backplane outputs (for 3:1 and 4:1 multiplex drive modes)
3.1
Display Data Register
D Waveform examples for the different LCD drive
modes Figure 26 is a functional block diagram of the LCD driver circuitry. The internal I/O bus is connected to the LCD control register (Port 2 auxiliary register) and the LCD data register (Port 2). The LCD driver circuitry offers the following features:
The LCD data register receives the data from the mC and writes the data in the shadow register addressed by the address pointer. After any write access the pointer is decremented and the next data can be written in the next data register. The data in the display buffer is displayed at the LCD. A logical 1 in the display buffer's bit-map indicates the ON state of the corresponding LCD segment. Similiarly a logical 0 indicates the OFF state. There is a 1:1 correspondence between each stage of the buffer register and the segment outputs, and between the individual bits of a buffer nibble and the backplane outputs. The LSB of each nibble corresponds to the 32 segments operated with respect of backplane COM0. In multiplexed LCD applications the segment data of the second, third and fourth column of the display buffer are time multiplexed with COM1, COM2 and COM3 respectively. The LCD specific segment decoding is done via qFORTH software routines, thus omitting the need for separate decoding circuitry.
D Drives up to 128 display segments D Supports 3 V or 5 V LCD panels over the full supply
voltage range
D Built-in LCD voltage generation with temperature
compensation (constant LCD contrast)
D Current consumption of LCD panel adaptable to display size
D Display continues when mC in SLEEP mode D Programmable multiplex rate (1/3 or 1/4 duty)
COM3
COM2
COM1
Display blanking
LCD drivers
Bit 3 Bit 2 Bit 1 Bit 0
SR31 SR30 SR29
COM0 Voltage and timing generator Frame frequency Prescaler LCD configuration register
S31
S30
S29
S03
S02
S01
S00
LCD display buffer
Port configuration
SR3 SR2 SR1 SR0
Bit 3 Bit 2 Bit 1 Bit 0
Power save
Shadow register Mux rate Address pointer
Display rotate Set address pointer LCD Control register
LCD Data port
Figure 26. LCD driver - functional block diagram
TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97
Preliminary Information
AA AA
I/O bus
SUBCL
14013
35 (44)
M44C588
3.2 Display Control Register
LCD Control Register (LCR) The LCD control register receives the operation mode at the Port 2 auxiliary register to configure the LCD driver circuitry. The control register also loads the LCD configuration register and port configuration register. The LCD control register is 4-bit wide. Only the upper 3 bits, if non-zero, are significant. If the upper 3 bits are zero the following 5 bits define the address loaded into the address pointer, that means 8 bits must be written.
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA
AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AA A
Bit 3 Bit 2 Bit 1 Bit 0 LCR LCR2 LCR1 LCR0 ADR4 Reset value: 1111b LCR2...LCR0 - LCD Control Register data ADR4 - Highest address bit if set address pointer
Table 23.LCD Control Register (LCR)
Auxiliary register address: '2'hex
Code 3210 1111 0011 0111 0101 1001 1011 1101 cccc pppp 000a aaaa
Function Powersave Load all segments Display rotate Display normal Blanking Clear/Init Setup LCD/ port configuration with two control nibble -1. LCD configuration register LCFR -2. LCD port configuration register LPCR Set LCD segment address pointer to binary address `aaaaa`
LCD Frequency Configuration Register (LFCR)
The LCD configuration register is loaded with the SET LCD/PORT CONFIGURATION term (see table 23). The first nibble following this term is loaded in the LCD frequency configuration register as described in table 24. Note, a second nibble must follow (see table 25). Primary register address: '2'hex
AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AA A
Bit 3 Bit 2 Bit 1 LFF Bit 0 LFCR LPF1 LPF0 LMR Reset value: 0000b LPF1...LPF0 LFF - LCD pump frequency - LCD frame frequency - LCD multiplex rate LMR 36 (44)
Preliminary Information
TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97
M44C588
Table 24. LCD Configuration Register (LCFR)
AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAA
LCD Port Configuration (LPCR) The LCD port configuration register is loaded with the SET LCD/PORT CONFIGURATION term (see table 23). The second nibble following this term at the LCD control register (LCR) defines the port configuration as described in table 25. Primary register address: '2'hex
Code 3210 xxx0 xxx1 xx0x xx1x 00xx 01xx 10xx 11xx
Function Mux 3:1 Mux 4:1 Frame frequency high (64 Hz at 1/4 duty, 85 Hz at 1/3 duty) Frame frequency low (32 Hz at 1/4 duty, 43 Hz at 1/3 duty) Pump frequency 2048 Hz Pump frequency 1024 Hz Pump frequency 512 Hz Pump frequency 256 Hz
AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA
AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AA A
Bit 3 Bit 2 Bit 1 Bit 0 LPCR LPCR3 LPCR2 LPCR1 LPCR0 Reset value: 1111 b LPCR3...LPCR0 - LCD port configuration
Table 25. LCD Port configuration (LPCR)
Code 3210 0000 0001 0010 0011 0100 0101 0111 1xxx
Function Segment 32 ... 17 acts as bidirectional port Segment 32 ... 19 acts as bidirectional port Segment 32 ... 21 acts as bidirectional port Segment 32 ... 23 acts as bidirectional port Segment 32 ... 25 acts as bidirectional port Segment 32 ... 27 acts as bidirectional port Segment 32 ... 30 acts as bidirectional port LCD output only
3.2.1
Initializing the LCD Driver
After power-on the LCD driver circuitry is set automatically into 3:1 multiplex drive, LCD-segment output and powersave mode. This means all LCD outputs (COM0...COM3, S01...S32) are at VSS level. The contents of the LCD display buffer and the shadow register are set to 0. The CLEAR/INIT term will initialise the LCD control logic after power-on into a well-defined state.
3.2.2
LCD operating modes
After power-on or the CLEAR/INIT term the LCD display buffer and the shadow register are loaded with 0.
With the LOAD ALL SEGMENTS term the whole shadow register is loaded with a data nibble following the term. To display the data at the LCD panel there are two terms available - the DISPLAY NORMAL and the DISPLAY ROTATE term. With the DISPLAY NORMAL term the data available in the shadow register is copied to the LCD display buffer and then displayed at the LCD panel. The DISPLAY ROTATE works in a different way. The data from the shadow register is moved into the LCD display buffer and displayed. The previous data of the LCD display buffer will be available in the shadow register. This term is useful by displaying alternating display information.
TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97
37 (44)
Preliminary Information
M44C588
The BLANKING term causes a blank display. Note that the contents of LCD display buffer and the shadow register are not influenced by this term. By using the address pointer a direct read/write access to any nibble of the shadow register is possible. On any write access to the shadow register the address pointer is postdecremented. A shadow register read access after an address pointer setup will suppress the pre-increment cycle for the first data nibble read. The POWERSAVE term blanks the LCD by switching all the LCD levels to VSS, thus causing a reduction of display power consumption. This mode is only effective if the display is generally to be blanked for periods of more then 5 seconds. The LCD display buffer and the shadow register are unchanged. This function may also be helpful in radio-controlled clock applications to increase the sognal sensitivity by turning off the noise (EMI) of the switching LCD backplane/ segment outputs.
Example for a LCD shadow register read/write access (see also table ): : TogFlags 2h 8h OUT 0001b 2h OUT 0110b 2h OUT 2h IN 2h IN 0101b XOR 2h OUT 0101b XOR 2h OUT \ select auxiliary switch register of Port 2 \ upper 3 bits = 000, that means the lowest bit of this nibble and the next \ nibble define the address -> load address pointer with 10110b = 16h \ read the nibble from address 16h without preincr. on first access \ read the nibble from address 17h (pointer is preincremented) \ XOR with 0101b and nibble of address 17h from the TOS \ write result to the address 17h (pointer now 16h) \ XOR with 0101b and nibble of address 16h from the TOS \ write result to the address 17h (pointer now 15h)
;
3.2.3
Programming the LCD Frequency and Port Configuration Register
To modify the LCD frequency and the LCD port configuration register the following command sequence must be executed without being interrupted (see tables 23...25):
D select the auxiliary switch register of Port 2 (LCR) D write the SET LCD/PORT CONFIGURATION
(110x) command Example: : SetConfiguration CCR@ DI 2h 8h OUT 1100b 2h OUT 0101b 2h OUT 0100b 2h OUT CCR!
D output the nibble defining the LCD frequency configuration (LFCR)
D write the nibble defining the Port configuration to the
Port 2 address (LPCR)
\ disable interrupts \ select the auxiliary switch register of Port 2 (LCR) \ 2 control nibble following \ mux 4:1, frame frequency high, pump frequency 1024 Hz \ seg 31:24 acts as bidirectional ports \ restore interrupt status
;
3.2.4
Reduction of LCD Charge Pump and Frame Frequency
quency and frame frequency under software control (see also table 12).
After any power-on or hardware reset, the LCD voltage generator is in the fast charge mode and the frame frequency is high. This mode is used to quickly charge the capacitance of large displays by using a high charge pumping frequency of the LCD voltage generator. For smaller displays and to reduce the overall system current the M44C588 allows the modification of the charge fre38 (44)
3.2.5
LCD Port Configuration
The M44C588 has 32 segment outputs to drive a LCD panel. The upper 16 segment drivers of the LCD32 module can be configured as bidirectional port pins. The port configuration register allows the reconfiguration of segments pairwise into I/O pins, WHEREBY THE DATA DIRECTION OF EACH I/O pin is bitwise programmable TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97
Preliminary Information
M44C588
(see table 25). The port data and direction information is cells are used, the upper cell acting as data register and the mapped into the LCD shadow register cells SR31 down one below as the data direction register. For example the to SRn as shown in figure 27. Because each block of 4 I/O MSBs of these two cells provide the data direction inpins only require two register cells (4 bit for data register formation for the upper I/O pin. and 4 bit for data direction register), only the upper two S24 S25 S26 S27 S28 S29 S30 S31
LCD driver
I/O
I/O
I/O
I/O
I/O
I/O
LCD display buffer
Bit 0 LCD
X data X
X X
DDR28 DAT28 DDR29 DAT29 DDR30 DAT30 DDR31 DAT31 SR28 SR29 SR30 SR31
Shadow register
Bit 1 Bit 2 Bit 3 SR24
DDR26 DAT26 DDR27 DAT27 SR25 SR26 SR27
not used Address pointer
DATx = data of I/O pin Sx DDRx = direction of I/O pin Sx
Figure 27. LCD 32 - 6 segment outputs used as I/O ports
If two I/O pins are used, the upper two cells are used as data direction and data register and the shadow register cells below are used for driving the LCD segments. In this case only the upper two bits are significant for the port and port data direction (see figure 27 ). The access to the port direction and data register is identical to the LCD shadow register read/write access. A data direction (logical '1') bit sets the corresponding I/O pin into output mode and a logical '0' into input mode
ponents for the LCD voltage generation (one pump and two storage capacitors) should be connected to the mC as shown in figure 28. For very small LCD panels the capacitor values and charge pumping frequency may be reduced to save costs and system current. The capacitor values may be reduced from 100 nF to 47 nF. The user has to connect the mC and the LCD as it will be in the final product in order to select the capacitor value. To examine the LCD driver waveforms, an oscilloscope with a low capacitance probe should be used.
100 nF
3.3
LCD Voltage and Timing Generator
VEE2 C1
The LCD voltage generator circuitry boosts the regulated liquid crystal display voltage (VREG) to the doubled and tripled voltage components (VEE1, VEE2) required by multiplexed liquid crystal displays. These voltage levels are applied to the driver circuitry (see figure 28). Most low voltage (3 V) LCD panels have a temperature coefficient of -6 mV/C. The temperature compensated reference for the LCD voltage booster circuitry (VREG), has the task of meeting this requirement directly, so that the user gets the best LCD contrast over the full operating temperature and supply voltage range. The external com-
100 nF C2 VEE1 TP VREG VSS
100 nF
Figure 28. External components
TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97
39 (44)
Preliminary Information
M44C588
3.4 3:1 Multiplex Drive Mode
S n+1 Sn+2 a f g e d
Attenuator (n.c.) COM0 Figure 27 shows the connection of a 3:1 multiplex LCD panel having the numeric display pattern shown in figure 29, the segment outputs (S00-S31), and the backplane outputs (COM0-COM2). Backplane and segment drive waveforms for this mode are shown in figure 31.
b c
Sn
a f g e
DP
b c COM1 d
COM2 DP
94 9027
Figure 29. 3:1 multiplex 7 segment digit
LCD display buffer
0 0 0 x 1 1 0 x 0 0 x x 1 1 1 x 1 0 0 x 0 0 x x 1 1 1 x 1 1 0 x 1 0 x x 0 1 0 x 1 1 x x 1 1 1 x 0
1 f 1 a 1 b
1 0 e 0g 1 c 1 x
x x 0 d 0 x
Bit0 Bit1 Bit2
x
DP
LCD panel
Figure 30. 3:1 multiplex LCD panel connection
40 (44)
Preliminary Information
TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97
COM0 COM1 COM2 N.C. COM3
96 115
S31 S30 S29 S28 S27 S26 S25 S24
S05 S04 S03 S02 S01 S00
M44C588
(a) Waveforms at driver
43 Hz Time frame COM0 V EE2 V EE1 V REG V SS state1 state2 COM1 LCD segments
COM2
S00
S01
S02 Segment ON Segment OFF
(b) Resultant waveforms at LCD segment
V EE2 V EE1 V REG 0 -VREG -VEE1 -VEE2 0 Figure 31. Waveforms for 3:1 multiplex drive mode
state1
state2
94 9029
The following formulas are valid in the 3:1 multiplex drive mode at any instant (t): V State1(t) V ON(rms)
+V + V9
S01
(t) - V COM0(t) and 33
V State2(t)
EE2
Contrast ratio
+V
+ 0.638 V
ON(rms)
EE2
and V OFF(rms)
V OFF(rms)
+ 1.915
+ V (t) - V + V3
S02 EE2
COM1
(t)
TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97
41 (44)
Preliminary Information
M44C588
3.5 4:1 Multiplex Drive Mode
Sn Figure 33 shows the connection of a 4:1 multiplex 16 digit LCD panel having the numeric display pattern shown in figure 32, the segment outputs (S00-S31), and the backplane outputs (COM0-COM3). Backplane and segment drive waveforms for this mode are shown in figure 34.
a f g e d
Sn+1
COM0
a f g b c d
COM3 DP
94 9030
b
COM2 DP
COM1
c
e
Figure 32. 4:1 multiplex 7 segment digit
LCD display buffer
0 0 0 0 0 1 1 0 0 1 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 0 1 1 0 0 1 1f 0 1 g 1 1e 0 1d 1 1 1 0 a b c
Bit0 Bit1 Bit2 Bit3
DP
S06 S05 S04 S03 S02 S01 S00 S31 S30 S29 S28 S27 S26 S25 S24 S23
LCD panel
Figure 33. 4:1 multiplex LCD panel connection
42 (44)
Preliminary Information
TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97
COM0 COM1 COM2 COM3
96 115
M44C588
(a) Waveforms at driver
64 Hz VEE2 COM0 V EE1 V REG V SS COM1 state2 COM2 Time frame LCD segments
state1
COM3
S00
S01
S02
S03
Segment ON Segment OFF
(b) Resultant waveforms at LCD segment
state1 V EE2 0 -V EE2 state2 V REG 0 -V REG Figure 34. Waveforms for 4:1 multiplex drive mode
94 9032
The following formulas are valid in the 4:1 multiplex drive mode at any instant (t): V State1(t) V ON(rms)
+V + V3
S01
(t) - V COM0(t) and 3
V State2(t)
EE2
Contrast ratio
+V
+ 0.577 V
ON(rms)
EE2
and V OFF(rms)
V OFF(rms)
+ 1.732
+ V (t) - V + V3
S02 EE2
COM1
(t)
TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97
43 (44)
Preliminary Information
M44C588
4 Extended RAM
XRAM
256 x 4 bit
The M44C588 contains a 256 4-bit wide extended random access memory (XRAM). The extended RAM is addressed by the 8-bit wide peripheral RAM address register. This is loaded trough the auxiliary switch register of port address C. The extended RAM allows random access to any of the 256 data nibbles and supports postdecrement after any WRITE access and pre-increment after any READ access. A peripheral RAM read access after a new address setup/ write cycle will suppress the pre-increment cycle before the addressed data nibble is read. This will deliver the specified data nibble on TOS.
XRAM address pointer
I/O bus
Data
Figure 35. Extended RAM
5
5.1
Electrical Characteristics
Absolute Maximum Ratings
Symbol VDD VIN tshort Tamb Tstg RthJA Tsd Value -0.3 to + 6.5 indefinite -40 to +85 -40 to +130 110 260 Unit V V sec C C K/W C
Voltages are given relative to VSS .
AAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA
VSS -0.3
Parameters Supply voltage Input voltage (on any pin) Output short circuit duration Operating temperature range Storage temperature range Thermal resistance (DIP40) Soldering temperature (t 10 sec)
VIN VDD +0.3
Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at any condition above those indicated in the operational section of these specification is not implied. Exposure to absolute maximum rating condition for an extended period may affect device reliability. All inputs
and outputs are protected against high electrostatic voltages or electric fields. However, precautions to minimize built-up of electrostatic charges during handling are recommended. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g. VDD).
We reserve the right to make changes to improve technical design without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized application, the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. TEMIC TELEFUNKEN microelectronic GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 ( 0 ) 7131 67 2831, Fax Number: 49 ( 0 ) 7131 67 2423
44 (44)
Preliminary Information
TELEFUNKEN Semiconductors Rev. A1, 11-Nov-97

▲Up To Search▲

Price & Availability of M44C588

	To Download M44C588 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .