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LP3985 Micropower, 150mA Low-Noise Ultra Low-Dropout CMOS Voltage Regulator
October 2000
LP3985 Micropower, 150mA Low-Noise Ultra Low-Dropout CMOS Voltage Regulator
General Description
The LP3985 is designed for portable and wireless applications with demanding performance and space requirements. LP3985 is stable with a small 1F 30% ceramic or high-quality tantalum output capacitor requiring smallest possible PC board area. The total application circuit area is less than 2.0mm x 2.5mm, a fraction of a 1202 case size. The LP3985's performance is optimized for battery powered systems to deliver ultra low noise, extremely low dropout voltage and low quiescent current. Regulator ground current increases only slightly in dropout, further prolonging the battery life. Optional external bypass capacitor reduces the output noise further without slowing down the load transient response. Fast start-up time is achieved by utilizing an internal power-on circuit that actively pre-charges the bypass capacitor. Power supply rejection is better than 60 dB at low frequencies and starts to roll off at 10 kHz. High power supply rejection is maintained down to lower input voltage levels common to battery operated circuits. The device is ideal for mobile phone and similar battery powered wireless applications. It provides up to 150 mA, from a 2.5V to 6V input, consuming less than 1.5A in disable mode and has fast turn-on time less than 200s. The LP3985 is available in micro SMD and 5 pin SOT-23 package. Performance is specified for -40C to +125C temperature range and is available in 2.5V, 2.8V and 3.0V output voltages. For other output voltage options from 2.5V to 5.0V or for a dual LP3985, please contact National Semiconductor sales office.
Key Specifications
n n n n n n n n n 2.5 to 6.0V input range 150mA guaranteed output 60dB PSRR at 1kHz, 50dB at 10kHz @ 3.1VIN 1.5A quiescent current when shut down Fast Turn-On time: 200 s (typ.) 100mV maximum dropout with 150mA load 30Vrms output noise over 10Hz to 100kHz -40 to +125C junction temperature range for operation 2.5V, 2.8V and 3.0V outputs standard
Features
n n n n n Miniature 5-I/O micro SMD and SOT-23-5 package Logic controlled enable Stable with ceramic and high quality tantalum capacitors Fast turn-on Thermal shutdown and short-circuit current limit
Applications
n n n n n CDMA cellular handsets Wideband CDMA cellular handsets GSM cellular handsets Portable information appliances Tiny 3.3V 5% to 2.5V, 150mA converter
Typical Application Circuit
DS101364-2
Note: Pin Numbers in parenthesis indicate micro SMD package. * Optional Noise Reduction Capacitor.
(c) 2000 National Semiconductor Corporation
DS101364
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LP3985
Block Diagram
DS101364-1
Pin Description
Name VEN GND VOUT VIN BYPASS SMD 1 2 3 4 5 SOT 3 2 5 1 4 Function Enable Input Logic, Enable High Common Ground Output Voltage of the LDO Input Voltage of the LDO Optional Bypass Capacitor for Noise Reduction
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LP3985
Connection Diagrams
SOT-23-5 Package (MF) micro SMD, 5 Bump Package (BPA05)
DS101364-7
Top View See NS Package Number MF05A
DS101364-70
Note: The actual physical placement of the package marking will vary from part to part. The package marking X will designate the date code and will vary considerably. Package marking does not correlate to device type in any way.
Top View See NS Package Number BPA05
Ordering Information For micro SMD Package
Output Voltage (V) 2.5 2.8 3.0 Grade STD STD STD LP3985 Supplied as 250 Units, Tape and Reel LP3985IBP-2.5 LP3985IBP-2.8 LP3985IBP-3.0 LP3985 Supplied as 3000 Units, Tape and Reel LP3985IBPX-2.5 LP3985IBPX-2.8 LP3985IBPX-3.0
For SOT Package
Output Voltage (V) 2.5 2.8 3.0 Grade STD STD STD LP3985 Supplied as 1000 Units, Tape and Reel LP3985IM5-2.5 LP3985IM5-2.8 LP3985IM5-3.0 LP3985 Supplied as 3000 Units, Tape and Reel LP3985IM5X-2.5 LP3985IM5X-2.8 LP3985IM5X-3.0 Package Marking LCSB LCJB LCRB
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LP3985
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VIN,VOUT, VEN Junction Temperature Storage Temperature Lead Temp. (Note 3) Pad Temp. (Note 3) Power Dissipation (Note 4) JA (SOT23-5) JA (micro SMD) Maximum Power Dissipation SOT23-5 (micro SMD) -0.3 to 6.5V 150C -65C to +150C 235C 235C 220C/W 255C/W 364mW 355mW
ESD Rating(Note 5) Human Body Model Machine Model
2kV 150V
Operating Ratings (Notes 1, 2)
VIN VEN Junction Temperature Maximum Power Dissipation (Note 6) SOT23-5 (micro SMD) 2.5 to 6V 0 to (VIN + 0.3V) -40C to +125C
250mW 244mW
Electrical Characteristics
Unless otherwise specified: VIN = VOUT(nom) + 0.5V, CIN = 1 F, IOUT = 1mA, COUT = 1 F, CBYPASS = 0.01F. Typical values and imits appearing in standard typeface are for TJ = 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40C to +125C. (Note 7) (Note 8) Symbol Parameter Output Voltage Tolerance Line Regulation Error VOUT Load Regulation Error (Note 9) Output AC Line Regulation Conditions IOUT = 1mA VIN = (VOUT(nom) + 0.5V) to 6.0V, IOUT = 1 mA IOUT = 1 mA to 150 mA LP3985IM5 (SOT23-5) LP3985IBP (micro SMD) VIN = VOUT(nom) + 1V, IOUT = 150 mA (Figure 1) VIN = VOUT(nom) + 0.2V, f = 1 kHz, IOUT = 50 mA (Figure 2) VIN = VOUT(nom) + 0.2V, f = 10 kHz, IOUT = 50 mA (Figure 2) VEN = 1.4V, IOUT = 0 mA VEN = 1.4V, IOUT = 0 to 150 mA VEN = 0.4V Dropout Voltage (Note 10) IOUT = 1 mA IOUT = 50 mA IOUT = 100 mA IOUT = 150 mA ISC IOUT(PK) TON en Short Circuit Current Limit Peak Output Current Turn-On Time (Note 11) Output Noise Voltage Output Noise Density IEN Maximum Input Current at EN Output Grounded (Steady State) VOUT VOUT(nom) - 5% CBYPASS = 0.01 F BW = 10 Hz to 100 kHz, COUT = 1F CBP = 0 VEN = 0.4 and VIN = 6.0 0.005 Typ Limit Min -2 -3 -0.10 Max 2 3 0.10 %/V 0.0025 0.0004 1.5 60 0.005 %/mA 0.002 mVP-P Units % of VOUT(nom)
PSRR
Power Supply Rejection Ratio
50
dB
IQ
Quiescent Current
85 140 0.003 0.4 20 45 60 600 550 200 30 230 300
150 200 1.5 2 35 70 100 mA mA s Vrms nV/ nA mV A
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LP3985
Electrical Characteristics
(Continued)
Unless otherwise specified: VIN = VOUT(nom) + 0.5V, CIN = 1 F, IOUT = 1mA, COUT = 1 F, CBYPASS = 0.01F. Typical values and imits appearing in standard typeface are for TJ = 25C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40C to +125C. (Note 7) (Note 8) Symbol VIL VIH Parameter Maximum Low Level Input Voltage at EN Minimum High Level Input Voltage at EN Thermal Shutdown Temperature Thermal Shutdown Hysteresis Conditions VIN = 2.5 to 6.0V VIN = 2.5 to 6.0V 160 20 1.4 Typ Limit Min Max 0.4 Units V V C C
TSD
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: All voltages are with respect to the potential at the GND pin. Note 3: Additional information on lead temperature and pad temperature can be found in National Semiconductor Application Note (AN-1112). Note 4: The Absolute Maximum power dissipation depends on the ambient temperature and can be calculated using the formula:
PD = (TJ - TA)/JA,
Where TJ is the junction temperature, TA is the ambient temperature, and JA is the junction-to-ambient thermal resistance. The 364mW rating appearing under Absolute Maximum Ratings results from substituting the Absolute Maximum junction temperature, 150C, for TJ, 70C for TA, and 220C/W for JA. More power can be dissipated safely at ambient temperatures below 70C . Less power can be dissipated safely at ambient temperatures above 70C. The Absolute Maximum power dissipation can be increased by 4.5mW for each degree below 70C, and it must be derated by 4.5mW for each degree above 70C. Note 5: The human body model is 100pF discharged through 1.5k resistor into each pin. The machine model is a 200 pF capacitor discharged directly into each pin. Note 6: Like the Absolute Maximum power dissipation, the maximum power dissipation for operation depends on the ambient temperature. The 250mW rating appearing under Operating Ratings results from substituting the maximum junction temperature for operation, 125C, for TJ, 70C for TA, and 220C/W for JA into (Note 4) above. More power can be dissipated at ambient temperatures below 70C . Less power can be dissipated at ambient temperatures above 70C. The maximum power dissipation for operation can be increased by 4.5mW for each degree below 70C, and it must be derated by 4.5mW for each degree above 70C. Note 7: All limits are guaranteed. All electrical characteristics having room-temperature limits are tested during production with TJ = 25C or correlated using Statistical Quality Control (SQC) methods. All hot and cold limits are guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Note 8: The target output voltage, which is labeled VOUT(nom), is the desired voltage option. Note 9: An increase in the load current results in a slight decrease in the output voltage and vice versa. Note 10: Dropout voltage is the input-to-output voltage difference at which the output voltage is 100mV below its nominal value. This specification does not apply for input voltages below 2.5V. Note 11: Turn-on time is time measured between the enable input just exceeding VIH and the output voltage just reaching 95% of its nominal value.
DS101364-8
FIGURE 1. Output AC Line Regulation Input Perturbation
DS101364-9
FIGURE 2. PSRR Input Perturbation
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LP3985
Typical Performance Characteristics
Output Voltage Change vs Temperature
Unless otherwise specified, CIN = COUT = 1 F Ceramic, CBP = 0.01 F, VIN = VOUT + 0.2V, TA = 25C, Enable pin is tied to VIN. Dropout Voltage vs Load Current
DS101364-41
DS101364-33
Ground Current vs Load Current
Ground Current vs VIN @ 25C
DS101364-40
DS101364-35
Ground Current vs VIN @ -40C
Ground Current vs VIN @ 125C
DS101364-37
DS101364-39
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LP3985
Typical Performance Characteristics
Short Circuit Current (SMD)
Unless otherwise specified, CIN = COUT = 1 F Ceramic, CBP = 0.01 F, VIN = VOUT + 0.2V, TA = 25C, Enable pin is tied to VIN. (Continued) Short Circuit Current (SMD)
DS101364-45
DS101364-46
Short Circuit Current (SOT)
Short Circuit Current (SOT)
DS101364-47
DS101364-48
Short Circuit Current (SOT)
Short Circuit Current (SOT)
DS101364-49
DS101364-50
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LP3985
Typical Performance Characteristics
Short Circuit Current (SMD)
Unless otherwise specified, CIN = COUT = 1 F Ceramic, CBP = 0.01 F, VIN = VOUT + 0.2V, TA = 25C, Enable pin is tied to VIN. (Continued) Short Circuit Current (SMD)
DS101364-51
DS101364-52
Output Noise Spectral Density
Ripple Rejection (VIN = VOUT + 0.2V)
DS101364-10
DS101364-11
Ripple Rejection (VIN = VOUT + 1V)
Ripple Rejection (VIN = 5.0V)
DS101364-12
DS101364-13
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LP3985
Typical Performance Characteristics
Start Up Time (VIN = 3.2V)
Unless otherwise specified, CIN = COUT = 1 F Ceramic, CBP = 0.01 F, VIN = VOUT + 0.2V, TA = 25C, Enable pin is tied to VIN. (Continued) Start Up Time (VIN = 4.2V)
DS101364-14
DS101364-15
Start Up Time
Start Up Time
DS101364-16
DS101364-17
Start Up Time
Start Up Time
DS101364-18
DS101364-19
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LP3985
Typical Performance Characteristics
Line Transient Response
Unless otherwise specified, CIN = COUT = 1 F Ceramic, CBP = 0.01 F, VIN = VOUT + 0.2V, TA = 25C, Enable pin is tied to VIN. (Continued) Line Transient Response
DS101364-20
DS101364-21
Load Transient Response (VIN = 3.2V)
Load Transient Response (VIN = 4.2V)
DS101364-23
DS101364-22
Load Transient Response (VIN = 3.2V)
Load Transient Response (VIN = 4.2V)
DS101364-24
DS101364-25
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LP3985
Typical Performance Characteristics
Load Transient Response
Unless otherwise specified, CIN = COUT = 1 F Ceramic, CBP = 0.01 F, VIN = VOUT + 0.2V, TA = 25C, Enable pin is tied to VIN. (Continued) Load Transient Response
DS101364-26
DS101364-27
Load Transient Response
Load Transient Response
DS101364-28
DS101364-29
Load Transient Response
Load Transient Response
DS101364-30
DS101364-31
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LP3985
Typical Performance Characteristics
Load Transient Response
Unless otherwise specified, CIN = COUT = 1 F Ceramic, CBP = 0.01 F, VIN = VOUT + 0.2V, TA = 25C, Enable pin is tied to VIN. (Continued) Enable Response (VIN = 3.2V)
DS101364-32
DS101364-53
Enable Response (VIN = 4.2V)
Enable Response (VIN = 3.0V)
DS101364-54
DS101364-55
Enable Response (VIN = 3.2V)
Enable Response (VIN = 3.2V)
DS101364-56
DS101364-57
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LP3985
Typical Performance Characteristics
Enable Response (VIN = 3.2V)
Unless otherwise specified, CIN = COUT = 1 F Ceramic, CBP = 0.01 F, VIN = VOUT + 0.2V, TA = 25C, Enable pin is tied to VIN. (Continued) Enable Response (VIN = 5.5V)
DS101364-58
DS101364-59
Enable Response (VIN = 5.5V)
Enable Response (VIN = 5.5V)
DS101364-60
DS101364-61
Output Impedance (VIN = 4.2V)
Output Impedance (VIN = VOUT + 0.2V)
DS101364-65
DS101364-66
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LP3985
Application Hints
External Capacitors Like any low-dropout regulator, the LP3985 requires external capacitors for regulator stability. The LP3985 is specifically designed for portable applications requiring minimum board space and smallest components. These capacitors must be correctly selected for good performance. Input Capacitor An input capacitance of ) 1F is required between the LP3985 input pin and ground (the amount of the capacitance may be increased without limit). This capacitor must be located a distance of not more than 1cm from the input pin and returned to a clean analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input. Important: Tantalum capacitors can suffer catastrophic failures due to surge current when connected to a low-impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input, it must be guaranteed by the manufacturer to have a surge current rating sufficient for the application. There are no requirements for the ESR on the input capacitor, but tolerance and temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will be ) 1F over the entire operating temperature range. Output Capacitor The LP3985 is designed specifically to work with very small ceramic output capacitors. A ceramic capacitor (dielectric types Z5U, Y5V or X7R) in 1 to 22 F range with 5m to 500m ESR range is suitable in the LP3985 application circuit. It may also be possible to use tantalum or film capacitors at the output, but these are not as attractive for reasons of size and cost (see next section Capacitor Characteristics). The output capacitor must meet the requirement for minimum amount of capacitance and also have an ESR (Equivalent Series Resistance) value which is within a stable range (5 m to 500 m). No-Load Stability The LP3985 will remain stable and in regulation with no external load. This is specially important in CMOS RAM keep-alive applications. Capacitor Characteristics The LP3985 is designed to work with ceramic capacitors on the output to take advantage of the benefits they offer: for capacitance values in the range of 1F to 4.7F range, ceramic capacitors are the smallest, least expensive and have the lowest ESR values (which makes them best for eliminating high frequency noise). The ESR of a typical 1F ceramic capacitor is in the range of 20 m to 40 m, which easily meets the ESR requirement for stability by the LP3985. The ceramic capacitor's capacitance can vary with temperature. Most large value ceramic capacitors () 2.2F) are manufactured with Z5U or Y5V temperature characteristics, which results in the capacitance dropping by more than 50% as the temperature goes from 25C to 85C.
A better choice for temperature coefficient in a ceramic capacitor is X7R, which holds the capacitance within 15%. Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more expensive when comparing equivalent capacitance and voltage ratings in the 1F to 4.7F range. Another important consideration is that tantalum capacitors have higher ESR values than equivalent size ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the stable range, it would have to be larger in capacitance (which means bigger and more costly ) than a ceramic capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about 2:1 as the temperature goes from 25C down to -40C, so some guard band must be allowed. Noise Bypass Capacitor Connecting a 0.01F capacitor between the CBP pin and ground significantly reduces noise on the regulator output. This cap is connected directly to a high impedance node in the band gap reference circuit. Any significant loading on this node will cause a change on the regulated output voltage. For this reason, DC leakage current through this pin must be kept as low as possible for best output voltage accuracy. The types of capacitors best suited for the noise bypass capacitor are ceramic and film. High-quality ceramic capacitors with either NPO or COG dielectric typically have very low leakage. Polypropolene and polycarbonate film capacitors are available in small surface-mount packages and typically have extremely low leakage current. Unlike many other LDO's, addition of a noise reduction capacitor does not effect the transient response of the device. On/Off Input Operation The LP3985 is turned off by pulling the VEN pin low, and turned on by pulling it high. If this feature is not used, the VEN pin should be tied to VIN to keep the regulator output on at all time. To assure proper operation, the signal source used to drive the VEN input must be able to swing above and below the specified turn-on/off voltage thresholds listed in the Electrical Characteristics section under VIL and VIH. Fast On-Time The LP3985 utilizes a speed up circuitry to ramp up the internal VREF voltage to its final value to achieve a fast output turn on time. The optional bypass capacitor connected to the output of the bandgap is charged by a 70 A current source. The current source is turned off when bandgap voltage reaches approximately 95% of its final value. Micro SMD Mounting The micro SMD package requires specific mounting techniques which are detailed in National Semiconductor Application Note (AN-1112). Referring to the section Surface Mount Technology (SMT) Assembly Considerations, it should be noted that the pad style which must be used with the 5 pin package is NSMD (non-solder mask defined) type. For best results during assembly, alignment ordinals on the PC board may be used to facilitate placement of the micro SMD device.
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LP3985
Application Hints
Micro SMD Light Sensitivity
(Continued)
Exposing the micro SMD device to direct sunlight will cause misoperation of the device. Light sources such as Halogen lamps can effect electrical performance if brought near to the device.
The wavelengths which have most detrimental effect are reds and infra-reds, which means that the fluorescent lighting used inside most buildings has very little effect on performance. A micro SMD test board was brought to within 1cm of a fluorescent desk lamp and the effect on the regulated output voltage was negligible, showing a deviation of less than 0.1% from nominal.
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LP3985
Physical Dimensions
inches (millimeters) unless otherwise noted
5-Lead Small Outline Package (MF) NS Package Number MF05A
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LP3985 Micropower, 150mA Low-Noise Ultra Low-Dropout CMOS Voltage Regulator
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
micro SMD, 5 Bump, Package (BPA05) NS Package Number BPA05CMC The dimensions for X1, X2 and X3 are as given: X1 = 0.828 +/- 0.03mm X2 = 1.387 +/- 0.03mm X3 = 0.900 +/- 0.10mm
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