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LMH6502 Wideband, Low Power, Linear-in-dB Variable Gain Amplifier
October 2003
LMH6502 Wideband, Low Power, Linear-in-dB Variable Gain Amplifier
General Description
The LMH6502 is a wideband DC coupled differential input voltage controlled gain stage followed by a high-speed current feedback Op Amp which can directly drive a low impedance load. Gain adjustment range is more than 70dB for up to 10MHz. Maximum gain is set by external components and the gain can be reduced all the way to cut-off. Power consumption is 300mW with a speed of 130MHz. Output referred DC offset voltage is less than 350mV over the entire gain control voltage range. Device-to-device Gain matching is within 0.6dB at maximum gain. Furthermore, gain at any VG is tested and the tolerance is guaranteed. The output current feedback Op Amp allows high frequency large signals (Slew Rate = 1800V/s) and can also drive heavy load current (75mA). Differential inputs allow common mode rejection in low level amplification or in applications where signals are carried over relatively long wires. For single ended operation, the unused input can easily be tied to ground (or to a virtual half-supply in single supply application). Inverting or non-inverting gains could be obtained by choosing one input polarity or the other. To provide ease of use when working with a single supply, VG range is set to be from 0V to +2V relative to pin 11 potential (ground pin). In single supply operation, this ground pin is tied to a "virtual" half supply. LMH6502 gain control is linear in dB for a large portion of the total gain control range. This makes the device suitable for AGC circuits among other applications. For linear gain control applications, see the LMH6503 datasheet. The LMH6502 is available in the SOIC-14 package.
Features
VS = 5V, TA = 25C, RF = 1k, RG = 174, RL = 100, AV = AV(MAX) = 10 Typical values unless specified. n -3dB BW 130MHz n Gain control BW 100MHz n Adjustment range (typical over temp) 70dB 0.6dB n Gain matching (limit) n Slew rate 1800V/s n Supply current (no load) 27mA 75mA n Linear output current 3.2V n Output voltage (RL = 100) n Input voltage noise 7.7nV/ n Input current noise 2.4pA/ n THD (20MHz, RL = 100, VO = 2VPP) -53dBc n Replacement for CLC520
Applications
n n n n Variable attenuator AGC Voltage controller filter Video imaging processing
Gain vs. VG for Various Temperature
Typical Application
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AVMAX = 10V/V
(c) 2003 National Semiconductor Corporation
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LMH6502
Absolute Maximum Ratings
(Note 1)
Storage Temperature Range Junction Temperature Soldering Information: Infrared or Convection (20 sec) Wave Soldering (10 sec)
-65C to +150C +150C 235C 260C
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ESD Tolerance (Note 4): Human Body Machine Model Input Current VIN Differential Output Current Supply Voltages (V - V ) Voltage at Input/ Output pins
+ - + -
2KV 200V
10mA (V+ -V-)
120mA (Note 3) 12.6V V +0.8V,V - 0.8V
Operating Ratings (Note 1)
Supply Voltages (V+ - V-) Temperature Range Thermal Resistance: 14-Pin SOIC (JC) 45C/W 5V to 12V -40C to +85C (JA) 138C/W
Electrical Characteristics(Note 2)
Unless otherwise specified, all limits guaranteed for TJ = 25C, VS = 5V, AV(MAX) = 10, VCM = 0V, RF = 1k, RG = 174, VIN_DIFF = 0.1V, RL = 100, VG = +2V. Boldface limits apply at the temperature extremes. Symbol BW GF Parameter -3dB Bandwidth Gain Flatness Conditions VOUT < 0.5PP VOUT < 0.5PP, AV(MAX) = 100 VOUT < 0.5VPP 0.6V VG 2V, 0.3dB Min (Note 6) Typ (Note 6) 130 50 30 16 7.5 100 1.5 2.5 -47 72 67 2.2 10 1800 4.8 Max (Note 6) Units
Frequency Domain Response MHz MHz
Att Range Flat Band (Relative to Max Gain) Attenuation Range (Note 14) BW Control PL G Delay CT (dB) GR Gain control Bandwidth Linear Phase Deviation Group Delay Feed-through Gain Adjustment Range
0.2dB, f < 30MHz 0.1dB, f < 30MHz
VG = 1V (Note 13) DC to 60MHz DC to 130MHz VG = 0V, 30MHz (Output Referred) f < 10MHz f < 30MHz
dB MHz deg ns dB
dB
Time Domain Response tr, tf OS % SR G Rate Rise and Fall Time Overshoot Slew Rate Gain Change Rate 0.5V Step 0.5V Step 4V Step VIN = 0.3V, 10%-90% of Final Output 2VPP, 20MHz 2VPP, 20MHz 2VPP, 20MHz 1MHz to 150MHz 1MHz to 150MHz f = 4.43MHz, RL = 150, Neg. Sync f = 4.43MHz, RL = 150, Neg. Sync ns % V/s dB/ns
Distortion & Noise Performance HD2 HD3 THD En tot IN DG DP 2nd Harmonic Distortion 3
rd
-55 -57 -53 7.7 2.4 0.34 0.10
dBc dBc dBc nV/ pA/ % deg
Harmonic Distortion
Total Harmonic Distortion Total Equivalent Input Noise Input Noise Current Differential Gain Differential Phase
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LMH6502
Electrical Characteristics(Note 2)
(Continued) Unless otherwise specified, all limits guaranteed for TJ = 25C, VS = 5V, AV(MAX) = 10, VCM = 0V, RF = 1k, RG = 174, VIN_DIFF = 0.1V, RL = 100, VG = +2V. Boldface limits apply at the temperature extremes. Parameter Gain Accuracy (See Application Note) Gain Matching (See Application Note) Gain Multiplier (See Application Notes) Input Voltage Range Differential Input Voltage RG Current Bias Current Pin 3 & 6 Common Mode, |CMRR| > 55dB (Note 9) Between pins 3 & 6 Pins 4 & 5 Pins 3 & 6(Note 7) Pins 3 & 6 (Note 7), VS = 2.5V Conditions VG = 2.0V 1V < VG < 2V VG = 2.0V 1 < VG < 2V 1.61 1.58 Min (Note 6) Typ (Note 6) 0.0 +0.6/-0.3 - - 1.72 Max (Note 6) +0.6 +3.1/-3.6 Units
Symbol GACCU G Match K VCM VIN_DIFF I
RG_MAX
DC & Miscellaneous Performance dB dB V/V V
0.6
+2.8/-3.9 1.84 1.91
2.0 1.70 0.3 0.12 1.70 1.56
2.2 0.39 2.22
9 2.5 100 0.01 5 750 5 -300 20 10 1.3 2.0 3.6 18 20 5 6
V mA
IBIAS
A
TC IBIAS I
OFF
Bias Current Drift Offset Current Offset Current Drift Input Resistance Input Capacitance VG Bias Current VG Bias Drift VG Input Resistance VG Input Capacitance Output Voltage Range
Pin 3 & 6(Note 8) Pin 3 & 6 (Note 8) Pin 3 & 6 Pin 3 & 6 Pin 2, VG = 0V(Note 7) Pin 2(Note 8) Pin 2 Pin 2 RL = 100 RL = Open
nA/C A nA/C k pF A nA/C k pF
TC IOFF RIN CIN IVG TC IVG R C
VG VG
VOUT
3.00 2.95 3.95 3.82 80 75
3.20 4.00
0.1 V
ROUT IOUT VO
OFFSET
Output Impedance Output Current Output Offset Voltage +Power Supply Rejection Ratio (Note 10) -Power Supply Rejection Ratio (Note 10) Common Mode Rejection Ratio (Note 9) Supply Current
DC VOUT = 4V from Rails 0V < VG < 2V Input Referred, 1V change, VG = 2.2V Input Referred, 1V change, VG = 2.2V Input Referred,VG = 2V -1.8V < VCM < 1.8V No Load VS = 2.5V, RL = Open
mA
90 80
-69 -58 -72 27 9.3 38 41 16 19
300 380
-47 -45 -41 -40
mV dB
+PSRR -PSRR CMRR IS
dB dB
mA
3
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LMH6502
Electrical Characteristics(Note 2)
(Continued)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications, see the Electrical Characteristics tables. Note 2: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Note 3: The maximum output current (IOUT) is determined by device power dissipation limitations or value specified, whichever is lower. Note 4: Human body model: 1.5k in series with 100pF. Machine model: 0 in series with 200pF. Note 5: Slew Rate is the average of the rising and falling rates. Note 6: Typical values represent the most likely parametric norm. Bold numbers refer to over temperature limits. Note 7: Positive current corresponds to current flowing in the device. Note 8: Drift determined by dividing the change in parameter distribution average at temperature extremes by the total temperature change. Note 9: CMRR definition: [|VOUT/VCM| / AV] with 0.1V differential input voltage. Note 10: +PSRR definition: [|VOUT/V+| / AV], -PSRR definition: [|VOUT/V-| / AV] with 0.1V differential input voltage. Note 11: Gain/Phase normalized to low frequency value at 25C. Note 12: Gain/Phase normalized to low frequency value at each AV. Note 13: Gain Control Frequency Response Schematic:
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Note 14: Flat Band Attenuation (Relative to Max Gain) Range Definition: Specified as the attenuation range from maximum which allows gain flatness specified (either 0.2dB or 0.1dB) relative to AVMAX gain. For example, for f < 30MHz, here are the Flat Band Attenuation ranges:
0.2dB 0.1dB
20dB down to 4dB = 16dB range 20dB down to 12.5 dB = 7.5dB range
Connection Diagram
14-Pin SOIC
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Top View
Ordering Information
Package 14-pin SOIC Part Number LMH6502MA LMH6502MAX Package Marking LMH6502MA Transport Media 55 Units/Rail 2.5k Units Tape and Reel NSC Drawing M14A
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LMH6502
Typical Performance Characteristics Unless otherwise specified: VS = 5V, 25C, VG = VGMAX, VCM = 0V, RF = 1k, RG = 174, both inputs terminated in 50, RL = 100, Typical values, results referred to device output.
Small Signal Frequency for Various VG Large Signal Frequency for Various VG
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Frequency Response Over Temperature (AV = 10)
Frequency Response for Various VG (AVMAX = 10)
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Frequency Response for Various VG (AVMAX = 10) (2.5V)
Small Signal Frequency Response for Various AVMAX
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LMH6502
Typical Performance Characteristics Unless otherwise specified: VS = 5V, 25C, VG = VGMAX, VCM
= 0V, RF = 1k, RG = 174, both inputs terminated in 50, RL = 100, Typical values, results referred to device output. (Continued) Frequency Response for Various VG (AVMAX = 100) (Small Signal)
Large Signal Frequency Response for Various AVMAX
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Frequency Response for Various VG (AVMAX = 100) (Large Signal)
IS vs. VS
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IS vs. VS
Input Bias Current vs. VS
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LMH6502
Typical Performance Characteristics Unless otherwise specified: VS = 5V, 25C, VG = VGMAX, VCM
= 0V, RF = 1k, RG = 174, both inputs terminated in 50, RL = 100, Typical values, results referred to device output. (Continued) AVMAX vs. VCM AVMAX vs. VCM
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PSRR 5V
PSRR 2.5V
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CMRR 5V
CMRR 2.5V
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LMH6502
Typical Performance Characteristics Unless otherwise specified: VS = 5V, 25C, VG = VGMAX, VCM
= 0V, RF = 1k, RG = 174, both inputs terminated in 50, RL = 100, Typical values, results referred to device output. (Continued) AVMAX vs. Supply Voltage Supply Current vs. VCM
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Supply Current vs. VCM
Output Offset Voltage vs. VCM (Typical Unit #1)
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Output Offset Voltage vs. VCM (Typical Unit #2)
Output Offset Voltage vs. VCM (Typical Unit #3)
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LMH6502
Typical Performance Characteristics Unless otherwise specified: VS = 5V, 25C, VG = VGMAX, VCM
= 0V, RF = 1k, RG = 174, both inputs terminated in 50, RL = 100, Typical values, results referred to device output. (Continued) Feed through Isolation Gain Flatness and Linear Phase Deviation vs. VG
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Gain Flatness Frequency vs. Gain (Note 14)
Group Delay vs. Frequency
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K Factor vs. RG
Gain vs. VG Including Limits
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LMH6502
Typical Performance Characteristics Unless otherwise specified: VS = 5V, 25C, VG = VGMAX, VCM
= 0V, RF = 1k, RG = 174, both inputs terminated in 50, RL = 100, Typical values, results referred to device output. (Continued) BW vs. RF Gain vs. VG (5V)
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Gain vs. VG (2.5V)
Output Offset Voltage vs. VG (Typical Unit #1)
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Output Offset Voltage vs. VG (Typical Unit #2)
Output Offset Voltage vs. VG (Typical Unit #3)
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LMH6502
Typical Performance Characteristics Unless otherwise specified: VS = 5V, 25C, VG = VGMAX, VCM
= 0V, RF = 1k, RG = 174, both inputs terminated in 50, RL = 100, Typical values, results referred to device output. (Continued) Output Offset Voltage vs. VS for various VG (Typical Unit# 1) Output Offset Voltage vs. VS for various VG (Typical Unit# 2)
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Output Offset Voltage vs. VS for various VG (Typical Unit# 3)
Noise vs. Frequency (AVMAX = 2)
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Noise vs. Frequency (AVMAX = 10)
Noise vs. Frequency (AVMAX = 100)
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LMH6502
Typical Performance Characteristics Unless otherwise specified: VS = 5V, 25C, VG = VGMAX, VCM
= 0V, RF = 1k, RG = 174, both inputs terminated in 50, RL = 100, Typical values, results referred to device output. (Continued) -1dB Compression Output Voltage vs. Output Current
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HD2 & HD3 vs. POUT
THD vs. POUT
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THD vs. POUT
HD2 & HD3 vs. VG
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LMH6502
Typical Performance Characteristics Unless otherwise specified: VS = 5V, 25C, VG = VGMAX, VCM
= 0V, RF = 1k, RG = 174, both inputs terminated in 50, RL = 100, Typical values, results referred to device output. (Continued) THD vs. VG THD vs. VG
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VG Bias Current vs. VG
Step Response Plot
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Step Response Plot
Gain vs. VG Step
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LMH6502
Typical Performance Characteristics Unless otherwise specified: VS = 5V, 25C, VG = VGMAX, VCM
= 0V, RF = 1k, RG = 174, both inputs terminated in 50, RL = 100, Typical values, results referred to device output. (Continued) Feedthrough from VG
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Application Information
THEORY OF OPERATION A simplified schematic is shown in Figure 1. +VIN and -VIN are buffered with closed loop voltage followers inducing a signal current in Rg proportional to (+VIN) - (-VIN), the differential input voltage. This current controls a current source which supplies two well-matched transistor, Q1 and Q2. The current flowing through Q2 is converted to the final output voltage using RF and the output amplifier, U1. By changing the fraction of the signal current "I" which flows through Q2, the gain is changed. This is done by changing the voltage applied differentially to the bases of Q1 and Q2. For example, with VG = 0V, Q1 conducts heavily and Q2 is off. With none of "I" flowing through RF, the LMH6502's input to output gain is strongly attenuated. With VG = +2V, Q1 is off and the entire signal current flows through Q2 to RF producing maximum gain. With VG set to 1V, the bases of Q1 and Q2 are set to approximately the same voltage, Q1 and Q2 have the same collector currents - equal to one half of the signal current "I", thus the gain is approximately one half the maximum gain.
CHOOSING RF & RG Maximum input amplitude and maximum gain are the two key specifications that determine component values in a LMH6502 application. The output stage op amp is a current-feedback type amplifier optimized for RF = 1k. RG can then be computed as:
(1) To determine whether the maximum input amplitude will overdrive the LMH6502, compute: (2) VDMAX = (RG + 3.0) x 1.70mA the maximum differential input voltage for linear operation. If the maximum input amplitude exceeds the above VDMAX limit, then LMH6502 should either be moved to a location in the signal chain where input amplitudes are reduced, or the LMH6502 gain AVMAX should be reduced or the values for RG and RF should be increased. The overall system performance impact is different based on the choice made. If the input amplitude is reduced, re-compute the impact on signalto-noise ratio. If AVMAX is reduced, post LMH6502 amplifier gain, should be increased, or another gain stage added to make up for reduced system gain. To increase RG and RF, compute the lowest acceptable value for RG: (3) RG > 590 x VDMAX - 3 Operating with RG larger than this value insures linear operation of the input buffers. RF may be computed from selected RG and AVMAX: RF should be > = 1k for overall best performance, however RF < 1k can be implemented if necessary using a loop gain reducing resistor to ground on the inverting summing node of the output amplifier (see application note QA-13 for details). ADJUSTING OFFSET Offset can be broken into two parts; an input-referred term and an output-referred term. The input-referred offset shows up as a variation in output voltage as VG is changed. This can be trimmed using the circuit in Figure 2 by placing a low frequency square wave (VLOW = 0V, VHIGH = 2V into VG with
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FIGURE 1. LMH6502 Block Diagram
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LMH6502
Application Information
(Continued)
NOISE Figure 3 describes the LMH6502's output-referred spot noise density as a function of frequency with AVMAX = 10V/V. The plot includes all the noise contributing terms. However, with both inputs terminated in 50, the input noise contribution is minimal. At AVMAX = 10V/V, the LMH6502 has a typical flatinput-referred spot noise density (ein) of 7.7nV/ band. For applications extending well into the flat-band region, the input RMS voltage noise can be determined from the following single-pole model:
VIN = 0V, the input referred VOS term shows up as a small square wave riding a DC value. Adjust R10 to null the VOS square wave term to zero. After adjusting the input-referred offset, adjust R14 (with VIN = 0, VG = 0) until VOUT is zero. Finally, for inverting applications VIN may be applied to pin 6 and the offset adjustment to pin 3. These steps will minimize the output offset voltage. However, since the offset term itself varies with the gain setting, the correction is not perfect and some residual output offset will remain at in-between VG's. Also, this offset trim does not improve output offset temperature coefficient.
(5)
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FIGURE 2. Nulling the output offset voltage GAIN ACCURACY Defined as the actual gain compared against the theoretical gain at a certain VG (results expressed in dB). Theoretical gain is given by:
FIGURE 3. Output Referred Voltage Noise vs. Frequency CIRCUIT LAYOUT CONSIDERATIONS & EVALUATION BOARD A good high frequency PCB layout including ground plane construction and power supply bypassing close to the package are critical to achieving full performance. The amplifier is sensitive to stray capacitance to ground at the I- input (pin 12); keep node trace area small. Shunt capacitance across the feedback resistor should not be used to compensate for this effect. For best performance at low maximum gains (AVMAX < 10) +RG and -RG connections should be treated in a similar fashion. Capacitance to ground should be minimized by removing the ground plane from under the body of RG.. Parasitic or load capacitance directly on the output (pin 10) degrades phase margin leading to frequency response peaking. The LMH6502 is fully stable when driving a 100 load. With reduced load (e.g. 1k) there is a possibility of instability at very high frequencies beyond 400MHz especially with a capacitive load. When the LMH6502 is connected to a light load as such, it is recommended to add a snubber network to the output (e.g. 100 and 39pF in series tied between the LMH6502 output and ground). CL can also be isolated from the output by placing a small resistor in series with the output (pin 10). Component parasitics also influence high frequency results. Therefore it is recommended to use metal film resistors such as RN55D or leadless components such as surface mount devices. High profile sockets are not recommended.
(4) Where K = 1.72 (nominal) & VC = 90mV @ room temperature. For a VG range, the value specified in the tables represents the worst case accuracy over the entire range. The "Typical" value would be the worst case difference between the "Typical Gain" and the "Theoretical gain". The "Max" value would be the worst case difference between the max/min gain limit and the "Theoretical gain". GAIN MATCHING Defined as the limit on gain variation at a certain VG (expressed in dB). Specified as "Max" only (no "Typical"). For a VG range, the value specified represents the worst case matching over the entire range. The "Max" value would be the worst case difference between the max/min gain limit and the typical gain.
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LMH6502
Application Information
(Continued)
National Semiconductor suggests the following evaluation boards as a guide for high frequency layout and as an aid in device testing and characterization: Device LMH6502MA Package SOIC-14 Evaluation Board Part Number CLC730033
OPERATING AT LOWER SUPPLY VOLTAGES The LMH6502 is rated for operation down to 5V supplies (V+ -V-). There are some specifications shown for operation at 2.5V within the data sheet (i.e. Frequency Response, CMRR, PSRR, Gain vs. VG, etc.). Compared to 5V operation, at lower supplies: a) VG range shifts lower. Here are the approximate expressions for various VG voltages as a function of V+: TABLE 1. VG Definition Based on V+ VG VG_MIN VG_MID VG_MAX Definition Gain Cut-off AVMAX/2 AVMAX Expression (V) 0.2 x V+ -1 0.2 x V+ 0.2 x V+ +1
The evaluation board is shipped when a device sample request is placed with National Semiconductor SINGLE SUPPLY OPERATION It is possible to operate the LMH6502 with a single supply. Two examples are shown in Figure 4 & Figure 5.
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FIGURE 4. AC Coupled Single Supply VGA
b) VG_LIMIT (maximum permissible voltage on VG) is reduced. This is due to limitations within the device arising from transistor headroom. Beyond this limit, device performance will be affected (non-destructive). This could reveal itself as premature high frequency response rolloff. With 2.5V supplies, VG_LIMIT is below 1.1V whereas VG = 1.5V is needed to get maximum gain. This means that operating under these conditions has reduced the maximum permissible voltage on VG to a level below what is needed to get Max gain. If supply voltages are asymmetrical with V+ being lower, further "pinching" of VG range could result; for example, with V+ = 2V, and V- = -3V, VG_LIMIT = 0.40V which results in maximum gain being 2.5dB less than what would be expected when VS is higher. c) "Max_gain" reduces. There is an intrinsic reduction in max gain when the total supply voltage is reduced (see Typical Performance Characteristics plots for Gain vs. VG (VS = 2.5V). In addition, there is the more drastic mechanism described in "b" above. Beyond VG_LIMIT, high frequency response is also effected.
Application Circuits
AGC LOOP Figure 6 shows a typical AGC circuit. The LMH6502 is followed up with a LMH6714 for higher overall gain. The output of the LMH6714 is rectified and fed to an inverting integrator using a LMH6657 (wideband voltage feedback op amp). When the output voltage, VOUT, is too large the integrator output voltage ramps down reducing the net gain of the LMH6502 and VOUT. If the output voltage is too small, the integrator ramps up increasing the net gain and the output voltage. Actual output level is set with R1. To prevent shifts in DC output voltage with DC changes in input signal level, trim pot R2 is provided. AGC circuits are always limited in the range of input signals over which constant output level can be maintained. In this circuit, we would expect that reasonable AGC action could be maintained for at least 40dB. In practice, rectifier dynamic range limits reduce this slightly.
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FIGURE 5. Transformer Coupled Single Supply VGA
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LMH6502
Application Circuits
(Continued)
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FIGURE 6. Automatic Gain Control (AGC) Loop FREQUENCY SHAPING Frequency Shaping Frequency shaping and bandwidth extension of the LMH6502 can be accomplished using parallel networks connected across the RG ports. The network shown in the Figure 7 schematic will effectively extend the LMH6502's bandwidth.
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FIGURE 7. Frequency Shaping
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LMH6502 Wideband, Low Power, Linear-in-dB Variable Gain Amplifier
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Pin SOIC NS Package Number M14A
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