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| BS228 / BS2216 Utopia Level 2 Slave Bridges Device Datasheet Version 1.0 - July 2001 Utopia Level 2 Slave/Slave Bridge Datasheet 1 BS228 / BS2216 Utopia Level 2 Slave Bridges Device Datasheet Version 1.0 - July 2001 CONTENTS 1 2 3 4 5 6 7 INTRODUCTION ............................................................................................................................. 3 1.1 UTOPIA OVERVIEW...................................................................................................................... 3 UTOPIA SLAVE/SLAVE BRIDGE APPLICATION......................................................................... 4 UTOPIA LEVEL 2 BRIDGE CORE FEATURES............................................................................. 5 APPLICATION................................................................................................................................. 6 CORE PINOUT ................................................................................................................................ 7 5.1 SIGNAL DESCRIPTIONS ................................................................................................................ 8 GLOBAL SIGNAL DISTRIBUTION .............................................................................................. 12 FUNCTIONAL DESCRIPTION - UTOPIA INTERFACE .............................................................. 13 7.1 UTOPIA INTERFACE SINGLE PHY TRANSMIT INTERFACE ............................................................. 13 Cell Level Transfer - Single Cell ................................................................................................... 13 Cell Level Transfer - Back to Back Cells.......................................................................................13 7.2 UTOPIA INTERFACE SINGLE PHY RECEIVE INTERFACE ............................................................... 14 Cell Level Transfer - Single Cell ................................................................................................... 14 Cell Level Transfer - Back to Back Cells.......................................................................................15 8 9 CORE MANAGEMENT AND ERROR HANDLING ...................................................................... 16 COMPLEXITY AND PERFORMANCE SUMMARY...................................................................... 17 9.1 9.2 10 10.1 10.2 10.3 10.4 10.5 11 12 TIMING PARAMETERS DEFINITION .............................................................................................. 17 ECLIPSE IMPLEMENTATION ........................................................................................................ 18 DEVICE PINOUT ....................................................................................................................... 20 SIGNALS OVERVIEW .................................................................................................................. 20 208 PIN PQFP (PQ208) PINOUT TABLE ................................................................................... 22 208 PIN PQFP (PQ208) DEVICE DIAGRAM ............................................................................... 23 280 PIN FPBGA (PT280) PINOUT TABLE.................................................................................. 24 280 PIN FPGBA (PT280) DEVICE DIAGRAM ............................................................................. 25 REFERENCES........................................................................................................................... 26 CONTACT.................................................................................................................................. 26 2 BS228 / BS2216 Utopia Level 2 Slave Bridges Device Datasheet Version 1.0 - July 2001 1 Introduction 1.1 Utopia Overview The Utopia (Universal Test & Operations PHY Interface for ATM) interface is defined by the ATM Forum to provide a standard interface between ATM devices and ATM PHY or SAR (segmentation and Re-assembly) devices. Higher Layers AAL Management Master Utopia Slave ATM Master Utopia Slave PHY Figure 1: Utopia Reference Model The Utopia Standard defines a full duplex bus interface with a Master/Slave paradigm. The Slave interface responds to the requests from the Master. The Master performs PHY arbitration and initiates data transfers to and from the Slave device. The ATM forum has standardized the Utopia Levels 1 (L1) to 3 (L3). Each level extends the maximum supported interface speed from OC3, 155Mbps (L1) over OC12, 622Mbps (L2) to 3.2Gbit/s (L3). The following Table 1 gives an overview of the main differences in these three levels. Table 1: Utopia Level Differences Utopia Level 1 2 3 Interface Width 8 bit 8 bit, 16 bit 8 bit, 32 bit Max. Interface Speed 25 MHz 50 MHz 104MHz Theoretic (typical) Throughput 200Mbps (typ. OC3 155Mbps) 800Mbps (typ. OC12 622MBps) 3.2Gbps (typ. OC 48 2.5GBps) Utopia Level 1 implements an 8-bit interface running at up to 25MHz. Level 2 adds a 16 Bit interface and increases the speed to 50MHz. Level 3 extends the interface further by a 32 Bit word-size and speeds up to 104MHz providing rates up to 3.2 Gbit/s over the interface. 3 BS228 / BS2216 Utopia Level 2 Slave Bridges Device Datasheet Version 1.0 - July 2001 In addition to the differences in throughput, Utopia Level 2 uses a shared bus offering to physically share a single interface bus between one master and up to 31 slave devices (Multi-PHY or MPHY operation). This allows the implementation of aggregation units that multiplex several slave devices to a single Master device. The Level 1 and Level 3 are point-to-point only, whereas Level 1 has no notion of multiple slaves. Level 3 still has the notion of multiple slaves, but they must be implemented in a single physical device connected to the Utopia Interface. 2 Utopia Slave/Slave Bridge Application As it is not possible to connect two Master devices together, the Slave/Slave Bridge provides the necessary interfaces to convey between two Master devices as shown in Figure 2. Utopia Master Utopia Slave Utopia Slave Utopia Master ATM PHY Device ATM Layer Device Slave/Slave Bridge Figure 2: Utopia Slave Bridge The Bridge automatically transfers data as soon as it becomes available from one side to the other. Internal asynchronous FIFOs enable independent clock domains for each interface. 4 BS228 / BS2216 Utopia Level 2 Slave Bridges Device Datasheet Version 1.0 - July 2001 3 Utopia Level 2 Bridge Core Features * * * * * * * * * * * * * * Implements two Utopia L2 Slaves providing a solution to bridge Utopia Master devices Compliant with ATM-Forum af-phy-0039.000, June 1995 Available with 8bit (BS228), 16bit (BS2216) data bus widths, single PHY Meets 50MHz performance offering up to 800Mbps cell rate transfers Single chip solution for improved system integration Support cell level transfer mode Cell and clock rate decoupling with on chip FIFOs Up to 1.5 KByte of on chip FIFO per data direction Integrated management interface and built-in errored cell discard ATM Cell size programmable via external pins from 16 to 128 bytes Optional Utopia parity generation/checking enable/disable via external pin Built in JTAG port (IEEE1149 compliant) Simulation model available for system level verification (Contact Quicklogic or MorethanIP for details) Solution also available as flexible Soft-IP core, delivered with a full device modelization and verification testbenches. 5 BS228 / BS2216 Utopia Level 2 Slave Bridges Device Datasheet Version 1.0 - July 2001 4 Application Master RxClk RxClav RxEnb* RxAddr[4:0] RxData[31:0] RxSoc RxEnb* RxAddr[4:0] RxData[31:0] RxSoc Ing. Port RxClk RxClav Slave Egress Port Slave TxClk TxClav TxEnb* TxAddr[4:0] TxData[31:0] TxSoc TxClk TxClav TxEnb* TxAddr[4:0] Master TxData[31:0] TxSoc TxClav TxEnb* TxAddr[4:0] TxData[31:0] TxSoc TxClk Egress Port TxClav TxEnb* TxAddr[4:0] TxData[31:0] TxSoc TxClk RxClav RxEnb* Ing. Port RxAddr[4:0] RxData[31:0] RxSoc RxClk RxClav RxEnb* RxAddr[4:0] RxData[31:0] RxSoc RxClk ATM Device 1 Slave/Slave Bridge ATM Device 2 Figure 3: Slave/Slave Bridge connecting two Master Devices Data flows from the Bridge's TX Ports to the corresponding RX Ports on the other side of the bridge. 6 BS228 / BS2216 Utopia Level 2 Slave Bridges Device Datasheet Version 1.0 - July 2001 5 Core Pinout On the Utopia interfaces, the Core implements all the required Utopia signals and provides all the Utopia optional signals (Indicated by an `O' in the following tables). The optional Utopia signals are activated during the Core configuration and inactive Utopia signals should be left unconnected (Outputs) or tied to a zero logic level (inputs) as specified in the following Tables. In addition to the Utopia Interface signals, error indication signals are available for error monitoring or statistics. An error indication always shows that a cell has been discarded by the bridge. Possible errors are parity or cell-length errors on the receive interface of the corresponding Utopia Interfaces. All Utopia interfaces work in the same transfer mode (cell level). A mix is not possible. To identify the sides of the core the notion "WEST" and "EAST" for the corresponding interfaces will be used. WEST Slave Interface wrxclk EAST Slave Interface etxclav[3:0] etxenb etxaddr[4:0] Utopia Receive wrxclav[3:0] wrxenb wrxaddr[4:0] wrxdat[N:0] wrxsoc wrxprty Ingress Egress etxdat[N:0] etxsoc etxprty etxclk Utopia Transmit wtxclav[3:0] Utopia Transmit wtxenb wtxaddr[4:0] wtxdat[N:0] wtxsoc wtxprty wtxclk Utopia L2 Slave/Slave Bridge erxclk erxclav[3:0] erxenb erxaddr[4:0] erxdat[N:0] erxsoc(0) erxprty(0) Utopia Receive Egress Ingress Error Indication from Transmit wtx_err wtx_err_stat[1:0] etx_err etx_err_stat[1:0] Error Indication from Transmit prty_en reset cellsize[7:0] Configuration Figure 4: Utopia Level 3 Slave/Slave Bridge Top Entity 7 BS228 / BS2216 Utopia Level 2 Slave Bridges Device Datasheet Version 1.0 - July 2001 5.1 Signal descriptions Table 2: Global Signal Pin reset Mode In Active high chip reset. Description Table 3: Device Management Interface Pin Mode Description Transmit error indication on west interface. When driven high, indicates that an errored cell (Wrong parity or wrong length) was received from the device connected to the west interface and is discarded. Transmit error status information for west interface. When wtx_err is driven, indicates the error status of the discarded cell: * wtx_err_stat(1:0) Out * wtx_err_stat(0) : When set to `1' indicates that a cell is discarded because of a parity error. wtx_err_stat(1) : When set to `1' indicates that a cell is discarded because it has a wrong length (Consecutive assertion of ut_tx_soc on the Utopia interface within less than a complete cell time). wtx_err Out etx_err Out Transmit error indication on east interface. When driven high, indicates that an errored cell (Wrong parity or wrong length) was received from the device connected to the east interface side. Transmit error status information for east receive interface. When etx_err is driven, indicates the error status of the discarded cell: * etx_err_stat(1:0) Out etx_err_stat(0) : When set to `1' indicates that a cell is discarded because of a parity error. etx_err_stat(1) : When set to `1' indicates that a cell is discarded because it has a wrong length (Consecutive assertion of ut_tx_soc on the Utopia interface within less than a complete cell time). * Note: wtx_.. signals are sampled with west transmit clock (wtxclk). etx_.. signals are sampled with west receive clock (wrxclk). Table 4: West Utopia Slave Transmit Interface Pin wtxclk wtxdata[N:0] Mode In In Description 50MHz transmit byte clock. The Core samples all Utopia Transmit signals on txclk rising edge. Transmit data bus. The width of the data bus can be 8 or 16 bit. Bit N is the MSB. 8 BS228 / BS2216 Utopia Level 2 Slave Bridges Device Datasheet Version 1.0 - July 2001 Transmit data bus parity. Standard odd or non-standard even parity can be optionally checked by the connected Slave. When the parity check is disabled during the Core configuration, or not used in the design, the pin txprty should be tied to '0'. Transmit start of cell. Asserted by the Master to indicate that the current word is the first word of a cell. Active low transmit data transfer enable. Cell buffer available. Asserted in octet level transfers to indicate to the Master that the FIFO is almost full (Active low) or, in cell level transfers, to indicate to the Master that the PHY port FIFO has space to accept one cell. Extra FIFO Full / Cell buffer available. In MPHY mode and when direct status indication is selected during the Core configuration, one txclav signal is implemented per PHY port. The maximum number of clav signals is limited to four. Utopia transmit address. When the Core operates in MPHY mode, address bus used during polling and slave port selection. Bit 4 is the MSB. txaddr(4:0) becomes optional (And should be left open) when the Core does not operate in MPHY mode. Note: (O) indicates optional signals. Table 5: West Utopia Slave Receive Interface Pin wrxclk wrxdata[N:0] Mode In Out Description 50MHz receive byte clock. The Core samples all Utopia Receive signals on rxclk rising edge. Receive data bus. The width of the data bus can be 8,16 or 32 bit. Bit N is the MSB. Receive data bus parity. Standard odd or non standard even parity can be optionally generated by the Utopia Slave Core. When the parity generation is disabled during the Core configuration, the pin rxprty can be let unconnected. Receive start of cell. Asserted to indicate that the current word is the first word of a cell. Active low transmit data transfer enable. Cell buffer available. Asserted in octet level transfers to indicate to the Master that the FIFO is almost empty (Active low) or, in cell level transfers, to indicate to the Master that the PHY port FIFO has space one cell available in the FIFO. Extra FIFO Full / Cell buffer available. In MPHY mode and when direct status indication is selected, one rxclav signal is implemented per PHY port. The maximum number of clav signals wtxprty In wtxsoc wtxenb In In wtxclav[0] Out wtxclav[3:1] (O) Out wtxaddr[4:0] In wrxprty (O) Out wrxsoc wrxenb Out In wrxclav[0] Out wrxclav[3:1] (O) Out 9 BS228 / BS2216 Utopia Level 2 Slave Bridges Device Datasheet Version 1.0 - July 2001 is limited to four. Utopia receive address. When the Core operates in MPHY mode, address bus used during polling and slave port selection. Bit 4 is the MSB. txaddr(4:0) becomes optional (And should be left open) when the Core does not operate in MPHY mode. Table 6: East Utopia Slave Transmit Interface Pin etxclk etxdata[N:0] Mode In In Description 50MHz transmit byte clock. The Core samples all Utopia Transmit signals on txclk rising edge. Transmit data bus. The width of the data bus is user programmable and can be set to 8 or 16 or 32 bit. Bit N is the MSB. Transmit data bus parity. Standard odd or non-standard even parity can be optionally checked by the connected Slave. When the parity check is disabled during the Core configuration, or not used in the design, the pin txprty should be left open. Transmit start of cell. Asserted by the Master to indicate that the current word is the first word of a cell. Active low transmit data transfer enable. Cell buffer available. Asserted in octet level transfers to indicate to the Master that the FIFO is almost full (Active low) or, in cell level transfers, to indicate to the Master that the PHY port FIFO has space to accept one cell. Extra FIFO Full / Cell buffer available. In MPHY mode and when direct status indication is selected during the Core configuration, one txclav signal is implemented per PHY port. The maximum number of clav signals is limited to four. Utopia transmit address. When the Core operates in MPHY mode, address bus used during polling and slave port selection. Bit 4 is the MSB. txaddr(4:0) becomes optional (And should be left open) when the Core does not operate in MPHY mode. Note: (O) indicates optional signals. Table 7: East Utopia Slave Receive Interface Pin erxclk Mode In Description 50MHz receive byte clock. The Core samples all Utopia Receive signals on rxclk rising edge. wrxaddr(4:0) In etxprty In etxsoc etxenb In In etxclav[0] Out etxclav[3:1] (O) Out etxaddr[4:0] In 10 BS228 / BS2216 Utopia Level 2 Slave Bridges Device Datasheet Version 1.0 - July 2001 Receive data bus. The width of the data bus can be 8,16 or 32 bit. Bit N is the MSB. Receive data bus parity. Standard odd or non standard even parity can be optionally generated by the Utopia Slave Core. When the parity generation is disabled during the Core configuration, the pin rxprty can be let unconnected. Receive start of cell. Asserted to indicate that the current word is the first word of a cell. Active low transmit data transfer enable. Cell buffer available. Asserted in octet level transfers to indicate to the Master that the FIFO is almost empty (Active low) or, in cell level transfers, to indicate to the Master that the PHY port FIFO has space one cell available in the FIFO. Extra FIFO Full / Cell buffer available. In MPHY mode and when direct status indication is selected, one rxclav signal is implemented per PHY port. The maximum number of clav signals is limited to four. Utopia receive address. When the Core operates in MPHY mode, address bus used during polling and slave port selection. Bit 4 is the MSB. taddr(4:0) becomes optional (And should be left open) when the Core does not operate in MPHY mode. Table 8: Device Configuration Pins Pin Mode Description Enable parity checking on the Utopia interface. prty_en In If disabled (tied to 0), the wrx_err_stat(0) signal can be ignored and left open and the rx parity input should be tied to 0. Also the tx parity pins can be left open. Define cellsize: sets the size in bytes of a cell. Binary value to be set usually by board wiring. For 16 bit implementations the size must be a multiple of 2 and cellsize[0] becomes a "not connected" and should be left open. erxdata[N:0] Out erxprty (O) Out erxsoc erxenb Out In erxclav[0] Out rxclav[3:1] (O) Out erxaddr(4:0) In cellsize[7:0] In The configuration pins are not intended for change during operation. They are usually board wired to configure the device for operation. 11 BS228 / BS2216 Utopia Level 2 Slave Bridges Device Datasheet Version 1.0 - July 2001 6 Global Signal Distribution The externally provided Utopia Transmit and Receive clocks are connected to global resources to provide low skew and fast chip level distribution. In both data directions, the two corresponding Utopia Interfaces are decoupled by asynchronous FIFOs. Therefore each interface runs completely independently each at its own tx and rx clocks which typically are 50 MHz. The Error indications of the two receive interfaces are always sampled within the west clock domains. The errors of the east tx (receiving) interface is available on the etx_err signal, which is handled using the west clock domain (wrxclk). The west tx (receiving) error is directly derived from the west tx block (wtxclk). wrxclk WEST Interface (SLAVE) read write EAST Interface (SLAVE) etxclk (Ingress clock) RX TX ~ ~ etx_err wtxclk (Egress clock) TX wtx_err RX ~ write erxclk read ~ Clocks West Clocks East Figure 5: Slave/Slave Bridge Clock Distribution 12 BS228 / BS2216 Utopia Level 2 Slave Bridges Device Datasheet Version 1.0 - July 2001 7 Functional Description - Utopia Interface The Utopia Bridge operates in single PHY mode. Therefore no address bus and only a single status pin (clav[0]) per direction is used on the interfaces. 7.1 Utopia Interface Single PHY Transmit Interface The Transmit interface is controlled by the Master. The transmit interface has data flowing in the same direction as the ATM enable ut_tx_enb. The ATM transmit block generates all output signals on the rising edge of the ut_txclk. Transmit data is transferred from the Master to Slave via the following procedure. The Slave indicates it can accept data using the ut_txclav signal, then the Master drives data onto ut_txdat and asserts ut_txenb. The Slave controls the flow of data via the ut_txclav signal. Cell Level Transfer - Single Cell The Slave asserts ut_txclav 1 when it is capable of accepting the transfer of a whole cell. The Master asserts ut_txenb (Low) to indicates that it drives valid data to the Slave 2. Together with the first octet of a cell, the Master device asserts ut_txsoc for one clock cycle 3. To ensure that the Master does not cause transmit overrun, the Slave deasserts ut_txclav at least 4 cycles before the end of a cell if it cannot accept the immediate transfer of the subsequent cell 4. The Master can pause the cell transfer by de-asserting ut_txenb 5. To complete the transfer to the Slave, the Master de-asserts ut_tx_enb 6. 4 1 2 3 5 6 ut_txclk ut_txclav_dir ut_txenb ut_txsoc /ut_txdat ut_txprty 1 1 19 1A 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 Figure 6: Single Cell Transfer - Cell Level Transfer Cell Level Transfer - Back to Back Cells When, during a cell transfer, the Slave is able to receive a subsequent cell, the Master can keep ut_txenb asserted between two cells 1 and asserts ut_txsoc, to start a new cell transfer, immediately after the last octet of the previous cell 2. 13 BS228 / BS2216 Utopia Level 2 Slave Bridges Device Datasheet Version 1.0 - July 2001 1 ut_txclk ut_txclav ut_txenb ut_txsoc ut_txdat ut_txprty Cell N 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F 0010 0011 0012 0013 0014 0015 0016 0017 0018 0019 001A 001B 0001 0002 0003 0004 0005 0006 0007 2 0008 0009 000A 000B 000C 000D 000E 000F 0010 0011 0012 0013 0014 0015 0016 0017 0018 0019 001A 001B 0000 Cell N+1 Figure 7: Back to Back Cell Transfer - Cell Level Transfer 7.2 Utopia Interface Single PHY Receive Interface The Receive interface is controlled by the Master. The receive interface has data flowing in the opposite direction to the Master enable ut_rxenb. Receive data is transferred from the Slave to Master via the following procedure. The Slave indicates it has valid data, then the Master asserts ut_rxenb to read this data from the Slave. The Slave indicates valid data (thereby controlling the data flow) via the ut_rxclav signal. Cell Level Transfer - Single Cell The Slave asserts ut_rx_clav when it is ready to send a complete cell to the Master device 1. The Master interface asserts ut_rxenb to start the cell transfer. The Slave samples ut_rxenb and starts driving data 2. The Slave asserts ut_rxsoc together with the cell first word to indicate the start of a cell 3. The Master can pause a transfer by de-asserting ut_rxenb 4. The Slave samples high ut_rxenb and stops driving data 5. To resume the transfer, the Master re-asserts ut_rxenb 6. The Slave samples low ut_rxenb and starts driving valid data 7. The Master drives ut_txenb high one before the expected end of the current cell if the Slave has no more cell to transfer 8. The Slave de-asserts ut_rxclav to indicate that no new cell is available 9. 14 BS228 / BS2216 Utopia Level 2 Slave Bridges Device Datasheet Version 1.0 - July 2001 9 1 3 4 6 8 ut_rclk ut_rclav ut_renb ut_rsoc ut_rdat ut_rprty Z Z 2 5 7 Figure 8: Single Cell Transfer - Cell Level Transfer Cell Level Transfer - Back to Back Cells If the Master keeps ut_rxenb asserted at the end of a cell transfer 1 and if the Slave has a new cell to send, the Slave keeps ut_rxclav asserted 2 and immediately drives the new cell asserting ut_rxsoc to indicate the start of a new cell 3. 1 2 3 ut_rxclk ut_rxclav ut_rxenb ut_rxsoc ut_rxdat ut_rxprty Cell N Cell N+1 Figure 9: Back to Back Cells Transfer - Cell Level Transfer Note: If the Master keeps ut_rxenb asserted at the end of a packet and if the Slave does not have a new cell available, the Slave de-asserts ut_rxclav and the data of the bus ut_rxdat are invalid. 15 BS228 / BS2216 Utopia Level 2 Slave Bridges Device Datasheet Version 1.0 - July 2001 8 Core Management and Error Handling On Egress, the Core is designed to handle and report Utopia errors such as Parity error or wrong cell length. Errored cells are discarded with an error status indication provided to the user PHY application. When an errored cell is received on the Utopia interface, the Core discards the complete cell and provides a cell discard indication to the User PHY application (Signal eg_err(n) asserted) 1 together with a cell discard status (Signal eg_err_stat(1:0)) 2. Note: eg_err is routed to the corresponding wtx_err and etx_err respectively (see Figure 4). 1 ff_eg_clk(0) ff_eg_cav(0) ff_eg_rdy(0) ff_eg_dval(0) ff_eg_soc(0) ff_eg_data(0) ff_eg_err(0) ff_eg_err_stat(0) 000A 000B 000C 000D 000E Cell N Cell N+2 2 Figure 10: Cell Discard Indication Table 9: Error Status Word Bit Coding Error Status Bit 0 Name PARITY_ERR Description Valid when wtx/etx_err is asserted. If set to one indicates that a cell is discarded with a parity error decoded by the Core. Valid when wtx/etx_err is asserted. If set to one indicates that a cell is discarded with a cell length error detected on the Utopia interface. 1 LENGTH_ERR The signals are sampled on the corresponding clocks from the west interface: * * etx_... sampled with wrxclk (west receive clock) wtx_... sampled with wtxclk (west transmit clock) 16 BS228 / BS2216 Utopia Level 2 Slave Bridges Device Datasheet Version 1.0 - July 2001 9 Complexity and Performance Summary 9.1 Timing Parameters Definition ut_tclk ut_rclk tco ut_rxdat, ut_rxsoc ut_rxprty, ut_rxenb ut_rxclav, ut_txclav Figure 11: Tco Timing Parameter Definition ut_tclk ut_rclk tsu ut_txdat, ut_txsoc ut_txprty, ut_txaddr ut_rxaddr, ut_txenb ut_rxenb Figure 12: Tsu Timing Parameter Definition 17 BS228 / BS2216 Utopia Level 2 Slave Bridges Device Datasheet Version 1.0 - July 2001 9.2 Eclipse Implementation Table 10: Eclipse Implementation Summary FIFO depth Utopia Interface MPHY Ingress Egress Parity Cells Selected Options Implementation RAM Blocks 16 Bit 1 256 per port 512 per port 128 per port 256 per port odd 934 16 8 Bit 1 odd 802 18 Table 11: 16-Bit Utopia Interface Timing Characteristics QL6325-PQ208 typ Parameter -5 -6 10.0 2.0 65 72 116 101 50 ns ns MHz MHz MHz MHz ns Max Unit tco tsu wrxclk wtxclk erxclk etxclk minimum reset time 10.0 2.5 10.1 Note: QL6325 with timing model "worst" used. 18 BS228 / BS2216 Utopia Level 2 Slave Bridges Device Datasheet Version 1.0 - July 2001 Table 12: 8-Bit Utopia Interface Timing Characteristics QL6250-PQ208 typ Parameter -5 -6 6.5 2.1 59 73 111 102 ns ns MHz MHz MHz MHz ns Max Unit tco tsu wrxclk wtxclk erxclk etxclk minimum reset time 7.5 2.5 9.1 3.0 47 52 60 57 50 Note: QL6250 with timing model "worst" used. 19 BS228 / BS2216 Utopia Level 2 Slave Bridges Device Datasheet Version 1.0 - July 2001 10 Device Pinout 10.1 Signals Overview Signals wrxclk, wrxclav, wrxenb*, wrxdat, wrxsoc wtxclk, wtxclav, wtxenb*, wtxdata, wtxsoc wtx_err, wtx_err_stat erxclk, erxclav, erxenb*, erxdata, erxsoc etxclk, etxclav, etxenb*, etxdata, etxsoc etx_err, etx_err_stat prty_en, cellsize Description West Utopia Receive Interface. West Utopia Transmit Interface. West Interface error indication (sampled with wtxclk). East Utopia Receive Interface. East Utopia Transmit Interface. East Interface error indication (sampled with wrxclk). Configuration Pins to be board wired. BS228: Cellsize[0] only for 8-bit data busses. BS2216: Cellsize [0] Should be tied to GND. reset GND VCC clk(x) IOCTRL(x) VCCIO(x) INREF(x) PLLRST(x) PLLOUT(x) VCCPLL(x) GNDPLL(x) TCK, TRSTB TMS, TDI TDO iov nc *: active low signal not connected. should be left open JTAG signals. connect to GND JTAG signals. connect to VCC JTAG signal. leave open IO Power 3.3 V connect to GND connect to GND or VCC connect to GND or VCC Active high device reset Ground Device Power 3.3 V unused clock inputs should be tied to GND 20 BS228 / BS2216 Utopia Level 2 Slave Bridges Device Datasheet Version 1.0 - July 2001 Unused Pins (data busses) in the following tables are to be handled like "nc". 21 BS228 / BS2216 Utopia Level 2 Slave Bridges Device Datasheet Version 1.0 - July 2001 10.2 208 Pin PQFP (PQ208) Pinout Table PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Function pllrst(3) vccpll(3) gnd gnd wtxclav[0] wtxprty wtxenb vccio(a) wtxsoc wtxdat[0] ioctrl(a) vcc inref(a) ioctrl(a) wtxdat[1] wtxdat[2] wtxdat[3] wtxdat[4] vccio(a) wtxdat[5] gnd wtxdat[6] tdi wtxclk clk(1) vcc wrxclk clk(3) vcc clk(4) wtxdat[7] wtxdat[8] gnd vccio(b) wtxdat[9] wtxdat[10] wtxdat[11] wtxdat[12] ioctrl(b) inref(b) ioctrl(b) wtxdat[13] wtxdat[14] vccio(b) wtxdat[15] vcc nc wrxclav[0] gnd tdo pllout(1) gndpll(2) PIN 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 Function gnd vccpll(2) pllrst(2) vcc wrxprty gnd wrxenb vccio(c) wrxsoc wrxdat[0] wrxdat[1] wrxdat[2] wrxdat[3] wrxdat[4] ioctrl(c) inref(c) ioctrl(c) wrxdat[5] wrxdat[6] vccio(c) wrxdat[7] wrxdat[8] gnd vcc wrxdat[9] trstb vcc wrxdat[10] wrxdat[11] wrxdat[12] gnd vccio(d) wrxdat[13] vcc wrxdat[14] wrxdat[15] vcc wtx_err wtx_err_stat[0] ioctrl(d) inref(d) ioctrl(d) wtx_err_stat[1] etx_err etx_err_stat[0] vccio(d) etx_err_stat[1] reset gnd pllout(0) gnd gndpll(1) PIN 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 Function pllrst(1) vccpll(1) etxclav[0] gnd etxprty etxenb vccio(e) etxsoc vcc etxdat[0] etxdat[1] etxdat[2] ioctrl(e) inref(e) ioctrl(e) etxdat[3] etxdat[4] vccio(e) gnd etxdat[5] etxdat[6] etxdat[7] clk(5) etxclk vcc erxclk vcc clk(8) tms etxdat[8] etxdat[9] etxdat[10] gnd vccio(f) etxdat[11] etxdat[12] etxdat[13] etxdat[14] etxdat[15] ioctrl(f) inref(f) vcc ioctrl(f) nc erxclav[0] vccio(f) erxprty erxenb gnd erxsoc pllout(3) gndpll(0) PIN 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Function gnd vccpll(0) pllrst(0) gnd erxdat[0] vccio(g) erxdat[1] erxdat[2] vcc erxdat[3] erxdat[4] erxdat[5] ioctrl(g) inref(g) ioctrl(g) erxdat[6] erxdat[7] iov vcc erxdat[8] vccio(g) gnd erxdat[9] erxdat[10] erxdat[11] vcc tck vcc erxdat[12] erxdat[13] erxdat[14] gnd vccio(h) erxdat[15] cellsize[7] ioctrl(h) cellsize[6] inref(h) vcc ioctrl(h) cellsize[5] cellsize[4] cellsize[3] cellsize[2] cellsize[1] cellsize[0] vccio(h) gnd prty_en pllout(2) gnd gndpll(3) 22 BS228 / BS2216 Utopia Level 2 Slave Bridges Device Datasheet Version 1.0 - July 2001 10.3 208 Pin PQFP (PQ208) Device Diagram Figure 13: PQ208 top view 23 BS228 / BS2216 Utopia Level 2 Slave Bridges Device Datasheet Version 1.0 - July 2001 10.4 PIN A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 280 Pin FPBGA (PT280) Pinout Table Function pllout(3) gndpll(0) etx_err etx_err_stat[0] etx_err_stat[1] ioctrl(f) wtxclav[0] wtxprty wtxenb wtxclk wtxsoc wtxdat[0] wtxdat[1] ioctrl(e) wtxdat[2] wtxdat[3] wtxdat[4] pllrst(1) gnd pllrst(0) gnd wtxdat[5] wtxdat[6] wtxdat[7] inref(f) wtxdat[8] wtxdat[9] tms clk(6) wtxdat[10] wtxdat[11] ioctrl(e) wtxdat[12] wtxdat[13] wtxdat[14] vccpll(1) gndpll(1) pllout(0) wtxdat[15] vccpll(0) wtxdat[16] wtxdat[17] vccio(f) ioctrl(f) wtxdat[18] wtxdat[19] vccio(f) wrxclk vccio(e) wtxdat[20] wtxdat[21] wtxdat[22] vccio(e) wtxdat[23] wtxdat[24] wtxdat[25] wtxdat[26] PIN D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 F1 F2 F3 F4 F5 F15 F16 F17 F18 F19 G1 G2 G3 G4 G5 G15 G16 G17 G18 Function wtxdat[27] wtxdat[28] wtxdat[29] wtxdat[30] wtxdat[31] cellsize[0] prty_en reset clk(8) wrxclav[0] wrxprty wrxenb inref(e) wrxsoc wrxdat[0] wrxdat[1] wrxdat[2] wrxdat[3] wrxdat[4] cellsize[3] cellsize[2] vccio(g) cellsize[1] gnd vcc vcc vcc vcc gnd gnd vcc vcc gnd gnd wrxdat[5] vccio(d) inref(d) ioctrl(d) inref(g) ioctrl(g) cellsize[5] cellsize[4] gnd vcc ioctrl(d) wrxdat[6] wrxdat[7] wrxdat[8] erxdat[31] cellsize[7] ioctrl(g) cellsize[6] vcc vcc wrxdat[9] wrxdat[10] wrxdat[11] PIN G19 H1 H2 H3 H4 H5 H15 H16 H17 H18 H19 J1 J2 J3 J4 J5 J15 J16 J17 J18 J19 K1 K2 K3 K4 K5 K15 K16 K17 K18 K19 L1 L2 L3 L4 L5 L15 L16 L17 L18 L19 M1 M2 M3 M4 M5 M15 M16 M17 M18 M19 N1 N2 N3 N4 N5 N15 Function wrxdat[12] erxdat[27] erxdat[28] erxdat[29] erxdat[30] vcc vcc vcc wrxdat[13] wrxdat[14] wrxdat[15] erxdat[24] erxdat[25] vccio(g) erxdat[26] gnd vcc wrxdat[16] vccio(d) wrxdat[17] wrxdat[18] vcc tck erxdat[22] erxdat[23] gnd gnd wrxdat[19] wrxdat[20] wrxdat[21] trstb erxdat[19] erxdat[20] vccio(h) erxdat[21] vcc gnd wrxdat[22] vccio(c) wrxdat[23] wrxdat[24] erxdat[15] erxdat[16] erxdat[17] erxdat[18] vcc vcc inref(c) wrxdat[25] wrxdat[26] wrxdat[27] ioctrl(h) erxdat[12] erxdat[13] erxdat[14] vcc vcc PIN N16 N17 N18 N19 P1 P2 P3 P4 P5 P15 P16 P17 P18 P19 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 U1 U2 U3 U4 U5 Function wrxdat[28] wrxdat[29] ioctrl(c) ioctrl(c) erxdat[10] erxdat[11] ioctrl(h) inref(h) vcc gnd wrxdat[30] wrxdat[31] wtx_err wtx_err_stat[0] erxdat[7] erxdat[8] vccio(h) erxdat[9] gnd gnd vcc vcc gnd gnd vcc vcc vcc vcc gnd etxdat[3] vccio(c) etxenb wtx_err_stat[1] erxdat[2] erxdat[3] erxdat[4] erxdat[5] erxdat[6] ioctrl(a) etxdat[28] etxdat[24] etxdat[22] etxdat[21] clk(3) etxdat[16] etxdat[12] etxdat[11] etxdat[8] etxdat[4] vccpll(2) etxsoc etxclav[0] erxsoc erxdat[0] vccpll(3) erxdat[1] vccio(a) PIN U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 Function inref(a) etxdat[29] etxdat[25] vccio(a) erxclk vccio(b) etxdat[17] etxdat[13] ioctrl(b) vccio(b) etxdat[5] tdo pllrst(2) etxprty pllout(2) gndpll(3) gnd erxprty erxenb ioctrl(a) etxdat[30] etxdat[26] etxdat[23] clk(1) clk(4) etxdat[18] etxdat[14] inref(b) etxdat[9] etxdat[6] etxdat[1] gndpll(2) gnd gnd pllrst(3) nc nc nc erxclav[0] etxdat[31] etxdat[27] tdi etxclk etxdat[20] etxdat[19] etxdat[15] ioctrl(b) etxdat[10] etxdat[7] etxdat[2] etxdat[0] pllout(1) Note: For BS228: xxxdat[8 .. 31] are "nc". For BS2216: xxxdat[16 .. 31] are "nc". 24 BS228 / BS2216 Utopia Level 2 Slave Bridges Device Datasheet Version 1.0 - July 2001 10.5 280 Pin FPGBA (PT280) Device Diagram WEST TX wtxdat [4 ] wtxda t[3] wtxda t[2 ] wtxda t[1 ] wtxd at [0] wtxs oc wt xclk wtxe nb wt xprty wt xcla v[0] EAST receive error indication e tx_ e rr_s ta t[1]e tx_err_st at [0 ] e tx_e rr A19 GND B19 wtxda t[2 6] A18 A17 A16 I/O wtxda t[14] A15 wt xd at [13] A14 wtx da t[12] A13 A12 I/O wt xdat[11 ] A11 I/O wtxda t[10 ] A10 GCLK/I B10 GCLK/I wrxclk A9 I/O A8 I/O wt xdat[9] A7 wtxda t[8 ] A6 A5 wt xda t[7] A4 I/O wtxda t[6] A3 wtxd at [5] A2 A1 PLLRST1 I/O wtxdat [2 5] I/O wrxda t[0 ] I/O wtxd at [18] I/O wt xda t[16 ] B17 wt xda t[24] B16 wtxda t[23] B14 wtx da t[22] B13 wtxd a t[21] B12 wt xdat[20 ] B11 I/O wrxp rt y B8 I/O wtxda t[19] B6 B5 B4 I/O wtxdat [1 7] B2 GND C2 wtxda t[2 8] B1 PLLRST0 wtxdat [15] PLLOUT0 GNDPLL1 VCCPLL1 I/O wrxda t[4] I/O wrxs oc I/O prt y_en C18 I/O wrxd a t[3] C17 I/O wrxdat [2 ] C16 I/O wrxda t[1] C13 I/O C12 I/O wrxe n b C10 GCLK/I wrxcla v[0 ] C8 I/O res et C6 C5 wtxd a t[31 ] C4 I/O wtxdat [3 0] C3 wt xda t[29 ] C1 wtxdat [27] I/O I/O c ells z e [5] i D19 I/O wrxda t[8] D18 I/O wrxd a t[7] D17 I/O wrxdat [6 ] D16 I/O wrxda t[5] D15 I/O et xdat [8] D14 D12 D11 I/O D10 I/O D8 I/O D4 I/O ce llsize [1] D2 I/O ce llsiz e[2 ] D1 I/O ce llsize [3] I/O E 16 I/O wrxda t[9] E4 I/O ce llsize [4] E2 I/O ce llsiz e[7 ] E1 I/O e rxda t[31] IOCTL wrxda t[1 2] F18 I/O wrxdat [1 1] F17 wrxda t[10] I/O wrxda t[13] G19 I/O wrxda t[1 5] G18 I/O wrxdat [1 4] G16 I/O wrxda t[16] QuickLogic pAS IC QL6325-7PT280C R14 VCC e txd a t[11] F4 I/O ce llsize [6] F3 I/O e rxda t[29 ] G4 erxdat[30] G2 erxdat [2 8] G1 I/O e rxda t[27] I/O erxdat[26] H19 H18 I/O wrxdat [1 7] H17 I/O wrxda t[20] H3 I/O e rxda t[22 ] H2 I/O erxdat [2 5] H1 I/O e rxda t[24] WEST RX I/O wrxda t[1 8] J19 I/O wrxda t[2 4] J18 I/O wrxdat [2 1] J16 I/O wrxda t[19] J4 I/O erxdat[23] J2 I/O erxdat [2 0] J1 I/O e rxda t[15] K18 I/O wrxdat [2 3] K17 I/O wrxda t[25] K16 I/O wrxda t[22] K4 I/O erxdat[21] K3 I/O e rxda t[17 ] L19 I/O wrxda t[2 7] L18 I/O wrxdat [2 6] L16 I/O wrxda t[28] L4 I/O erxdat[18] L2 I/O erxdat [1 6] M19 M18 I/O wtx_ err M17 wrxda t[29] M4 I/O erxdat[14] M3 I/O e rxda t[13 ] M2 I/O erxdat [1 2] M1 I/O e rxda t[10] WEST receive error Indication I/O wt x_e rr_ sta t[0] I/O wrxda t[31] VCC N5 VCC P5 VCC R6 G ND T6 R5 GND e rxda t[6 ] N16 I/O wrxda t[30] N4 I/O erxdat [9] N3 I/O N2 erxdat [1 1] IOCTL wt x_e rr_ sta t[1] I/O e rxd a t[8] P18 I/O e txe nb P17 I/O P 16 I/O e txd a t[3] P1 I/O erxdat [7] INREF erxdat [5] R19 I/O e txcla v[0] R18 I/O e txs oc R16 I/O e txd a t[4] R13 VCC et xd at[12] R12 VCC e tx da t[16 ] R11 VCC T11 GCLK/I U11 VCCIO V11 e txda t[20] R10 GND et xdat [21 ] R9 GND e txda t[2 2] R8 VCC e txdat [24] R7 VCC et xda t[28] R3 VCCIO e rxda t[4] R2 I/O e rxd a t[3] R1 I/O erxdat [2] T19 I/O e txprty T18 T16 e txd a t[5] T15 I/O U15 et xdat [9] T14 I/O U14 T13 I/O et xd at[13] T12 I/O e tx da t[17 ] T10 I/O e rxc lk T9 I/O U9 VCCIO e txda t[2 3] T8 I/O e txdat [25] T7 et xda t[29] T5 T4 I/O erxdat [1] T3 I/O U3 T2 I/O e rxd a t[0] T1 I/O e rxs oc I/O VCCPLL2 I/O U18 U17 TDO etx da t[1] I/O IOCTL I/O U7 et xda t[30] U19 U16 I/O e txd a t[6] U13 et xd at[14] U12 I/O e tx da t[18 ] U10 GCLK/I V10 e txc lk U8 I/O e txdat [26] U6 U5 e rxenb U4 e rxprt y U2 U1 I/O V1 I/O PLLRST2 V19 V18 e txd at [0] VCCIO IOCTL I/O V15 e txda t[10] I/O INREF VCCIO V7 et xda t[31] I/O VCCPLL3 I/O V4 I/O W4 I/O V3 V2 V17 etx da t[2] V16 I/O e txd a t[7] V14 V13 et xd at[15] V12 I/O e tx da t[19 ] V9 I/O W9 TDI V8 I/O e txdat [27] V6 erxcla v[0] V5 GND GNDPLL2 I/O W19 W18 W17 I/O I/O INREF I/O W15 W14 W13 HWCLK GCLK/I W11 I/O W10 GCLK/I I/O IOCTL I/O W7 I/O W6 I/O W5 I/O GND G NDPLL3 P LLOUT2 W3 W2 W1 GND W16 I/O W12 I/O W8 I/O PLLOUT1 I/O I/O IOCTL I/O I/O P LLRS T3 EAST TX Figure 14: PT280 bottom view 25 EAST RX e rxda t[19] device configuration BS228 / BS2216 Utopia Level 2 Slave Bridges Device Datasheet Version 1.0 - July 2001 11 References * * ATM Forum, Utopia Level 2, af-phy-0039.000 Quicklogic, Eclipse Family Datasheet (Preliminary, 8/24/2000) 12 Contact MorethanIP Tel FAX E-Mail Internet : +49 (0) 89 3219599 0 : +49 (0) 89 3219599 1 : info@morethanip.com : www.morethanip.com QuickLogic Corp. Tel : 408 990 4000 (US) : + 44 1932 57 9011 (Europe) : + 49 89 930 86 170 (Germany) : + 852 8106 9091 (Asia) : + 81 45 470 5525 (Japan) E-mail : info@quicklogic.com Internet : www.quicklogic.com 26 |
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