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Components for Entertainment Electronics
2 Band TV Tuner KTS6027, KTS6029 Mixer-Oscillator-PLL with unbalanced IF-Amplifier
Preliminary Data Sheet
06.99
Edition 06.99 Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstrae 73, 81541 Munchen (c) Siemens AG 1995. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
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KTS6027, KTS6029 Revision History:Current Version: 06.99 Previous Version:03.99 old Page new Page 15 Subjects (major changes since last revision) Voltage gain for VHF and UHF changed
Data Classification Maximum Ratings Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Characteristics The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 C and the given supply voltage. Operating Range In the operating range the functions given in the circuit description are fulfilled. For detailed technical information about "Processing Guidelines" and "Quality Assurance" for ICs, see our "Product Overview".
Preliminary Data Sheet
KTS6027, KTS6029
1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.3.6 9.3.7 9.3.8 10 10.1 10.2 10.3 11 11.1 11.2 12 12.1 13 13.1 13.2 13.3
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Mixer-Oscillator block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PLL block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 I2C-Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Bit Allocation Read / Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Description of symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 UHF/VHF Bandswitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Address selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Reference divider ratio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 A/D Converter levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 I2C Bus Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 DC and RF Parameter Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Measurement of Crystal Oscillator Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Application Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Application Circuit (Evaluation Board) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Electrical Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Input admittance VHF mixer input Y0 = 20mS (single ended) . . . . . . . . . . . . . . . . 20 Input impedance UHF mixer input Z0 = 50 W (symmetrical) . . . . . . . . . . . . . . . . . 20 Output impedance IF output Y0 = 20mS (single ended) . . . . . . . . . . . . . . . . . . . . 21
Semiconductor Group
2.6.99
2 Band TV Tuner Mixer-Oscillator-PLL with unbalanced IF-Amplifier
Preliminary Data Sheet
KTS6027, KTS6029
BIPOLAR
1
Features
General
* Suitable for TV tuners * Full ESD protection Mixer/Oscillator * * * * High impedance mixer input for VHF Low impedance mixer input for UHF 4 pin oscillator for VHF 4 pin oscillator for UHF IF-Amplifier
P-TSSOP-28-1
* unbalanced SAW preamplifier * Low output impedance PLL * PLL with short lock-in time; no asynchronous divider stage * High voltage VCO tuning output * Fast I2C bus * * * * * 4 NPN bandswitch buffers Internal VHF/UHF switch Lock-in flag Power-down reset Programmable reference divider ratio (64, 80, 128) * Programmable charge pump current
Package
2
Ordering Information
Type KTS6027XS KTS6027-K KTS6027-S KTS6029XS KTS6029-K KTS6029-S Package P-TSSOP-28-1 P-TSSOP-28-1 P-TSSOP-28-1 P-TSSOP-28-1 P-TSSOP-28-1 P-TSSOP-28-1 Ordering Code Q67037-A1087 Q67037-A1088 Q67037-A1059 Q67037-A1089 Q67037-A1090 Q67037-A1091
Semiconductor Group
1
2.6.99
Preliminary Data Sheet
KTS6027, KTS6029
3
Functional Description
The KTS6027, KTS6029 device combines a digitally programmable phase locked loop (PLL), with a mixeroscillator block including two balanced mixers and oscillators for use in TV tuners. The PLL block with four hard-switched chip addresses forms a digitally programmable phase locked loop. With a 4 MHz quartz crystal, the PLL permits precise setting of the frequency of the tuner oscillator up to 850 MHz in increments of 62.5 kHz. The tuning process is controlled by a microprocessor via an I2C bus. The device has four output ports, two of them (P0 and P1) can also be used as TTL input ports. A flag is set when the loop is locked. The input ports and lock flag can be read by the processor via the I2C bus. The mixer-oscillator block includes two balanced mixers (one mixer with high-impedance input and one mixer with a balanced low-impedance input), two frequency and amplitude-stable balanced oscillators for VHF, HYPER and UHF, a low-noise reference voltage source and a band switch.
4
Application
The IC is suitable for NTSC tuners in TV- and VCR-sets or cable set-top receivers for analog TV and Digital Video Broadcasting.
Semiconductor Group
2
2.6.99
Preliminary Data Sheet
KTS6027, KTS6029
5
Pin Configuration
OU-B1 OU-C2 OU-C1 OU-B2 OV-B1 OV-C2 OV-C1 OV-B2 GNDA ADC IFout P3 TUNE CHGPMP MIXU MIXUx MIXV VVCC MIXout MIXoutx GNDD SDA SCL CAS Q P2 P1/I1 P0/I0 MIXU MIXUx MIXV VVCC MIXout MIXoutx GNDD SDA SCL CAS Q P2 P1/I1 P0/I0 OU-B1 OU-C2 OU-C1 OU-B2 OV-B1 OV-C2 OV-C1 OV-B2 GNDA ADC IFout P3 TUNE CHGPMP
1 2 3 4 5 6
28 27 26 25 24 23
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23
KTS6027
7 8 9 10 11 12 13 14
22 21 20 19 18 17 16 15
KTS6029
22 21 20 19 18 17 16 15
6
Package Outlines
Semiconductor Group
3
2.6.99
Preliminary Data Sheet
KTS6027, KTS6029
7
Pin Definitions and Functions
Pin No. KTS6027 KTS6029 Symbol Function
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
OU-B2 OU-C1 OU-C2 OU-B1 OV-B2 OV-C1 OV-C2 OV-B1 GNDA ADC IFout P3 TUNE CHGPMP P0/I0 P1/I1 P2 Q CAS SCL SDA GNDD MIXoutx MIXout VVCC MIXV MIXUx MIXU
UHF oscillator amplifier, high-impedance base input, symmetrical to OU-B1 UHF oscillator amplifier, high-impedance collector output, symmetrical to OU-C2 UHF oscillator amplifier, high-impedance collector output, symmetrical to OU-C1 UHF oscillator amplifier, high-impedance base input, symmetrical to OU-B2 HYPER oscillator amplifier, high-impedance base input, symmetrical to OV-B1 HYPER oscillator amplifier, high-impedance collector output, symmetrical to OV-C2 HYPER oscillator amplifier, high-impedance collector output, symmetrical to OV-C1 HYPER oscillator amplifier, high-impedance base input, symmetrical to OV-B2 Analog Ground ADC input IF output Port output VCO tuning voltage output Charge pump output / loop filter Port output / TTL input Port output / TTL input Port output 4 MHz low-impedance crystal oscillator input Chip address select Clock input for the I2C bus Data input/output for the I2C bus Digital Ground Inverse Mixer output, symmetrical to MIXout Mixer output, symmetrical to MIXoutx Analog supply voltage VHF mixer input, high-impedance UHF mixer input, low-impedance, symmetrical to MIXU UHF mixer input, low-impedance, symmetrical to MIXUx
Semiconductor Group
4
2.6.99
Preliminary Data Sheet
KTS6027, KTS6029
8
Block Diagram
The pin numbers given in parenthesis refer to the KTS6029
Semiconductor Group
5
2.6.99
Preliminary Data Sheet
KTS6027, KTS6029
9
Circuit Description
9.1 Mixer-Oscillator block
The mixer oscillator section includes two balanced mixers (double balanced mixer), two balanced oscillators for VHF and / or HYPER band and UHF, a reference voltage source and a band switch. Filters between tuner input and IC separate the TV frequency signals into two bands. The band switching in the tuner front-end is done by using two or three port outputs. In the selected band the signal passes a tuner input stage with MOSFET amplifier, a double-tuned bandpass filter and is then fed to the balanced mixer input of the IC which has in case of VHF / Hyperband a high-impedance input and in case of UHF a low-impedance input. The input signal is mixed there with the signal from the activated on chip oscillator to the IF frequency which is filtered out at the balanced high-impedance output pair by means of a parallel tuned circuit. The following SAW preamplifier has a low output impedance to drive a 75 load directly.
9.2 PLL block
The mixer-oscillator signal VCO/VCOx is internally DC-coupled as a differential signal at the programmable divider inputs. The signal subsequently passes through a programmable divider with ratio N = 256 through 32767 and is then compared in a digital frequency / phase detector to a reference frequency fref = 62.5 kHz. This frequency is derived from a unbalanced, low-impedance 4 MHz crystal oscillator (pin Q) divided by Q = 64. The phase detector has two outputs UP and DOWN that drive two current sources I+ and I- of a charge pump. If the negative edge of the divided VCO signal appears prior to the negative edge of the reference signal, the I+ current source pulses for the duration of the phase difference. In the reverse case the I- current source pulses. If the two signals are in phase, the charge pump output (CHGPMP) goes into the high-impedance state (PLL is locked). An active low-pass filter integrates the current pulses to generate the tuning voltage for the VCO (internal amplifier, external pullup resistor at TUNE and external RC circuitry). The charge pump output is also switched into the high-impedance state when the control bit T0 = 1. Here it should be noted, however, that the tuning voltage can alter over a long period in the high-impedance state as a result of selfdischarge in the peripheral circuity. TUNE may be switched off by the control bit OS to allow external adjustments. If the VCO is not working the PLL locks to a tuning voltage of 33V. By means of control bit 5I the pump current can be switched between two values by software. This programmability permits alteration of the control response of the PLL in the locked-in state. In this way different VCO gains can be compensated, for example. The software-switched ports P0, P1 and P2 are general-purpose open-collector outputs. The test bit T1 = 1, switches the test signals fref (4 MHz / 64) and Cy (divided input signal) to P0 and P1 respectively. P0, P1 are bidirectional. The lock detector resets the lock flag FL when the width of the charge pump current pulses is greater than the period of the crystal oscillator (i.e. 250 ns). Hence, when FL = 1, the maximum deviation of the input frequency from the programmed frequency is given by f = IP (KVCO / fQ) (C1+C2) / (C1C2) where IP is the charge pump current, KVCO the VCO gain, fQ the crystal oscillator frequency and C1, C2 the capacitances in the loop filter (see application circuit). As the charge pump pulses at 62.5 kHz (= fref), it takes a maximum of 16 s for FL to be reset after the loop has lost lock state. Once FL has been reset, it is set only if the charge pump pulse width is less than 250 ns for eight consecutive fref periods. Therefore it takes between 128 and 144 s for FL to be set after the loop regains lock.
Semiconductor Group
6
2.6.99
Preliminary Data Sheet
9.3 I2C-Bus Interface
KTS6027, KTS6029
Data is exchanged between the processor and the PLL via the I2C bus. The clock is generated by the processor (input SCL), while pin SDA functions as an input or output depending on the direction of the data (open collector, external pull-up resistor). Both inputs have hysteresis and a low-pass characteristic, which enhance the noise immunity of the I2C bus. The data from the processor pass through an I2C bus controller. Depending on their function the data are subsequently stored in registers. If the bus is free, both lines will be in the marking state (SDA, SCL are HIGH). Each telegram begins with the start condition and ends with the stop condition. Start condition: SDA goes LOW, while SCL remains HIGH. Stop condition: SDA goes HIGH while SCL remains HIGH. All further information transfer takes place during SCL = LOW, and the data is forwarded to the control logic on the positive clock edge. The table "Bit Allocation" (see 9.3.1 Bit Allocation Read / Write on page 8) should be referred to the following description. All telegrams are transmitted byte-by-byte, followed by a ninth clock pulse, during which the control logic returns the SDA line to LOW (acknowledge condition). The first byte is comprised of seven address bits. These are used by the processor to select the PLL from several peripheral components (chip select). The LSB bit (R/W) determines whether data are written into (R/W = 0) or read from (R/W = 1) the PLL. In the data portion of the telegram during a WRITE operation, the MSB bit of the first or third data byte determines whether a divider ratio or control information is to follow. In each case the second byte of the same data type has to follow the first byte. If the address byte indicates a READ operation, the PLL generates an acknowledge and then shifts out the status byte onto the SDA line. If the processor generates an acknowledge, a further status byte is output; otherwise the data line is released to allow the processor to generate a stop condition. The status word consists of two bits from the TTL input ports, three bits from the A/D converter, the lock flag and the power-on flag. Four different chip addresses can be set by appropriate cDC level atf pin CAS (see 9.3.4 Address selection on page 9). When the supply voltage is applied, a power-on reset circuit prevents the PLL from setting the SDA line to LOW, which would block the bus. The power-on reset flag POR is set at power-on and if VVCC falls below 3.2 V. It will be reset at the end of a READ operation.
Semiconductor Group
7
2.6.99
Preliminary Data Sheet
KTS6027, KTS6029
9.3.1
Bit Allocation Read / Write
Byte MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB Ack Remarks
Write Data Address Byte Progr. Divider Byte 1 Progr. Divider Byte 2 Control Byte 1 Control Byte 2 Read Data Address Byte Status Byte 1 POR 1 FL 0 x 0 I1 0 I0 MA1 A2 MA0 A1 1 A0 A A 1 0 n7 1 x 1 n14 n6 5I x 0 n13 n5 T1 x 0 n12 n4 T0 x 0 n11 n3 1 P3 MA1 n10 n2 RSA P2 MA0 n9 n1 RSB P1 0 n8 n0 OS P0 A A A A A
9.3.2
Description of symbols
Symbol Description Address selection bits (see 9.3.4 Address selection on page 9) programmable divider bits: N = 214 x n14 + 213 x n13 + ..... + 23 x n3 + 22 x n2 + 21 x n1 + n0 charge pump current: bit = 0 : charge pump current = 50 A bit = 1 : charge pump current = 220A test bits (see 9.3.5 Test modes on page 9) reference divider bits (see 9.3.6 Reference divider ratio on page 9) tuning amplifier control bit: bit = 0 : enable VTUNE bit = 1 : disable VTUNE NPN ports control bits bit = 0 : NPN open-collector output is inactive, TTL inputs at P0, P1 bit = 1 : NPN open-collector output is active UHF / VHF bandswitch (see 9.3.3 UHF/VHF Bandswitch on page 9) ADC bits (see 9.3.7 A/D Converter levels on page 9) input data from P0/I0, P1/I1 PLL lock flag bit = 1 : loop is locked Power-on reset flag flag is set at power-on and reset at the end of READ operation don`t care
MA0, MA1 n14 to n0 5I T1, T0 RSA, RSB OS
PO, P1, P2, P3 A0, A1, A2 I0, I1 FL POR x
Semiconductor Group
8
2.6.99
Preliminary Data Sheet
KTS6027, KTS6029
9.3.3
UHF/VHF Bandswitch
IC is in UHF mode Ports Pn P0 x x x P1 1 x x P2 x 1 x P3 x x 1
KTS6027XS, KTS6029XS KTS6027-K, KTS6029-K KTS6027-S, KTS6029-S
9.3.4
Address selection
MA1 0 0 1 1 MA0 0 1 0 1
Voltage at CAS (0...0.1) * VVCC open circuit (0.4...0.6) * VVCC (0.9...1) * VVCC
9.3.5
Test modes
T1 0 0 1 1 T0 0 1 0 1
Test mode Normal operation Charge pump output, CHGPMP is in high-impedance state P1 = Cy output, P0 = fref output TTL-inputs I1/I0 are Cy/fref inputs of phase detector
9.3.6
Reference divider ratio
RSA x 0 1 RSB 0 1 1
Reference divider ratio 80 128 64
9.3.7
A/D Converter levels
A2 0 0 0 0 1 A1 0 0 1 1 0 A0 0 1 0 1 0
Voltage at ADC (0...0.15) * VVCC (0.15...0.3) * VVCC (0.3...0.45) * VVCC (0.45...0.6) * VVCC (0.6...1) * VVCC
Semiconductor Group
9
2.6.99
Semiconductor Group Addressing Ack. 1st Byte Ack. 2nd Byte Ack. 3rd Byte Ack. 4th Byte MA MA R/W Note: SDA 10 Telegram examples: Start-Addr-DR1-DR2-CW1-CW2-Stop Start-Addr-CW1-CW2-DR1-DR2-Stop Start-Addr-DR1-DR2-Stop Start-Addr-CW1-CW2-Stop Abbreviations: Start Addr DR1 DR2 CW1 CW2 Stop = start condition = address byte = prog. divider byte 1 = prog. divider byte 2 = control byte 1 = control byte 2 = stop condition 2.6.99 SCL
9.3.8 I2C Bus Timing Diagram
Preliminary Data Sheet KTS6027, KTS6029
Preliminary Data Sheet
KTS6027, KTS6029
10 Electrical Characteristics
10.1 Absolute Maximum Ratings
The maximal ratings may not be exceeded under any circumstances, not even momentary and individual, as permanent damage to the IC will result.
Ambient Temperature under bias: TA= -20 to +85C Limit Values Symbol min Supply voltage Junction temperature Storage temperature Thermal resistance (junction to ambient) PLL CHGPMP VCHGPMP ICHGPMP Crystal oscillator pins Q Bus input/output SDA Bus output current SDA Bus input SCL Chip address switch CAS VCO tuning output (loop filter) Port outputs P0...P3 Total port output current Mixer-Oscillator Mix inputs VHF / Hyper Mix inputs UHF VCO base voltage VCO collector voltage VMIX V VMIX U IMIX U VB VC -5 -0.3 -0.3 3 2 6 3 VVCC V V mA V V VQ IQ VSDA ISDA(L) VSCL VCAS VTUNE VP IP(L) IP(L) -0.3 -0.3 -0.3 -0.3 -1 -5 -0.3 VVCC 5 VVCC VVCC 35 VVCC 15 40 -0.3 3 1 VVCC V mA V mA V mA V V V V mA mA tmax = 0.1 sec. at 5.5 V tmax = 0.1 sec. at 5.5 V open collector VVCC TJ TStg RthSA -40 -0.3 max 6 +150 +125 120 V C C K/W Unit Test Conditions
Parameter1
ESD-Protection2
all pins VESD 1 kV
1. All values are referred to ground (pin), unless stated otherwise. Currents with a positive sign flows into the pin and currents with a negative sign flows out of pin. 2. according to MIL STD 883D, method 3015.7 and EOS/ESD assn. standard S5.1 - 1993
Semiconductor Group
11
2.6.99
Preliminary Data Sheet
KTS6027, KTS6029
10.2 Operating Range
Within the operational range the IC operates as described in the circuit description. The AC / DC characteristic limits are not guaranteed.
Limit Values Parameter Supply voltage Programmable divider factor VHF Mixer input frequency range UHF Mixer input frequency range VHF Oscillator frequency range UHF Oscillator frequency range Ambient temperature Symbol min VVCC N fMIXV fMIXU fOV fOU Tamb +4.5 256 40 350 75 380 -20 max +5.5 32767 500 900 560 950 +85 MHz MHz MHz MHz C V Unit Test Conditions
Semiconductor Group
12
2.6.99
Preliminary Data Sheet
KTS6027, KTS6029
10.3 AC/DC Characteristics
AC / DC characteristics involve the spread of values guaranteed in the specified supply voltage and ambient temperature range. Typical characteristics are the median of the production.
Limit Values Symbol min typ max Unit Test conditions
Parameter TA = 25 C,VVCC
Supply
Supply voltage Current consumption VVCC IVCC 4.5 56 5 70 5.5 84 V mA
Digital Unit PLL
Crystal oscillator connections Q Crystal frequency Crystal resistance Oscillation frequency Input impedance Charge pump output CHGPMP HIGH output current LOW output current Tristate current Output voltage ICPH ICPL ICPZ VCP 1.0 90 22 220 50 +1 2.5 300 75 A A nA V 5I = 1, VCP = 2 V 5I = 0, VCP = 2 V T0 = 1, VCP = 2 V locked fQ RQ fQ ZQ 3.2 10 3,99975 -700 4,000 -900 4.0 4.8 100 MHz series resonance series resonance fQ = 4 MHz fQ = 4 MHz
4,00025 MHz -1100
Drive output TUNE (open collector) HIGH output current LOW output voltage ITH VTL 10 0.5 A V VTH = 33 V, T0 = 1 ITL = 1.0 mA
I2C-Bus
Bus inputs SCL, SDA HIGH input voltage LOW input voltage HIGH input current LOW input current VIH VIL IIH IIL -10 3 0 5.5 1.5 10 V V A A A V VIH = VS VIL = 0 V
Bus output SDA (open collector) HIGH output current LOW output voltage Edge speed SCL,SDA Rise time Fall time tr tf 300 300 ns ns IOH VOL 10 0.4 VOH = 5.5 V IOL = 3 mA
Semiconductor Group
13
2.6.99
Preliminary Data Sheet
KTS6027, KTS6029
Parameter TA = 25 C,VVCC Clock timing SCL Frequency HIGH pulse width LOW pulse width Start condition Set-up time Hold time Stop condition Set up time Bus free Data transfer Set-up time Hold time Input hysteresis SCL, SDA (1) Pulse width of spikes which are suppressed Capacitive load for each bus line
Limit Values Symbol min typ max Unit Test conditions
fSCL tH tL
0 0.6 1.3
400
kHz s s s s s s s s
tsusta thsta
0.6 0.6
tsusto tbuf
0.6 1.3
tsudat thdat Vhys tsp CL
0.1 0 200 0 50 400
mV ns pF
Port outputs P0, P1, P2,P3 (open collector) HIGH output current LOW output voltage TTL port inputs P0, P1 HIGH input voltage LOW input voltage HIGH input current LOW input current ADC port input HIGH input current LOW input current Address selection input CAS HIGH input current LOW input current ICASH ICASL -50 50 A A VCASH = 5 V VCASL = 0 V IADCH IADCL -10 10 A A VPIH VPIL IPIH IPIL -10 2.7 0.8 10 V V A A VPIH = 5.5 V VPIL = 0 V IPOH VPOL 1 0.4 A V VPOH = 5 V IPOL = 15 mA
Semiconductor Group
14
2.6.99
Preliminary Data Sheet
KTS6027, KTS6029
Parameter TA = 25 C,VVCC
Limit Values Symbol min typ max Unit Test conditions
Analog Unit
VHF low and VHF high Band Section (including IF amplifier) Voltage gain GMixV 15 18 21 dB fRF = 43.25 to 463.25 MHz, fIF = 33.4 to 58.75 MHz fRF = 43.25 to 463.25 MHz serial equivalent circuit, fMixV = 100 MHz serial equivalent circuit, fMixV = 100 MHz VS = 5 V10% T = 25 C t = 5 s up to 15 min after switching on f = 10 kHz fRF = 48.25 MHz f = 10 kHz fRF = 399.25 MHz fm = 10kHz, application circuit VMixB = 80 dBV
Mixer noise figure
FMixV RMixV 1
9 2 2
11 3 3 400
dB k pF kHz kHz kHz dBV dBV dBc/ Hz dB
Mixer input impedance CMixV
Oscillator drift, PLL unlocked
fOscV
500 100 100 108 88 -86 20
Oscillator pulling, PLL unlocked
VMIXV 80
Oscillator phase noise IF suppression
L(fm)VHF aIF
-80 15
UHF Band Section (including IF amplifier) fRF = 367.25 MHz to 863.25 MHz, fIF = 33.4MHz to 58.75 MHz fRF = 367.25 to 615.25 MHz fRF = 623.25 to 863.25 MHz serial equivalent circuit, fMixU = 600 MHz serial equivalent circuit, fMixU = 600 MHz VS = 5 V10% T = 25 C t = 5 s up to 15 min after switching on
Voltage gain
GMixU
26
29
32
dB
6 Mixer noise figure FMixU 7 RMixU Mixer input impedance LMixU 6 10 14 20
9 10 26 14 400
dB dB nH kHz kHz kHz
Oscillator drift, PLL unlocked
fOscU
800 100
Semiconductor Group
15
2.6.99
Preliminary Data Sheet
KTS6027, KTS6029
Parameter TA = 25 C,VVCC
Limit Values Symbol min 100 typ 108 108 -86 20 max dBV dBV dBc/ Hz dB f = 10 kHz fRF = 375.25 MHz f = 10 kHz fRF = 847.25 MHz fm = 10kHz, application circuit VMixB = 80 dBV Unit Test conditions
Oscillator pulling, PLL unlocked
VMIXU 100
Oscillator phase noise IF suppression SAW preamplifier
L(fm)UHF aIF
-80 15
RIFout IF output impedance LIFout Rejection at the IFoutput tbf
80
nH
serial equivalent circuit, fIF = 38.9 MHz
Channel 6 beat
INTCH6
tbf
tbf
dBc
VRFpix = VRFsnd = 80 dBV; note 1 VRFpix = 80 dBV; note 2
Channel A-5 beat Notes:
1. 2.
INTCHA-5
tbf
tbf
dBc
Channel 6 beat is the interfering product of fRFpix, fRFsnd - fOSC of channel 6 at 42 MHz. Channel A-5 beat is the interfering product of fRFpix + fRFsnd - fOSC of channel A-5,fBEAT = 45.5 MHz. The possible mechanisms are: fOSC - 2 x fIF or 2 x fRFpix - fOSC. For the measurement VRF = 80 dBV.
Semiconductor Group
16
2.6.99
Preliminary Data Sheet
KTS6027, KTS6029
11 Test Circuit
11.1 DC and RF Parameter Measurement
RGEN = 75 UHF VHF SDA SCL CAS P2
4MHz 18p
P1/I1 P0/I0
1:1 50*)
1:1**)
VVCC
22p 2p2 22p 1n
68p L3
68p
47n
28
27
26
25
24
23
22
21
20
19
18
17
16
15
KTS6027
1 2
1p2
3
1p2 L1 1p2
4
1p2
5
2p7
6
7
2p2 L2 2p2
8
2p7
9
10
11
12
13
4n7
14
22n
100p
18p
ADC
BB565 100p 100p 33k 1k
4k7 4k7 1k BB619C 47k
P3
4n7
IFoutput RLOAD =75 +33V
1n
Coils: *) not for noise measurement **) 1:2 transformer for noise measurement coil L1 L2 L3 turns wire size coil diameter [mm] [mm] 2 0.4 3 4 0.4 3 Neosid Part-No. 00503600 0.58H
Semiconductor Group
17
22k
4n7
4n7
2.6.99
Preliminary Data Sheet
KTS6027, KTS6029
11.2 Measurement of Crystal Oscillator Frequency
Test mode: VVCC IVCC Q 18 pF 4 MHz KTS6027, KTS6029 P0 5k P1 fcy GNDD Counter 5V
T1 = HIGH T0 = LOW
5k
fref Counter
fQ = fref * reference divider ratio
fVCO = fcy * N N: divider ratio
Semiconductor Group
18
2.6.99
Preliminary Data Sheet
KTS6027, KTS6029
12 Application Circuit
12.1 Application Circuit (Evaluation Board)
RGEN = 75 UHF VHF SDA SCL CAS P2/P3 P1/I1 P0/I0
4MHz 18p
1:1*)
1:2**)
220
22p 2p2
22p
1n
L4
220
VVCC
68p
68p
4n7
100p
100p
4n7
4n7
4n7
4n7
28
27
26
25
24
23
22
21
20
19
18
17
16
15
KTS6027
1 2
1p2
3
1p2 L1 1p2
4
1p2
5
6
2p7 L2
7
2p2 L3 2p2
8
2p7
9
10 ADC
4n7
11
12
13
4n7
14
22n
4n7 22k
18p
BB659C
120p 1p2 47p BA 892 4n7 1k 4k7 2k7 BB659C 2k7 3k3
1k 100k
4n7 4k7
P3
4n7
IFoutput RLOAD =75 +33V
1n
Transformers: *) TOKO B4F Type 617DB-1023 **) TOKO B4F Type 617PT-1026
RF-Bands: 55.25 MHz to 127.25 MHz 133.25 MHz to 361.25 MHz 367.25 MHz to 803.25 MHz
Coils: coil L1 L2 L3 L4 turns wire size coil diameter [mm] [mm] 1.5 0.4 2 3.5 0.4 2.5 9.5 0.4 2.5 12.5 0.3 3.5
Semiconductor Group
19
33k 1k
2.6.99
Preliminary Data Sheet
KTS6027, KTS6029
13 Electrical Diagrams
13.1 Input admittance VHF mixer input Y0 = 20mS (single ended)
1
0.9
0.8
1.5
0.7
0.6
0.5
2
0.4
3
0.3
1.5
1 0.9 0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
20
10
5
4
3
2
20
4
3
1.5
13.2 Input impedance UHF mixer input Z0 = 50 (symmetrical)
0.7
0.8
0.9
1
1
0.9
0.8
0.6
1.5
0.7
0.6
0.5
2
0.5
2
3
0.3
4
0
0.3
0.4
0.5 2
0.6
0.7
0.8
0.9
Semiconductor Group
20
1
1.5
5
0.2
4
10
0.1
20
tbd
0.7 0.8 0.9 1
0.1
0.2
0.3
0.4
0.5
0.6
1.5
10
20
2
3
4
5
0.2
5
5
0.1
10
10
20
0
0.3
3
0.4
0.4
4
0.2
0.2
5
0.1
0.1
10
tbd
20
2.6.99
Preliminary Data Sheet
KTS6027, KTS6029
13.3 Output impedance IF output Y0 = 20mS (single ended)
0.7
0.8
0.9
1
0.6
1.5
0.5
2
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8 0.9 1
1.5
10
0
20
20
2
3
4
0.3
0.4
0.5 2
0.6
0.7
0.8
0.9
Semiconductor Group
21
1
1.5
5
0.2
4
10
0.1
5
3
0.4
3
0.3
4
5
0.2
10
0.1
tbd
20
2.6.99

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