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| Integrated Circuit Systems, Inc. ICS9DB202-01 PCI EXPRESSTM JITTER ATTENUATOR Features * One 0.7V current mode differential HCSL output pair * 1 differential clock input * CLK and nCLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL * Maximum output frequency: 140MHz * Cycle-to-cycle jitter: 30ps (maximum) * RMS phase jitter @ 100MHz, (1.5MHz - 22MHz): 2.31ps (typical) * 3.3V operating supply * 0C to 70C ambient operating temperature * Lead-Free package available * Industrial temperature information available upon request GENERAL DESCRIPTION The ICS9DB202-01 is a high performance 1-to-1 ICS Differential-to HCSL Jitter Attenuator designed for HiPerClockSTM use in PCI ExpressTM systems. In some PCI ExpressTM systems, such as those found in desktop PCs, the PCI ExpressTM clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuating device may be necessary in order to reduce high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. BLOCK DIAGRAM IREF + Current Set PIN ASSIGNMENT GND nc 32 31 30 29 28 27 26 25 IREF nc VDDA CLK nCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 nc PCIEXC0 nc nc nc PCIEXT0 VDD nc ICS9DB202-01 nc nc nc nc nc nc 24 23 22 21 20 19 18 17 nc nc nc nc VDD nc nc nc nCLK CLK Phase Detector Loop Filter VCO PCIEXT0 nPCIEXC0 nc nc nc Internal Feedback 32-Lead VFQFN 5mm x 5mm x 0.95 package body K Package Top View 9DB202CK-01 www.icst.com/products/hiperclocks.html 1 REV. A OCTOBER 5, 2004 Integrated Circuit Systems, Inc. ICS9DB202-01 PCI EXPRESSTM JITTER ATTENUATOR Type Input Description A fixed precision resistor (475) from this pin to ground provides a reference current used for differential current-mode PCIEX clock outputs. TABLE 1. PIN DESCRIPTIONS Number 1 2, 6, 7, 8, 11, 12, 14, 15, 16, 17, 18, 19, 21, 22, 23, 24, 25, 26, 28, 29, 30, 31, 32 3 4 5 9, 10 13, 20 27 Name IREF nc Unused No connect. VDDA CLK nCLK PCIEXT0, PCIEXC0 VDD GND Power Input Input Output Power Power Analog supply pin. Requires 24 series resistor. Pulldown Non-inver ting differential clock input. Pullup/ Inver ting differential clock input. VDD/2 default when left floating. Pulldown Differential output pairs. HCSL interface levels. Core supply pins. Power supply ground. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF K K 9DB202CK-01 www.icst.com/products/hiperclocks.html 2 REV. A OCTOBER 5, 2004 Integrated Circuit Systems, Inc. ICS9DB202-01 PCI EXPRESSTM JITTER ATTENUATOR 4.6V -0.5V to VDD + 0.5 V -0.5V to VDD + 0.5V 34.8C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = 0C TO 70C, RREF = 475 Symbol VDD VDDA IDD IDDA Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 112 22 Units V V mA mA TABLE 3B. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = 0C TO 70C, RREF = 475 Symbol IIH IIL V PP Parameter Input High Current Input Low Current CLK, nCLK CLK, nCLK Test Conditions VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V 0.15 Minimum Typical Maximum 150 150 1.3 VDD - 0.85 Units A A V V Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 VCMR NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V. TABLE 3C. HCSL DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = 0C TO 70C, RREF = 475 Symbol IOH VOH VOL IOZ VOX Parameter Output Current Output High Voltage Output Low Voltage High Impedance Leakage Current Output Crossover Voltage -10 250 Test Conditions Minimum 12 745 -5 10 550 Typical 14 Maximum 16 Units mA mV mV A mV TABLE 4. AC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = 0C TO 70C, RREF = 475 Symbol fMAX Parameter Output Frequency RMS Phase Jitter (Random); NOTE 1 Cycle-to-Cycle Jitter Output Rise/Fall Time Output Duty Cycle 20% to 80% 200 48 Integration Range: 1.5MHz - 22MHz 2.31 30 700 52 Test Conditions Minimum Typical Maximum 140 Units MHz ps ps ps % tjit(O) tjit(cc) tR / tF odc NOTE 1: Please refer to the Phase Noise Plot following this section. 9DB202CK-01 www.icst.com/products/hiperclocks.html 3 REV. A OCTOBER 5, 2004 Integrated Circuit Systems, Inc. ICS9DB202-01 PCI EXPRESSTM JITTER ATTENUATOR TYPICAL PHASE NOISE AT 100MHZ 0 -10 -20 -30 -40 -50 -60 PCI ExpressTM Filter 100MHz RMS Phase Jitter (Random) 1.5MHz to 22MHz = 2.31ps (typical) NOISE POWER dBc Hz -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M Raw Phase Noise Data The illustrated phase noise plot was taken using a low phase noise signal generator, the noise floor of the signal generator is less than that of the device under test. Using this configuration allows one to see the true spectral purity or phase noise performance of the PLL in the device under Phase Noise Result by adding PCI ExpressTM Filter to raw data OFFSET FREQUENCY (HZ) test. Due to the tracking ability of a PLL, it will track the input signal up to its loop bandwidth. Therefore, if the input phase noise is greater than that of the PLL, it will increase the output phase noise performance of the device. It is recommended that the phase noise performance of the input is verified in order to achieve the above phase noise performance. www.icst.com/products/hiperclocks.html 4 9DB202CK-01 REV. A OCTOBER 5, 2004 Integrated Circuit Systems, Inc. ICS9DB202-01 PCI EXPRESSTM JITTER ATTENUATOR PARAMETER MEASUREMENT INFORMATION 3.3V5% VDD VDD, V DDA SCOPE Qx nCLK V PP Cross Points V CMR CLK HCSL GND GND 0V 3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL PCIEXC0 PCIEXT0 PCIEXC0 PCIEXT0 Pulse Width tcycle n tjit(cc) = tcycle n -tcycle n+1 1000 Cycles CYCLE-TO-CYCLE JITTER 80% Clock Outputs 20% tR tF HCSL OUTPUT RISE/FALL TIME 9DB202CK-01 tcycle n+1 t PERIOD odc = t PW t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 80% VSW I N G 20% www.icst.com/products/hiperclocks.html 5 REV. A OCTOBER 5, 2004 Integrated Circuit Systems, Inc. ICS9DB202-01 PCI EXPRESSTM JITTER ATTENUATOR APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS9DB202-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 24 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA pin. 3.3V VDD .01F V DDA .01F 10F 24 FIGURE 1. POWER SUPPLY FILTERING WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 9DB202CK-01 www.icst.com/products/hiperclocks.html 6 REV. A OCTOBER 5, 2004 Integrated Circuit Systems, Inc. ICS9DB202-01 PCI EXPRESSTM JITTER ATTENUATOR here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50 R3 50 LVPECL Zo = 50 Ohm CLK nCLK HiPerClockS Input HiPerClockS Input R1 50 R2 50 FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER BY FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER BY 3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125 3.3V 3.3V Zo = 50 Ohm LVDS_Driv er R1 100 Zo = 50 Ohm CLK nCLK Receiv er FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER BY FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER BY 9DB202CK-01 www.icst.com/products/hiperclocks.html 7 REV. A OCTOBER 5, 2004 Integrated Circuit Systems, Inc. ICS9DB202-01 PCI EXPRESSTM JITTER ATTENUATOR nation, which has a slightly better signal integrity, is recommended for all other applications. SCHEMATIC EXAMPLE The schematic below illustrates two different terminations. Both are reliable and adequate. The PCI ExpressTM termination is recommended for all PCI ExpressTM application. The optional termiVDD VDDA R2 24 C3 10uF C4 0.01u U1 VDD R1 475 1 2 3 4 5 6 7 8 nc nc nc nc nc GND nc nc 32 31 30 29 28 27 26 25 CLK nCLK PCIEXT0 PCIEXC0 nc nc VDD nc nc nc IREF nc VDDA CLK nCLK nc nc nc nc nc nc nc VDD nc nc nc 24 23 22 21 20 19 18 17 Zo = 50 TL1 + HCSL Zo = 50 TL2 R3 50 R4 50 - 9DB202-01_lqf p32_short VDD (U1-14) (U1-20) C1 10uf C2 0.1uF C1 0.1uF FIGURE 4. EXAMPLE 9 10 11 12 13 14 15 16 OF ICS9DB202-01 RELIABILITY INFORMATION TABLE 5. JAVS. AIR FLOW TABLE FOR 32 LEAD VFQFN PACKAGE JA 0 Air Flow (Linear Feet per Minute) 0 Multi-Layer PCB, JEDEC Standard Test Boards 34.8C/W TRANSISTOR COUNT The transistor count for ICS9DB202-01 is: 2471 9DB202CK-01 www.icst.com/products/hiperclocks.html 8 REV. A OCTOBER 5, 2004 Integrated Circuit Systems, Inc. ICS9DB202-01 PCI EXPRESSTM JITTER ATTENUATOR 32 LEAD VFQFN PACKAGE OUTLINE - K SUFFIX FOR TABLE 6. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A3 b e ND NE D D2 E E2 L 1.25 0.30 1.25 5.0 3.25 0.50 0.18 0.50 BASIC 8 8 5.0 3.25 0.80 0 0.25 Reference 0.30 MINIMUM 32 1.0 0.05 MAXIMUM Reference Document: JEDEC Publication 95, MO-220 9DB202CK-01 www.icst.com/products/hiperclocks.html 9 REV. A OCTOBER 5, 2004 Integrated Circuit Systems, Inc. ICS9DB202-01 PCI EXPRESSTM JITTER ATTENUATOR Marking Package 32 Lead VFQFN 32 Lead VFQFN on Tape and Reel 32 Lead "Lead-Free" VFQFN 32 Lead "Lead-Free" VFQFN on Tape and Reel Count 490 per Tray 2500 490 per Tray 2500 Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C TABLE 7. ORDERING INFORMATION Part/Order Number ICS9DB202CK-01 ICS9DB202CK-01T ICS9DB202CK-01LF ICS9DB202CK-01LFT ICS9DB202CK-01 ICS9DB202CK-01 ICS9DB202CK-01L ICS9DB202CK-01L The aforementioned trademarks, HiPerClockSTM and PCI ExpressTM iare trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 9DB202CK-01 www.icst.com/products/hiperclocks.html 10 REV. A OCTOBER 5, 2004 |
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