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Integrated Circuit Systems, Inc.
ICS889831
LOW SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
FEATURES
* 4 differential LVPECL/ECL outputs * IN, nIN pair can accept the following differential input levels: LVPECL, LVDS, CML, SSTL * 50 internal input termination to VT * Maximum output frequency: > 2.1GHz * Output skew: 30ps (maximum) * Part-to-part skew: 185ps (maximum) * Additive phase jitter, RMS: 0.27ps (typical) * Propagation delay: 570ps (maximum) * LVPECL mode operating voltage supply range: VCC = 2.5V 5%, 3.3V 5%, VEE = 0V * ECL mode operating voltage supply range: VCC = 0V, VEE = -3.3V 5%, 2.5V 5% * -40C to 85C ambient operating temperature * Lead-Free package fully RoHS compliant
GENERAL DESCRIPTION
The ICS889831 is a high speed 1-to-4 Differentialto-LVPECL/ECL Fanout Buffer and is a member HiPerClockSTM of the HiPerClockSTM family of high performance clock solutions from ICS. The ICS889831 is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The internally terminated differential input and VREF_AC pin allow other differential signal families such as LVDS, LVHSTL and CML to be easily interfaced to the input with minimal use of external components. The device also has an output enable pin which may be useful for system test and debug purposes. The ICS889831 is packaged in a small 3mm x 3mm 16-pin VFQFN package which makes it ideal for use in space-constrained applications.
ICS
BLOCK DIAGRAM
EN D Q LE IN VT nIN
5 0
PIN ASSIGNMENT
nQ0 VCC
Q0 nQ0 Q1 nQ1
Q1 1 nQ1 2 Q2 3 nQ2 4
16 15 14 13 12 11 10 9 5
Q3
VEE
Q0
IN VT VREF_AC nIN
6
nQ3
7
VCC
8
EN
5 0
Q2 nQ2
ICS889831
16-Lead VFQFN 3mm x 3mm x 0.95 package body K Package Top View
VREF_AC
Q3 nQ3
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REV. A JUNE 16, 2005
Integrated Circuit Systems, Inc.
ICS889831
LOW SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
Type Description Differential output pair. LVPECL / ECL interface levels. Differential output pair. LVPECL / ECL interface levels. Differential output pair. LVPECL / ECL interface levels. Positive supply pins. Synchronizing clock enable. When LOW, Q outputs will go LOW and nQ outputs will go HIGH on the next LOW transition at IN inputs. Input threshold is VCC/2V. Includes a 37k pull-up resistor. Default state is HIGH when left floating. The internal latch is clocked on the falling edge of the input signal IN. LVTTL / LVCMOS interface levels. Inver ting differential clock input. 50 internal input termination to VT. Reference voltage for AC-coupled applications. Termination input. Non-inver ting differential clock input. 50 internal input termination to VT. Negative supply pin.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 4 5, 6 7, 14 Name Q1, nQ1 Q2, nQ2 Q3, nQ3 VCC Output Output Output Power
8
EN
Input
Pullup
9 10 11 12 13
nIN VREF_AC VT IN VEE
Input Output Input Input Power
15, 16 Q0, nQ0 Output Differential output pair. LVPECL / ECL interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol RPULLUP Parameter Input Pullup Resistor Test Conditions Minimum Typical 37 Maximum Units k
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Integrated Circuit Systems, Inc.
ICS889831
LOW SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
Outputs
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Input EN 0 Q0:Q3 Disabled; LOW nQ0:nQ3 Disabled; HIGH
1 Enabled Enabled After EN switches, the clock outputs are disabled or enabled following a falling input clock edge as shown in Figure 1.
EN
VCC/2 tS
nIN IN nQx Qx
VCC/2 tH
VIN
tPD
VOUT Swing
FIGURE 1. EN TIMING DIAGRAM
TABLE 3B. TRUTH TABLE
Inputs IN 0 1 X nIN 1 0 X EN 1 1 0 0 1 0(1) Outputs Q0:Q3 nQ0:nQ3 1 0 1(1)
NOTE 1: On next negative transition of the input signal (IN).
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ICS889831
LOW SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
4.6V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage -4.6V (ECL mode, VCC = 0) to the device. These ratings are stress specifi-0.5V to VCC + 0.5 V cations only. Functional operation of product at 0.5V to VEE - 0.5V these conditions or any conditions beyond those 50mA 100mA 50mA 100mA 0.5mA -65C to 150C 51.5C/W (0 lfpm) listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Negative Supply Voltage, VEE Inputs, VI (LVPECL mode) Inputs, VI (ECL mode) Outputs, IO Continuous Current Surge Current Input Current, IN, nIN VT Current, IVT Input Sink/Source, IREF_AC Storage Temperature, TSTG Package Thermal Impedance, JA
(Junction-to-Ambient)
Operating Temperature Range, TA -40C to +85C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.5V 5%, 3.3V 5%; VEE = 0V
Symbol VCC IEE Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 2.375 Typical 3.3 Maximum 3.465 60 Units V mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 2.5V 5%, 3.3V 5%; VEE = 0V
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V -150 Test Conditions Minimum 2 0 Typical Maximum VCC + 0.3 0.8 5 Units V V A A
TABLE 4C. DC CHARACTERISTICS, VCC = 2.5V 5%, 3.3V 5%; VEE = 0V
Symbol RIN VIH VIL VIN VREF_AC VDIFF_IN IIN Parameter Differential Input Resistance Input High Voltage Input Low Voltage Input Voltage Swing Reference Voltage Differential Input Voltage Swing Input Current; NOTE 1 (IN, nIN) (IN, nIN) (IN, nIN) (IN, nIN) Test Conditions IN-to-VT Minimum 40 1.2 0 0.15 VCC - 1.42 0.3 VCC - 1.37 Typical 50 Maximum 60 VCC VIH - 0.15 2.8 VCC - 1.32 3.4 35 Units V V V V V mA
NOTE 1: Guaranteed by design.
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REV. A JUNE 16, 2005
Integrated Circuit Systems, Inc.
ICS889831
LOW SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
Conditions Minimum VCC - 1.125 VCC - 1.895 0.6 1.2 Typical VCC - 1.005 VCC - 1.78 Maximum VCC - 0.935 VCC - 1.67 1.0 2.0 Units V V V V
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 2.375V TO 3.465V; VEE = 0V
Symbol VOH VOL VOUT VDIFF_OUT Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Output Voltage Swing Differential Output Voltage Swing
NOTE 1: Outputs terminated with 50 to VCC - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -3.3V 5%, -2.5V 5% OR VCC = 2.5 5%, 3.3V 5%; VEE = 0V
Symbol fMAX Parameter Maximum Output Frequency Propagation Delay; (Differential); NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section Output Rise/Fall Time Clock Enable Setup Time Clock Enable Hold Time EN to IN, nIN EN to IN, nIN 155.52MHz, Integration Range: 12kHz - 20MHz 20% to 80% 100 300 300 Condition Output Swing 450mV Input Swing: 100mV Input Swing: 800mV Minimum 2.1 300 255 435 370 570 485 30 185 0.27 250 Typical Maximum Units GHz ps ps ps ps ps ps ps ps
tPD tsk(o) tsk(pp) tjit
tR/tF tS tH
All parameters characterized at 1GHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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ICS889831
LOW SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in
0 -10 -20 -30 -40 -50 -60
the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 155.52MHz
(12kHz to 20MHz) = 0.27ps typical
SSB PHASE NOISE dBc/HZ
-70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de-
vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment.
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ICS889831
LOW SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V VCC VCC Qx
SCOPE
nIN
V Cross Points V
LVPECL
nQx VEE V EE -0.375V to -1.465V IN
IN
IH
V
IL
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx PART 1 Qx nQy PART 2 Qy
tsk(pp)
nQx Qx nQy Qy
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nIN
80% Clock Outputs
80% VSW I N G
IN nQ0:nQ3 Q0:Q3
tPD
20% tR tF
20%
OUTPUT RISE/FALL TIME
nIN IN
PROPAGATION DELAY
VIN, VOUT
VDIFF_IN, VDIFF_OUT 1600mV (typical)
EN
t HOLD t SET-UP
800mV (typical)
SETUP & HOLD TIME
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ICS889831
LOW SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER APPLICATION INFORMATION
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50
125
FOUT FIN
125
Zo = 50
Zo = 50
FOUT
50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FIN
Zo = 50 84 84
RTT =
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
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ICS889831
LOW SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
ground level. The R3 in Figure 3B can be eliminated and the termination is shown in Figure 3C.
TERMINATION FOR 2.5V LVPECL OUTPUTS
Figure 3A and Figure 3B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V VCC=2.5V
2.5V 2.5V VCC=2.5V R1 250 Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R2 62.5 R4 62.5 R3 250
Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
R3 18
FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE
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REV. A JUNE 16, 2005
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ICS889831
LOW SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
BUILT-IN 50 TERMINATION INTERFACES
by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
2.5V LVPECL INPUT
WITH
The IN /nIN with built-in 50 terminations accepts LVDS, LVPECL, LVHSTL, CML, SSTL and other differential signals. Both V OUT and V OH must meet the V PP and V CMR input requirements.Figures 4A to 4D show interface examples for the HiPerClockS IN/nIN input with built-in 50 terminations driven
3.3V or 2.5V
2.5V
2.5V
2.5V
Zo = 50 Ohm IN Zo = 50 Ohm LVDS VT nIN
Zo = 50 Ohm IN Zo = 50 Ohm VT nIN 2.5V LVPECL R1 18
Receiver With Built-In 50 Ohm
Receiver With Built-In 50 Ohm
FIGURE 4A. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY AN LVDS DRIVER
FIGURE 4B. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY AN LVPECL DRIVER
2.5V
2.5V
2.5V
2.5V
Zo = 50 Ohm IN Zo = 50 Ohm VT nIN CML - Open Collector
Zo = 50 Ohm IN Zo = 50 Ohm VT nIN CML - Built-in 50 Ohm Pull-up
Receiver With Built-In 50 Ohm
Receiver With Built-In 50 Ohm
FIGURE 4C. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY AN OPEN COLLECTOR CML DRIVER
FIGURE 4D. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY A CML DRIVER WITH BUILT-IN 50 PULLUP
2.5V R1 25 Zo = 50 Ohm IN Zo = 50 Ohm R2 25 VT nIN
2.5V
SSTL
Receiver With Built-In 50
FIGURE 4E. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY AN SSTL DRIVER
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REV. A JUNE 16, 2005
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ICS889831
LOW SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
BUILT-IN 50 TERMINATION INTERFACES
by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
3.3V LVPECL INPUT
WITH
The IN /nIN with built-in 50 terminations accepts LVDS, LVPECL, LVHSTL, CML, SSTL and other differential signals. Both VOUT and VOH must meet the VPP and VCMR input requirements. Figures 5A to 5E show interface examples for the HiPerClockS IN/nIN input with built-in 50 terminations driven
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm IN Zo = 50 Ohm LVDS VT nIN
Zo = 50 Ohm IN Zo = 50 Ohm VT nIN LVPECL R1 50
Receiver With Built-In 50 Ohm
Receiver With Built-In 50 Ohm
FIGURE 5A. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY AN LVDS DRIVER
FIGURE 5B. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY AN LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm IN Zo = 50 Ohm VT nIN CML- Open Collector
Zo = 50 Ohm IN Zo = 50 Ohm VT nIN CML- Built-in 50 Ohm Pull-Up
Receiver With Built-In 50 Ohm
Receiver With Built-In 50 Ohm
FIGURE 5C. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY A CML DRIVER WITH OPEN COLLECTOR
FIGURE 5D. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY A CML DRIVER WITH BUILT-IN 50 PULLUP
3.3V
3.3V
R1
25
Zo = 50 Ohm IN Zo = 50 Ohm VT nIN
SSTL
R2
25
Receiver With Built-In 50 Ohm
FIGURE 5E. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY AN SSTL DRIVER
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ICS889831
LOW SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
BUILT-IN 50 TERMINATION UNUSED INPUT HANDLING
3.3V DIFFERENTIAL INPUT
WITH
To prevent oscillation and to reduce noise, it is recommended to have pullup and pulldown connect to true and compliment of the unused input as shown in Figure 6.
3.3V 3.3V R1 1K IN VT nIN
R2 1K
Receiver with Built-In 50 Ohm
FIGURE 6. UNUSED INPUT HANDLING
2.5V DIFFERENTIAL INPUT
WITH
BUILT-IN 50 TERMINATION UNUSED INPUT HANDLING
To prevent oscillation and to reduce noise, it is recommended to have pullup and pulldown connect to true and compliment of the unused input as shown in Figure 7.
2.5V 2.5V R1 680 IN VT nIN
R2 680
Receiver with Built-In 50 Ohm
FIGURE 7. UNUSED INPUT HANDLING
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ICS889831
LOW SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
2.5V LVPECL driver with AC couple. The ICS889831 outputs are LVPECL driver. In this example, we assume the traces are long transmission line and the receiver is high input impedance without built-in matched load. An example of 3.3V LVPECL termination is shown in this schematic. Additional termination approaches are shown in the LVPECL Termination Application Note.
SCHEMATIC EXAMPLE
Figure 8 shows a schematic example of the ICS889831. This schematic provides examples of input and output handling. The ICS889831 input has built-in 50 termination resistors. The input can directly accept various types of differential signal without AC couple. For AC couple termination, the ICS889831 also provides the VREF_AC pin for proper offset level after the AC couple. This example shows the ICS889831 input driven by a
3.3V 3.3V C2 3.3V 0.1u Zo = 50 R3 133 R5 133 8 7 6 5
2.5V Zo = 50 C5 9 10 11 12 C6 R2 100 nIN VREF_AC VT IN
EN VCC nQ3 Q3
U1 ICS889831
Zo = 50
+
Zo = 50 LVPECL R1 100
nQ2 Q2 nQ1 Q1 VEE VCC Q0 nQ0
4 3 2 1
R4 82.5
R6 82.5
3.3V 3.3V Zo = 50 R7 133 R9 133 -
3.3V Zo = 50 C1 0.1u R8 82.5 R10 82.5 +
FIGURE 8. ICS889831 APPLICATION SCHEMATIC EXAMPLE
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ICS889831
LOW SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS839831. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS889831 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.63V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* * *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.63V * 60mA = 217.8mW Power (outputs)MAX = 30.94mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 30.94mW = 123.8mW Power Dissipation at built-in terminations: Assume the input is driven by a 3.3V SSTL driver as shown in Figure 5E and estimated approximately 1.75V drop across IN and nIN. Total Power Dissipation for the two 50 built-in terminations is: (1.75V)2 / (50 + 50) = 30.6mW
Total Power_MAX (3.63V, with all outputs switching) = 217.8mW + 123.8mW + 30.6mW = 372.2mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 0 linear feet per minute and a multi-layer board, the appropriate value is 51.5C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.372W * 51.5C/W = 104C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA
FOR
16-PIN VFQFN, FORCED CONVECTION
JAvs. 0 Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 51.5C/W
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3. Calculations and Equations.
ICS889831
LOW SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 9.
VCC
Q1
VOUT
RL
50 VCC - 2V
FIGURE 9. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = V
OH_MAX
=V
CC_MAX
- 0.935V
(VCC_MAX - VOH_MAX) = 0.935V * For logic low, VOUT = V (V
CC_MAX
OL_MAX
=V
CC_MAX
- 1.67V
-V
OL_MAX
) = 1.67V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V
OH_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OH_MAX
) = [(2V - (V
CC_MAX
-V
OH_MAX
))/R ] * (V
L
CC_MAX
-V
OH_MAX
)=
[(2V - 0.935V)/50] * 0.935V = 19.92mW
Pd_L = [(V
OL_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.67V)/50] * 1.67V = 11.02mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
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ICS889831
LOW SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
16 LEAD VFQFN
JA vs. 0 Air Flow (Linear Feet per Minute)
Multi-Layer PCB, JEDEC Standard Test Boards
51.5C/W
TRANSISTOR COUNT
The transistor count for ICS889831 is: 234 Pin compatible with SY89831U
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ICS889831
LOW SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
16 LEAD VFQFN
PACKAGE OUTLINE - K SUFFIX
FOR
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A3 b e ND NE D D2 E E2 L 0.25 0.30 0.25 3.0 1.25 0.50 0.18 0.50 BASIC 4 4 3.0 1.25 0.80 0 0.25 Reference 0.30 MINIMUM 16 1.0 0.05 MAXIMUM
Reference Document: JEDEC Publication 95, MO-220
889831AK
www.icst.com/products/hiperclocks.html
17
REV. A JUNE 16, 2005
Integrated Circuit Systems, Inc.
ICS889831
LOW SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
Marking 831A 831A TBD TBD Package 16 Lead VFQFN 16 Lead VFQFN 16 Lead "Lead-Free" VFQFN 16 Lead "Lead-Free" VFQFN Shipping Packaging tube 3500 tape & reel tube 3500 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS889831AK ICS889831AKT ICS889831AKLF ICS889831AKLFT
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 889831AK
www.icst.com/products/hiperclocks.html
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REV. A JUNE 16, 2005

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