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HM-6617
March 1997
2K x 8 CMOS PROM
Description
The HM-6617 is a 16,384 bit fuse link CMOS PROM in a 2K word by 8-bit/word format with "Three-State" outputs. This PROM is available in the standard 0.600 inch wide 24 pin SBDIP, the 0.300 inch wide slimline SBDIP, and the JEDEC standard 32 pad CLCC. The HM-6617 utilizes a synchronous design technique. This includes on-chip address latches and a separate output enable control which makes this device ideal for applications utilizing recent generation microprocessors. This design technique, combined with the Intersil advanced self-aligned silicon gate CMOS process technology offers ultra-low standby current. Low ICCSB is ideal for battery applications or other systems with low power requirements. The Intersil NiCr fuse link technology is utilized on this and other Intersil CMOS PROMs. This gives the user a PROM with permanent, stable storage characteristics over the full industrial and military temperature voltage ranges. NiCr fuse technology combined with the low power characteristics of CMOS provides an excellent alternative to standard bipolar PROMs or NMOS EPROMs. All bits are manufactured storing a logical "0" and can be selectively programmed for a logical "1" at any bit location.
Features
* Low Power Standby and Operating Power - ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100A - ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA at 1MHz * Fast Access Time. . . . . . . . . . . . . . . . . . . . . . . 90/120ns * Industry Standard Pinout * Single 5.0V Supply * CMOS/TTL Compatible Inputs * High Output Drive . . . . . . . . . . . . . . . . 12 LSTTL Loads * Synchronous Operation * On-Chip Address Latches * Separate Output Enable
Ordering Information
PACKAGE TEMP. RANGE SBDIP SMD# SLIM SBDIP SMD# CLCC SMD# 90ns 120ns HM16617-9 PKG. NO. D24.6 -40oC to +85oC HM16617B-9
-55oC to +125oC 59625962D24.6 8954002JA 8954001JA -40oC to +85oC HM66617B-9 HM66617-9 D24.3
-55oC to +125oC 59625962D24.3 8954002LA 8954001LA -40oC to +85oC HM46617B-9 HM46617-9 J32.A
-55oC to +125oC 59625962J32.A 8954002XA 8954001XA
Pinouts
HM-6617 (SBDIP) TOP VIEW
A7
HM-6617 (CLCC) TOP VIEW
VCC NC NC NC NC NC
PIN DESCRIPTION PIN
29 A8 28 A9 27 NC 26 P 25 G 24 A10 23 E 22 Q7 21 Q6
DESCRIPTION No Connect Address Inputs Chip Enable Data Output Power (+5V) Output Enable Output Enable
A7 A6 A5 A4 A3 A2 A1 A0 Q0
1 2 3 4 5 6 7 8 9
24 VCC 23 A8 22 A9 21 P 20 G 19 A10 18 E 17 Q7 16 Q6 15 Q5 14 Q4 13 Q3 A6 5 A5 6 A4 7 A3 8 A2 9 A1 10 A0 11 NC 12 Q0 13
4
3
2
1
32 31 30
NC A0-A10 E Q VCC G P (Note)
Q1 10 Q2 11 GND 12
14 15 16 17 18 19 20 Q1 Q2 Q3 Q4 GND NC Q5
NOTE: P should be hardwired to VCC except during programming.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
3017.1
6-1
HM-6617 Functional Diagram
MSB A10 A9 A8 A7 A6 A5 A4 A LATCHED ADDRESS REGISTER A 7 LSB L G 16 16 16 16 16 16 16 16 G E GATED COLUMN DECODER AND DATA OUTPUT CONTROL A 4 G L ALL LINES POSITIVE LOGIC: ACTIVE HIGH MSB A3 A2 A1 A0 THREE-STATE BUFFERS: A HIGH OUTPUT ACTIVE ADDRESS LATCHES AND GATED DECODERS: LATCH ON FALLING EDGE OF E GATE ON FALLING EDGE OF G LATCHED ADDRESS REGISTER LSB A 4 Q6 Q7 8 Q3 Q4 Q5 Q2 7 GATED ROW DECODER 128 x 128 MATRIX Q0 Q1
128
6-2
HM-6617 Background Information Programming Algorithm
The HM-6617 CMOS PROM is manufactured with all bits containing a logical zero (output low). Any bit can be programmed selectively to a logical one (output high) state by following the procedure shown below. To accomplish this, a programmer can be built that meets the specifications shown, or any of the approved commercial programmers can be used. Programming Sequence Of Events 1. Apply a voltage of VCC1 to VCC of the PROM. 2. Read all fuse locations to verify that the PROM is blank (output low). 3. Place the PROM in the initial state for programming: E = VIH, P = VIH, G = VIL. 4. Apply the correct binary address for the word to be programmed. No inputs should be left open circuit. 5. After a delay of tD, apply voltage of VIL to E (pin 18) to access the addressed word. 6. The address may be held through the cycle, but must be held valid at least for a time equal to tD after the falling edge of E. None of the inputs should be allowed to float to an invalid logic level. 7. After a delay of tD, disable the outputs by applying a voltage of VIH to G (pin 20). 8. After a delay of tD, apply voltage of VIL to P (pin 21). 9. After delay of tD, raise VCC (pin 24) to VCCPROG with a rise time of tR. All outputs at VIH should track VCC with VCC -2.0V to VCC +0.3V. This could be accomplished by pulling outputs at VIH to VCC through pull-up resistors of value Rn. 10. After a delay of tD, pull the output which corresponds to the bit to be programmed to VIL. Only one bit should be programmed at a time. 11. After a delay of tPW, allow the output to be pulled to VIH through pull-up resistor Rn. 12. After a delay of tD, reduce VCC (pin 24) to VCC1 with a fall time of tF. All outputs at VIH should track VCC with VCC 2.0V to VCC +0.3V. This could be accomplished by pulling outputs at VIH to VCC through pull-up resistors of value Rn. 13. Apply a voltage of VIH to P (pin 21). 14. After a delay of tD, apply a voltage of VIL to G (pin 20). 15. After a delay of tD, examine the outputs for correct data. If any location verifies incorrectly, repeat steps 4 through 14 (attempting to program only those bits in the word which verified incorrectly) up to a maximum of eight attempts for a given word. If a word does not program within eight attempts, it should be considered a programming reject. 16. Repeat steps 3 through 15 for all other bits to be programmed in the PROM. Post-Programming Verification 17. Place the PROM in the post-programming verification mode: E = VIH, G = VIL, P = VIH, VCC (pin 24) = VCC1. 18. Apply the correct binary address of the word to be verified to the PROM. 19. After a delay of tD, apply a voltage of VIL to E (pin 18). 20. After a delay of tD, examine the outputs for correct data. If any location fails to verify correctly, the PROM should be considered a programming reject. 21. Repeat steps 17 through 20 for all possible programming locations Post-Programming Read 22. Apply a voltage of VCC2 = 4.0V to VCC (pin 24). 23. After a delay of tD, apply a voltage of VIH to E (pin 18). 24. Apply the correct binary address of the word to be read. 25. After a delay of TAVEL, apply a voltage of VIL to E (pin 18). 26. After a delay of TELQV, examine the outputs for correct data. If any location fails to verify correctly, the PROM should be considered a programming reject. 27. Repeat steps 23 through 26 for all address locations. 28. Apply a voltage of VCC2 = 6.0V to VCC (pin 24). 29. Repeat steps 23 through 26 for all address locations.
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HM-6617 Programming Cycle
PROGRAMMING VCC PROG VIH VIL VIH VIL tD G VCC PROG VIH VIL VCC PROG VIH VIL VCC PROG VCC GND VCC PROG VIH/VOH VIL/VOL tR tD
VERIFY
A
VALID tD
VALID TEHEL
E
tD
P
tD
VCC
tD
tPW
tD
tF READ DATA
Q
FIGURE 1. HM-6617 PROGRAMMING CYCLE
A
VIH VIL TAVEL
VALID TEHEL TEHEL
E
VIH VIL TEHEL 6.0V 5.0V 4.0V tD tD
VCC
0.0V TELQV VOH VOL TELQV TELQV
Q
READ
READ
READ
FIGURE 2. HM-6617 POST PROGRAMMING VERIFY CYCLE
6-4
HM-6617 Background Information HM-6617 Programming
Programming Specifications
SYMBOL VIL VIH VCCPROG VCC1 VCC2 tD tR tF TEHEL TAVEL TELQV tPW tIP IOP Rn TA NOTES: 1. All inputs must track VCC (pin 24) within these limits. 2. VCCPROG must be capable of supplying 500mA. 3. See Steps 22 through 29 of the Programming Algorithm. 4. See Step 11 of the Programming Algorithm. 5. All outputs should be pulled up to VCC through a resistor of value Rn. 6. Except during programming (See Programming Cycle Waveforms). Input "0" Voltage "1" (Note 6) Programming VCC (Note 2) Operating VCC Special Verify VCC (Note 3) Delay Time Rise Time Fall Time Chip Enable Pulse Width Address Valid to Chip Enable Low Time Chip Enable Low to Output Valid Time Programming Pulse Width (Note 4) Input Leakage at VCC = VCCPROG Data Output Current at VCC = VCCPROG Output Pull-Up Resistor (Note 5) Ambient Temperature PARAMETER MIN 0.0 VCC-2 12.0 4.5 4.0 1.0 1.0 1.0 50 20 90 -10 5 TYP 0.2 VCC 12.0 5.5 1.0 10.0 10.0 100 +1.0 -5.0 10 25 MAX 0.8 VCC+0.3 12.5 5.5 6.0 10.0 10.0 120 110 10 -10 15 UNITS V V V V V s s s ns ns ns s A mA k
oC
6-5
HM-6617
Absolute Maximum Ratings
Supply Voltage (All Voltages Reference to Device GND) . . . . . +7.0V Input or Output Voltage Applied for All Grades. . . . . . .GND -0.3V to VCC +0.3V Typical Derating Factor . . . . . . . . . . . . 5mA/MHz Increase in ICCOP ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical) JA JC SBDIP Package . . . . . . . . . . . . . . . . . . 48oC/W 9oC/W Slim SBDIP . . . . . . . . . . . . . . . . . . . . . 65oC/W 14oC/W CLCC Package . . . . . . . . . . . . . . . . . . 58oC/W 19oC/W Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range: HM-6617-9, B-9 . . . -40oC to +85oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5473 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications
SYMBOL VIH VIL VOH1 VOH2 VOL II IOZ ICCSB ICCOP
VCC = 5V 10%; (HM-6617B-9, HM-6617-9) MIN 2.4 -0.3 2.4 VCC-1.0 -1.0 -1.0 MAX VCC+0.3 0.8 0.4 +1.0 +1.0 100 20 UNITS V V V V V A A A mA VCC = 5.5V VCC = 4.5V IOH = -2.0mA, VCC = 4.5V IOH = -100A, VCC = 4.5V IOL = +4.8mA, VCC = 4.5V VIN = VCC or GND, VCC = 5.5V VO = VCC or GND, G = VCC, VCC = 5.5V VIN = VCC or GND, VCC = 5.5V, IO = 0 f = 1MHz, VCC = 5.5V, IO = 0, VIN = VCC or GND TEST CONDITIONS
PARAMETER Logical One Input Voltage Logical Zero Input Voltage Logical One Output Voltage Logical One Output Voltage (Note 2) Logical Zero Output Voltage Input Leakage Output Leakage Standby Power Supply Current Operating Power Supply Current (Note 3)
AC Electrical Specifications
HM-6617B-9 SYMBOL (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) TAVQV TELQV TELQX TAVEL TELAX TELEH TEHEL TELEL TGLQV TGLQX TGHQZ TEHQZ PARAMETER Address Access Time Chip Enable Access Time Chip Enable Time Address Setup Time Address Hold Time Chip Enable Low Width Chip Enable High Width Cycle Time Output Access Time Output Enable Time Output Disable Time Chip Enable Disable Time MIN 5 15 20 95 40 136 5 MAX 105 90 40 40 45 HM-6617-9 MIN 5 20 25 120 40 160 5 MAX 140 120 50 50 50 UNITS ns ns ns ns ns ns ns ns ns ns ns ns TEST CONDITIONS (Notes 1, 4) (Notes 1, 4) (Notes 2, 4) (Notes 1, 4) (Notes 1, 4) (Notes 1, 4) (Notes 1, 4) (Notes 1, 4) (Notes 1, 4) (Notes 2, 4) (Notes 2, 4) (Notes 2, 4)
6-6
HM-6617
Capacitance
SYMBOL CIN COUT NOTES: 1. Input pulse levels: 0 to 3.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate equivalent CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF. 2. Tested at initial design and after major design changes. 3. Typical derating 5mA/MHz increase in ICCOP. 4. VCC = 4.5V and 5.5V. TA = +25oC PARAMETER Input Capacitance (Note 2) Output Capacitance (Note 2) MAX 10 12 UNITS pF pF TEST CONDITIONS f = 1MHz, All Measurement are Referenced to Device GND f = 1MHz, All Measurement are Referenced to Device GND
Switching Waveforms
TAVQV (1) ADDRESSES 1.5V VALID ADDRESS TAVEL (4) 1.5V TEHEL (7) G 1.5V (10) TGLQX DATA OUTPUT Q0-Q7 (3) TELQX TELAX 1.5V TELQV (2) TGLQV (9) 1.5V 0V (11) TGHQZ VALID DATA TS 1.5V TELEL (8) TELEH (6) 1.5V TEHQZ (12) 3.0V 1.5V 0V VALID ADDRESSES 3.0V 0V
(5)
3.0V
E
FIGURE 3. READ CYCLE
Test Circuit
DUT CL (NOTE)
IOH NOTE: TEST HEAD CAPACITANCE
1.5V
IOL
EQUIVALENT CIRCUIT
FIGURE 4. TEST CIRCUIT
6-7
HM-6617
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Sales Office Headquarters
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6-8

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