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TC9WMA1FK
TOSHIBA CMOS Digital Integrated Circuits Silicon Monolithic
TC9WMA1FK
1,024-Bit (128 x 8 Bit) Serial E PROM
2
The TC9WMA1FK is electrically nonvolatile memory (E2PROM). erasable/programmable
Features
* * * * * * * * Serial data input/output Programmable in units of one word and collectively erasable in one operation Automatically set programming time (built-in timer) Programming time: 10 ms (max) (VCC = 3.0 to 3.6 V) 13 ms (max) (VCC = 2.7 to 3.6 V) Overwriting enabled or disabled by software Single power supply and low power consumption Operating power supply voltage (2.7 to 3.6 V) Wide operating temperature range (-40 to 85C) Weight: 0.01 g (typ.)
Product Marking
US8
Type name
Pin Assignment (top view)
CS CLK
8
7
DI 6
DO 5
1 2 3 4 VCC NC RST GND
000707EBA1
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
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Block Diagram
Chip select CS Clock input CLK
Timing generator
Control circuit
Power supply (booster circuit)
VCC Power supply Reset input
RST
Data Input DI Input/Output circuit Data Output DO
Command register Memory cell Address Address register decoder GND Ground
Data register
Pin Function
Pin Name Input/Output Function Chip select A low on CS selects the chip. Always return CS high temporarily before executing instructions. Clock input The data on DI is latched by a rising edge of CLK . Data is output to DO by a falling edge of CLK . CLK is effective when CS is low. Serial data input This pin is used to enter addresses, commands, and data into the chip. Serial data output This pin outputs data from the chip. Reset input A low on this input resets the chip. No connection (not connected internally) 2.7 V~3.6 V 0 V (GND)
CS
Input
CLK
Input
DI DO
RST
Input Output Input Power supply
NC VCC GND
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Functional Description
1. Types of Instructions
Operation Read Program All erase Busy monitor Overwrite enable Overwrite disable Address A0~A6, 0 A0~A6, 0 ******** ******** ******** ******** 1 0 0 1 1 1 0 1 0 0 0 1 0 1 1 1 0 0 Command C0 C1 C2 C3 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D0~D7 Data
*: Don't care
2. Operation Method
Be sure to return CS and CLK high temporarily before entering instructions. After CS is asserted low, CLK becomes effective, acting as a serial transfer synchronizing signal. The data on DI is latched by a rising edge of CLK , while data is output to DO by a falling edge of CLK . Instructions can only be executed when the chip is not being programmed or collectively erased (i.e., when the ready/busy status signal is high). However, the Busy Monitor instruction can be entered at any time. Only the commands listed in the above table can be used. Do not use any other command. (1) Read When the Read instruction is entered, memory data at the specified address is read out and is serially output from the DO pin. Program When the Program instruction is entered, overwrite operation automatically starts internally in the chip, and memory data at the specified address is overwritten with the input data. After the instruction is entered, CS can be returned high even while overwrite operation is in progress internally. All Erase When the All Erase instruction is entered, erase operation automatically starts internally in the chip, and memory data at all addresses are erased. After the instruction is entered, CS can be returned high even while erase operation is in progress internally. Execution of this command clears the memory data to 0. Busy Monitor When the Busy Monitor instruction is entered, a ready/busy status signal is output from the DO pin. This output signal is low while the chip is being programmed or collectively erased, and is high after programming or collective erase operation is completed. The ready/busy status signal is output continuously until CS is returned high. Overwrite Enable/Disable When the Overwrite Enable instruction is entered, the chip is placed in overwrite enable mode, where the Program and All Erase instructions are enabled. When the Overwrite Disable instruction is entered, the chip is placed in overwrite disable mode, where the Program and All Erase instructions both are disabled. Once the chip is placed in overwrite disable mode, it remains disabled against overwriting unless the Overwrite Enable instruction is entered.
(2)
(3)
(4)
(5)
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3. Precautions to be Taken at Power ON/OFF
(1) (2) (3) A wait time of 1 ms is required before the chip starts operation after it is powered on. RST must be pulled low when the power to the chip turns ON or OFF. The chip is placed in overwrite disable mode by reset.
4. Timing Chart
(1) Read
CS
1
CLK
2
7
8
9
10
11
12
13
14
15
16
17
23
24
DI
A0
A1
A6
0
1
0
0
0
0
0
0
0
Address
Command
DO Hi-Z
D0
D6 Data
D7 Hi-Z
(2)
Program
CS
1
CLK
2
7
8
9
10
11
12
13
14
15
16
17
23
24
DI
A0
A1 Address
A6
0
0
1
1
0
0
0
0
0
D0
D6
D7
Command
DO Hi-Z
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(3) All Erase
CS
1
CLK
2
7
8
9
10
11
12
13
14
15
16
DI
0
0
1
1
0
0
0
0
Command
DO Hi-Z
(4)
Busy Monitor
CS
1
CLK
2
7
8
9
10
11
12
13
14
15
16
DI
1
0
1
1
0
0
0
0
Command
DO Hi-Z Hi-Z
(5)
Overwrite Enable/Disable
CS
1
CLK
2
7
8
9
10
11
12
13
14
15
16
Enable DI Disable
1
0
0
1
0
0
0
0
Command
1
1
0
1
0
0
0
0
Command
DO Hi-Z
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Maximum Ratings (GND = 0 V)
Characteristics Power supply voltage Input voltage Output voltage Power dissipation Soldering temperature (in time) Storage temperature Operating temperature Symbol VCC VIN VOUT PD Tsld Tstg Topr Rating -0.3~4.6 -0.3~VCC + 0.3 -0.3~VCC + 0.3 200 (25C) 260 (10 s) -55~125 -40~85 Unit V V V mW C C C
Recommended Operating Conditions (GND = 0 V, Topr = -40~85C)
Characteristics Power supply voltage Symbol VCC Test Condition Min 2.7 Max 3.6 Unit V
Recommended Operating Conditions (GND = 0 V, VCC = 2.7~3.6 V, Topr = -40~85C)
Characteristics Low level input voltage High level input voltage Operating frequency Symbol VIL VIH1 VIH2 fCLK
CS , DI, RST CLK
Pin
Test Condition VCC = 2.7 V VCC = 3.6 V VCC = 3.6 V
Min 0 1.6 2.2 0
Max 0.45 VCC VCC 1
Unit V V MHz
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Electrical Characteristics D.C. Characteristics (GND = 0 V, VCC = 2.7~3.6 V, Topr = -40~85C)
Characteristics Input current Output leakage current High level output voltage Low level output voltage Quiescent supply current Supply current during read Supply current during all erase/program Symbol ILI ILO VOH VOL ICC1 (Note1) ICC2 (Note2) ICC3 (Note3) VCC = 2.7 V, IOH = -1 mA VCC = 2.7 V, IOL = 2 mA Test Condition Min Typ. Max 5 5 Unit A A V V A mA mA

VCC - 0.4

0.4 5 1.5 1.0

Note1: CS = 1 (except when busy, however) Note2: Current that flows for a period from a fall of the 14th to a fall of the 17th CLK pulse when executing the read instruction. Note3: Current that flows while executing the all erase or program instruction.
A.C. Characteristics (GND = 0 V, VCC = 2.7~3.6 V, Topr = -40~85C)
Characteristics Maximum clock frequency Minimum clock pulse width Minimum reset pulse width Minimum chip select pulse width Reset setup time Clock setup time
CS setup time
Symbol fMAX twCLK (L) twCLK (H) tWRST tWCS tRSS tCKS tCSS tpLH tpHL
Test Condition
Min 0 400 1 1
Max 1
Unit MHz ns s s s ns ns
RST setup time when CS is switched over CLK setup time when CS is switched over CS setup time when CLK is switched over
1 250 250

Propagation delay time
(Note4)
tpZH tpZL tpLZ tpHZ
Time from CLK switchover until valid data is output
250 ns
Time from CS switchover until output data goes Hi-Z Input data setup time when CLK is switched over Input data hold time when CLK is switched over
250 250
500
Input data setup time Input data hold time
ts th

ns ns
Note4: CL = 100 pF, RL = 1 k
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< < E PROM Characteristics (GND = 0 V, 3.0 V = VCC = 3.6 V, Topr = -40~85C)
Characteristics All erase time Program time Endurance Data retention time Symbol tE tP NEW tRET Test Condition Min 1 x 10 10
5
2
Typ. 6 6
Max 10 10
Unit ms ms Times Year
< < E PROM Characteristics (GND = 0 V, 2.7 V = VCC = 3.6 V, Topr = -40~85C)
Characteristics All erase time Program time Endurance Data retention time Symbol tE tP NEW tRET Test Condition Min 1 x 10 10
5
2
Typ. 7 7
Max 13 13
Unit ms ms Times Year
Capacitance Characteristics (Ta = 25C)
Characteristics Input capacitance Output capacitance Equivalent Internal capacitance Symbol CIN CO CPD fIN = 1 MHz (Note5) Test Condition VCC (V) 3.3 3.3 3.3 4 3 8.5 pF pF pF Typ. Unit
Note5: CPD denotes the IC's internal equivalent capacitance calculated from the amount of current it consumes while operating. The average current consumption during non-loaded operation is obtained from the equations below. ICC (Read) = fCLK CPD VCC + ICC1 + ICC2 3.5/24 ICC (Prog) = fCLK CPD VCC + ICC1 + ICC3
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A.C. Characteristics Timing Chart
tCKS
CS
tCSS VCC/2
tCKS
tCSS VCC GND VCC
CLK
VCC/2 GND ts th VCC VCC/2 GND VCC/2 tPLH tPHL tPLH tPHL VCC
CLK
DI
CLK
VCC/2 GND VCC/2 tPLZ tPHZ VCC
DO
CS
VCC/2 GND VCC
CLK
GND HiZ DO tPZH tPZL VCC
CLK
VCC/2
VCC/2 GND HiZ VCC/2
DO
tWCLK (L) tWCLK (H) VCC
CLK
VCC/2
VCC/2 GND tWRST VCC
RST
VCC/2
VCC/2 GND tRSS VCC
RST
VCC/2 GND VCC/2
CS
tWCS VCC
CS
VCC/2
VCC/2 GND
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Input/Output Circuits of Pins
Pin Name
CS
Type
Input/Output Circuit
Remarks
DI RST
Input
CLK
Input
Hysteresis input
Output control signal
VCC
DO
Output
Initial "HiZ"
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Package Dimensions
Weight: 0.01 g (typ.)
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