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FUJITSU SEMICONDUCTOR DATA SHEET
DS06-20206-1E
Semicustom
CMOS
Standard cell array
CS81 Series
s DESCRIPTION
The CS81 series of 0.18 m CMOS standard cell arrays is a line of highly integrated CMOS ASICs featuring high speed and low power consumption at the same time. This series incorporates up to 40 million gates which have a gate delay time of 11 ps, resulting in both integration and speed about three times higher than conventional products. In addition, this series can operate at a power-supply voltage of up to 1.1 V, substantially reducing power consumption.
s FEATURES
* Technology * * * * * * * * * * * * * * * * * * * * : 0.18 m silicon-gate CMOS, 3- to 5-layer wiring capable of integrating a mixture of highspeed processes and cells on a single chip (under development) Supply voltage : +1.8 V 0.15 V (typical) to +1.1 V 0.1 V Junction temperature range : -40 to +125 C (standard specification) Gate delay time : tpd = 11 ps (1.8 V, inverter, F/O = 1) Gate power consumption : 5 nW/MHz/BC (1.1 V, 2-NAND, F/O = 1) High-load drive capability : IOL = 2/4/8/12 mA mixable Output buffer cells with noise reduction circuits Inputs with on-chip input pull-up/pull-down resistors (33 k typical) and bidirectional buffer cells Buffer cell dedicated to crystal oscillator Special interfaces (P-CML, LVDS, PCI, AGP, USB, SDRAM-I/F, SSTL, etc. under development) IP macros (CPU, DSP, PCI, IEEE1394, USB, IrDA, PLL, ADC, DAC, etc. under development) Capable of incorporating compiled cells (RAM/ROM/multiplier, etc.) Configurable internal bus circuits Advanced hardware/software co-design environment Short-term development using a timing driven layout tool Support for static timing sign-off Dramatically reducing the time for generating test vectors for timing verification and the simulation time Hierarchical design environment for supporting large-scale circuits Simulation (before layout) considering the input slew rate and detailed RC delay calculation (after layout) , supporting development with minimized timing trouble after trial manufacture Support for memory (RAM/ROM) SCAN Support for memory (RAM) BIST Support for boundary SCAN (Continued)
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CS81 Series
(Continued) * Support for path delay test * A variety of package options (TQFP, HQFP, EBGA, FBGA, TAB-BGA, FCBGA)
s MACRO LIBRARY (Including macros being prepared)
1.
* * * * * * * * * *
Logic cells (about 400 types)
Adder AND-OR Inverter Clock Buffer Latch NAND AND NOR SCAN Flip Flop ENOR AND-OR * * * * * * * * * * Decoder Non-SCAN Flip Flop Inverter Buffer OR-AND Inverter OR Selector BUS Driver EOR Others
2. IP macros
CPU/DSP Interface macro Multimedia processing macros Mixed signal macros Compiled macros PLL FR, SPARClite, standard CPU (under preparation) Communications DSP, DSP for AV PCI, IEEE1394, USB, IrDA, etc. JPEG, MPEG, etc. ADC, DAC, OPAMP, etc. RAM, ROM, multiplier, adder, multiplier-accumulator, etc. Analog PLL, digital PLL
3. Special I/O interface macros
* T-LVTTL * LVDS * IEEE1394 * SSTL * PCI * HSTL * AGP * P-CML * USB
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CS81 Series
s COMPILED CELLS
Compiled cells are macro cells which are automatically generated with the bit/word configuration specified. The CS81 series has the following types of compiled cells. (Note that each macro is different in word/bit range depending on the column type.)
1. Clock synchronous single-port RAM (1 address, 1 RW)
Column type 4 16 Memory capacity 16 to 72 K 64 to 72 K Word range 16 to 1 K 64 to 4 K Bit range 1 to 72 1 to 18 Unit Bit Bit
2. Clock synchronous dual-port RAM (2 addresses, 1 RW/ 1 R)
Column type 4 16 Memory capacity 16 to 72 K 64 to 72 K Word range 16 to 1 K 64 to 4 K Bit range 1 to 72 1 to 18 Unit Bit Bit
3. Clock synchronous ROM
Column type 8 16 Memory capacity 128 to 512 K 128 to 512 K Word range 32 to 4 K 64 to 8 K Bit range 4 to 128 2 to 64 Unit Bit Bit
s HIGH-CAPACITY MEMORY
* Clock synchronous single port RAM (1 address, 1 RW) Column type Memory capacity Word range Under development Bit range Unit
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CS81 Series
s ABSOLUTE MAXIMUM RATINGS
(VSS = 0 V) Parameter Power supply voltage Symbol VDD Application VDD, VDDI (Internal) VDDE (External) 1.8 V input pin Input voltage*1 VI 3.3 V input pin 1.8 V output pin Output voltage VO 3.3 V output pin Storage temperature Power-supply pin current *2 TST ID Plastic package Per VDD/VDDI/VDDE pin Per VSS pin L type output buffer IOL = 2 mA Output current*3 IO M type output buffer IOL = 4 mA H type output buffer IOL = 8 mA V type output buffer IOL = 12 mA VSS - 0.5 -55 VSS - 0.5 VSS - 0.5 Rating Min. VSS - 0.5 VSS - 0.5 VSS - 0.5 Max. +2.5 +4.0 VDDI + 0.5 ( 2.5 V) VDDE + 0.5 ( 4.0 V) VDDI + 0.5 ( 2.5 V) VDDE + 0.5 ( 4.0 V) +125 TBD TBD 13 13 13 26 Unit V V V V V V C mA mA mA mA mA mA
*1 : Do not apply any voltage of 1.1 V or more between the LVDS (resistor built-in type) differential inputs. *2 : Maximum supply current which can be supplied constantly. *3 : Maximum output current which can be supplied constantly. Exceeding the rating is allowed only within 1 second for only one LSI pin. The maximum rating of the P-CML output buffer is 20 mA. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
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CS81 Series
s RECOMMENDED OPERATING TEMPERATURE
* Single power supply (VDD = +1.8 V 0.15 V) Parameter Power supply voltage (1.8 V supply voltage) "H" level input voltage (1.8 V CMOS level) "L" level input voltage (1.8 V CMOS level) Operating junction temperature Symbol VDD VIH VIL Tj Value Min. 1.65 VDD x 0.65 -0.3 -40 Typ. 1.8 Max. 1.95 VDD + 0.3 VDD x 0.35 +125 (VSS = 0 V) Unit V V V C
* Dual power supply (VDDI = +1.8 V 0.15 V, VDDE = +3.3 V 0.3 V) Parameter Power supply voltage "H" level input voltage "L" level input voltage 1.8 V supply voltage 3.3 V supply voltage 1.8 V CMOS level 3.3 V CMOS level 1.8 V CMOS level 3.3 V CMOS level Symbol VDDI VDDE VIH VIL Tj Value Min. 1.65 3.0 VDD x 0.65 2.0 -0.3 -0.3 -40 Typ. 1.8 3.3 Max. 1.95 3.6 VDDI + 0.3 VDDE + 0.3 VDD x 0.35 0.8 +125
(VSS = 0 V) Unit V V V C
Operating junction temperature
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
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CS81 Series
s ELECTRICAL CHARACTERISTICS
1. DC characteristics
* Single power supply : VDD = 1.8 V Parameter Power supply voltage "H" level output voltage "L" level output voltage Symbol IDDS VOH VOL Conditions Static state*1, *2 IOH = -100 A IOL = -100 A L type "H" level output current IOH M type Output pin VOH = VDD - 0.2 V H type V type L type "L" level output current IOL Output pin VOL = 0.2 V M type H type V type L type M type Output short-circuit current*3 IOS1 H type V type U type Input leak current*4 Input pull-up/pull-down resistance*5 ILI ILZ RP Input pin Tristate pin (for input) Pull-up VI = 0 Pull-down VI = VDD TBD 18 5 5 TBD A k TBD mA 1.0 2.0 4.0 6.0 mA (VDDI = 1.8 V 0.15 V, VSS = 0 V, Tj = -40 C to +125 C) Value Min. VDD - 0.2 VDDE - 0.2 Typ. Max. TBD VDD VDDE -1.0 -2.0 -4.0 -6.0 mA Unit mA V V
*1 : When the memory macro is in standby mode and analog macro is in power-down mode. At both case, conditions are VIH = VDD, VIL = VSS, and Tj = +25 C. *2 : The above value may not be guaranteed when the input/output buffer with pull-up/pull-down resistor or crystal oscillator buffer is used. *3 : The maximum current which flows when the output pin is shorted to VDD or VSS. Keep the output short-circuit current below the maximum rating. *4 : The input leakage current may exceed the above value when the input buffer with pull-up/pull-down resistor is used. *5 : Input pull-up/pull-down is optional in input and bidirectional buffers.
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CS81 Series
* Dual power supply : VDDI = 1.8 V and VDDE = 3.3 V (VDDI = 1.8 V 0.15 V, VDDE = 3.3 V 0.3 V, VSS = 0 V, Tj = -40 C to +125 C) Parameter Power supply voltage Symbol IDDS Conditions Static state*1, *2 3.3 V Output pin IOH = -100 A 1.8 V Output pin IOH = -100 A IOL = -100 A L type 3.3 V Output pin M type VOH = VDDE - 0.4 V H type "H" level output current IOH V type L type 1.8 V Output pin M type VOH = VDDI - 0.2 V H type V type L type 3.3 V Output pin VOL = 0.4 V "L" level output current IOL 1.8 V Output pin VOL = 0.2 V M type H type V type L type M type H type V type L type Output short-circuit current*3 IOS1 Output pin VO = 0 V or VDD M type H type V type Input leak current*4 ILI ILZ Input pin Tristate pin (for input) 1.8 V I/O buffer Pull-up VI = 0 Pull-down VI = VDDI 3.3 V I/O buffer Pull-up VI = 0 Pull-down VI = VDDE TBD 18 5 5 TBD k 10 33 60 A TBD mA 2.0 4.0 8.0 12.0 1.0 2.0 4.0 6.0 mA mA Value Min. VDDE - 0.2 VDDI - 0.2 VDDE - 0.2 Typ. Max. TBD VDDE VDDI VDDE -2.0 -4.0 -8.0 -12.0 -1.0 -2.0 -3.0 -6.0 mA mA Unit mA V V V
"H" level output voltage
VOH
"L" level output voltage
VOL
Input pull-up/pull-down resistance*5
RP
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CS81 Series
*1 : When the memory macro is in standby mode and analog macro is in power-down mode. At both case, conditions are VIH = VDD, VIL = VSS, and Tj = +25 C. *2 : The above value may not be guaranteed when the input/output buffer with pull-up/pull-down resistor or crystal oscillator buffer is used. *3 : The maximum current which flows when the output pin is shorted to VDD or VSS. Keep the output short-circuit current below the maximum rating. *4 : The input leakage current may exceed the above value when the input buffer with pull-up/pull-down resistor is used. *5 : Input pull-up/pull-down is optional in input and bidirectional buffers.
2. AC characteristics
Parameter Delay time Symbol tpd*1
(VDD = 1.8 V 0.15 V, VSS = 0 V, Tj = -40 C to +125 C) Value Min. typ*2 x m (TBD) Max. typ*2 x n (TBD) Unit ns
*1 : Delay time = propagation delay time, Enable time, Disable time *2 : "typ" is calculated from the cell specification.
s INPUT/OUTPUT CAPACITANCE
(f = 1 MHz, VDD = VI = 0 V, Ta = +25 C) Parameter Input pin Output pin Input/output capacitance Symbol CIN COUT CI/O Value Max.16 Max.16 Max.16 Unit pF pF pF
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CS81 Series
s DESIGN METHOD
SCCAD2 is the standard cell integrated design environment providing three major functions, enabling highquality, large-scale system LSIs to be developed in a shorter period of time. They include: the timing driven layout function for automatic placement/routing based on timing constraints to prevent timing problems after layout, the function for shortening the development cycle time by dividing a large-scale circuit and performing simultaneous logical/physical design of multiple circuits, and the function for automatically generating power/signal wiring patterns while evaluating the supply voltage drop, signal noise, delay penalty, and crosstalk (Contact your nearest Fujitsu office for more information and availability.).
s SUPPORT TOOLS
* Simulation Synopsys, Inc. : VSS, VCS Cadence Design Systems, Inc. : Verilog-XL, NC-Verilog, Leapfrog Model Technology, Inc. : V-System FUJITSU LIMITED : LCADFE * Logic synthesis Synopsys, Inc. : DesignCompiler * Floor plan Cadence Design Systems, Inc. : LDP, PDP * Clock tree Cadence Design Systems, Inc. : CT-Gen * Timing analysis Synopsys, Inc. : PrimeTime FUJITSU LIMITED : GISTA * Power calculation Sente, Inc. : Watt Watcher Synopsys, Inc. : DesignPower, PowerCompiler FUJITSU LIMITED : PScope, SilicoScope IRD * Layout Cadence Design Systems, Inc. : SiliconEnsemble DSM * Test tools FUJITSU LIMITED : ATREX, FANTCAD, RAPARA, TERBAN, FANSCAD * Format verification Chrysalis Symbolic Design, Inc. : Design VERIFYer * Verification tool Cadence Design Systems, Inc. : Dracula * Design environment tool FUJITSU LIMITED : METRO/SCCAD2/IPSymphony * HW/SW co-simulation Synopsys, Inc. : EAGLE-i Yokogawa Electric Corporation : VIRTUAL-ICE GAIO Technology Co. LTD. : Asim-G
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CS81 Series
s PACKAGES
The table below lists the package types available and the reference number of gates used. Consult Fujitsu for the combination of each package and the time of availability. * Number of gates used and package types
Package and pin count T BA GB A 304 352 480 560 660 720 576 672 Material Usable gate numbers 0 2000K 4000K 6000K 8000K 10000K 12000K 14000K 16000K 20000K
Cavity
Pin pitch
DOWN DOWN DOWN DOWN DOWN DOWN DOWN DOWN
0.80 mm/4 rows 0.80 mm/4 rows 1.00 mm/5 rows 1.00 mm/5 rows 1.00 mm/5 rows 1.00 mm/6 rows -
1167 K 1660 K 2547 K 3620 K 4885 K 12513 K 8474 K 11246 K
E B G A H Q F P T Q F P L Q F P F B G A
208 240 304 256 100 120
UP UP UP UP UP UP
0.50 mm 0.50 mm 0.50 mm 0.40 mm -
1561 K 2948 K 5305 K 737 K 737 K
21569 K
144 176 208 112 144 168 176 192 224 272 320 288 240 304 368 1089 1225 1369 1681 1849 2116
UP UP UP UP UP UP UP UP UP UP UP UP UP UP UP DOWN DOWN DOWN DOWN DOWN DOWN
-
737 K 1028 K 1561 K 737 K 737 K 1028 K 1028 K 1561 K 2202 K 3813 K 3813 K 6643 K 3813 K 6643 K 6643 K
0.80 mm 0.80 mm 0.80 mm 0.80 mm 0.80 mm 0.80 mm 0.80 mm 0.80 mm 0.75 mm 0.50 mm 0.50 mm 0.50 mm 1.27 mm 1.27 mm 1.27 mm 1.00 mm 1.00 mm 1.00 mm
F C B G A
TBD
Note : This list contains packages under planning.
q : Plastic
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CS81 Series
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
http://www.fujitsu.co.jp/
North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179
http://www.fujitsumicro.com/
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http://www.fujitsu-ede.com/
Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
http://www.fmap.com.sg/
F9906 (c) FUJITSU LIMITED Printed in Japan

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