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FUJITSU SEMICONDUCTOR DATA SHEET
DS04-21336-2E
ASSP
Single Serial Input PLL Frequency Synthesizer
On-Chip 2.5 GHz Prescaler
MB15E06
s DESCRIPTION
The Fujitsu MB15E06 is serial input Phase Locked Loop (PLL) frequency synthesizers with a 2.5 GHz prescaler. A 64/65 or a 128/129 can be selected for the prescaler that enables pulse swallow operation. The latest BiCMOS process technology is used, resuItantly a supply current is limited as low as 8 mA typ. This operates with a supply voltage of 3.0 V (typ.) . Furthermore, a super charger circuit is included to get a fast tuning as well as low noise performance. As a result of this, MB15E06 is ideally suitable for digital mobile communications, such as GPS (Global Positioning System) , Wireless LAN, CATV (CAble TeleVision) etc.
s FEATURES
* * * * * * * High frequency operation : 2.5 GHz max Low power supply voltage : VCC = 2.7 to 3.6 V Very Low power supply current : ICC = 8.0 mA typ. (VCC = 3 V) Power saving function : IPS = 10 A max. Pulse swallow function : 64/65 or 128/129 Serial input 14-bit programmable reference divider : R = 5 to 16, 383 Serial input 18-bit programmable divider consisting of: - Binary 7-bit swallow counter : 0 to 127 - Binary 11-bit programmable counter : 5 to 2, 047 * Wide operating temperature : Ta = -40 to 85 C * Plastic 16-pin SSOP package (FPT-16P-M05)
s PACKAGE
16-pin plastic SSOP 16-pad plastic BCC
(FPT-16P-M05)
(LCC-16P-M06)
MB15E06
s PIN ASSIGNMENT
(TOP VIEW) (TOP VIEW)
OSCIN OSCOUT VP VCC DO GND Xfin fin
1 2 3 4 5 6 7 8
16 15 14 TOP 13 VIEW 12 11 10 9
R P LD/fout ZC PS LE Data Clock fin Clock OSCOUT VP VCC DO GND Xfin OSCIN R 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 P LD/fout ZC PS LE Data
(FPT-16P-M05)
(LCC-16P-M06)
2
MB15E06
s PIN DESCRIPTIONS
Pin No. 1 (16) 2 (1) 3 (2) 4 (3) 5 (4) 6 (5) 7 (6) 8 (7) Pin Name OSCIN OSCOUT VP VCC DO GND Xfin fin I/O I O O I I Descriptions Programmable reference divider input. Oscillator input connection to a TCXO. Oscillator output. Power supply voltage input for the charge pump. Power supply voltage input. Charge pump output. Phase of the charge pump can be reversed by FC input. Ground. Prescaler complementary input, and should be grounded via a capacitor. Prescaler input. Connection with an external VCO should be done with AC coupling. Clock input for the 19-bit shift register. Data is shifted into the shift register on the rising edge of the clock. (Open is prohibited.) Serial data input using binary code. The last bit of the data is a control bit. (Open is prohibited.) Control bit = "H" ; Data is transmitted to the programmable reference counter. Control bit = "L" ; Data is transmitted to the programmable counter. Load enable signal input (Open is prohibited.) When LE is high, the data in the shift register is transferred to a latch, according to the control bit in the serial data. Power saving mode control. This pin must be set at "L" at Power-ON. (Open is prohibited.) PS = "H" ; Normal mode PS = "L" ; Power saving mode Forced high-impedance control for the charge pump (with internal pull up resistor.) ZC = "H" ; Normal Do output. ZC = "L" ; Do becomes high impedance. Lock detect signal output (LD) /phase comparator monitoring output (fout) . The output signal is selected by LDS bit in the serial data. LDS = "H" ; outputs fout (fr/fp monitoring output) LDS = "L" ; outputs LD ("H" at locking, "L" at unlocking.) Phase comparator output for an external charge pump. Phase comparator output for an external charge pump.
9 (8)
Clock
I
10 (9)
Data
I
11 (10)
LE
I
12 (11)
PS
I
13 (12)
ZC
I
14 (13)
LD/fout
O
15 (14) 16 (15)
P R
O O
( ) : for Bcc Package.
3
MB15E06
s BLOCK DIAGRAM
(16) OSCIN 1
fr Crystal Oscillator circuit Phase comparator
(15)
16 R
(1) OSCOUT 2 Binary 14-bit reference counter (2) VP 3 14-bit latch SW FC LDS Lock detector
(14)
15 P
3-bit latch fp
LD/fr/fp selector
(13) LD/ 14 fout
(3) VCC
4
C N T
19-bit shift register
(12)
13 ZC
Super charger
7-bit latch Binary 7-bit swallow counter
11-bit latch Binary 11-bit programmable counter Intermittent mode control (power save)
(4) DO 5
(11)
12 PS
(5) GND 6 Control 1-bit (6) X fin 7 Prescaler 64/65, 128/129 (7) fin 8
(10)
11 LE
(9) MD
10 Data
(8)
9
Clock
for SSOP Package ( ) for BCC Package
4
MB15E06
s ABSOLUTE MAXIMUM RAGINGS
Parameter Power supply voltage Output voltage Input voltage Output current Open drain withstand voltage Storage temperature Symbol VCC VP VO VI IO VOOP Tstg Rating Min. -0.5 VCC -0.5 -0.5 -10 -0.5 -55 Max. +4.0 +6.0 VCC +0.5 VCC +0.5 +10 +7.0 +125 Unit V V V V mA V C Remark
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
Parameter Power supply voltage Input voltage Operating temperature Symbol VCC VP VI Ta Value Min. 2.7 VCC GND -40 Typ. 3.0 Max. 3.6 6.0 VCC +85 Unit V V V C Remark
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
5
MB15E06
s ELECTRICAL CHARACTERISTICS
Parameter Power supply current*1 Symbol ICC Condition finIF = 2500 MHz, fosc = 12 MHz Vcc current at PS = "L" and ZC = "H" min. 500 mVp-p 50 termination (Refer to the test circuit.) Pull up input Open drain output Open drain output VCC = 3.0 V, Vp = 5 V, VDOH = 4.0 V VCC = 3.0 V, Vp = 5 V, VDOL = 1.0 V Value Min. 100 3 -10 500 VCC x 0.7 -1.0 -1.0 -1.0 -100 0 -100 VCC - 0.4 VP - 0.4 1.0 1.0 Typ. 8.0 -10.0*2 Max. 10 2500 40 +2 VCC VCC x 0.3 +1.0 +1.0 +1.0 0 +100 0 0.4 - 0.4 - 0.4 1.1 -1.0 mA 10.0*2 Unit mA A MHz MHz dBm mVp-p V A A A V V V A mA mA
Power saving current*2 Operating frequency Crystal oscillator operating frequency fin OSCin Input voltage Data, Clock, LE, PS, ZC Data, Clock, LE, PS Input current ZC OSCin P Output voltage R, LD/fout Do High impedance cutoff current Do P R, LD/fou Output current Do
Ips fin fOSC VfinIF VOSC VIH VIL IIH IIL IIH IIL IIH IIL VOL VOH VOL VDOH VDOL IOFF IOL IOH IOL IDOH
Input sensitivity
IDOL
*1 : Conditions ; VCC = 3.0 V, Ta = 25 C, in locking state. *2 : Conditions ; Ta = 25 C
6
MB15E06
s FUNCTION DESCRIPTIONS
Pulse Swallow Function The divide ratio can be calculated using the following equation : fVCO = [ (M x N) + A] x fOSC / R (A < N) fVCO : Output frequency of external voltage controlled oscillator (VCO) N : Preset divide ratio of binary 11-bit programmable counter (5 to 2,047) A : Preset divide ratio of binary 7-bit swallow counter (0 A 127) fOSC : Output frequency of the reference frequency oscillator R : Preset divide ratio of binary 14-bit programmable reference counter (5 to 16,383) M : Preset divide ratio of modules prescaler (64 or 128) Serial Data Input Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference divider and the programmable divider separately. Binary serial data is entered through the Data pin. One bit of data is shifted into the shift register on the rising edge of the clock. When the load enable pin is high, stored data is latched according to the control bit data as follows: Table.1 Control Bit Control bit (CNT) H L Destination of serial data 17 bit latch (for the programmable reference divider) 18 bit latch (for the programmable divider)
Shift Register Configuration Programmable Reference Counter LSB 1 C N T 2 R 1 3 R 2 4 R 3 5 R 4 6 R 5 Data Flow 7 R 6 8 R 7 9 R 8 10 R 9 11 R 10 12 R 11 13 R 12 14 R 13 15 16 17 MSB 18
R 14 SW FC LDS
CNT R1 to R14 SW FC LDS
: Control bit : Divide ratio setting bit for the programmable reference counter (5 to 16,383) : Divide ratio setting bit for the prescaler (64/65 or 128/129) : Phase control bit for the phase comparator : LD/fout signal select bit
[Table. 1] [Table. 2] [Table. 5] [Table. 7] [Table. 6]
Note : Start data input with MSB first
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MB15E06
Programmable Reference Counter LSB Data Flow MSB
1 C N T
2 A 1
3 A 2
4 A 3
5 A 4
6 A 5
7 A 6
8 A 7
9 N 1
10 N 2
11 N 3
12 N 4
13 N 5
14 N 6
15 N 7
16 N 8
17 N 9
18 N 10
19 N 11
CNT A1 to A7
: Control bit : Divide ratio setting bits for the swallow counter (0 to 127)
N1 to N11 : Divide ratio setting bits for the programmable counter (5 to 2,047)
[Table. 1] [Table. 3] [Table. 4]
Note : Start data input with MSB first
Table2. Binary 14-bit Programmable Reference Counter Data Setting Divide ratio (R) 5 6 * 16383 R 14 0 0 * 1 R 13 0 0 * 1 R 12 0 0 * 1 R 11 0 0 * 1 R 10 0 0 * 1 R 9 0 0 * 1 R 8 0 0 * 1 R 7 0 0 * 1 R 6 0 0 * 1 R 5 0 0 * 1 R 4 0 0 * 1 R 3 1 1 * 1 R 2 0 1 * 1 R 1 1 0 * 1
Note : * Divide ratio less than 5 is prohibited. Table.3 Binary 11-bit Programmable Counter Data Setting Divide ratio (N) 5 6 * 2047 N 11 0 0 * 1 N 10 0 0 * 1 N 9 0 0 * 1 N 8 0 0 * 1 N 7 0 0 * 1 N 6 0 0 * 1 N 5 0 0 * 1 N 4 0 0 * 1 N 3 1 1 * 1 N 2 0 1 * 1 N 1 1 0 * 1
Note : * Divide ratio less than 5 is prohibited. * Divide ratio (N) range = 5 to 2,047
8
MB15E06
Table.4 Binary 7-bit Swallow Counter Data Setting Divide ratio (A) 0 1 * 127 A 7 0 0 * 1 A 6 0 0 * 1 A 5 0 0 * 1 A 4 0 0 * 1 A 3 0 0 * 1 A 2 0 0 * 1 A 1 0 1 * 1
Note : * Divide ratio (A) range = 0 to 127 Table. 5 Prescaler Data Setting SW H L Prescaler Divide ratio 64/65 128/129
Table. 6 LD/fout Output Select Data Setting LDS H L fout signal LD signal LD/fout output signal
Relation between the FC input and phase characteristics The FC bit changes the phase characteristics of the phase comparator. Both the internal charge pump output level (DO) and the phase comparator output (R, P) are reversed according to the FC bit. Also, the monitor pin (fOUT) output is controlled by the FC bit. The relationship between the FC bit and each of DO, R, and P is shown below. Table. 7 FC Bit Data Setting (LDS = "H") FC = High Do fr > fp fr < fp fr = fp H L Z* R L H L P L Z* Z* LD/fout (fr) (fr) (fr) Do L H Z* H L L FC = Low R P Z* L Z* LD/fout (fp) (fp) (fp)
* : High impedance
9
MB15E06
When designing a synthesizer, the FC pin setting depends on the VCO and LPF characteristics.
* : When the LPF and VCO characteristics are similar to (1) , set FC bit high. * : When the VCO characteristics are similar to (2) , set FC bit low.
High
(1)
VCO Output Frequency ( 2) LPF Output Voltage Large
3. Power Saving Mode (Intermittent Mode Control Circuit) Setting a PS pin to Low, the IC enters into power saving mode resultatly current sonsumption can be limited to 10 A (max.) . Setting PS pin to High, power saving mode is released so that the IC works normally. In addition, the intermittent operation control circuit is included which helps smooth start up from the power saving mode. In general, the power consumption can be saved by the intermittent operation that powering down or waking up the synthesizer. Such case, if the PLL is powered up uncontrolled, the resulting phase comparator output signal is unpredictable due to an undefined phase relation between reference frequency (fr) and comparison frequency (fp) and may in the worst case take longer time for lock up of the loop. To prevent this, the intermittent operation control circuit enforces a limited error signal output of the phase detector during power up, thus keeping the loop locked. During the power saving mode, the corresponding section except for indispensable circuit for the power saving function stops working, then current consumption is reduced to 10 A (max.) . Note : * While the power saving mode is executed, ZC pin should be set at "H" or open. If ZC is set at "L" during power saving mode, approximately 10 A current flows. * PS pin must be set "L" at Power-ON. * The power saving mode can be released (PS : L H) 1 s later after power supply remains stable. * During the power saving mode, it is possible to input the serial data.
OFF VCC Clock Data LE PS tV 1 s
ON
tPS 100 ns
(1)
(2)
(3)
(1) PS = L (power saving mode) at Power ON (2) Set serial data 1 s later after power supply remains stable (VCC 2.2 V) . (3) Release power saving mode (PS : L H) 100 ns later after setting serial data. 10
MB15E06
Table.8 PS Pin Setting PS pin H L Normal mode Power saving mode Status
Table.9 ZC Pin Setting ZC pin H L Do output Normal output High impedance
11
MB15E06
s SERIAL DATA INPUT TIMING
t0 100 ns , t 1, t 2 , t4 20 ns , t 3, t 5 3 0 n s , t 6 1 0 0 n s
( M SB)
C:Control bit (LSB)
Clock t0 LE
t1
t2
t5
t3 t6 t4
On rising edge of the clock, one bit of the data is transferred into the shift register.
12
MB15E06
s PHASE COMPARATOR OUTPUT WAVEFORM
fr
fp
tWU
tWL
LD
[FC = " H"] P
R
H DO Z L
[FC = "L"] P
R
H DO Z L
Note : 1. Phase error detection range : -2 to +2 2. Pulses on Do output signal during locked state are output to prevent dead zone. 3. LD output becomes low when phase is tWU or more. LD output becomes high when phase error is tWL or less and continues to be so for three cysles or more. 4. tWU and tWL depend on OSCin input frequency. 5. LD becomes high during the power saving mode (PS = "L".)
tWU 8/fosc (e. g. tWU 625ns, foscin = 12.8 MHz) tWL 16/fosc (e. g. tWL 1250ns, foscin = 12.8 MHz)
13
MB15E06
s TEST CIRCUIT (for Measuring Input Sensitivity fin/OSCin)
VCC = VP = 3 V 1000 pF 1000 pF S*G 50 50 0.1 F 0.1 F 1000 pF S*G
8
7
6
5
4
3
2
1
9
10
11
12 VCC
13
14
15
16
Controller (setting divide ratio)
Oscilloscope
Note : SSOP
14
MB15E06
s TYPICAL CHARACTERISTICS
1. fin Input Sensitivity
Vfin vs. fin +10
0
V fin (dBm)
-10
,,,,,,,,,,,,,, ,,,,,,,,,,,,,, ,,,,,,,,,,,,,,
SPEC
Ta = +25 C
-20
-30
VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V 0 1000 2000 fin (MHz) 3000 4000
-40
2. OSCin Input Sensitivity
Vfosc vs. fosc
+10
Vfosc (dBm)
-10 -20 -30 -40
,,,,,,,, ,,,,,,,,
SPEC 0
Ta = +25 C
VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V 0 50 fosc (MHz) 100
15
MB15E06
3. Do Output Current
VOH vs. IOH Ta = +25 C VCC = 3 V
5.0
VP = 5 V
4.0 VP = 3 V
VOH (V)
3.0
2.0
1.0
0 0 -5 -10 IOH (mA) -15 -20
VOL vs. IOL
5.0
Ta = +25 C VCC = 3 V
VP = 5 V
4.0
VP = 3 V
VOL (V)
3.0
2.0
1.0
0 0 5 10 IOL (mA) 15 20
16
MB15E06
4. fin Input Impedance
4 3
1; 10.188 -36.666 1 GHz 2; 10.731 1.4438 1.5 GHz 3; 16.474 31.454 2 GHz
2 4; 29.314 50.516 2.5 GHz
1
5. OSCin Input Impedance
1;
3.516 k -43.99 k 1 MHz 150.5 -4.8388 k 10 MHz 30.13 -2.389 k 20 MHz
2;
3; 3 1 2 4
4; 12.844 -948.37 50 MHz
17
MB15E06
s REFERENCE INFORMATION
Typical plots measured with the test circuit are shown below. Each plot shows lock up time, phase noise and reference leakage. * * * * * fvco = 1835 MHz Kv = 87 MHz/v fr = 200 kHz fosc = 13 MHz LPF :
Test Circuit S.G OSCin Do fin LPF
15 k 910 VCO 3000 pF 0.03 F 400 pF
Spectrum Analyzer
PLL Lock Up Time = 500 s (1797.6 MHz 1872.4 MHz, within 1kHz)
REF MKr x : 500.01844 s y : -74.8009 MHz 38.00500 MHz RBW 300 Hz VBW 300 Hz 10 dB/
PLL Phase Noise @ within loop band = 69.4 dBc/H
0.0 dBm ATT 10 dB
2.000 kHz/div
29.99500 MHz 10.1339 s 1.9903829 ms
SPAN 50.0 kHz CENTER 1.8350000 GHz
MKr x : 500.01844 s y : -74.8009 MHz 250.0000 MHz REF 10 dB/
PLL Reference Leakage @ 200 kHz offset = 74.6 dBc
0.0 dBm ATT 10 dB
50.00000 MHz/div RBW 10 kHz 10.1339 s 1.9903829 ms VBW 10 kHz SPAN 1.00 MHz CENTER 1.83500 GHz
0 Hz
18
MB15E06
s APPLICATION EXAMPLE
VP 10 k 12 k 12 k LPF VCO
Output
10 k Lock detect. From a controller
R 16
P 15
LD/fout
ZC 13
PS 12
LE 11
Data 10
Clock 9
MB15E06
1 OSCIN
2 OSCOUT
3 VP
4 VCC
5 DO
6 GND
7 Xfin
8 fin 1000 pF
1000 pF 1000 pF TCXO 0.1 F 0.1 F
Vp : 5.5 V Max
Note : 1. SSOP-16 2. In case of using a crystal resonator, it is necessary to optimize matching between the crystal and this LSI, and perform detailed system evaluation. It is recommended to consult with a supplier of the crystal resonator. (Reference oscillator circuit provides its own bias, feedback resistor is 100 k (typ) .)
19
MB15E06
s ORDERING INFORMATION
Part number MB15E06PFV1 MB15E06PV1 Package 16-pin Plastic SSOP (FPT-16P-M05) 16-pad plastic BCC (LCC-16P-M06) Remarks
20
MB15E06
s PACKAGE DIMENSION
16-pin Plastic SSOP (FPT-16P-M05)
* 5.000.10(.197.004)
* : These dimensions do not include resin protrusion.
1.25 -0.10 .049 -.004
+0.20 +.008
(Mounting height)
0.10(.004)
INDEX
* 4.400.10
(.173.004)
6.400.20 (.252.008)
5.40(.213) NOM
0.650.12 (.0256.0047)
0.22 -0.05 .009
+0.10 +.004 -.002
"A"
0.15 -0.02 .006 -.001
+0.05 +.002
Details of "A" part 0.100.10(.004.004) (STAND OFF)
4.55(.179)REF
0
10
0.500.20 (.020.008)
C
1994 FUJITSU LIMITED F16013S-2C-4
Dimensions in : mm (inches)
21
MB15E06
16-pad Plastic BCC (LCC-16P-M06)
4.550.10 (.179.004)
14 9
0.80(.031)MAX Mounting height 0.400.10 (.016.004) 0.80(.031) REF 0.65(.026) TYP
9
3.40(.134)TYP 0.3250.10 (.013.004)
14
INDEX AREA 3.400.10 (.134.004) 2.45(.096) TYP "A" "B" 1.15(.045) REF
1
6
0.0750.025 (.003.001) (Stand off)
6
1.725(.068) REF
1
Details of "A" part 0.750.10 (.030.004) 0.05(.002)
Details of "B" part 0.600.10 (.024.004)
0.400.10 (.016.004)
0.600.10 (.024.004)
C
1999 FUJITSU LIMITED C16017S-1C-1
Dimensions in : mm (inches)
22
MB15E06
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F9907 (c) FUJITSU LIMITED Printed in Japan

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