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TMP91PW18A
Low Voltage/Low power
CMOS 16-Bit Microcontrollers
TMP91PW18AF 1. Outline and Device Characteristics
TMP91PW18A is OTP type MCU which 128-Kbyte One-time PROM. Using the adapter-socket, you can write and verify the data for TMP91PW18A. TMP91PW18A has the same pin-assignment with TMP91CW18A (Mask ROM type). Writing the program to Built-in PROM, TMP91PW18A operates as the same way with TMP91CW18A.
000000H Internal I/O (4 Kbytes) 001000H Internal RAM (4 Kbytes)
002000H
FE0000H
Internal PROM (128 Kbytes)
FFFF00H FFFFFFH Internal vector table (256 bytes)
Internal area
Momory map of TMP91PW18A
Product No. TMP91PW18AF ROM OTP 128 Kbytes RAM 4 Kbytes Packege 80-QFP Adaptor socket BM11179
000707EBP1
For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance / Handling Precautions. TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. The products described in this document are subject to the foreign exchange and foreign trade laws. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. The information contained herein is subject to change without notice.
Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
91PW18A-1
2002-12-03
TMP91PW18A
25 MHz (P61) CTS /INT1 Port 6 H-OSC X1 X2 EMU0 EMU1 RESET AM0 AM1 ALE AD0 (P00) AD1 (P01) AD2 (P02) AD3 (P03) AD4 (P04) AD5 (P05) AD6 (P06) AD7 (P07) AD8/A8 (P10) AD9/A9 (P11) AD10/A10 (P12) AD11/A11 (P13) AD12/A12 (P14) AD13/A13 (P15) AD14/A14 (P16) AD15/A15 (P17) A0/A16 (P20) A1/A17 (P21) A2/A18 (P22) A3/A19 (P23) A4/A20 (P24) A5/A21 (P25) A6/A22 (P26) A7/A23 (P27)
(P62) SCOUT/INT2 (P60) INT0
Interrupt controller
CPU (TLCS-900/L1) XWA XBC XDE XHL XIX XIY XIZ XSP WA BC DE HL IX IY IZ SP 32 bits SR PC Port 1 Watchdog timer (WDT) 4-KB RAM Port 2 F
NMI
8-bit timer (TMRA0) (P70) TA1OUT 8-bit timer (TMRA1) 8-bit timer (TMRA2) (P71) TA3OUT Port 7 8-bit timer (TMRA3) 8-bit timer (TMRA4) 8-bit timer (TMRA5)
(P72)TA5OUT
(P73) INT5/TB0IN0 (P74) INT6/TB0IN1 (P75) TB0OUT0
16-bit timer (TMRB0) 3
(P76) SCK0/INT3 I C Bus/SIO interface 0
2
Port 0
RD (P30) WR (P31) HWR (P32)
Port 3(P.O.D) Wait controller 8-bit timer (TMRA6) 8-bit timer (TMRA7)
(P80) SDA0/SO0 (P81) SCL0/SI0 (P82) TXD (P83) RXD (P84) SDA1 (P85) SCL1 (P86) SDA2 (P87) SCL2
Port 80-83 (P.O.D.), P84-87 (O.D.)
WAIT (P33)
(P34) TA6IN (P35) TA7OUT (P36) INT4 (P37)
UART interface I C Bus interface 1 I2C Bus interface 2
2
128-KB ROM
AN11 (P43) AN10 (P42) AN9 (P41) ADTRG /AN8 (P40) AN7 (P57) AN6 (P56) AN5 (P55) AN4 (P54) AN3 (P53) AN2 (P52) AN1 (P51) AN0 (P50) AVCC AVSS VREFL VREFH
DVCC2 [5 V] DVCC2 [5 V] DVSS2 10-bit 12-ch AD converter Port 5
DVCC1 [5 V]
I/O (5 V)
DVSS1 DVSS2
( ): Initial function after reset
Figure 1.1 Block diagram of TMP91PW18A
Port 4
91PW18A-2
2002-12-03
TMP91PW18A
2.
Pin Assignment and Functions
This section shows TMP91PW18A pin assignment, and the names and an outline of the functions of the input/output pins.
2.1
Pin Assignment Diagram
Figure 2.1.1 is a pin assignment diagram for TMP91PW18A.
A10/AD10(P12) A8/AD8(P10)
A9/AD9(P11)
SDA2(P86)
SCL1(P85)
AD3(P03)
AD2(P02)
AD1(P01)
AD0(P00)
SDA1(P84)
SCL2(P87)
AD7(P07)
AD6(P06)
AD5(P05)
AD4(P04)
DVCC2
RESET
EMU1
EMU0
ALE
AM1
X1
DVSS1
(P13)A11/AD11 (P14)A12/AD12 (P15)A13/AD13 (P16)A14/AD14 (P17)A15/AD15 (P20)A0/A16 (P21)A1/A17 DVSS2
NMI DVCC2
(P22)A2/A18 (P23)A3/A19 (P24)A4/A20 (P25)A5/A21 (P26)A6/A22 (P27)A7/A23
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
X2
Top View
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
DVCC1 AM0 (P83)RXD (P82)TXD (P81)SCL0/SI0 (P80)SDA0/SO0 (P76)SCK0/INT3 (P75)TB0OUT0 (P74)TB0IN1/INT6 (P73)TB0IN0/INT5 (P72)TA5OUT (P71)TA3OUT (P70)TA1OUT AVCC AVSS VREFL
(P40)AN8/ADTRG (P41)AN9
(P36)TA7OUT
(P42)AN10
(P43)AN11
(P55)AN5
(P50)AN0
(P52)AN2
(P51)AN1
(P53)AN3
(P54)AN4
(P56)AN6
(P37)INT4
(P57)AN7
(P31)WR
(P61)CTS/INT1
(P32)HWR
(P60)INT0
(P62)SCOUT/INT2
(P33)WAIT
(P35)TA6IN
(P30)RD
( ): Initial function for after reset
Figure 2.1.1 Pin assignment diagram (80-pin QFP)
VREFH
P34
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
91PW18A-3
2002-12-03
TMP91PW18A
2.2
Pin Names and Functions
The names of the input/output pins and their functions are described below. Table 2.2.1 Pin names and functions (1/3)
Pin name
P00 to P07 AD0 to AD7 P10 to P17 AD8 to AD15 A8 to A15 P20 to P27 A0 to A7 A16 to A23 P30
RD
Number of pins
8 8
I/O
I/O Tri-state I/O Tri-state Output I/O Output Output I/O Output
Functions
Port 0: I/O port that allows I/O to be selected at the bit level Address and data (lower): Bits 0 to 7 of address and data bus Port 1: I/O port that allows I/O to be selected at the bit level Address and data (upper): Bits 8 to 15 for address and data bus Address: Bits 8 to 15 of address bus Port 2: I/O port that allows I/O to be selected at the bit level Address: Bits 0 to 7 of address bus Address: Bits 16 to 23 of address bus Port 30: Output port By setting (P3 0, P3FC 1), RD signal is generated during
8
1
reading internal areas. Read: Strobe signal for reading external memory Open-drain output pin by programmable P31
WR
1
I/O Output I/O Output I/O Input I/O I/O Input I/O Output I/O Input
Port 31: Output port Write: Strobe signal for writing data to pins AD0 to AD7 Open-drain output pin by programmable Port 32: I/O port (with pull-up resistor) High Write: Strobe signal for writing data to pins AD8 to AD15 Open-drain output pin by programmable Port 33: I/O port (with pull-up resistor) Wait: Pin used to request CPU bus wait Open-drain output pin by programmable Port 34: I/O port Open-drain output pin by programmable Port 35: I/O port Timer A6 input Open-drain output pin by programmable Port 36: I/O port Timer A7 output Open-drain output pin by programmable Port 37: I/O port Interrupt request pin 4: Interrupt request pin with programmable rising edge/falling edge levels Open-drain output pin by programmable Port 40: Pin used to input port Analog input: Pin used to input to AD converte AD Trigger: Signal used to request start of AD conversion Port 5: Pin used to input port Analog input: Pin used to input to AD converter Port 60: I/O port Interrupt request pin 0: Interrupt request pin with programmable rising edge/falling edge levels Port 61: I/O port Serial data send enable (Clear to Send) Interrupt request pin 1: Interrupt request pin with programmable rising edge/falling edge levels Port 62: I/O port System clock output: outputs fFPH or fs clock Interrupt request pin 2: Interrupt request pin with programmable rising edge/falling edge levels
P32
HWR
1
P33
WAIT
1
P34 P35 TA6IN P36 TA7OUT P37 INT4
1 1
1
1
P40 to P43 AN8 to AN11
ADTRG
4
Input Input Input Input Input I/O Input I/O Input Input I/O Output Input
P50 to P57 AN0 to AN7 P60 INT0 P61
CTS
8 1
1
INT1 P62 SCOUT INT2 1
91PW18A-4
2002-12-03
TMP91PW18A
Table 2.2.2 Pin names and functions (2/3) Pin name
P70 TA1OUT P71 TA3OUT P72 TA5OUT P73 TB0IN0 INT5 P74 TB0IN1 INT6 P75 TB0OUT0 P76 SCK0 INT3 P80 SO0 SDA0 P81 SI0 SCL0 P82 TXD P83 RXD P84 SDA1 P85 SCL1 P86 SDA2 P87 SCL2
Number of pins
1 1 1 1
I/O
I/O Output I/O Output I/O Output I/O Input Input I/O Input Input I/O Output I/O I/O Input I/O Output I/O I/O Input I/O I/O Output I/O Input I/O I/O I/O I/O I/O I/O I/O I/O Port 70: I/O port Timer A1 output Port 71: I/O port Timer A3 output Port 72: I/O port Timer A5 output
Functions
Port 73: I/O port Timer B0 input 0 Interrupt request pin 5: Interrupt request pin with programmable rising edge/falling edge levels Port 74: I/O port Timer B0 input 1 Interrupt request pin 6: Interrupt request pin with programmable rising edge/falling edge levels Port 75: I/O port Timer B0 output 0 Port 76: I/O port Serial clock I/O 0 Interrupt request pin 3: Interrupt request pin with programmable rising edge/falling edge levels Port 80: I/O port Serial bus interface send data at SIO mode 0. Serial bus interface send/receve data at I2C mode 0. Open-drain output pin by programmable Port 81: I/O port Serial bus interface receve data at SIO mode 0. Serial bus interface clock I/O data at I2C mode 0. Open-drain output pin by programmable Port 82: I/O port Serial send data (UART) Open-drain output pin by programmable Port 83: I/O port Serial recive data (UART) Open-drain output pin by programmable Port 84: I/O port Serial bus interface send/receve data at I2C mode 1 N-ch FET open-drain output Port 85: I/O port Serial bus interface clock I/O data at I2C mode 1 N-ch FET open-drain output Port 86: I/O port Serial bus interface send/receve data at I2C mode 2 N-ch FET open-drain output Port 87: I/O port Serial bus interface clock I/O data at I2C mode 2 N-ch FET open-drain output
1
1 1
1
1
1
1
1
1
1
1
91PW18A-5
2002-12-03
TMP91PW18A
Table 2.2.3 Pin names and functions (3/3) Pin name
ALE
NMI
Number of pins
1 1 2 1 1 1 1 1 1 2 3 2
I/O
Output Input Input Output Input Input Input
Functions
Address latch enable can be disabled to reduce noise. Non-maskable interrupt request pin: Interrupt request pin with programmable falling edge level or with both edge levels programmable Address mode: The Vcc pin should be connected. Test pins: Open pins Reset: Initializes TMP91CW18. (with pull-up resistor) Pin for reference voltage input to AD converter (H) Pin for reference voltage input to AD converter (L) Power supply pin for AD converter GND pin for AD converter (0 V) I/O High-frequency oscillator connection pins Power supply pins GND pins (0 V)
AM0 to 1 EMU0/EMU1
RESET
VREFH VREFL AVCC AVSS X1/X2 DVCC DVSS
91PW18A-6
2002-12-03
TMP91PW18A
2.3
PROM Mode
Table 2.3.1 Names and functions of PROM mode
Pin function
A7 to A0 A15 to A8 A16 D7 to D0
CE OE PGM
Pin number
8 8 1 8 1 1 1 1 4 4 1 1 1 1 1 1 12
I/O
Input
Function
Input Program memory address input Input
Pin name (MCU mode)
P27 to P20 P17 to P10 P33 P07 to P00 P32 P30 P31 AM1 DVCC, AVCC DVSS, AVSS
Input/Output Program memory data I/O Input Chip enable input Input Output control input Input Program control input Power supply 12.75 V/5 V (Power supply of program) Power supply 6.25 V/5 V Power supply 0V Input Fix to low level (security pin) Input Input Fix to low level (PROM mode)
VPP VCC VSS P34
RESET
AM0 ALE X1 X2 P43 to P41, P37 to P35, P75 to P70 P40 P57 to P50 P62 to P60 P87 to P80 VREFH VREFL NMI , EMU1, 0
Output Open Input Crystal Output Input Fix to high level
51
Input/Output Open
91PW18A-7
2002-12-03
TMP91PW18A
3.
Operation
This section describes in blocks the functions and basic operations of TMP91PW18A. TMP91PW18A has PROM in place of the mask ROM which is included in the TMP91CW18A. The other configuration and functions are the same as the TMP91CW18A. Regarding the function of the TMP91PW18A, which is not described herein, see the TMP91CW18A. The TMP91PW18A has two operational modes: MCU mode and PROM mode.
3.1
MCU Mode
(1) Mode-setting and function The MCU mode is set by driving AM1 pin and AM0 pin. In the MCU mode, the operation is same as TMP91CW18A.
3.2
Memory Map
Figure 3.2.1, 2 are memory map of TMP91PW18A.
000000H Internal I/O 001000H Internal RAM 002000H External FE0000H Internal PROM (128 Kbytes) 00000H
Internal PROM (128 Kbytes)
1FFFFH
FFFF00H Internal vector table FFFFFFH
Figure 3.2.1 Memory map in MCU mode
Figure 3.2.2 Memory map in PROM mode
91PW18A-8
2002-12-03
TMP91PW18A
4.
4.1
Electrical Characteristics
Absolute Maximum Ratings
Parameter
Power Supply Voltage Input Voltage Output Current Output Current Output Current (total) Output Current (total) Power Dissipation (Ta Storage Temperature Operating Temperature 70C) Soldering Temperature (10 s) Vcc VIN IOL IOH IOL IOH PD TSOLDER TSTG TOPR
Symbol
Rating
0.5 to 6.5 0.5 to Vcc 2 2 80 80 600 260 65 to 150 30 to 70 0.5
Unit
V V mA mA mA mA mW C C C
4.2
DC Characteristics (1/2)
Parameter Symbol Condition Min Typ. (Note) Max Unit
Power Supply Voltage Avcc DVcc Avss DVss 0 V P00 to P17 (AD0 to 15) Input Low Voltage P20 to P87 RESET , NMI AM0, 1 X1 P00 to P17 (AD0 to 15) P20 to P87 RESET , NMI AM0 to 1 X1 Output Low Voltage Output High Voltage
VCC VIL VIL1 VIL2 VIL3 VIL4 VIH VIH1 VIH2 VIH3 VIH4 VOL VOH
fc Vcc
8 to 25 MHz 4.5 V
4.5
5.5 0.8 0.3 Vcc
V
Vcc
4.5 to 5.5 V
0.3
0.25 Vcc 0.3 0.2 Vcc
Vcc
4.5 to 5.5 V
0.7 Vcc 0.7 Vcc 0.75 Vcc Vcc 0.3 0.8 Vcc Vcc 0.3
V
Vcc
4.5 to 5.5 V
IOL 1.6 mA (Vcc 4.5 to 5.5 V) IOH (Vcc 400 A 5.0 V 10 %) 0.8Vcc
0.45 V
Note: Typical values are for when Ta
25C and Vcc
5.0 V uncles otherwise noted.
91PW18A-13
2002-12-03
TMP91PW18A
4.2 DC Characteristics (2/2)
Parameter
Input Leakage Current Output Leakage Current Power Down Voltage (at STOP, RAM Back up) RESET Pull-up Resistor Pin Capacitance Schmitt Width RESET , NMI Programmable Pull-up Resistor NORMAL (Note 2) IDLE2 IDLE1 STOP Icc
Symbol
ILI ILO VSTOP RRST CIO VTH RKH Vcc 0.0 0.2
Condition
VIN VIN Vcc Vcc 0.2
Min
Typ.
(Note 1)
0.02 0.05
Max
5 10 5.5 200 10
Unit
A V k pF V
V IL2 0.2 Vcc, V IH2 0.8 Vcc Vcc fc 5V 1 MHz 10%
2.0 40
0.4 5V 10% 40
1.0 200 23.5 9.5 4.4 0.2 35.0 15.0 9.0 20
k
Vcc 5 V 10 % fc 25 MHz (Typ. Vcc 5.0 V) Ta 70C Vcc 4.5 to 5.5 V
mA
A
Note 1: Typical values are for when Ta
25C and Vcc
5.0 V unless otherwise noted.
Note 2: Icc measurement conditions (NORMAL): All functions are operational; output pins are open and input pins are fixed.
91PW18A-14
2002-12-03
TMP91PW18A
4.3
AC Characteristics
(1) Vcc 5.0 V 10 %
No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 fFPH Period (
Parameter
x) ALE Fall
Symbol
tFPH tAL tLA tLL tLC tCLR tCLW tACL tACH tCAR tCAW tADL tADH tRD tRR tHR tRAE tWW tDW tWD
1 wait n Mode 1 wait n Mode 1 wait n Mode
Variable Min
40 0.5x 0.5x x 0.5x 0.5x x x 1.5x 0.5x x 15 15 20 20 15 15 25 50 20 20 3.0x 3.5x 2.0x 2.0x 0 x 1.5x 1.5x x 15 20 50 15 3.5x 3.0x 2.0x 3.5x 3.5x 100 0 3.5x 120 90 80 20 45 35 40
fFPH Min
40 5 5 20 0 5 25 15 10 0 20
25 MHz Max
Unit
ns ns ns ns ns ns ns ns ns ns ns
Max
31250
A0 to A15 Vaild ALE Fall ALE Fall
RD Rise WR Rise
A0 to A15 Hold
RD / WR Fall
ALE High Width ALE Rise ALE Rise
RD / WR Fall RD / WR Fall
A0 to A15 Valid A0 to A23 Valid
RD Rise WR Rise
A0 to A23 Hold A0 to A23 Hold D0 to D15 Input D0 to D15 Input
A0 to A15 Valid A0 to A23 Valid
RD Fall RD Low Width RD Rise RD Rise
75 105 40 60 0 25 40 10 25 50 40 80 20 140 319
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
D0 to D15 Input D0 to A15 Hold A0 to A15 Output
WR Rise
WR Low Width
D0 to D15 Valid
WR Rise
D0 to D15 Hold
WAIT Input WAIT Input WAIT Hold
A0 to A23 Valid A0 to A15 Valid
RD / WR Fall
tAWH tAWL tCW tAPH tAPH2 tAP
A0 to A23 Valid A0 to A23 Valid A0 to A23 Valid
Port Input Port Hold Port Valid
AC Measuring Conditions Output level: High 0.7 Vcc, Low 0.3 Vcc, CL Input level: High 0.9 Vcc, Low 0.1 Vcc
50 pF
91PW18A-15
2002-12-03
TMP91PW18A
(2) Vcc 1. 5.0 V 10 %
Raed cycle
tFPH
fFPH
A0 to A23
CS3 to CS0
R/ W
tAWH tAWL
tCW
WAIT
tAP tAPH2 Port input tADH
RD
tCAR tRR tRAE tHR D0 to D15
tACH tAC tLC
tRD tADL
AD0 to AD15
A0 to A15 tAL tLA
tCLR
ALE
tLL
91PW18A-16
2002-12-03
TMP91PW18A
.2 Write cycle
fFPH
A0 to 23
CS3 to CS0
R/ W
WAIT
tAP Port output
WR , HWR
tCAW tWW tDW tWD
AD0 to AD15
A0 to A15
D0 to D15 tCLW
ALE
91PW18A-17
2002-12-03
TMP91PW18A
4.4
AD Conversion Characteristics
AVcc parameter
Analog Input Voltage Range( ) Analog Input Voltage Range( ) Analog Input Voltage Range Analog Input Voltage Range 1 0 Error (Not including quantizing erros)
Vcc, AVss Max
Vcc Vss 0.2 V
Vss Unit
V mA A LSB
Symbol
VREFH VREFL VAIN IREF (VREFL
Condition
VCC VCC VCC 5V 5V 5V 10% 10% 10%
Min
VCC 1.5 V VSS VREFL
Typ.
Vcc Vss 1.44 0.02 1.0
VREFH 2.00 5.0 4.0
0 V)
VCC VCC
2.7 V to 5.5 V 5V 10%
Note 1: 1 LSB
(VREFH
VREFL)/1024 [V] 4 MHz.
Note 2: The operation above is guaranteed for fFPH
Note 3: The value for ICC includes the current which flows through the AVCC pin.
4.5
Event Counter (TA0IN, TA4IN, TB0IN0, TB0IN1, TB1IN0, TB1IN1)
Variable Min
8X 4X 4X 100 40 40
Parameter
Clock Perild Clock Low Level Width Clock High Level Width
Symbol
tVCK tVCKL tVCKH
25 MHz
Max
Min
420 200 200
Max
Unit
ns ns ns
4.6
Interrupt, Capture
(1) NMI , INT0 to INT4 Interrupts
Parameter
NMI , INT0 to INT4 Low Level Width NMI , INT0 to INT4 High Level Width
Symbol
tINTAL tINTAH 4X 4X
Variable Min
40 40
25 MHz Min
200 200
Unit
ns ns
Max
Max
(2) INT5 to INT6 Interrupts, Capture The INT5 to INT6 input width depends on the system clock and prescaler clock settings.
System Clock Selected
0 (fc)
Prescaler Clock Selected
00 (fFPH) 10 (fc/16)
tINTBL (INT5 to INT6 low level width)
tINTBH (INT5 to INT6 high level width)
Unit
Variable fFPH Min
8X 128Xc 100 0.1
25 MHz Max
420 5.22
Variable Min
8X 128Xc 100 0.1
fFPH
25 MHz Max
420 5.22 ns s
Note:
Xc
Perild of clock fc
91PW18A-18
2002-12-03
TMP91PW18A
4.7
SCOUT Pin AC Characteristics
Variable Min
0.5T 0.5T 15 15
Parameter
Low Level Width High Level Width tSCH tSCL
Symbol
25 MHz Min
5 5
Max
Max
Condition
Vcc Vcc 5V 5V 10% 10%
Unit
ns ns
Note: T
Period of SCOUT
tSCH tSCL SCOUT
4.8
Read Operation in PROM Mode
DC/AC characteristics Ta Parameter Symbol
VPP VIH1 VIL1 tACC CL 50 PF
25
5C Vcc Min
4.5 2.2 0.3
5V Max
5.5 Vcc
10 % Unit
V V V ns
Condition
VPP Read Voltage Input High Voltage (A0 to A16, CE , OE , PGM ) Input Low Voltage (A0 to A16, CE , OE , PGM ) Address to Output Delay
0.3
0.8 2.25 TCYC
TCYC 400 ns (10 MHz Clock) 200 ns
4.9
Program Operation in PROM Mode
DC/AC characteristics Ta Parameter Symbol
VPP VIH VIL ICC IPP tPW fc VPP CL 10 MHz 13.00 V 50 PF 0.095 0.1
25
5C Vcc
6.25 V Typ
12.75
0.25 V Max
13.00 Vcc 0.3
Condition
Min
12.50 2.6 0.3
Unit
V V V mA mA ms
Programing Supply Voltage Input High Voltage (D0 to D7, A0 to A16, CE , OE , PGM ) Input Low Voltage (D0 to D7, A0 to A16, CE , OE , PGM ) Vcc Supply Current VPP Supply Current
PGM Program Pulse Width
0.8 50 50 0.105
91PW18A-19
2002-12-03
TMP91PW18A
4.10 Timing Chart of Read Operation in PROM Mode
A0 to A16
CE
OE
PGM
tACC
D0 to D7
Data output
91PW18A-20
2002-12-03
TMP91PW18A
4.11 Timing Chart of Program Operation in PROM Mode
A0 to A16
CE
OE
D0 to D7
Unknown
Data-in stable
Data-out valid
tPW
PGM
VPP
Note 1: The power supply of Vpp (12.75 V) must be turned on at the same time or the later time for a power supply of Vcc and must be turned off at the same time or early time for a power supply of Vcc. Note 2: The device suffers a damage taking out and putting in on the condition of Vpp 12.75 V.
Note 3: The maximum spec of Vpp pin is 14.0 V. Be carefull a overshoot at the programming.
91PW18A-21
2002-12-03

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