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3 Volt Fast Boot Block Flash Memory
28F800F3 and 28F160F3
Product Features
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High Performance -- Up to 60 MHz Effective Zero Wait-State Performance -- Synchronous Burst-Mode Reads -- Asynchronous Page-Mode Reads SmartVoltage Technology -- 2.7 V-3.6 V Read and Write Operations for Low Power Designs -- 12 V VPP Fast Factory Programming Flexible I/O Voltage -- 1.65 V I/O Reduces Overall System Power Consumption 5 V-Safe I/O Enables Interfacing to 5 V Devices Enhanced Data Protection -- Absolute Write Protection with VPP = GND -- Block Locking -- Block Erase/Program Lockout during Power Transitions Density Upgrade Path -- 8 and 16 Mbit Manufactured on ETOXTM V Flash Technology
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Supports Code Plus Data Storage -- Optimized for Intel(R) Flash Data Integrator (IFDI) and other Intel(R) Software -- Fast Program Suspend Capability -- Fast Erase Suspend Capability Flexible Blocking Architecture -- Eight 4-Kword Blocks for Data -- 32-Kword Main Blocks for Code -- Top or Bottom Boot Configurations Extended Cycling Capability -- Minimum 100,000 Block Erase Cycles Low Power Consumption -- Automatic Power Savings Mode Decreases Power Consumption Automated Program and Block Erase Algorithms -- Command User Interface for Automation -- Status Register for System Feedback Industry-Standard Packaging -- 56-Lead SSOP -- 56-Lead TSOP -- BGA* CSP -- Intel(R) Easy BGA
Intel(R) 3 Volt Fast Boot Block Flash memory offers the highest performance synchronous burst reads--making it an ideal memory solution for burst CPUs. The Intel 3 Volt Fast Boot Block Flash memory also supports asynchronous page mode operation for non-clocked memory subsystems. Combining high read performance with the intrinsic nonvolatility of flash memory eliminates the traditional redundant memory paradigm of shadowing code from a slower nonvolatile storage source to a faster execution memory device, (e.g., SRAM SDRAM), for improved system performance. By adding 3 Volt Fast Boot Block Flash memory to your system you could reduce the total memory requirement, which helps increase reliability and reduce overall system power consumption--all while reducing system cost. This family of products is manufactured on Intel(R) 0.4 m ETOXTM V process technology. They are available in a wide variety of industry-standard packaging technologies.
Notice: This document contains information on products in full production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.
Order Number: 290644-005 January 2000
Information in this document is provided in connection with Intel(R) products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 28F800F3 and 28F160F3 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) Intel Corporation 1998-2000 *Other brands and names are the property of their respective owners.
28F800F3 and 28F160F3
Contents
1.0 2.0 Introduction .................................................................................................................. 1
1.1 2.1 2.2 2.3 Product Overview .................................................................................................. 1 Pinouts .................................................................................................................. 2 Pin Description ...................................................................................................... 2 Memory Blocking Organization ............................................................................. 7 2.3.1 Parameter Blocks ..................................................................................... 7 2.3.2 Main Blocks .............................................................................................. 7 Bus Operations....................................................................................................10 3.1.1 Read.......................................................................................................10 3.1.2 Output Disable........................................................................................10 3.1.3 Standby ..................................................................................................11 3.1.4 Write .......................................................................................................11 3.1.5 Reset ......................................................................................................11 Read Array Command.........................................................................................13 Read Identifier Codes Command ........................................................................13 Read Status Register Command.........................................................................14 Clear Status Register Command.........................................................................14 Block Erase Command........................................................................................14 Program Command .............................................................................................15 Block Erase Suspend/Resume Command ..........................................................16 Program Suspend/Resume Command ...............................................................16 Set Read Configuration Command .....................................................................17 4.9.1 Read Configuration - (RCR.15) .............................................................18 4.9.2 Frequency Configuration Code Setting (FCC) - (RCR.13-11) ...............18 4.9.3 Data Output Configuration - (RCR.9) ....................................................20 4.9.4 Wait # Configuration - (RCR.8)..............................................................21 4.9.5 Burst Sequence - (RCR.7).....................................................................21 4.9.6 Clock Configuration - (RCR.6) ...............................................................22 4.9.7 Burst Length - (RCR.2--0) ....................................................................22 4.9.8 Continuous Burst Length........................................................................22 VPP VPPLK for Complete Protection..................................................................27 WP# = VIL for Block Locking ...............................................................................27 WP# = VIH for Block Unlocking ...........................................................................27
Product Description .................................................................................................. 2
3.0
Principles of Operation..........................................................................................10
3.1
4.0
Command Definitions.............................................................................................12
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9
5.0
Data Protection .........................................................................................................27
5.1 5.2 5.3
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6.0 7.0
VPP Voltages............................................................................................................... 28 Power Consumption ............................................................................................... 28
7.1 7.2 7.3 7.4 Active Power ....................................................................................................... 28 Automatic Power Savings ................................................................................... 28 Standby Power.................................................................................................... 28 Power-Up/Down Operation ................................................................................. 29 7.4.1 RST# Connection................................................................................... 29 7.4.2 VCC, VPP and RST# Transitions............................................................. 29 Power Supply Decoupling ................................................................................... 29 7.5.1 VPP Trace on Printed Circuit Boards ...................................................... 30 Absolute Maximum Ratings ................................................................................ 30 Extended Temperature Operating Conditions..................................................... 31 Capacitance ........................................................................................................ 31 DC Characteristics--Extended Temperature...................................................... 32 AC Characteristics--Read-Only Operations--Extended Temperature............... 35 AC Characteristics--Write Operations--Extended Temperature ....................... 41 AC Characteristics--Reset Operation--Extended Temperature ........................ 43 Extended Temperature Block Erase and Program Performance........................ 44
7.5
8.0
Electrical Specifications........................................................................................ 30
8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8
9.0 10.0
Ordering Information.............................................................................................. 45 Additional Information ........................................................................................... 46
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Revision History
Date of Revision 05/12/98 11/15/98 Version -001 -002 Original version Minor text modifications Revised Page mode read waveform Revised Single synchronous read waveform Improved automotive specifications Changed name from Fast Boot Block Flash Memory Family 8 and 16 Mbit. Added Easy BGA pinout graphic Added TSOP and Easy BGA part number nomenclature Minor text modifications Revised Figure 1, 8x8 Easy BGA Package Ballout Revised Section 4.9.2, Frequency Configuration Added Figure 7, Data Output with FCC Setting at Code 3 Revised Figure 12, Block Erase Suspend/Resume Flowchart Revised tELCH, and tCHQX Specification Added tEHEL Specification Corrected TSOP Pinout Diagram Corrected Frequency Configuration Settings Table Added ICCES and ICCWS specifications Increased tELCH and tCHQV Description
03/22/99 09/17/99
-003 -004
01/12/2000
-005
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1.0
Introduction
This datasheet contains 8- and 16-Mbit 3 Volt Intel(R) Fast Boot Block Flash memory information. Section 1.0 provides a flash memory overview. Sections 2.0 through 8.0 describe the memory functionality and electrical specifications for extended temperature product offerings.
1.1
Product Overview
The 3 Volt Fast Boot Block Flash memory provides density upgrades with pinout compatibility for 8- and 16-Mbit densities. This family of products is a high-performance, low-voltage memory with a 16-bit data bus and individually erasable blocks. These blocks are optimally-sized for code and data storage. Eight 4-Kword parameter blocks are positioned at either the top (denoted by -T suffix) or bottom (denoted by -B suffix) of the address map. The rest of the device is grouped into 32-Kword main blocks. The upper two (or lower two) parameter blocks can be locked (WP# = VIL) for complete code protection. The device's optimized architecture and interface dramatically increase read performance beyond previously attainable levels. It supports synchronous burst reads and asynchronous page-mode reads from main blocks (parameter blocks support single synchronous and asynchronous reads). Upon initial power-up or return from reset, the main blocks of the device default to a page-mode read configuration. Page-mode read configuration is ideal for non-clocked memory systems and is compatible with page-mode ROM. Synchronous burst reads are enabled by configuring the read configuration register using the standard two-bus-cycle algorithm. In synchronous burst mode, the CLK input increments an internal burst address generator, synchronizes the flash memory with the host CPU, and outputs data on every rising (or falling) CLK edge up to 60 MHz. An output signal, WAIT#, is also provided to ease CPU-to-flash memory communication and synchronization during continuous burst operations that are not initiated on a four-word boundary. In addition to the enhanced architecture and optimized interface, this family of products incorporates SmartVoltage technology which enables fast 12 Volt factory programming and 2.7 V- 3.6 V in system programming for low power designs. Specifically designed for low-voltage systems, 3 Volt Fast Boot Block Flash memory components support read operations at 2.7 V-3.6 V (3.0 V-3.6 V for automotive temperature) V CC and block erase and program operations at 2.7 V- 3.6 V (3.0 V-3.6 V for automotive temperature) and 12 V VPP. The 12 V VPP option renders the fastest program performance to increase factory programming throughput. With the 2.7 V -3.6 V (3.0 V-3.6 V for automotive temperature) VPP option, VCC and VPP can be tied together for a simple, low power design. In addition to the voltage flexibility, the dedicated VPP pin gives complete data protection when VPP VPPLK. The flexible input/output (I/O) voltage feature of the device helps reduce system power consumption and simplifies interfacing to sub 2.7 V CPUs. Powered by the VCCQ pins, the I/O buffers can operate independently of the core voltage. The Flexible I/O ring of the device works in three modes:
1. With VCCQ voltage at 1.65 V, the I/Os can swing between GND and 1.65 V, reducing I/O power
consumption by 65% over standard 3 V flash memory components.
2. With VCC and VCCQ at 2.7 V-3.6V the device is an ideal fit for single supply voltage, low power,
and battery-powered applications.
3. The 5 V-safe feature allows easy interface to 5 V I/O systems by tolerating 5 V CMOS input
levels. This helps ease CPU interfacing by adapting to CPU's bus voltage without using buffers or level shifters.
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The device's Command User Interface (CUI) serves as the interface between the system processor and internal flash memory operation. A valid command sequence written to the CUI initiates device automation. This automation is controlled by an internal Write State Machine (WSM) which automatically executes the algorithms and timings necessary for block erase and program operations. The status register provides WSM feedback by signifying block erase or program completion and status. Block erase and program automation allows erase and program operations to be executed using an industry-standard two-write command sequence. A block erase operation erases one block at a time, and data is programmed in word (16 bit) increments. The erase suspend feature allows system software to suspend an ongoing block erase operation in order to read from or program data to any other block. The program suspend feature allows system software to suspend an ongoing program operation in order to read from any other location. The 3 Volt Fast Boot Block Flash memory devices offer two low-power savings features: Automatic Power Savings (APS) and standby mode. The device automatically enters APS mode following the completion of a read cycle. Standby mode is initiated when the system deselects the device by driving CE# inactive or RST# active. RST# also resets the device to read array, provides write protection, and clears the status register. Combined, these two features significantly reduce power consumption.
2.0
Product Description
This section describes the pinout and block architecture of the device family.
2.1
Pinouts
Intel 3 Volt Fast Boot Block Flash memory provides upgrade paths in each package pinout up to the 16-Mbit density. The family is available in Easy BGA, BGA CSP, 56-lead SSOP and 56-lead TSOP packages. Pinouts for the 8- and 16-Mbit components are illustrated in Figure 1, Figure 2, Figure 3 and Figure 4.
2.2
Pin Description
The pin description table describes pin usage.
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Figure 1. 8 x 8 Easy BGA Package Ballout
1 A A1 B A2 C A3 D A4 E DQ8 F CE# DQ 0 DQ10 DQ11 DQ5 DQ14 G A0 H A22(1) OE# VCCQ VCC VSSQ DQ7 VCCQ WAIT# VSSQ DQ2 DQ4 DQ13 DQ15 GND A16 DU DU G A16 GND D15 D7 D13 VSSQ DQ4 VCC DQ2 VSSQ A0 H WAIT# VCCQ DQ 1 DQ9 DQ3 DQ12 DQ6 DU DU F DU DU DQ14 DQ5 DQ11 DQ10 DQ0 CE# A5 DU DU DU DU A8 A9 E DU DU DQ6 DQ12 DQ3 DQ9 DQ1 DQ8 A7 WP# WE# ADV# A21(1) A12 A13 D A9 A8 DU DU DU DU A5 A4 A17 A19 RST# CLK A20(1) A11 A14 C A13 A12 A21(1) ADV# WE# WP# A7 A3 A6 A18 VPP VCC GND A10 A15 B A14 A11 A20(1) CLK RST# A19 A17 A2 2 3 4 5 6 7 8 A A15 A10 GND VCC VPP A18 A6 A1 8 7 6 5 4 3 2 1
VCCQ OE# A22(1)
Top View - Ball Side Down
Bottom View - Ball Side Up
EasyPin01
NOTES: 1. A20 is only valid on 32-Mbit densities and above, A21 is only valid on 64-Mbit densities and above, A22 is only valid on 128-Mbit densities and above. All locations are populated with solder balls. 2. Shaded connections on the Top View indicate possible future upgrade address connections. 3. Reference the Preliminary Mechanical Specification for Easy BGA Package at the Intel(R) Flash Packaging Data website, http://developer.intel.com/design/flash/packdata/index.htm, for detailed package specifications.
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Figure 2. 56-Ball BGA* Package Ballout
Pin #1 Indicator
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4
5
6
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A
A15 A12 GND CLK VCC VPP A4 A1
B
A14 A11 A8 A20 ADV# WE# A19 A17 A5 A2
C
A13 A10 A9 A21 RST# WP# A18 A7 A6 A3
D
VCCQ DQ7 DQ13 DQ12 DQ4 DQ11 DQ10 DQ9 DQ0 CE#
E
A16 DQ15 DQ6 DQ5 VCC DQ3 DQ2 DQ1 OE# A0
F
WAIT# GND DQ14 GND VCCQ DQ8 GND
Top View, Ball Side Down
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5
4
3
2
1
A
A1 A4 VPP VCC CLK GND A12 A15
B
A2 A5 A17 A19 WE# ADV# A20 A8 A11 A14
C
A3 A6 A7 A18 WP# RST# A21 A9 A10 A13
D
CE# DQ0 DQ9 DQ10 DQ11 DQ4 DQ12 DQ13 DQ7 VCCQ
E
A0 OE# DQ1 DQ2 DQ3 VCC DQ5 DQ6 DQ15 A16
F
GND DQ8 VCCQ GND DQ14 GND WAIT#
Bottom View, Ball Side Up
NOTES: 1. Shaded connections on the Top View indicate upgrade address connections. Lower density devices will not have upper address solder balls. Routing is not recommended in this area. 2. A20 and A21 are the upgrade addresses for potential 32-Mbit and 64-Mbit devices. 3. Reference the BGA* Package Mechanical and Shipping Media Specification at the Intel(R) Flash Packaging Data website, http://developer.intel.com/design/flash/packdata/index.htm, for detailed package specifications.
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Figure 3. SSOP Pinout
16-Mbit
VCC CLK ADV# GND NC A15 A14 A13 A12 A11 A10 A9 A8 NC GND DQ6 DQ14 DQ7 DQ15 GND VCCQ A16 WAIT# DQ13 DQ5 DQ12 DQ4 VCC
8-Mbit
VCC CLK ADV# GND NC A15 A14 A13 A12 A11 A10 A9 A8 NC GND DQ6 DQ14 DQ7 DQ15 GND VCCQ A16 WAIT# DQ13 DQ5 DQ12 DQ4 VCC 1 2 3 4 5 --A 20 32-Mbit 6 7 8 9 10 11 12 13 14--A 21 64-Mbit 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
8-Mbit
WE# RST# VPP WP# NC A1 A2 A3 A4 A5 A6 A7 A17 A18 DQ9 DQ1 DQ8 DQ0 OE# GND CE# A0 NC VCCQ DQ2 DQ10 DQ3 DQ11
16-Mbit
WE# RST# VPP WP# A19 A1 A2 A3 A4 A5 A6 A7 A17 A18 DQ9 DQ1 DQ8 DQ0 OE# GND CE# A0 NC VCCQ DQ2 DQ10 DQ3 DQ11
56-Lead SSOP 16 mm x 23.7 mm TOP VIEW
NOTE: A20 and A21 are the upgrade addresses for potential 32-Mbit and 64-Mbit devices.
Figure 4. TSOP Pinout
16Mbit 28F800F3 A15 A14 A13 A12 A11 A10 A9 A8 NC NC GND ADV# CLK VCC WE# RST# VPP WP# A19 A18 A17 A7 A6 A5 A4 A3 A2 A1 8Mbit 28F800F3 A15 A14 A13 A12 A11 A10 A9 A8 NC NC GND ADV# CLK VCC WE# RST# VPP WP# NC A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 --A 21 64MBit 10 --A 20 32MBit 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 8Mbit 28F800F3 WAIT# A16 VCCQ GND DQ15 DQ7 DQ14 DQ6 GND DQ13 DQ5 DQ12 DQ4 VCC DQ 11 DQ3 DQ10 DQ2 VCCQ DQ 9 DQ1 DQ8 DQ0 OE# GND CE# A0 NC 16Mbit 28F160F3 WAIT# A16 VCCQ GND DQ15 DQ7 DQ14 DQ6 GND DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 VCCQ DQ 9 DQ1 DQ8 DQ0 OE# GND CE# A0 NC
56-Lead TSOP 14 mm x 20 mm Top View
NOTE: A20 and A21 are the upgrade addresses for potential 32-Mbit and 64-Mbit devices.
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Table 1.
Sym
Pin Descriptions
Type Name and Function ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are internally latched during read and write cycles. 8-Mbit: A0-18, 16-Mbit: A0-19 DATA INPUT/OUTPUTS: Inputs data and commands during write cycles, outputs data during memory array, status register (DQ0-DQ7), and identifier code read cycles. Data pins float to high-impedance when the chip is deselected or outputs are disabled. Data is internally latched during a write cycle. CLOCK: Synchronizes the flash memory to the system operating frequency during synchronous burst mode read operations. When configured for synchronous burst-mode reads, the address is latched on the first rising (or falling, depending upon the read configuration register setting) CLK edge when ADV# is active or upon a rising ADV# edge, whichever occurs first. CLK is ignored during asynchronous page-mode read and write operations. ADDRESS VALID: Indicates that a valid address is present on the address inputs. Addresses are latched on the rising edge of ADV# during read and write operations. ADV# may be tied active during asynchronous read and write operations. CHIP ENABLE: Activates the device's control logic, input buffers, decoders, and sense amplifiers. CE#-high deselects the device and reduces power consumption to standby levels. RESET: When driven low, RST# inhibits write operations which provides data protection during power transitions, and it resets internal automation. RST#-high enables normal operation. Exit from reset sets the device to asynchronous read array mode. OUTPUT ENABLE: Gates data outputs during a read cycle. WRITE ENABLE: Controls writes to the CUI and array. Addresses and data are latched on the rising edge of the WE# pulse. WRITE PROTECTION: Provides a method for locking and unlocking two parameter blocks. When WP# is at logic low, lockable blocks are locked. If a program or erase operation is attempted on a locked block, SR.1 and either SR.4 [program] or SR.5 [block erase] will be set to indicate the operation failed. When WP# is at logic high, the lockable blocks are unlocked and can be programmed or erased. WAIT: Provides data valid feedback only when configured for synchronous burst mode and the burst length is set to continuous. This signal is gated by OE# and CE# and is internally pull-up to VCCQ via a resistor. WAIT# from several components can be tied together to form one system WAIT# signal. BLOCK ERASE AND PROGRAM POWER SUPPLY (2.7 V-3.6 V, 11.4 V-12.6 V): For erasing array blocks or programming data, a valid voltage must be applied to this pin. With VPP VPPLK, memory contents cannot be altered. Block erase and program with an invalid VPP voltage should not be attempted. Applying 11.4 V-12.6 V to VPPcan only be done for a maximum of 1000 cycles on main blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80 hours maximum (see Section 6.0 for details).
A0-A19
INPUT
DQ0- DQ15
INPUT/ OUTPUT
CLK
INPUT
ADV#
INPUT
CE#
INPUT
RST# OE# WE#
INPUT INPUT INPUT
WP#
INPUT
WAIT#
OUTPUT
VPP
SUPPLY
VCC
SUPPLY
DEVICE POWER SUPPLY (2.7 V-3.6 V): With VCC VLKO, all write attempts to the flash memory are inhibited. Device operations at invalid VCC voltages should not be attempted. OUTPUT POWER SUPPLY (1.65 V-2.5 V, 2.7 V-3.6 V): Enables all outputs to be driven to 1.65 V to 2.5 V or 2.7 V to 3.6 V. When VCCQ equals 1.65 V-2.5 V, VCC voltage must not exceed 3.3 V and should be regulated to 2.7 V-2.85 V to achieve lowest power operation (see DC Characteristics for detailed information). For 5 V-tolerant operation VCCQ must equal VCC voltage and must be regulated to 2.7 V to 3.6 V. This input may be tied directly to VCC.
VCCQ
SUPPLY
GND NC
SUPPLY
GROUND: Do not float any ground pins. NO CONNECT: Lead is not internally connected; it may be driven or floated. (Pins noted as possible upgrades to 32-Mbit and 64-Mbit densities can be connected to the appropriate address lines to preenable designs for possible future devices.).
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2.3
Memory Blocking Organization
The 3 Volt Fast Boot Block Flash memory family is an asymmetrically-blocked architecture that enables system integration of code and data within a single flash device. For the address locations of each block, see the memory maps in Figure 5, "8- and 16-Mbit Top Boot Memory Map" on page 8 (top boot blocking) and Figure 6, "8- and 16-Mbit Bottom Boot Memory Map" on page 9 (bottom boot blocking).
2.3.1
Parameter Blocks
The 3 Volt Fast Boot Block Flash memory architecture includes parameter blocks to facilitate storage of frequently updated small parameters that would normally be stored in an EEPROM. By using software techniques, the word-rewrite functionality of EEPROMs can be emulated. Each 8and 16-Mbit device contains eight 4-Kwords (4,096-words) parameter blocks.
2.3.2
Main Blocks
After the parameter blocks, the remainder of the array is divided into equal size main blocks for code and/or data storage. The main blocks are the area of the device that support four-, eight-, and continuous burst operations. The 8-Mbit device contains fifteen 32-Kword (32,768-word) main blocks, and the 16-Mbit device contains thirty-one 32-Kword (32,768-word) main blocks.
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Figure 5. 8- and 16-Mbit Top Boot Memory Map
8-Mbit
Lockable Blocks
4-Kword Parameter Block 22 4-Kword Parameter Block 21 4-Kword Parameter Block 20 4-Kword Parameter Block 19 4-Kword Parameter Block 18 4-Kword Parameter Block 17 4-Kword Parameter Block 16 4-Kword Parameter Block 15
Address Range
7F000H - 7FFFFH 7E000H -7EFFFH 7D000H - 7DFFFH 7C000H - 7CFFFH 7B000H - 7BFFFH 7A000H - 7AFFFH 79000H - 79FFFH 78000H - 78FFFH Parameter Blocks
Lockable Blocks
16-Mbit
4-Kword Parameter Block 38 4-Kword Parameter Block 37 4-Kword Parameter Block 36 4-Kword Parameter Block 35
Address Range
FF000H - FFFFFH FE000H - FEFFFH FD000H - FDFFFH FC000H - FCFFFH FB000H - FBFFFH FA000H - FAFFFH F9000H - F9FFFH F8000H - F8FFFH
Parameter Blocks
EEPROM Replacement
EEPROM Replacement
4-Kword Parameter Block 34 4-Kword Parameter Block 33 4-Kword Parameter Block 32 4-Kword Parameter Block 31
32-Kword Main Block 14 32-Kword Main Block 13 32-Kword Main Block 12 32-Kword Main Block 11 32-Kword Main Block 10
32-Kword Main Block 30
F0000H - F7FFFH E8000H - EFFFFH E0000H - E7FFFH D8000H - DFFFFH D0000H - D7FFFH C8000H - CFFFFH C0000H - C7FFFH B8000H - BFFFFH B0000H - B7FFFH A8000H - AFFFFH A0000H - A7FFFH 98000H - 9FFFFH 90000H - 97FFFH 88000H - 8FFFFH 80000H - 87FFFH 78000H - 7FFFFH 70000H - 77FFFH 68000H - 6FFFFH 60000H - 67FFFH 58000H - 5FFFFH 50000H - 57FFFH 48000H - 4FFFFH 40000H - 47FFFH 38000H - 3FFFFH 30000H - 37FFFH 28000H - 2FFFFH 20000H - 27FFFH 18000H - 1FFFFH 10000H - 17FFFH 08000H - 0FFFFH 00000H - 07FFFH
70000H - 77FFFH 68000H - 6FFFFH 60000H - 67FFFH 58000H - 5FFFFH 50000H - 57FFFH 48000H - 4FFFFH 40000H - 47FFFH 38000H - 3FFFFH 30000H - 37FFFH 28000H - 2FFFFH 20000H - 27FFFH 18000H - 1FFFFH 10000H - 17FFFH Main Blocks Burstable Area 08000H - 0FFFFH 00000H - 07FFFH
32-Kword Main Block 29 32-Kword Main Block 28 32-Kword Main Block 27 32-Kword Main Block 26 32-Kword Main Block 25 32-Kword Main Block 24 32-Kword Main Block 23 32-Kword Main Block 22 32-Kword Main Block 21 32-Kword Main Block 20 32-Kword Main Block 19 32-Kword Main Block 18 32-Kword Main Block 17 32-Kword Main Block 16 32-Kword Main Block 15 32-Kword Main Block 14 32-Kword Main Block 13 32-Kword Main Block 12 32-Kword Main Block 11 32-Kword Main Block 10 32-Kword Main Block 9 32-Kword Main Block 8 32-Kword Main Block 7 32-Kword Main Block 6 32-Kword Main Block 5 32-Kword Main Block 4 32-Kword Main Block 3 32-Kword Main Block 2 32-Kword Main Block 1 32-Kword Main Block 0
Main Blocks Burstable Area
32-Kword Main Block 9 32-Kword Main Block 8 32-Kword Main Block 7 32-Kword Main Block 6 32-Kword Main Block 5 32-Kword Main Block 4 32-Kword Main Block 3 32-Kword Main Block 2 32-Kword Main Block1 32-Kword Main Block 0
0644_05
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Figure 6. 8- and 16-Mbit Bottom Boot Memory Map
8-Mbit
32-Kword Main Block 22 32-Kword Main Block 21 32-Kword Main Block 20 32-Kword Main Block 19 32-Kword Main Block 18
Address Range
78000H - 7FFFFH 70000H - 77FFFH 68000H - 6FFFFH 60000H - 67FFFH 58000H - 5FFFFH 50000H - 57FFFH 48000H - 4FFFFH 40000H - 47FFFH 38000H - 3FFFFH 30000h - 37FFFh 28000H - 2FFFFH 20000H - 27FFFH 18000H - 1FFFFH 10000H - 17FFFH Main Blocks Burstable Area 08000H - 0FFFFH
16-Mbit
32-Kword Main Block 38 32-Kword Main Block 37 32-Kword Main Block 36 32-Kword Main Block 35 32-Kword Main Block 34 32-Kword Main Block 33 32-Kword Main Block 32 32-Kword Main Block 31 32-Kword Main Block 30 32-Kword Main Block 29 32-Kword Main Block 28 32-Kword Main Block 27 32-Kword Main Block 26 32-Kword Main Block 25 32-Kword Main Block 24 32-Kword Main Block 23 32-Kword Main Block 22 32-Kword Main Block 21 32-Kword Main Block 20 32-Kword Main Block 19 32-Kword Main Block 18 32-Kword Main Block 17 32-Kword Main Block 16 32-Kword Main Block 15 32-Kword Main Block 14 32-Kword Main Block 13 32-Kword Main Block 12 32-Kword Main Block 11 32-Kword Main Block 10 32-Kword Main Block 9 32-Kword Main Block 8
Address Range
F8000H - FFFFFH F0000H - F7FFFH E8000H - EFFFFH E0000H - E7FFFH D8000H - DFFFFH D0000H - D8FFFH C8000H - CFFFFH C0000H - C7FFFH B8000H - BFFFFH B0000H - B7FFFH A8000H - AFFFFH A0000H - A7FFFH 98000H - AFFFFH 90000H - 97FFFH 88000H - 8FFFFH 80000H - 87FFFH 78000H - 7FFFFH 70000H - 77FFFH 68000H - 6FFFFH 60000h - 67FFFh 58000H - 5FFFFH 50000H - 57FFFH 48000H - 4FFFFH 40000H - 47FFFH 38000H - 3FFFFH 30000H - 37FFFH 28000H - 2FFFFH 20000H - 27FFFH 18000H - 1FFFFH 10000H - 17FFFH 08000H - 0FFFFH
Main Blocks Burstable Area
32-Kword Main Block 17 32-Kword Main Block 16 32-Kword Main Block 15 32-Kword Main Block 14 32-Kword Main Block 13 32-Kword Main Block 12 32-Kword Main Block 11 32-Kword Main Block 10 32-Kword Main Block 9 32-Kword Main Block 8
4-Kword Parameter Block 7
07000H - 07FFFH 06000H - 06FFFH 05000H - 05FFFH 04000H - 04FFFH 03000H - 03FFFH 02000H - 02FFFH 01000H - 01FFFH 00000H - 00FFFH
Parameter Blocks
EEPROM Replacement
4-Kword Parameter Block 6 4-Kword Parameter Block 5 4-Kword Parameter Block 4 4-Kword Parameter Block 3 4-Kword Parameter Block 2
Lockable Blocks
4-Kword Parameter Block 1 4-Kword Parameter Block 0
4-Kword Parameter Block 7
07000H - 07FFFH 06000H - 06FFFH 05000H - 05FFFH 04000H - 04FFFH 03000H - 03FFFH 02000H - 02FFFH 01000H - 01FFFH 00000H - 00FFFH
Parameter blocks
EEPROM Replacement
4-Kword Parameter Block 6 4-Kword Parameter Block 5 4-Kword Parameter Block 4 4-Kword Parameter Block 3 4-Kword Parameter Block 2
Lockable Blocks
4-Kword Parameter Block 1 4-Kword Parameter Block 0
0644_06
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3.0
Principles of Operation
The 3 Volt Fast Boot Block Flash memory components include an on-chip Write State Machine (WSM) to manage block erase and program. It allows for CMOS-level control inputs, fixed power supplies, and minimal processor overhead with RAM-like interface timings.
3.1
Bus Operations
The local CPU reads and writes flash memory in-system. All flash memory read and write cycles conform to standard microprocessor bus cycles.
3.1.1
Read
The flash memory has three read modes available: read array, identifier codes, and status register. These modes are accessible independent of the VPP voltage. The appropriate read command (Read Array, Read Identifier Codes, or Read Status Register) must be written to the CUI to enter the requested read mode. Upon initial power-up or exit from reset, the device defaults to read array mode. When reading information from main blocks in read array mode, the device supports two highperformance read configurations: synchronous burst mode and asynchronous page mode. Page mode and synchronous burst-mode reads are enabled by writing the Set Read Configuration Register command to any device address. Synchronous burst mode is enabled by writing to the read configuration register. This sets the read configuration, burst order, burst length, and frequency configuration. In synchronous burst mode, the device latches the initial address then outputs a sequence of data with respect to the input CLK and read configuration setting. Synchronous burst reads can be terminated after one cycle in main blocks. Asynchronous page mode is the default state and provides a high data transfer rate for nonclocked memory subsystems. In this state, data is internally read and stored in a high-speed page buffer. A1:0 addresses data in the page buffer. The page size is four words. Read operations from the parameter blocks, identifier codes and status register transpire as singlesynchronous or asynchronous read cycles. The read configuration register setting determines whether or not read operations are synchronous or asynchronous. For all read operations, CE# must be driven active to enable the devices, ADV# must be driven low to open the internal address latch, and OE# must be driven low to activate the outputs. In asynchronous mode, the address is latched when ADV# is driven high. In synchronous mode, the address is latched by ADV# going high or ADV# low in conjunction with a rising (falling) clock edge, whichever occurs first. WE# must be at VIH. Figure 17 through Figure 22 illustrate the different read cycles.
3.1.2
Output Disable
With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins DQ0-DQ15 are placed in a high-impedance state.
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3.1.3
Standby
Deselecting the device by bringing CE# to a logic-high level (VIH) places the device in standby mode, which substantially reduces device power consumption. In standby, outputs are placed in a high-impedance state independent of OE#. If deselected during program or erase operation, the device continues to consume active power until the program or erase operation is complete.
3.1.4
Write
Commands are written to the CUI using standard microprocessor write timings when ADV#, WE#, and CE# are active and OE# is inactive. The CUI does not occupy an addressable memory location. The address is latched on the rising edge of ADV#, WE#, or CE# (whichever occurs first) and data needed to execute a command is latched on the rising edge of WE# or CE# (whichever goes high first). Write operations are asynchronous. Therefore, CLK is ignored during write operations. Figure 23, "AC Waveform for Write Operations" on page 42 illustrates a write operation.
3.1.5
Reset
The device enters a reset mode when RST# is driven low. In reset mode, internal circuitry is turned off and outputs are placed in a high-impedance state. After return from reset, a time tPHQV is required until outputs are valid, and a delay (tPHWL or tPHEL) is required before a write sequence can be initiated. After this wake-up interval, normal operation is restored. The device defaults to read array mode, the status register is set to 80H, and the read configuration register defaults to asynchronous page-mode reads. If RST# is taken low during a block erase or program operation, the operation will be aborted and the memory contents at the aborted location are no longer valid. See Figure 24, "AC Waveform for Reset Operation" on page 43 for detailed information regarding reset timings.
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4.0
Command Definitions
Device operations are selected by writing specific commands into the CUI. Table 3 defines these commands.
Table 2.
Mode Reset Standby Output Disable Read
Bus Operations
Notes RST# VIL VIH VIH 1,2 VIH VIH 3,4 VIH CE# X VIH VIL VIL VIL VIL ADV# X X X VIL VIL VIL OE# X X VIH VIL VIL VIH WE# X X VIH VIH VIH VIL Address X X X X See Table 4 X VPP X X X X X X DQ0-15 High Z High Z High Z DOUT See Table 4 DIN
Read Identifier Codes Write
NOTES: 1. Refer to DC Characteristics. When VPP VPPLK, memory contents can be read, but not altered. 2. X can be VIL or VIH for control and address input pins and VPPLK or VPP1 or VPP2 for VPP. See DC Characteristics for VPPLK and VPP1 or VPP2 voltages. 3. Command writes involving block erase or program are reliably executed when VPP = VPP1 or VPP2 and VCC = VCC1 or VCC2 (see Section 8.0 for operating conditions at different temperatures). 4. Refer to Table 3 for valid DIN during a write operation.
Table 3.
Command Definitions(1)
Bus Cycles Required 1 2 2 1 2 2 1 1 2 6,7 6,7,8 6 6 5 First Bus Cycle Notes Oper(2) Write Write Write Write Write Write Write Write Write Addr(3) X X X X X X X X RCD Data(4) FFH 90H 70H 50H 20H 40H or 10H B0H D0H 60H Write RCD 03H Write Write BA WA D0H WD Read Read IA X ID SRD Oper(2) Addr(3) Data(4) Second Bus Cycle
Command Read Array/Reset Read Identifier Codes Read Status Register Clear Status Register Block Erase Program Block Erase and Program Suspend Block Erase and Program Resume Set Read Configuration
NOTES: 1. Commands other than those shown above are reserved by Intel for future device implementations and should not be used. 2. Bus operations are defined in Table 2. 3. X = Any valid address within the device. IA = Identifier Code Address. BA = Address within the block being erased. WA = Address of memory location to be written. RCD = Data to be written to the read configuration register. This data is presented to the device on A15-0; set all other address inputs to "0." See Table 6, "Read Configuration Register Definition" on page 17 for a description of the read configuration register bits.
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4. SRD = Data read from status register. See Table 5, "Status Register Definition" on page 15 for a description of the status register bits. WD = Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first). ID = Data read from identifier codes. See Table 4 for manufacturer and device codes. 5. Following the Read Identifier Codes command, read operations access manufacturer, device codes, and read configuration register. 6. Following a block erase, program, and suspend operation, read operations access the status register. 7. To issue a block erase, program, or suspend operation to a lockable block, hold WP# at VIH. 8. Either 40H or 10H are recognized by the WSM as the program setup.
4.1
Read Array Command
Upon initial device power-up or exit from reset, the device defaults to read array mode. The read configuration register defaults to asynchronous page mode. The Read Array command also causes the device to enter read array mode. The device remains enabled for reads until another command is written. Once the internal WSM has started a block erase or program, the device will not recognize the Read Array command until the WSM completes its operation or unless the WSM is suspended via an Erase or Program Suspend command. The Read Array command functions independently of the VPP voltage.
4.2
Read Identifier Codes Command
The identifier code operation is initiated by writing the Read Identifier Codes command. After writing the command, read cycles retrieve the manufacturer and device codes (see Table 4 for identifier code values). Page mode and burst reads are not supported in this read mode. To terminate the operation, write another valid command, like the Read Array command. The Read Identifier Codes command functions independently of the VPP voltage.
Table 4.
Identifier Codes
Code Manufacturer Code -T 8 Mbit -B Device Code -T 16 Mbit -B Read Configuration Register 00001H 00005H 88F4H RCD(1) 00001H 88F3H 00001H 88F2H Address 00000H 00001H Data 0089H 88F1H
NOTE: 1. Read Configuration Register = RCD.
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4.3
Read Status Register Command
The status register can be read at any time by writing the Read Status Register command to the CUI. After writing this command, all subsequent read operations output status register data until another valid command is written. Page mode and burst reads are not supported in this read mode. The status register content is updated and latched on the rising edge of ADV# or rising (falling) CLK edge when ADV# is low during synchronous burst mode or the falling edge of OE# or CE#, whichever occurs first. The Read Status Register command functions independently of the VPP voltage.
4.4
Clear Status Register Command
Status register bits SR.5, SR.4, SR.3, and SR.1 are set to "1"s by the WSM and can only be cleared by issuing the Clear Status Register command. These bits indicate various error conditions. By allowing system software to reset these bits, several operations may be performed (such as cumulatively erasing or writing several bytes in sequence). The status register may be polled to determine if a problem occurred during the sequence. The Clear Status Register command functions independently of the applied VPP voltage. After executing this command, the device returns to read array mode.
4.5
Block Erase Command
Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is written first, followed by a block erase confirm. This command sequence requires appropriate sequencing and address within the block to be erased (erase changes all block data to FFH). Block preconditioning, erase, and verify are handled internally by the WSM. After the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see Figure 10, "Automated Block Erase Flowchart" on page 23). The CPU can detect block erase completion by analyzing status register bit SR.7. When the block erase completes, check status register bit SR.5 for an error flag ("1"). If an error is detected, check status register bits SR.4, SR.3, and SR.1 to understand what caused the failure. After examining the status register, it should be cleared if an error was detected before issuing a new command. The device will remain in status register read mode until another command is written to the CUI.
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Table 5.
WSMS 7
Status Register Definition
ESS 6 ES 5 PS 4 VPPS 3 NOTES: PSS 2 DPS 1 R 0
SR.7 = WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy SR.6 = ERASE SUSPEND STATUS (ESS) 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE STATUS (ES) 1 = Error in Block Erasure 0 = Successful Block Erase SR.4 = PROGRAM STATUS (PS) 1 = Error in Program 0 = Successful Program SR.3 = VPP STATUS (VPPS) 1 = VPP Low Detect, Operation Abort 0 = VPP OK SR.2 = PROGRAM SUSPEND STATUS (PSS) 1 = Program Suspended 0 = Program in Progress/Completed SR.1 = DEVICE PROTECT STATUS (DPS) 1 = Block Erase or Program Attempted on a Locked Block, Operation Abort 0 = Unlocked SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
Check SR.7 to determine block erase or program completion. SR.6-0 are invalid while SR.7 = "0." When an Erase Suspend command is issued, the WSM halts execution and sets both SR.7 and SR.6 to "1." SR.6 remains set until an Erase Resume command is written to the CUI. If both SR.5 and SR.4 are "1"s after a block erase or program attempt, an improper command sequence was entered.
SR.3 does not provide a continuous VPP feedback. The WSM interrogates and indicates the VPP level only after a block erase or program operation. SR.3 is not guaranteed to report accurate feedback when VPP VPPH1 or VPPH2 or VPPLK. When a Program Suspend command is issued, the WSM halts execution and sets both SR.7 and SR.2 to "1." SR.2 remains set until a Program Resume command is written to the CUI. If a block erase or program operation is attempted on a locked block, SR.1 is set by the WSM and aborts the operation if WP# = VIL. SR.0 is reserved for future use and should be masked out when polling the status register.
4.6
Program Command
Program operation is executed by a two-cycle command sequence. Program setup (standard 40H or alternate 10H) is written, followed by a second write that specifies the address and data. The WSM then takes over, controlling the internal program algorithm. After the program sequence is written, the device automatically outputs status register data when read (see Figure 11, "Automated Program Flowchart" on page 24). The CPU can detect the completion of the program event by analyzing status register bit SR.7. When the program operation completes, check status register bit SR.4 for an error flag ("1"). If an error is detected, check status register bits SR.5, SR.3, and SR.1 to understand what caused the problem. After examining the status register, it should be cleared if an error was detected before issuing a new command. The device will remain in status register read mode until another command is written to the CUI.
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4.7
Block Erase Suspend/Resume Command
The Block Erase Suspend command allows block erase interruption to read or program data in another block. Once the block erase process starts, writing the Block Erase Suspend command requests that the WSM suspend the block erase operation after a certain latency period. The device continues to output status register data when read after the Block Erase Suspend command is issued. Status Register bits SR.7 and SR.6 indicate when the block erase operation has been suspended (both will be set to "1"). Specification tWHRH2 defines the block erase suspend latency. At this point, a Read Array command can be written to read data from blocks other than that which is suspended. A Program command sequence can also be issued during erase suspend to program data in other blocks. Using the Program Suspend command (see Section 4.8), a program operation can be suspended during an erase suspend. The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. During a block erase suspend, the chip can go into a pseudo-standby mode by taking CE# to VIH, which reduces active current draw. VPP must remain at VPP1 or VPP2 while block erase is suspended. WP# must also remain at VIL or VIH. To resume the block erase operation, write the Block Erase Resume command to the CUI. This will automatically clear status register bits SR.6 and SR.7. After the Erase Resume command is written, the device automatically outputs status register data when read (see Figure 12, "Block Erase Suspend/Resume Flowchart" on page 25). Block erase cannot resume until program operations initiated during block erase suspend have completed.
4.8
Program Suspend/Resume Command
The Program Suspend command allows program interruption to read data in other flash memory locations. Once the program process starts, writing the Program Suspend command requests that the WSM suspend the program operation after a certain latency period. The device continues to output status register data when read after issuing the Program Suspend command. Status register bits SR.7 and SR.2 indicate when the Program operation has been suspended (both will be set to "1"). Specification tWHRH1 defines the program suspend latency. At this point, a Read Array command can be written to read data from blocks other than that which is suspended. The only other valid commands while Program is suspended are Read Status Register and Program Resume. During a program suspend, the chip can go into a pseudo-standby mode by taking CE# to VIH, which reduces active current draw. VPP must remain at VPP1 or VPP2 while program is suspended. WP# must also remain at VIL or VIH. To resume the program, write the Program Resume command to the CUI. This will automatically clear status register bits SR.7 and SR.2. After the Program Resume command is written, the device automatically outputs status register data when read (see Figure 13, "Program Suspend/Resume Flowchart" on page 26).
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Table 6.
RM 15 BS 7
Read Configuration Register Definition
R 14 CC 6 FC2 13 R 5 FC1 12 R 4 FC0 11 R 3 NOTES: R 10 BL2 2 DOC 9 BL1 1 WC 8 BL0 0
RCR.15 = READ MODE (RM) 0 = Synchronous Burst Reads Enabled 1 = page mode Reads Enabled (Default) RCR.14 = RESERVED FOR FUTURE ENHANCEMENTS (R) RCR.13-11 = FREQUENCY CONFIGURATION (FC2-0) 001 = Code 1 reserved for future use 010 = Code 2 011 = Code 3 100 = Code 4 101 = Code 5 110 = Code 6 RCR.10 = RESERVED FOR FUTURE ENHANCEMENTS (R) RCR.9 = DATA OUTPUT CONFIGURATION (DOC) 0 = Hold Data for One Clock 1 = Hold Data for Two Clocks RCR.8 = WAIT CONFIGURATION (WC) 0 = WAIT# Asserted During Delay 1 = WAIT# Asserted One Data Cycle Before Delay RCR.7 = BURST SEQUENCE (BS) 0 = Intel Burst Order 1 = Linear Burst Order RCR.6 = CLOCK CONFIGURATION (CC) 0 = Burst Starts and Data Output on Falling Clock Edge 1 = Burst Starts and Data Output on Rising Clock Edge RCR.5-3 = RESERVED FOR FUTURE ENHANCEMENTS (R) RCR.2-0 = BURST LENGTH (BL2-0) 001 = 4 Word Burst 010 = 8 Word Burst 111 = Continuous Burst
Read mode configuration affects reads from main blocks. Parameter block, status register, and identifier reads support single read cycles. These bits are reserved for future use. Set these bits to "0." See Section 4.9.2 for information about the frequency configuration and its effect on the initial read. Undocumented combinations of bits RCR.14-11 are reserved by Intel Corporation for future implementations and should not be used.
These bits are reserved for future use. Set these bits to "0." Undocumented combinations of bits RCR.10-9 are reserved by Intel Corporation for future implementations and should not be used.
These bits are reserved for future use. Set these bits to "0." In the asynchronous page mode, the burst length always equals four words. Undocumented combinations of bits RCR.2-0 are reserved by Intel Corporation for future implementations and should not be used
4.9
Set Read Configuration Command
The Set Read Configuration command writes data to the read configuration register. This operation is initiated by a standard two bus cycle command sequence. The Read Configuration Setup command (60H) is written and the data to be written to the read configuration is presented, which is then followed by a second write that confirms the operation and again presents the data to be written to the read configuration register. The read configuration register data is placed on the address bus, A15:0,during both bus cycles and is latched on the rising edge of ADV#, CE#, or WE# (whichever occurs first). The read configuration register data sets the device's read configuration, burst order, frequency configuration, burst length and all other parameters. This command functions independently of the applied VPP voltage. After executing this command, the device returns to read array mode.
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4.9.1
Read Configuration - (RCR.15)
The device supports two high performance read configurations: Synchronous burst mode and asynchronous page mode. Bit RCR.15 in the read configuration register sets the read configuration to either synchronous burst or asynchronous page mode. Asynchronous page mode is the default read configuration state. Parameter blocks, status register, and identifier modes only support single-synchronous and asynchronous read operations.
4.9.2
Frequency Configuration Code Setting (FCC) - (RCR.13-11)
The frequency configuration code setting informs the device of the number of clocks that must elapse after ADV# is driven active before data will be available. This value is determined by the input clock frequency and the set up and hold requirements of the target system. See Table 7, "Frequency Configuration Settings" on page 20 for the specific input CLK frequency configuration codes. The frequency configuration codes in Table 7 are derived from equations (1), (2) and (3) with assumed values for the tAVQV, tADD, tDATA parameters. Below is the example of the calculation to obtain the frequency configuration code: Flash performance can be determined by the following equations: {1/Frequency (MHz)}1000 = CLK Period (ns) n(CLK Period) tAVQV (ns) + tADD(ns) + tDATA (ns) n-2 = Frequency Configuration Code (FCC)* n : # of Clock periods (rounded up to the next integer) (1) (2) (3)
*Must use FCC = n - 1 when operating in the continous burst mode.
Parameters defined by CPU: tADD = Clock to CE#, ADV#, or Address Valid whichever occurs last. tDATA = Data set up to Clock Parameters defined by flash: tAVQV = Address to Output Delay Example: CPU Clock Speed = 50 MHz tADD = 6 ns (typical speed from CPU) (max) tDATA = 4 ns (typical speed from CPU) (min) tAVQV = 90 ns (from Section 8.5 AC Characteristic - Read Only Operations Table) From Eq. (1): {1/50 (MHz)}1000 = 20 ns From Eq. (2) n(20 ns) 90 ns + 6 ns + 4 ns n(20 ns) 100 ns n 100/20 5 (Integer) From Eq. (3) n-2=5-2=3 Frequency Code Setting to the RCR is Code 3 The formula tAVQV (ns) + tADD(ns) + tDATA (ns) is also known as initial access time.
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Figure 7. Data Output with FCC Setting at Code 3
tADD tDATA
CLK (C) CE# ADV#
1st
2nd
3rd
4th
5th
A15-0 DQ15-0 (D/Q)
Valid Address
High Z
Valid Output
Valid Output
R13
NOTE: 1. Figure 7 shows the data output available and valid after 4 latencies from ADV# going low in the 1st clock period with the FCC setting at 3.
Figure 8 illustrates data output latency from ADV# going active for different frequency configuration codes. Figure 8. Frequency Configuration
CLK (C)
A19-0 (A)
Valid Address
ADV# (V)
Code 2
DQ15-0 (D/Q)
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Code 3
DQ15-0 (D/Q)
Valid Output
Valid Output
Valid Output
Valid Output
Code 4
DQ15-0 (D/Q)
Valid Output
Valid Output
Valid Output
Code 5
DQ15-0 (D/Q)
Valid Output
Valid Output
Code 6
DQ15-0 (D/Q)
Valid Output
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Table 7.
Frequency Configuration Settings
Input CLK Frequency Frequency Configuration Code VCC = 3.0 V-3.6 V 1 2 3 4 5 6 Reserved 40 MHz 50 MHz 60 MHz 66 MHz -- -95 VCC = 2.7 V-3.6 V Reserved 38 MHz 47 MHz 57 MHz 66 MHz -- -120 VCC = 2.7 V-3.6 V Reserved 30 MHz 38 MHz 46 MHz 53 MHz 60 MHz
NOTE: Table derived by using formulas (1), (2) and (3) in Section 4.9.2. Values of tADD, tDATA defined by CPU, assumed to be 6 ns and 4 ns respectively; value of tAVQV per Section 8.5.
4.9.3
Data Output Configuration - (RCR.9)
The output configuration determines the number of clocks during which data will be held valid. The data hold time is configurable as either one or two clocks. Subsequent reads in burst mode with zero wait-states can be defined by: tCHQV (ns) + tDATA (ns) One CLK Period (4) In Table 7, consider the CPU clock at 50 MHz, and FCC is 3. The clock period is 20 ns. This data applied to the formula above for the subsequent reads assuming the data output hold time is one clock: 14 ns + 4 ns 20 ns Data output will be available and valid at every clock period. Consider the CPU frequency at 60 MHz, and FCC is 4. Clock period is 16.6 ns. The initial access time is calculated to be 100 ns (4 latencies). This condition satisfies tAVQV (ns) + tADD(ns) + tDATA (ns) = 90 ns + 6 ns + 4 ns = 100 ns. However, the data output hold time of one clock violates burst data output zero wait-states: tCHQV (ns) + tDATA (ns) One CLK Period 14 ns + 4 ns = 18 ns is not less than one clock period. To satisfy the formula above the data output hold time must be set a 2 clocks to correctly allow for data output setup time. This formula is also satisfied if the CPU has tDATA (ns) 2 ns, which yields: 14 ns + 2 ns 16.6 ns In page mode reads the initial access time can be determined by the formula: tADD (ns) + tDATA (ns) + tAVQV (ns) (5) and subsequent reads in page mode are defined by: tAPA (ns) + tDATA (ns) (minimum time) (6)
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Figure 9. Output Configuration
CLK (C) 1 CLK Data Hold 2 CLK Data hold DQ15-0 (D/Q)
Valid Output Valid Output Valid Output
DQ15-0 (D/Q)
Valid Output
4.9.4
Wait # Configuration - (RCR.8)
The WAIT# configuration bit controls the behavior of the WAIT# output signal. This output signal can be set to be asserted during or one CLK cycle before an output delay when continuous burst length is enabled. Its setting will depend on the system and CPU characteristic.
4.9.5
Burst Sequence - (RCR.7)
The burst sequence specifies the order in which data is addressed in synchronous burst mode. This order is programmable as either linear or Intel burst order. The continuous burst length only supports linear burst order. The order chosen will depend on the CPU characteristic. See Table 8 for more details.
Table 8.
Starting Addr. (Dec.) 0 1 3 3 4 5 6 7 8 9 15
Sequence and Burst Length
Burst Addressing Sequence (Dec.) 4-Word Burst Length Linear 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 Intel 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 8-Word Burst Length Linear 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Intel 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 NA NA NA Continuous Burst Linear 0-1-2-3-4-5-6-... 1-2-3-4-5-6-7-... 2-3-4-5-6-7-8-... 3-4-5-6-7-8-9-... 4-5-6-7-8-9-10-.. 5-6-7-8-9-10-11-... 6-7-8-9-10-11-12-... 7-8-9-10-11-12-13-... 8-9-10-11-12-13-14-... ... 15-16-17-18-19-20-21-...
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4.9.6
Clock Configuration - (RCR.6)
The clock configuration configures the device to start a burst cycle, output data, and assert WAIT# on the rising or falling edge of the clock. CLK flexibility helps ease 3 Volt Fast Boot Block Flash memory interface to a wide range of burst CPUs.
4.9.7
Burst Length - (RCR.2--0)
The burst length is the number of words that the device will output. The device supports burst lengths of four and eight words. In four- or eight-word burst configuration the device will perform a wrap around type burst access (See Table 8). It also supports a continuous burst mode. In continuous burst mode, the device will linearly output data until the internal burst counter reaches the end of the device's burstable address space. Bits RCR.2-0 in the read configuration register set the burst length.
4.9.8
Continuous Burst Length
When operating in the continuous burst mode, the flash memory may incur an output delay when the burst sequence crosses the first 16-word boundary. The starting address dictates whether or not a delay will occur. If the starting address is aligned to a four-word boundary, the delay will not be seen. If the starting address is the end of a four-word boundary, the output delay will be equal to the frequency configuration setting; this is the worst case delay. The delay will only take place once during a continuous burst access, and if the burst sequence never crosses a 16-word boundary, the delay will never happen. Using the WAIT# output pin in the continuous burst configuration, the system is informed if this output delay occurs.
22
28F800F3 and 28F160F3
Figure 10. Automated Block Erase Flowchart
Start
Bus Operation
Command
Comments Data = 20H Addr = Within Block to Be Erased Data = D0H Addr = Within Block to Be Erased Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Write 20H, Block Address Write D0H, Block Address Suspend Blk. Erase Loop 0 1 Full Status Check if Desired No Suspend Block Erase Yes
Write
Erase Setup
Write
Erase Confirm
Read
Read Status Register
Standby
Repeat for subsequent block erasures. Full status check can be done after each block erase or after a sequence of block erasures. Write FFH after the last operation to place device in read array mode.
SR.7 =
Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = 0 SR.1 = 0 1 SR.4, 5 = 0 1 SR.5 = 0 Block Erase Successful Block Erase Error
If an error is detected, clear the status register before attempting retry or other error recovery. Bus Operation Standby Command Comments Check SR.3 1 = VPP Error Detect Check SR.1 1 = Device Protect Detect WP# = VIL Check SR.4, 5 Both 1 = Command Sequence Error Check SR.5 1 = Block Erase Error
VPP Range Error
Standby
1 Device Protect Error
Standby
Standby
Command Sequence Error
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Staus Register command, in cases where multiple blocks are erased before full status is checked.
23
28F800F3 and 28F160F3
Figure 11. Automated Program Flowchart
Start
Bus Operation
Command
Comments Data = 40H Addr = Location to Be Written Data = Data to Be Written Addr = Location to Be Written Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Write 40H, Address Write Data and Address
Write
Program Setup
Write
Data
Read
Read Status Register No Suspend Program
Suspend Program Loop 0
Standby Repeat for subsequent byte writes.
SR.7 = 1 Full Status Check if Desired
Yes
SR full status check can be done after each byte write or after a sequence of program operations. Write FFH after the last byte write operation to place device in read array mode.
Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above)
Bus Operation Command Comments Check SR.3 1 = VPP Error Detect Check SR.1 1 = Device Protect Detect WP# = VIL Check SR.4 1 = Data Write Error
1 SR.3 = 0 SR.1 = 0 1 SR.4 = 0 Program Successful Program Error VPP Range Error 1 Device Protect Error
Standby Standby
Standby
SR.4, SR.3 and SR.1 are only cleared by the Clear Staus Register command, in cases where multiple locations are written before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery.
24
28F800F3 and 28F160F3
Figure 12. Block Erase Suspend/Resume Flowchart
Bus Operation Write Command Erase Suspend Comments Data = B0H Addr = X Status Register Data Addr = X Check SR.7 1 = WSM Ready 0 = WSM Busy Check SR.6 1 = Block Erase Suspended 0 = Block Erase Completed Erase Resume Read Array or Program Data = D0H Addr = X Data = FFH Addr = X
Start
Write B0H
Read
Read Status Register
Standby
SR.7 = 1 SR.6 = 1 Read Read or Byte Write? No Done Yes Write D0H
0
Standby
Write
0
Block Erase Completed
Write
Read Array or Program Loop
Program
Read Array Data
Program Loop
Write FFH
Block Erase Resumed
Read Array Data
25
28F800F3 and 28F160F3
Figure 13. Program Suspend/Resume Flowchart
Start
Bus Operation Write
Command Program Suspend
Comments Data = B0H Addr = X Status Register Data Addr = X Check SR.7 1 = WSM Ready 0 = WSM Busy Check SR.2 1 = Program Suspended 0 = Program Completed
Write B0H
Read
Read Status Register
Standby
SR.7 = 1 SR.2 = 1 Write FFH
0
Standby
0
Write
Read Array
Data = FFH Addr = X Read array locations from block other than that being written
Program Completed
Read
Write
Program Resume
Data = D0H Addr = X
Read Array Data
Done Reading Yes Write D0H
No
Write FFH
Program Resumed
Read Array Data
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28F800F3 and 28F160F3
5.0
Data Protection
The 3 Volt Fast Boot Block Flash memory architecture features two hardware-lockable parameter blocks, so critical code can be kept secure while six other parameter blocks can be programmed or erased as necessary to facilitate EEPROM emulation.
5.1
VPP VPPLK for Complete Protection
The VPP programming voltage can be held low for complete write protection of all blocks in the flash device. When VPP is below VPPLK, any block erase or program operation will result in a error, prompting the corresponding status register bit (SR.3) to be set.
5.2
WP# = VIL for Block Locking
The lockable blocks are locked when WP# = V IL; any block erase or program operation to a locked block will result in an error, which will be reflected in the status register. For top configuration, the top two parameter blocks (blocks #37, #38 for the 16 Mbit, blocks #21, #22 for the 8 Mbit) are lockable. For the bottom configuration, the bottom two parameter blocks (blocks #0, #1) are lockable. Unlocked blocks can be programmed or erased normally (unless VPP is below VPPLK).
5.3
WP# = VIH for Block Unlocking
WP# controls all block locking and VPP provides protection against spurious writes. Table 9 defines the write protection methods.
Table 9.
Write Protection Truth Table
VPP X VIL VPPLK VPPLK WP# X X VIL VIH RST# VIL VIH VIH VIH Write Protection Provided All Blocks Locked All Blocks Locked Lockable Blocks Locked All Blocks Unlocked
27
28F800F3 and 28F160F3
6.0
VPP Voltages
Intel 3 Volt Fast Boot Block Flash memory provides in-system programming and erase at 2.7 V- 3.6 V (3.0 V-3.6 V for automotive temperature) VPP. For customers requiring fast programming in their manufacturing environment, this family of products includes an additional high-performance 12 V programming feature. The 12 V VPP mode enhances programming performance during short period of time typically found in manufacturing processes; however, it is not intended for extended use. 12 V may be applied to VPP during block erase and program operations for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80 hours maximum. Stressing the device beyond these limits may cause permanent damage.
7.0
Power Consumption
While in operation, the flash device consumes active power. However, Intel(R) Flash devices have power savings that can significantly reduce overall system power consumption. The Automatic Power Savings (APS) feature reduces power consumption when the device is idle. When CE# is not asserted, the flash enters its standby mode, where current consumption is even lower. The combination of these features minimizes overall memory power and system power consumption.
7.1
Active Power
With CE# at a logic-low level and RST# at a logic-high level, the device is in active mode. Active power is the largest contributor to overall system power consumption. Minimizing active current has a profound effect on system power consumption, especially for battery-operated devices.
7.2
Automatic Power Savings
Automatic Power Savings (APS) provides low-power operation during active mode, allowing the flash to put itself into a low current state when not being accessed. After data is read from the memory array, the device's power consumption enters the APS mode where typical I CC current is comparable to ICCS. The flash stays in this static state with outputs valid until a new location is read.
7.3
Standby Power
With CE# at a logic-high level (VIH) and the CUI in read mode, the flash memory is in standby mode, which disables much of the device's circuitry and substantially reduces power consumption. Outputs (DQ0-DQ15) are placed in a high-impedance state independent of the status of the OE# signal. If CE# transitions to a logic-high level during erase or program operations, the device will continue to perform the operation and consume corresponding active power until the operation is completed.
28
28F800F3 and 28F160F3
System engineers should analyze the breakdown of standby time versus active time and quantify the respective power consumption in each mode for their specific application. This will provide a more accurate measure of application-specific power and energy requirements.
7.4
Power-Up/Down Operation
The device is protected against accidental block erasure or programming during power transitions. Power supply sequencing is not required, since the device is indifferent as to which power supply, VPP, VCC, or VCCQ, powers-up first.
7.4.1
RST# Connection
The use of RST# during system reset is important with automated program/erase devices since the system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization will not occur because the flash memory may be providing status information instead of array data. Intel recommends connecting RST# to the system reset signal to allow proper CPU/flash initialization following system reset. System designers must guard against spurious writes when VCC voltages are above VLKO and VPP is active. Since both WE# and CE# must be low for a command write, driving either signal to VIH will inhibit writes to the device. The CUI architecture provides additional protection since alteration of memory contents can only occur after successful completion of the two-step command sequences. The device is also disabled until RST# is brought to VIH, regardless of the state of its control inputs. By holding the device in reset during power-up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection.
7.4.2
VCC, VPP and RST# Transitions
The CUI latches commands as issued by system software and is not altered by VPP or CE# transitions or WSM actions. Its default state upon power-up, after exit from deep power-down mode or after VCC transitions above VLKO (Lockout voltage), is read array mode. After any block erase or program operation is complete (even after VPP transitions down to VPPLK), the CUI must be reset to read array mode via the Read Array command if access to the flash memory array is desired.
7.5
Power Supply Decoupling
Flash memory's power switching characteristics require careful device de-coupling. System designers should consider three supply current issues:
* Standby current levels (ICCS) * Active current levels (ICCR) * Transient peaks produced by falling and rising edges of CE#.
29
28F800F3 and 28F160F3
Transient current magnitudes depend on the device outputs' capacitive and inductive loading. Twoline control and proper de-coupling capacitor selection will suppress these transient voltage peaks. Each flash device should have a 0.1 F ceramic capacitor connected between each V CC and GND, and between its VPP and GND. These high- frequency, inherently low-inductance capacitors should be placed as close as possible to the package leads.
7.5.1
VPP Trace on Printed Circuit Boards
Designing for in-system writes to the flash memory requires special consideration of the VPP power supply trace by the printed circuit board designer. The VPP pin supplies the flash memory cells current for programming and erasing. VPP trace widths and layout should be similar to that of VCC. Adequate VPP supply traces, and de-coupling capacitors placed adjacent to the component, will decrease spikes and overshoots.
8.0
8.1
Electrical Specifications
Absolute Maximum Ratings
Parameter Temperature under Bias Storage Temperature Voltage On Any Pin (except VCC, VCCQ, and VPP) VPP Voltage VCC and VCCQ Voltage Output Short Circuit Current Maximum Rating -40 C to +125 C -65 C to +125 C -0.5 V to +5.5 V(1) -0.5 V to +13.5 V(1, 2, 4) -0.2 V to +5.0 V(1) 100 mA(3)
NOTES: 1. All specified voltages are with respect to GND. Minimum DC voltage is -0.5 V on input/output pins and -0.2 V on VCC and VPP pins. During transitions, this level may undershoot to -2.0 V for periods <20 ns. Maximum DC voltage on input/output pins is 5.5 V and VCC and VCCQ is VCC + 0.5 V which, during transitions, may overshoot to VCC +2.0 V for periods <20 ns. 2. Maximum DC voltage on VPP may overshoot to +14.0 V for periods <20 ns. 3. Output shorted for no more than one second. No more than one output shorted at a time. 4. VPP Program voltage is normally 2.7 V-3.6 V. Connection to supply of 11.4 V-12.6 V can only be done for 1000 cycles on the main blocks and 2500 cycles on the parameter blocks during program/erase. VPP may be connected to 12 V for a total of 80 hours maximum.
NOTICE: This datasheet contains information on products in full production. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design.
Warning:
Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
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28F800F3 and 28F160F3
8.2
Extended Temperature Operating Conditions
Symbol TA VCC1 VCC2 VCC3 VCCQ1 VCCQ2 VCCQ3 VCCQ4 VPP1 VPP2 Cycling Parameter Operating Temperature VCC Supply Voltage VCC Supply Voltage VCC Supply Voltage I/O Voltage I/O Voltage I/O Voltage I/O Voltage VPP Supply Voltage VPP Supply Voltage Block Erase Cycling 1 1 1,4 1,2 1,2 1,2,4 1 1 1,4 3 Notes Min -40 2.7 2.7 2.7 1.65 1.8 2.7 4.75 2.7 11.4 100,000 Max +85 2.85 3.3 3.6 2.5 2.5 3.6 5.25 3.6 12.6 Unit C V V V V V V V V V Cycles
NOTE: 1. See DC Characteristics tables for voltage range-specific specifications. 2. The voltage swing on the inputs, VIN is required to match VCCQ . 3. Applying VPP = 11.4 V-12.6 V during a program or erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. A hard connection to VPP = 11.4 V-12.6 V is not allowed and can cause damage to the device. 4. VCC, VCCQ, and VPP1 must share the same supply when all three are between 2.7 V and 3.6 V.
8.3
Capacitance(1)
TA = +25 C, f = 1 MHz
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Typ 6 8 Max 8 12 Unit pF pF Condition VIN = 0.0 V VOUT = 0.0 V
NOTE: 1. Sampled, not 100% tested.
31
28F800F3 and 28F160F3
8.4
DC Characteristics--Extended Temperature(1)
VCC 2.7 V-3.6 V 2.7 V-3.6 V Typ Max 1 10 25 3 30 75 20 2.7 V-2.85 V 1.65 V-2.5 V Typ Max 1 10 25 75 150 2.7 V-3.3 V 1.8 V-2.5 V Typ Max 1 10 A Output Leakage Current for WAIT# VCC Standby Current 25 250 A A VCC = VCCMax VCCQ = VCCQMax VIN = VCCQ or GND VCC = VCCMax VCCQ = VCCQMax VIN = VCCQ or GND Unit Test Conditions
Sym
Parameter
VCCQ Note
ILI
Input Load Current Output Leakage Current
2
2
ILO
Iccs
VCC = VCCMax CE# = RST # = VCC Asynchronous tAVQV = Min VIN = VIH or VIL CE# = VIL OE# = VIH Synchronous CLK = 33 MHz CE# = VIL OE# = VIH Burst length = 8 Word VPP = VPP1 or VPP2 Program in Progress VPP = VPP1 or VPP2 Erase in Progress VPP VCC VPP > VCC VPP =VPP1 Program in Progress VPP = VPP2 Program in Progress VPP = VPP1 Program in Progress VPP = VPP2 Program in Progress VPP = VPP1 or VPP2 Program or Erase Suspend in Progress VCC = VCCMax CE# = RST# = VCC WP# = Vcc or GND
3 ICCR VCC Read Current
45
60
30
45
40
55
mA
45
60
30
45
40
55
mA
ICCW ICCE IPPR
VCC Program Current VCC Erase Current
3,4 3,4
8 8 2
20 20 15 200 35 10 25 25
8 8 2 50 10 2 13 8
20 20 15 200 35 10 25 25
8 8 2 50 10 2 13 8
20 20 15 200 35 10 25 25
mA mA A A mA mA mA mA
VPP Read Current
2,3 2,4,5
50 10 2
IPPW
VPP Program Current
2,4,5 IPPE VPP Erase Current
12 8
IPPES IPPWS ICCWS ICCES
VPP Erase Suspend Current VCC Program Suspend or Block Erase Suspend Current
2,3
50
200
50
200
50
200
A
1,8
95
95
250
A
32
28F800F3 and 28F160F3
DC Characteristics, Continued
VCC Sym Parameter VCCQ Note VIL Input Low Voltage 2.7 V-3.6 V 2.7 V-3.6 V Min -0.4 Max 0.22 * VCC 5.5 2.7 V-2.85 V 1.65 V-2.5 V Min -0.2 VCCQ - 0.2 -0.10 VCCQ - 0.1 1.5 2.7 3.6 2.7 2.85 2.7 11.4 1.5 1.2 12.6 11.4 1.5 1.2 12.6 11.4 1.5 1.2 3.3 12.6 1.5 Max 0.2 VCCQ + 0.2 0.10 2.7 V-3.3 V 1.8 V-2.5 V Min -0.2 VCCQ - 0.2 -0.10 VCCQ - 0.1 1.5 Max 0.2 VCCQ + 0.2 0.10 V Unit Test Conditions
VIH
Input High Voltage
2.0
V VCC = VCCMin VCCQ = VCCQMin IOL = 100 A VCC = VCCMin VCCQ = VCCQMin IOH = -100 A Complete Write Protection
VOL
Output Low Voltage VCCQ - 0.1 4 6 VPP during Program and Erase Operations 6 6 6,7 VCC Prog/Erase Lock Voltage VCCQ Prog/Erase Lock Voltage
0.10
V
VOH VPPLK VPP1 VPP2 VPP3 VPP4 VLKO VLKO2
Output High Voltage
V
VPP Lock-Out Voltage
V V V V V V V
NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at normal VCC, TA = +25 C. 2. Applying VPP = 11.4 V-12.6 V during program/erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80 hours maximum. 3. The specification is the sum of VCC and VCCQ currents. 4. Erases and program operations are inhibited when VPP VPPLK, and not guaranteed outside the valid VPP ranges of VPP1 and VPP2. 5. Sampled, not 100% tested. 6. ICCES is specified with device deselected. If device is read while in erase suspend, current draw is sum of ICCES and ICCR. 7. Automatic Power Savings (APS) reduces ICCR to approximate standby levels, in static operation. 8. ICCWS and ICCES are specified with the evice disabled. If the device is read or written while in suspend mode, the device's current draw is ICCR or ICCW.
33
28F800F3 and 28F160F3
Figure 14. AC Input/Output Reference Waveform for VCC = 2.7 V--3. 6 V
VCCQ Input 0V VCCQ/2
Test Points
VCCQ/2
Output
NOTE: AC test inputs are driven at VCCQ min. for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at VCCQ/2. Input rise and fall times (10% to 90%) < 5 ns. Worst case speed conditions are when VCCQ = 2.7 V.
Figure 15. AC Equivalent Testing Load Circuit
VCCQ R1
Device Under Test
Out CL R2
NOTE: See table for component values. Test Configuration 2.7 V Standard Test 1.65 V Standard Test NOTE: CL includes jig capacitance. CL (pF) 50 50 R1 () 25K 16.7K R2 () 25K 16.7K
34
28F800F3 and 28F160F3
8.5
AC Characteristics--Read-Only Operations(1,2)--Extended Temperature
Product -95 3.0 V-- 3.6 V Min 15 2.5 5 7 7 11 15 3 4 3 10 14 10 10 90 5 90 90 10 10 3 25 25 600 3 15 10 10 3 27 25 600 15 10 10 95 95 95 10 10 3 35 30 600 15 3 10 16 10 10 120 120 120 7 7 11 19 3 10 23 Max 2.7 V-- 3.6 V Min 15 2.5 5 7 7 11 23 Max -120 2.7 V-- 3.6 V Min 15 2.5 5 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
#
Symbol
Parameter
VCC Notes
R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22
tCLK tCH(tCL) tCHCL tAVCH tVLCH tELCH tCHQV tCHQX tCHAX tCHTL tAVVH tELVH tAVQV tELQV tVLQV tVLVH tVHVL tVHAX tAPA tGLQV tPHQV tEHQZ tGHQZ tOH tEHEL
CLK Period CLK High (Low) Time CLK Fall (Rise) Time Address Valid Setup to CLK ADV# Low Setup to CLK CE# Low Setup to CLK CLK to Output Delay Output Hold from CLK Address Hold from CLK CLK to WAIT# delay Address Setup to ADV# High CE# Low to ADV# High Address to Output Delay CE# Low to Output Delay ADV# Low to Output Delay ADV# Pulse Width Low ADV# Pulse Width High Address Hold from ADV# High Page Address Access Time OE# Low to Output Delay RST# High to Output Delay CE# or OE# High to Output in High Z, Whichever Occurs First Output Hold from Address, CE#, or OE# Change, Whichever Occurs First CE# High Pulse Width
R23 R24
3 6
0 0
0 0
0 0
ns ns
NOTES: 1. See Figure 14, "AC Input/Output Reference Waveform for VCC = 2.7 V--3. 6 V" on page 34 for timing measurements and maximum allowable input slew rate. 2. Data bus voltage must be less than or equal to VCCQ when a read operation is initiated to guarantee AC specifications. 3. Sampled, not 100% tested. 4. Address hold in synchronous burst mode is defined as tCHAX or tVHAX, whichever timing specification is satisfied first. 5. OE# may be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV. 6. ADV# tied to ground, tEHEL (CE# High Pulse Width) must be held high for a minimum of 15 ns.
35
28F800F3 and 28F160F3
Figure 16. AC Waveform for CLK Input
R3
CLK (C)
R2 R1
Figure 17. AC Waveform for Single Asynchronous Read Operations from Parameter Blocks, Status Register, Identifier Codes
VIH VIL
Valid Address
A19-0 (A)
R18 R13 R11
ADV# (V)
VIH VIL
R17
R16 R15 R22
CE# (E)
VIH VIL R12 R14 VIH VIL
OE# (G)
WE# (W)
VIH VIL
WAIT# (T)
VOH VOL R20 VOH R23
Valid Output
DQ15-0 (D/Q)
High Z
VOL R21
RST# (R)
VIH VIL
36
28F800F3 and 28F160F3
Figure 18. AC Waveform for Asynchronous Page Mode Read Operations from Main Blocks
A19-2 (A)
VIH VIL
Valid Address
A1-0 (A)
VIH VIL R13
Valid Address
Valid Address
Valid Address
Valid Address
R18 R11
R17
ADV# (V)
VIH VIL
R15
R22
CE# (E)
VIH VIL R14
OE# (G)
VIH VIL
WE# (W) WAIT# (T)
VIH VIL VOH VOL R20 R19
Valid Output Valid Output Valid Output
R23
Valid Output
DQ15-0 (D/Q)
VOH VOL
High Z
R21
RST# (R)
VIH VIL
37
28F800F3 and 28F160F3
Figure 19. AC Waveform for Single Synchronous Read Operations from Parameter Blocks, Status Register, Identifier Codes
VIH VIL R4 R9
CLK [C]
Note 1
A19-0 [A]
VIH VIL
Valid Address
R13 R11 R17 VIH VIL R16 R15 R5 R22 R7 R18
ADV# [V]
CE# [E]
VIH VIL R12 R14 R6
OE# [G]
VIH VIL
WE# [W]
VIH VIL R8
WAIT# [T]
VOH VOL R20
High Z Valid Output
R23
DQ15-0 [D/Q]
VOH VOL
NOTES: 1. 1.Depending upon the frequency configuration code value in the read configuration register, insert clock cycles: * Frequency Configuration 2 insert two clock cycles * Frequency Configuration 3 insert three clock cycles * Frequency Configuration 4 insert four clock cycles * Frequency Configuration 5 insert five clock cycles * Frequency Configuration 6 insert six clock cycles See Section 4.9.2 for further information about the frequency configuration and its effect on the initial read.
38
28F800F3 and 28F160F3
Figure 20. AC Waveform for Synchronous Burst Read Operations, Four-Word Burst Length, from Main Blocks
VIH VIL R4
CLK (C)
Note 1
A19-0 (A)
VIH VIL
Valid Address
R9
R18 R11
R17
ADV# (V)
VIH VIL R16 R22 R5
CE# (E)
VIH VIL R12
R6 VIH VIL
OE# (G)
WE# (W)
VIH VIL
WAIT# (T)
VOH VOL R20 R7
R8 VOH
R23
Valid Output Valid Output
DQ15-0 (D/Q)
High Z
VOL
Valid Output
Valid Output
NOTES: 1. 1.Depending upon the frequency configuration code value in the read configuration register, insert clock cycles: * Frequency Configuration 2 insert two clock cycles * Frequency Configuration 3 insert three clock cycles * Frequency Configuration 4 insert four clock cycles * Frequency Configuration 5 insert five clock cycles * Frequency Configuration 6 insert six clock cycles See Section 4.9.2 for further information about the frequency configuration and its effect on the initial read.
39
28F800F3 and 28F160F3
Figure 21. AC Waveform for Continuous Burst Read, Showing an Output Delay with Data Output Configuration Set to One Clock
CLK (C)
VIH VIL
Note 1
A19-0 (A) ADV# (V)
VIH VIL VIH VIL
CE# (E)
VIH VIL
OE# (G)
VIH VIL
WE# (W)
VIH VIL R10 R10
WAIT# (T)
VOH VOL VOH
Note 2
R7
DQ15-0 (D/Q)
VOL
Valid Output
High Z Valid Output
Valid Output
Valid Output
Valid Output
NOTES: 1. This delay will only occur when burst length is configured as continuous. See Section 4.9.7 for further information about burst length configuration. 2. WAIT# is configurable. It can be set to assert during or one CLK cycle before an output delay. See Section 4.9.2 for further information about the frequency configuration and its effect on the initial read.
Figure 22. AC Waveform for Continuous Burst Read, Showing an Output Delay with Data Output Configuration Set to Two Clocks
CLK (C)
VIH VIL
Note 1
A19-0 (A) ADV# (V)
VIH VIL VIH VIL
CE# (E)
VIH VIL
OE# (G)
VIH VIL
WE# (W)
VIH VIL R10 R10
WAIT# (T)
VOH VOL VOH
Note 2
R7
DQ15-0 (D/Q)
VOL
Valid High Z Output
Valid Output
NOTES: 1. This delay will only occur when burst length is configured as continuous. See Section 4.9.7 for further information about burst length configuration. 2. WAIT# is configurable. It can be set to assert during or two CLK cycles before an output delay. See Section 4.9.2 for further information about the frequency configuration and its effect on the initial read.
40
28F800F3 and 28F160F3
8.6
AC Characteristics--Write Operations(1, 2)--Extended Temperature
Valid for All Speed and Voltage Combinations Notes Min 600 0 75 10 5 5 70 75 75 10 0 0 0 3 6 3 3 7 3,8 3,8 20 200 200 15 0 0 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
#
Sym
Parameter
Unit
W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18
tPHWL (tPHEL) tELWL (tWLEL) tWP (tWLWH) tVLVH tDVWH (tDVEH) tAVWH (tAVEH) tVLEH (tVLWH) tAVVH tWHEH (tEHWH) tWHDX (tEHDX) tWHAX (tEHAX) tVHAX tWPH (tWHWL) tBHWH (tBHEH) tVPWH (tVPEH) tWHGL (tEHGL) tQVBL tQVVL
RST# High Recovery to WE# (CE#) Going Low CE# (WE#) Setup to WE# (CE#) Going Low Write Pulse Width ADV# Pulse Width Data Setup to WE# (CE#) Going High Address Setup to WE# (CE#) Going High ADV# Setup to WE# (CE#) Going High Address Setup to ADV# Going High CE# (WE#) Hold from WE# (CE#) High Data Hold from WE# (CE#) High Address Hold from WE# (CE#) High Address Hold from ADV# Going High Write Pulse Width High WP# Setup to WE# (CE#) Going High VPP Setup to WE# (CE#) Going High Write Recovery before Read WP# Hold from Valid SRD VPP Hold from Valid SRD
3 4 4
NOTES: 1. See Figure 14, "AC Input/Output Reference Waveform for VCC = 2.7 V--3. 6 V" on page 34 for timing measurements and maximum allowable input slew rate. 2. A write operation can be initiated and terminated with either CE# or WE#. 3. Sampled, not 100% tested. 4. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. 5. Refer to Table 3 for valid AIN and DIN for block erase or program. 6. Write pulse width high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low last). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL. 7. tWHGL is 15 ns unless resuming a program suspend or erase suspend command; then 30 ns is required before read can be commenced. 8. VPP should be held at VPPH1 or VPPH2 until determination of block erase or program success.
41
28F800F3 and 28F160F3
Figure 23. AC Waveform for Write Operations
Note 1 Note 2
Valid Address
Note 3
Valid Address
Note 4
Note 5
A20-0 (A)
VIH VIL
W12 W6
W11
W8
ADV# (V)
VIH VIL
W4 W7
CE# (WE#) [E(W)]
VIH VIL
W2 W9 W16
Note 6
OE# [G]
VIH VIL
W1 W13
WE# (CE#) [W(E)]
VIH VIL
W3 W5 W10 W19
Valid SRD
Note 6
DATA [D/Q]
VIH
Data In Data In
VIL VIH VIL VIH VIL
VPPH1/2 W15 W18 W14 W17
RST# [P]
WP# [B]
VPP [V]
VPPLK VIL
NOTES: 1. VCC power-up and standby. 2. Write block erase or program setup. 3. Write block erase confirm or valid address and data. 4. Automated erase or program delay. 5. Read status register data. 6. For read operations, OE# and CE# must be driven active, and WE# de-asserted.
42
28F800F3 and 28F160F3
8.7
AC Characteristics--Reset Operation--Extended Temperature
Figure 24. AC Waveform for Reset Operation
R20
RST# (R)
VIH VIL P1
(A) Reset while device is in read mode Abort Complete
P2 R20
RST# (R)
VIH VIL P1
(B) Reset during program or block erase, P1 P2 Abort Complete
P2 R20
RST# (R)
VIH VIL P1
(C) Reset during program or block erase, P1 P2
Table 10. Reset Specifications(1)
Number P1 P2 Symbol tPLPH tPLRH Parameter RST# Low to Reset during Read (If RST# is tied to VCC, this specification is not applicable) RST# Low to Reset during Block Erase or Program Notes 2,3 3,4 Min 100 22 Max Unit ns s
NOTES: 1. These specifications are valid for all product versions (packages and speeds). 2. If tPLPH is < 100 ns the device may still reset but this is not guaranteed. 3. Sampled, but not 100% tested. 4. If RST# is asserted while a block erase or word program operation is not executing, the reset will complete within 100 ns.
43
28F800F3 and 28F160F3
8.8
Extended Temperature Block Erase and Program Performance(1,2,3)
2.7 V-3.6 V VPP 11.4 V-12.6 V VPP Unit Typ(4) Program Time tWHRH1, tEHRH1 Block Program Time (Parameter) Block Program Time (Main) 5 5 5 5 5 23.5 0.10 0.8 1 1.8 6 13 Max 200 0.30 2.4 4 5 10 20 Typ(4) 8 0.03 0.24 0.8 1.1 5 10 Max 185 0.10 0.8 4 5 10 12 s sec sec sec sec s s
#
Sym
Parameter
Notes
W19 tWHRH2, tEHRH2
Block Erase Time (Parameter) Block Erase Time (Main) tWHRH5, tEHRH5 tWHRH6, tEHRH6 Program Suspend Latency Erase Suspend Time
NOTES: 1. These performance numbers are valid for all speed versions. 2. Sampled, but not 100% tested. 3. Reference the Figure 23, "AC Waveform for Write Operations" on page 42. 4. Typical values measured at TA = +25 C and nominal voltages. Subject to change based on device characterization. 5. Excludes system-level overhead.
44
28F800F3 and 28F160F3
9.0
Ordering Information
DT 2 8 F 1 6 0 F 3 T 1 2 0
Package DT = Extended temp., 56-Lead SSOP GT = Extended temp., 56-Ball BGA* CSP TE = Extended temp., 56-Lead TSOP RC = Extended temp., Easy BGA Access Speed (ns) (120,150)
T = Top Blocking B = Bottom Blocking
Product line designator for all Intel(R) Flash products Device Density 160 = x16 (16-Mbit) 800 = x16 (8-Mbit) Product Family F3 = 3 Volt Fast Boot Block VCC = 2.7 V - 3.6 V VPP = 2.7 V - 3.6 V or 11.4 V - 12.6 V
Valid Combinations
56-Lead SSOP Extended 16 M DT28F160F3T120 DT28F160F3B120 DT28F160F3T95 DT28F160F3B95 DT28F800F3T120 Extended 8 M DT28F800F3B120 DT28F800F3T95 DT28F800F3B95 56-Lead TSOP TE28F160F3T120 TE28F160F3B120 TE28F160F3T95 TE28F800F3B95 TE28F800F3T120 TE28F800F3B120 TE28F800F3T95 TE28F800F3B95 8 x 8 Easy BGA RC28F160F3T120 RC28F160F3B120 RC28F160F3T95 RC28F800F3B95 RC28F800F3T120 RC28F800F3B120 RC28F800F3T95 RC28F800F3B95 56-Ball BGA CSP(1) GT28F160F3T120 GT28F160F3B120 GT28F160F3T95 GT28F800F3B95
NOTE: 1. The 56-ball BGA package topside mark reads F160F3. All product shipping boxes or trays provide the correct information regarding bus architecture.
45
28F800F3 and 28F160F3
10.0
Additional Information
Order Number 297939 210830 292213 298161 Contact your Intel Representative 297874 Document/Tool
3 Volt Fast Boot Block Flash Memory Specification Update Flash Memory Databook AP-655 3 Volt Fast Boot Block Design Guide Intel(R) Flash Memory Chip Scale Package User's Guide Intel(R) Flash Data Integrator (IFDI) Software Developer's Kit IFDI Interactive: Play with Intel (R) Flash Data Integrator on Your PC
NOTES: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. Visit Intel's World Wide Web home page at http://www.intel.com or http://developer.intel.com for technical documentation and tools.
46

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