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DATA SHEET
MICRONAS
DRX 8872C COFDM Demodulator/FEC
Edition Feb. 18, 2004 6251-618-2DS
MICRONAS
DRX 8872C
Contents Page 4 4 4 5 6 6 6 6 8 8 9 10 11 11 11 11 12 13 14 14 15 15 16 16 17 18 20 21 21 21 22 22 22 23 23 23 24 24 24 24 25 26 26 26 26 Section 1. 1.1. 1.2. 1.3. 2. 2.1. 2.2. 2.3. 2.4. 2.5. 2.5.1. 2.6. 3. 3.1. 3.1.1. 3.1.2. 3.1.3. 3.1.4. 3.1.5. 3.1.6. 3.1.7. 3.1.8. 3.2. 3.2.1. 3.2.2. 3.2.3. 3.2.4. 3.2.5. 3.3. 3.3.1. 3.3.2. 3.3.3. 3.3.4. 3.3.5. 3.3.6. 3.3.7. 3.4. 3.4.1. 3.4.2. 3.4.3. 3.4.4. 3.5. 3.5.1. 3.5.2. 3.5.3. Title Introduction Features Applications DVB-T Front-End Application Functional Description Analog input AGC Crystal Manufacturing Guidelines Lock Indication Host Interface MPEG2 Output Application Programming Interface (API) Initialize System Settings SP7_LoadMicrocode SP7_LoadImage SP7_SetSamplingMode SP7_SetAGCParams SP7_SetOutputEnable SP7_GetOutputEnable SP7_TSOutput SP7_LCKMode Setup Signal Parameters SP7_SetChannelParams SP7_GetChannelParams SP7_SetOfdmParams SP7_GetOfdmParams SP7_Start Selecting Channels SP7_Tune_init SP7_Tune_properties SP7_Tune_program SP7_Tune_error SP7_Tune_get_freq SP7_EnableTunerAccess SP7_LockingStatus Monitor Channel Quality SP7_GetSN SP7_GetConstellationDiagram SP7_GetBer SP7_GetTpsInfo Commands and other Useful Functions SP7_Reboot SP7_Reset SP7_SysReset
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DRX 8872C
Contents, continued Page 26 26 26 26 26 27 27 27 27 28 29 29 30 33 34 34 35 35 36 36 36 36 37 37 38 39 39 39 40 40 41 44 Section 3.5.4. 3.5.5. 3.5.6. 3.5.7. 3.5.8. 3.5.9. 3.5.10. 3.6. 3.6.1. 3.6.2. 4. 4.1. 4.2. 4.3. 4.4. 4.4.1. 4.4.2. 4.4.2.1. 4.4.3. 4.4.3.1. 4.4.3.2. 4.4.3.3. 5. 5.1. 5.2. 6. 6.1. 6.2. 6.2.1. 6.2.2. 6.2.3. 7. Title SP7_Restart SP7_Halt SP7_Nop SP7_Wreg SP7_Rreg SP7_Wvar SP7_Rvar Interrupts and Events SP7_ReadIrq SP7_PollEvent Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Configurations Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions General Recommended Operating Conditions Characteristics DC Electrical Characteristics Temperature Ratings ADC Parameters Appendix A - API Data Types Basic Data Types Chip-specific Data Types Appendix B - API Required Platform Functions PC Platforms Running Windows 98, NT, 2000, and XP Other platforms SP7_I2C_Write SP7_I2C_Read I2ctest.c Data Sheet History
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DRX 8872C
COFDM Demodulator/FEC 1. Introduction The DRX 8872C is an ETS 300 744-compliant integrated demodulator and forward error corrector (FEC) for DVB-T receivers. The IC accepts 1st and 2nd IF COFDM signals as input data. The 1st IF sampling option further decreases system cost. The incoming signal is sampled by a highperformance 10-bit A/D converter. The internal microprocessor performs the detection of the COFDM parameters and configuration of the demodulator automatically, without any interaction with the host processor. The error correction unit corrects remaining errors and outputs a DVB-compliant MPEG-2 transport stream. The DRX 8872C can cope with very severe channel distortions due to its state-of-the-art channel estimation unit. - 1st and 2nd IF COFDM supported
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- No VCXO required because of digital resampling techniques - Quick synchronization after channel switch (<70 ms) - 6 MHz, 7 MHz, and 8 MHz channelcompliant with only one crystal - Supports all DVB-T modes including hierarchical modulation - Digital AFC - BER, S/N, packet error, constellation diagram, lock indication readout - Serial or parallel MPEG-2 transport stream output - Supply voltage: 2.5 V (core); 3.3V (I/O) - Control: via serial bus - Package: 80-pin PTQFP - Ambient operating temperature: 0 C to +70 C - IEEE 1149.1 boundary scan
1.1. Features - Excellent performance in presence of echoes, cochannel and AWGN - Integrated microprocessor to perform autonomous operation - Flexible concept by "micro-coded" algorithms - Detection of channel type (echoes, co-channel, gaussian noise ...) via channel classificator function - Very suitable for SFN operation - Complete software API for smooth integration - Integrated 10-bit ADC
1.2. Applications - IDTV receivers - Set-top boxes - Network Interface Modules (NIMs) - PC-TV cards
AGC
1st IF or 2nd IF OFDM
ADC
Signal Processing
8K/2K FFT/ Phase Rotation
Channel Estimation
Data Demultiplexer
Diversity MUX
Pilot Processor
Host Interface
Boundary Scan
Inner De-interleaver
Viterbi Decoder
Outer De-interleaver
ReedSolomon Decoder
Output Control
MPEG 2
Fig. 1-1: Block diagram of the DRX 8872C
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DRX 8872C
1.3. DVB-T Front-End Application Fig. 1-2 shows a block diagram of a typical DVB-T front-end using the DRX 8872C at the first intermediate frequency. The tuner converts the COFDM signal to a first intermediate frequency of about 36 MHz which is then band-pass-filtered by a SAW filter stage. The SAW filter is followed by a differential-in / differential-out IF amplifier. This chapter describes in detail how to connect the DRX 8872C in such an application.
61 MHz
RF-AGC
IF-AGC
RF COFDM
DownConverter
1st IF @ ~36 MHz
Gain SAW
Gain
ADC
DRX 8872C
MPEG2 Transport Stream
Fig. 1-2: Front-end block diagram for the DRX 8872C
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2. Functional Description 2.1. Analog input The input signal of the DRX 8872C consists of a 1st or 2nd IF COFDM signal with a bandwidth of 6, 7, or 8 MHz. The input of the demodulator is differential for optimal noise performance. The reference voltages that are needed for the ADC are generated internally. The reference voltages are connected to pins for decoupling reasons. Fig. 2-2: AGC application diagram.
VDDH 3.3 Volt digital VDDL 2.5 Volt digital VDDA 2.5 Volt analog digital ground analog ground for ADC 100 nF decoupling capacitor
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For tuners that need voltages other than 0 to 3.3 Volt a buffer connected to 5 Volt could be inserted for generating a higher control voltage.
2.3. Crystal Fig. 2-1: Input stage application diagram. A single crystal operates the DRX 8872C. Sample rate mismatches are corrected completely in the digital domain. The clock generated by the crystal is used as the system clock. A `divide by three'-block generates the sample clock for the ADC. There are two possible frequencies that can be used by the DRX 8872C. When using the 1st IF sampling technique, a 61 MHz crystal should be used. For 2nd IF sampling one should select a 55 MHz crystal. The next figure shows why.
2.2. AGC The DRX 8872C delivers a control signal for an amplifier in the tuner part of the system. The system controller controls a register that is used for a pulse train using a Pulse Width Modulator (PWM) circuit. 256 values can be distinguished. The SP7_SetAGCParams function of the API determines the way this register is controlled. By default, the maximum level is represented by all `1's and the minimum level is represented by all `0's. A low-pass RC filter connected to the AGC pin will filter the PWM signal, generating a stable analog signal for controlling the amplifier of the tuner. The bandwidth of this filter should be small enough to minimize the PWM-jitter on the control signal. The external AGC control is slow compared to the fast internal AGC. A filter bandwidth of 1 kHz is recommended for filtering the PWM-jitter.
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DRX 8872C
2nd IF Sampling
1st IF Sampling
Second down-conversion by external mixer + lowpass filter Energy Energy
Second down-conversion by subsampling first IF by internal ADC at 20.6 Mhz
18.3
(ADC sample frequency)
36.125
20.3
(ADC sample frequency)
36.125
Frequency (MHz)
Frequency (MHz)
Fig. 2-3: 1st or 2nd IF sampling
The API function SP7_SetSamplingMode has been defined to set the mode. Default 1st IF sampling is assumed. To generate 55 or 61 MHz, a third overtone crystal must be used. The fundamental tone must be filtered out using an LC network with a time constant defined by:
1 1 = ----------- , where = ------2f LC
with f=61 MHz for 1st IF sampling and f=55 MHz for baseband sampling. The application diagram shows the complete crystal circuitry, for example:
4.7H
4.7H
12 pF
15 pF
15 pF 61 MHz 1M
15pF
15pF
15pF 55 MHz 1M
1st IF Sampling
2nd IF Sampling
Fig. 2-4: Clocking circuitry for 1st IF or baseband sampling
A frequency mismatch of 100 ppm is allowed for the described crystals.
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DRX 8872C
2.4. Manufacturing Guidelines To maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the PCB within the footprint of the package corresponding to the exposed metal pad on the package, as shown in Fig. 2-5. 2.5. Lock Indication
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Two hardware lock indicators are available. They can be used for LED control as shown in Fig. 2-7.
150
150
Fig. 2-7: Lock indication LEDs
The lock indicator pins FEC_LCK and OFDM_LCK can also be put in two other modes: Fig. 2-5: Top layer solder mask
SAW filter select In this mode the two lock signal indicate whether the input signal has a 6, 7, or 8 MHz bandwidth. These pins can than be used directly to switch SAW filters in the tuner accordingly.
The dimensions of the PCB pad may be larger or smaller or even a different shape than the exposed metal pad but should have a clearance of at least 0.25 mm between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. To improve the thermal dissipation, a thermal via array should be made within the PCB pad area. The vias should be 0.3 mm in diameter at a pitch of between 1.0 and 1.2 mm and preferably with 1 oz copper via barrel plating.
User defined In this mode the value of the pins can be programmed via software by the host of the system. The API function SP7_LCKMode takes care of these settings.
Fig. 2-6: Thermal via array
For further information regarding the optimal usage of the Micronas exposed-pad QFP please refer to the Application Note "Surface Mount Assembly of Exposed-Pad QFP packages".
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DRX 8872C
2.5.1. Host Interface The DRX 8872C communicates via a serial protocol. The DRX 8872C only acts as a slave device. A write access consists of a `start' followed by the DRX 8872C device address, then the internal register address (2 bytes) and finally the data that needs to be written. During a read-access a repeated start should follow the internal register address definition, after which the data can be read.
Fig. 2-8: I2C_Write timing (NrOfBytes = 2)
Fig. 2-9: I2C_Read timing (NrOfBytes = 2)
The device address is either "1110000x" if the ASEL pin is tied low or "1110001x" if the ASEL pin is tied high.
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2.6. MPEG2 Output The DRX 8872C has a parallel or serial transport stream output. The system controller adjusts the MPEG2 clock (MCLK) in order to minimize the jitter on the gaps in between packets. The maximum jitter is limited to 20 s. There are several combinations of clock and data formats possible allowing flexible interfacing to MPEG2 decoders. The following figure shows the behavior of the MPEG2 output pins in parallel and serial mode.
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The DRX 8872C can output the parity bytes in between two transport stream packages or one can choose to have the transport stream packets output without parity bytes. The API function SP7_TSOutput lets the user control this. Furthermore, this function can be used to put the MPEG output pins in tristate mode. This can be useful in multistandard STBs where both satellite and terrestrial front-ends are connected to one common interface. No external multiplexer is needed.
XI
PAR MCLK
PAR MSTR
PAR MVAL
PAR MDAT
SYNC BYTE
BYTE 1
SER MCLK
SER MSTR
SER MVAL
SER MDAT
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
Fig. 2-10: MPEG2 TS output timing
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DRX 8872C
There are two versions of the microcode available: A basic version including only the code that will actually be uploaded to the chip and another version including a so-called symbol-table. The basic version is 16 kB and the extended code is about 20 kB. The symbol table includes a memory map of internal processor variables. When monitoring these variables, the symbol table tells the application which address to use. Most applications don't need to monitor the internal processor variables and then one only needs the basic code. In the API distribution, the source code for a tool called "SP7Strip" is included. This tool can strip the symbol table from the microcode as distributed. After start of the software application, uploading the microcode to the internal processors memory must be the first action. When uploading the originally distributed microcode, one should use the following function.
3. Application Programming Interface (API) For a description of the types used in the API prototypes, refer to Appendix A in Section 5. on page 37. Most functions in the API return a status (of type Status_t) that indicates whether the function completed successfully. The API assumes availability of low-level serial interface functions, as described in Appendix B.
3.1. Initialize System Settings The DRX 8872C integrates a processor. This processor performs the algorithms to synchronize and track the COFDM signal. The algorithms are described in microcode.
3.1.1. SP7_LoadMicrocode
Status_t SP7_LoadMicrocode ( ); pu16_t pu32_t mc_addr, version
Variable mc_addr version
Type pu16_t pu32_t
Description Memory address of the binary file containing the algorithms for the internal processor. Returns version of microcode uploaded.
For uploading the `stripped' version, the following function is available.
3.1.2. SP7_LoadImage
Status_t SP7_LoadImage ( u16_t pu8_t pu32_t image_size, image_addr, version
);
Variable image_size image_addr version
Type u16_t pu8_t pu32_t
Description Number of bytes to load (typically 16384). Memory address of the 16 kB stripped binary file containing the algorithms for the internal processor. Returns version of microcode uploaded.
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The processor inside the DRX 8872C needs to be given some basic information about the application in order to be able to automatically acquire lock. The first parameter is the sampling mode. The DRX 8872C supports 1st IF sampling as well as base-band sampling. All one needs to do is tell the processor which system clock frequency (crystal) and which input signal frequency - generally 36.125 MHz for 1st IF or 4.57 MHz for baseband sampling - is used. In combination with knowledge about whether the signal is mirrored or not, the chip will automatically calculate the correct settings for the internal sample-rate correction filters. The digital timing recovery enables the system to acquire lock when the system clock is within 500 ppm of the preprogrammed value.
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3.1.3. SP7_SetSamplingMode
Status_t SP7_SetSamplingMode ( u16_t u16_t Mirror_t SystemClockFrequency, SigInputFrequency, SigInputMirror
);
Variable SystemClockFrequency SigInputFrequency SigInputMirror
Type u16_t u16_t Mirror_t
Description Frequency of the crystal applied to the DRX 8872C, in kHz (e.g. set to 61000 when using a 61-MHz crystal). 16 bit integer number representing the center frequency of the COFDM signal that is applied to the DRX 8872C, in kHz (e.g. set to 36125 for 1st IF sampling). In case the input signal to the DRX 8872C is mirrored, depending on the number of down-conversion stages in the system, this can be indicated using this flag. The DRX 8872C will adjust automatic frequency correction algorithms accordingly.
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DRX 8872C
Depending on the tuner one uses, it is either preferred to have a slow AGC control or a fast feedback to changes on the incoming energy level. The type of control can be selected using the AGC control variable in the next API function. When not controlled by the internal processor, it is possible to adjust the level of the amplifier stages by changing the AGC-level variables as described in the next function.
3.1.4. SP7_SetAGCParams
Status_t SP7_SetAGCParams ( AGC_t Bool_t u16_t u16_t u16_t AGC_ctrl, AGC_SelectPin2, AGC_level1, AGC_level2, AGC_level3
);
Variable AGC_ctrl
Type AGC_t
Description Variable indicating type of control. AGC_OFF No control, the default levels will be applied. AGC_FAST Fast reaction to changes in energy level. In this mode the chip uses a hardwired AGC control function. AGC_SLOW Instead of the hardwired AGC functionality the internal processor controls the incoming energy level on symbol basis. AGC_INV By default, a positive control is used. With this setting this can be changed into a negative control. This is only possible in combination with AGC_SLOW. If one wants to negate the control in combination with AGC_FAST, one must use an external inverting component.
AGC_SelectPin2 AGC_level1 AGC_level2 AGC_level3
Bool_t u16_t u16_t u16_t
If TRUE, AGC is applied to the secondary PWM output (only DRX8872P). Unsigned integer indicating the default level of AGC1 when no control is applied to it. Unsigned integer indicating the default level of AGC2 when no control is applied to it. Unsigned integer indicating the default level of AGC3 when no control is applied to it.
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Upon power-on reset, all output pins are tri-stated to allow other demodulators (e.g. satellite or cable) to drive the TS signals. The output pins must be put in
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output mode using the following API function. The monitor-bus with real-time channel information is only available with the professional version.
3.1.5. SP7_SetOutputEnable
Status_t SP7_SetOutputEnable ( Bool_t Bool_t Bool_t MpegTS, MonitorBus, InterfacePins
);
Variable
MpegTS
Type
Bool_t
Description
Boolean indicating MPEG TS pin driver state. FALSE MPEG TS pins are tristated (default). TRUE MPEG TS pins are put in output mode.
MonitorBus
Bool_t
Boolean indicating Monitor bus pin driver state (MT8872P only). FALSE Monitor bus pins are tristated (default). TRUE Monitor bus pins are put in output mode.
InterfacePins
Bool_t
Boolean indicating pin driver state of OFDM_LCK, FEC_LCK, I2C2_EN, IRQN and SCL2 (DRX 8872C only). FALSE Pins are tristated. TRUE Pins are put in output mode.
The actual mode of the pins can be obtained using the following function.
3.1.6. SP7_GetOutputEnable
Status_t SP7_GetOutputEnable ( pBool_t pBool_t pBool_t MpegTS, MonitorBus, InterfacePins
);
Variable MpegTS
Type pBool_t
Description Boolean indicating MPEG TS pin driver state. FALSE MPEG TS pins are tristated (default). TRUE MPEG TS pins are in output mode.
MonitorBus
pBool_t
Boolean indicating Monitor bus pin driver state (MT8872P only). FALSE Monitor bus pins are tristated (default). TRUE Monitor bus pins are in output mode.
InterfacePins
pBool_t
Boolean indicating pin driver state of OFDM_LCK, FEC_LCK, I2C2_EN, IRQN and SCL2 (DRX 8872C only). FALSE Pins are tristated. TRUE Pins are in output mode.
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DRX 8872C
either be disabled or a continuous clock can be chosen. When using the continuous clock the MVAL signal can be used to indicate non-valid data.
The MPEG Transport Stream interface clocking can be configured. When no valid data bytes are output (the parity bytes in between two packets or during the remaining gap in the guard interval) the MCLK pin can
3.1.7. SP7_TSOutput
Status_t SP7_TSOutput ( ); Bool_t Bool_t Parity, SuppressClock
Variable Parity SuppressClock
Type Bool_t Bool_t
Description If TRUE, The Reed Solomon parity bytes will be output in between two transport stream packets. If TRUE, the MCLK pin is suppressed when no valid data is output (parity bytes and gaps between packets or during guard interval).
The last pins that can be configured are the OFDM_LCK and the FEC_LCK pins.
3.1.8. SP7_LCKMode
Status_t SP7_LCKMode ( ); LCK_t LCK_t OFDM_LCK_Ctrl, FEC_LCK_Ctrl
Variable OFDM_LCK_Ctrl
Type LCK_t
Description Parameter indicating use of the OFDM LCK pin. LCK_INDICATOR The OFDM_LCK pin reflects the locking state of the COFDM demodulator part of the chip. LCK_SAW_8 The OFDM_LCK pin will go high if an 8 MHz SAW filter must be selected, otherwise (for 7 or 6 MHz bandwidths) it will be low. LCK_SAW_7 The OFDM_LCK pin will go high if an 7 or 8 MHz SAW filter must be selected, otherwise (for 6 MHz bandwidths) it will be low. LCK_UIO_0 The OFDM_LCK pin will be always low. LCK_UIO_1 The OFDM_LCK pin will be always high.
FEC_LCK_Ctrl
LCK_t
Parameter indicating use of the FEC LCK pin. LCK_INDICATOR The FEC_LCK pin reflects the locking state of the FEC error correction part of the chip. LCK_SAW_8 The FEC_LCK pin will be high if an 8 MHz SAW filter must be selected, otherwise (for 7 or 6 MHz bandwidths) it will be low. LCK_SAW_7 The FEC_LCK pin will go high if an 7 or 8 MHz SAW filter must be selected, otherwise (for 6 MHz bandwidths) it will be low. LCK_UIO_0 The FEC_LCK pin will be always low. LCK_UIO_1 The FEC_LCK pin will be always high.
For function SP7_LCKMode to work correctly, the OFDM_LCK and FEC_LCK pins must have been configured for output, by using the function SP7_SetOutputEnable.
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3.2. Setup Signal Parameters All hardware related parameters have been set now. The next step is to configure the system for the incoming signal. In the application one can either let the DRX 8872C detect all settings automatically or one can choose to pre-program some parameters in case they are known. This can improve locking speed. The
DATA SHEET
functions SP7_GetChannelParams and SP7_SetChannelParams relate to channel parameters like frequency offsets and signal bandwidth. The SP7_GetOfdmParams and SP7_SetOfdmParams functions relate to the COFDM symbol parameters like code rate, FFT size etc. The parameters that are set up with these functions are not programmed until the chip is started using the SP7_Start function.
3.2.1. SP7_SetChannelParams
Status_t SP7_SetChannelParams( s16_t s16_t Bandwidth_t Mirror_t Cls_t SysFrequencyOffset, SigFrequencyOffset, SigBandwidth, SigMirror, SigClass
);
Variable SysFrequencyOffset
Type s16_t
Description Signed integer number indicating the known system clock frequency mismatch in kHz, relative to the value that was set with SP7_SetSamplingMode. Signed integer number indicating the known signal frequency mismatch in kHz. If unknown, set to zero. The bandwidth can be programmed. BANDWIDTH_6MHZ 6 MHz Channel. BANDWIDTH_7MHZ 7 MHz Channel. BANDWIDTH_8MHZ 8 MHz Channel (default).
SigFrequencyOffset SigBandwidth
s16_t Bandwidth_t
SigMirror
Mirror_t
This parameter indicates whether the spectrum is mirrored. MIRRORED Spectrum is mirrored. NORMAL Spectrum is normal. AUTO Detect automatically.
SigClass
Cls_t
This parameter sets the channel classification. CLS_GAUSS Gaussian noise. CLS_HEAVYGAUSS Heavy Gaussian noise. CLS_COCHANNEL Co-channel. CLS_STATIC Static echo. CLS_MOVING Moving echo. CLS_ZERODB Zero dB echo. AUTO Detect automatically.
Next to programming the values, the measured values can be obtained from the system.
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3.2.2. SP7_GetChannelParams
Status_t SP7_GetChannelParams( ps16_t SysFrequencyOffset, ps16_t SigFrequencyOffset, pBandwidth_tSigBandwidth, pMirror_t SigMirror, pCls_t SigClass
);
Variable SysFrequencyOffset FrequencyOffset
Type ps16_t ps16_t
Description Signed integer number indicating the system clock frequency mismatch in kHz, relative to the value that was set with SP7_SetSamplingMode. Signed integer number indicating the signal frequency mismatch in kHz. Depending on the step-size of the tuner, the mismatch can be minimized by re-tuning. The bandwidth is reported. This returns either a default value or the value that was set by a previous call of SP7_SetChannelParams. BANDWIDTH_6MHZ 6 MHz Channel. BANDWIDTH_7MHZ 7 MHz Channel. BANDWIDTH_8MHZ 8 MHz Channel.
SigBandwidth
pBandwidth_t
SigMirror
pMirror_t
This parameter indicates whether the spectrum is mirrored. MIRRORED Spectrum is mirrored. NORMAL Spectrum is normal.
SigClass
pCls_t
The channel classification is reported. CLS_GAUSS Gaussian noise. CLS_HEAVYGAUSS Heavy Gaussian noise. CLS_COCHANNEL Co-channel. CLS_STATIC Static echo. CLS_MOVING Moving echo. CLS_ZERODB Zero dB echo.
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The mode of the COFDM signal path is being transmitted using the TPS carriers can be detected automatically. The information can be obtained by using the SP7_GetOfdmParams function and the system can be told to use a specific mode using the SP7_SetOfdmParams API function.
DATA SHEET
3.2.3. SP7_SetOfdmParams
Status_t SP7_SetOfdmParams ( Mode_t Guard_t Const_t Hier_t Prior_t Rate_t Mode, Guard, Constellation, Hierarchy, Priority, CodeRate
);
Variable Mode
Type Mode_t
Description MODE_2K 8k Mode. MODE_8K 2k Mode. AUTO Detect automatically.
Guard
Guard_t
GUARD_32 1/32nd Guard interval. GUARD_16 1/16th Guard interval. GUARD_8 1/8th Guard interval. GUARD_4 1/4th Guard interval. AUTO Detect automatically.
Constellation
Const_t
CONST_QPSK QPSK constellation. CONST_QAM16 QAM16 constellation. CONST_QAM64 QAM64 constellation. AUTO Detect automatically.
Hierarchy
Hier_t
HIER_NONHIER No hierarchical transmission. HIER_ALPHA_1 Hierarchical transmission, is one. HIER_ALPHA_2 Hierarchical transmission, is two. HIER_ALPHA_4 Hierarchical transmission, is four. AUTO Detect automatically.
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Variable Priority
Type Prior_t
Description In case of hierarchical transmission: PRIOR_LOW Low priority. PRIOR_HIGH High priority.
CodeRate
Rate_t
RATE_1_2 Code rate 1/2nd. RATE_2_3 Code rate 2/3rd. RATE_3_4 Code rate 3/4th. RATE_5_6 Code rate 5/6th. RATE_7_8 Code rate 7/8th. AUTO Detect automatically.
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3.2.4. SP7_GetOfdmParams
Status_t SP7_GetOfdmParams ( pMode_t pGuard_t pConst_t pHier_t pPrior_t pRate_t Mode, Guard, Constellation, Hierarchy, Priority, CodeRate
DATA SHEET
);
Variable Mode
Type pMode_t
Description MODE_2K 8k Mode. MODE_8K 2k Mode.
Guard
pGuard_t
GUARD_32 1/32nd Guard interval. GUARD_16 1/16th Guard interval. GUARD_8 1/8th Guard interval. GUARD_4 1/4th Guard interval.
Constellation
pConst_t
CONST_QPSK QPSK constellation. CONST_QAM16 QAM16 constellation. CONST_QAM64 QAM64 constellation.
Hierarchy
pHier_t
HIER_NONHIER No hierarchical transmission. HIER_ALPHA_1 Hierarchical transmission, is one. HIER_ALPHA_2 Hierarchical transmission, is two. HIER_ALPHA_4 Hierarchical transmission, is four.
Priority
pPrior_t
In case of hierarchical transmission: PRIOR_LOW Low priority. PRIOR_HIGH High priority.
CodeRate
pRate_t
RATE_1_2 Code rate 1/2nd. RATE_2_3 Code rate 2/3rd. RATE_3_4 Code rate 3/4th. RATE_5_6 Code rate 5/6th. RATE_7_8 Code rate 7/8th.
The processor now knows all it needs to know and one can start to acquire lock.
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The SP7_Start function will start the internal processor and the demodulation process will start, making use of the settings that were applied using the previously described API functions.
3.2.5. SP7_Start
Status_t SP7_Start ( void );
If an COFDM signal is applied to the input of the DRX 8872C, the system will start to acquire lock.
3.3. Selecting Channels In order to get a correct COFDM signal, the tuner in front of the demodulator must be programmed to the right frequency. The DRX 8872C has been tested in combination with many tuners. Each tuner has its own specifications. The frequency range, step-size and charge pump settings vary per tuner. Also the optimal AGC setting can be different per tuner type. To ease the work of the customers some API functions have been made available. When using one of the tested tuner types the optimal settings will automatically be chosen. To initialize the API with the settings of the tuner that is currently in use, first the SP7_Tune_init function should be called.
3.3.1. SP7_Tune_init
Status_t SP7_Tune_init ( u16_t tune_type );
Variable tune_type
Type u16_t
Description Variable indicating which tuner is used. Refer to source code for list of tuners supported.
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The function SP7_Tune_properties can be called to retrieve the parameters of the tuner that is used (if known by the API). The output of this function can be used when setting up the system. In this case the user
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does not have to worry about whether the tuner outputs its signal at 1st or 2nd IF, whether the signal is mirrored or not and what the preferred AGC settings should be.
3.3.2. SP7_Tune_properties
Status_t SP7_Tune_properties ( pu8_t* pu32_t pu32_t pu16_t pu16_t pMirror_t pAGC_t pu16_t Name, FrequencyMin, FrequencyMax, FrequencyStep, FrequencyOut, FrequencyMirror, AgcType, Agc_level3
);
Variable Name FrequencyMin FrequencyMax FrequencyStep FrequencyOut FrequencyMirror AgcType AGC_level3
Type pu8_t* pu32_t pu32_t pu16_t pu16_t pMirror_t pAGC_t pu16_t
Description Returns the name of the tuner. Only relevant when more than one tuner is taken into account during compilation, for instance in applications like Signal Spyder. Minimum available frequency for this tuner, in kHz. Maximum supported frequency for this tuner, in kHz. RF frequency step-size for this tuner. Output frequency of this tuner. Variable indicating whether the output of this tuner is mirrored or not. Variable indicating the preferred AGC setting for the tuner currently used. Integer value indicating the optimum PGA level in combination with the tuner currently used.
Next to acquiring information related to the type of tuner used, the API supports functions that will actually program the tuner to the desired frequency with the appropriate settings.
3.3.3. SP7_Tune_program
Status_t SP7_Tune_program ( u32_t F );
Variable F
Type u32_t
Description Frequency to which the tuner should be programmed, in kHz.
In case communication with the tuner fails, the exact error status can be read back using the following function.
3.3.4. SP7_Tune_error
u16_t SP7_Tune_error ( void );
Returns number that represents an error code.
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Since the tuner has a finite step-size it will not be possible to exactly program the tuner to the desired frequency. The next function reports the frequency to which the tuner was actually programmed.
3.3.5. SP7_Tune_get_freq
u32_t SP7_Tune_get_freq ( void );
Returns exact frequency to which the tuner was programmed, in kHz. When not using the given tuner programming functions, one needs to calculate the tuner settings and generate the command string (5 bytes) using the tuner specification. The DRX 8872C supports a gated clockline to the tuner. This means that the tuner is not connected directly to the serial bus but via the demodulator and an external analog switch. If connected in this way, the serial lines towards the tuner can be kept quiet during normal operation to minimize noise on the PLL inside the tuner. To select a channel first the connection to the tuner must be enabled, then the tuner specific settings must be applied (5 I2C byte accesses), and finally the connection to the tuner can be closed again. The following API function has been defined for opening and closing this port.
3.3.6. SP7_EnableTunerAccess
Status_t SP7_EnableTunerAccess( Bool_t TunerAccess );
Variable TunerAccess
Type Bool_t
Description If TRUE, the secondary protocol port is opened for programming the tuner.
After programming the tuner, the chip will start to acquire lock. It is of course important to know whether
the chip has acquired lock. For this purpose the SP7_LockingStatus function has been defined.
3.3.7. SP7_LockingStatus
Status_t SP7_LockingStatus ( pBool_t Locked );
Variable Locked
Type pBool_t
Description If TRUE, chip has acquired lock.
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3.4. Monitor Channel Quality The channel estimator unit of the DRX 8872C performs a signal to noise measurement on the constellation diagram. The output of this calculation can be
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retrieved using the API function SP7_GetSN. From this measurement, a MER is also derived. The MER is calculated using the deviation of the continual pilots and is therefore an indication, not an exact value.
3.4.1. SP7_GetSN
Status_t SP7_GetSN ( ); pu16_t pu16_t SN, MER
Variable SN MER
Type pu16_t pu16_t
Description Integer number indicating the S/N ratio detected at the input of the demapper, in steps of 1/10th of a dB. Integer number indicating the MER, in steps of 1/10th of a dB.
The S/N ratio gives a very good indication of the channel quality, independent of the mode of the signal. For a graphical feedback one can use the constellation
diagram. A slow non-real-time diagram can be built using the following function.
3.4.2. SP7_GetConstellationDiagram
Status_t SP7_GetConstellationDiagram ( ps16_t ps16_t ); Real, Imag
Variable Real Imag
Type ps16_t ps16_t
Description Real part of the constellation point. The values 256/-256 correspond to the energy level of the pilots of the COFDM symbol. The maximum values range from -512 to +511. Imaginary part of the constellation point.
A more common way to give an indication of the signal quality is to look at the BER values. This also allows
for comparison of the quality of the DRX 8872C to the ETS300744 DVB-T standard.
3.4.3. SP7_GetBer
Status_t GetBer ( pu32_t pu32_t pu32_t PreViterbi, PostViterbi, PacketError
);
Variable PreViterbi PostViterbi PacketError
Type pu32_t pu32_t pu16_t
Description Bit error rate (BER) before error correction, with a scale of 1e-6. BER after Viterbi decoder, with a scale of 1e-6. A value of 200 corresponds to a BER of 2e-4, the so-called QEF level. Counter indicating the number of packet errors after Reed Solomon decoding.
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Next to using the previously described function SP7_GetOfdmParams to obtain information on the incoming COFDM signal, the TPS information contained in the COFDM signal can be read using the following API function.
3.4.4. SP7_GetTpsInfo
Status_t SP7_GetTpsInfo ( pMode_t pGuard_t pConst_t pHier_t pRate_t pRate_t pTpsFrame_t pu8_t pBool_t pu16_t TpsMode, TpsGuard, TpsConstellation, TpsHierarchy, TpsHiRate, TpsLoRate, TpsFrame, TpsLength, TpsCellIdRdy, TpsCellId
);
Variable
Type
Description
TPSMode TpsGuard TpsConstellation TpsHierarchy TpsHiRate TpsLoRate TpsFrame TpsLength TpsCellIdRdy TpsCellId
pMode_t pGuard_t pConst_t pHier_t pRate_t pRate_t pTpsFrame_ t pu8_t pBool_t pu16_t
Variable indicating the mode as described in the TPS parameters. Guard interval length as described in the TPS parameters. Constellation diagram depth as described in the TPS parameters. Level of Hierarchy as described in the TPS parameters. High priority code rate. Low priority code rate. Frame number. Integer number indicating the length of the TPS Frame. Flag indicating that the returned TpsCellId is valid. 16-Bit received Cell identifier.
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3.5. Commands and other Useful Functions Next to the application specific function as described in the previous paragraphs, also some low level functions are available. Other API functions also make use of these low-level functions themselves. 3.5.4. SP7_Restart
Status_t SP7_Restart
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( void );
Just restart algorithm, with current register settings and algorithm constants.
3.5.5. SP7_Halt 3.5.1. SP7_Reboot
Status_t SP7_Reboot ( void ); Status_t SP7_Halt ( void );
Reinstall all register settings, which were stored during the first start-up, and reload all default algorithm constants. Starts demodulator.
Halts the current state of the DRX 8872C. This is a useful function when debugging your application. The DRX 8872C remains executing commands.
3.5.6. SP7_Nop 3.5.2. SP7_Reset
Status_t SP7_Reset ( void ); Status_t SP7_Nop ( void );
Do nothing, but generate an interrupt on completion. The next two functions enable different algorithm constants to be programmed to influence the behavior of the algorithm. Also the state of all microcode variables can be queried. Reading and writing microcode variables is done "atomically".
Reinstalls all register settings, does not reinitialize algorithm constants, such that user patches remain active. Restarts algorithm.
3.5.3. SP7_SysReset
Status_t SP7_SysReset ( void );
First resets all internal hardware, then behaves like SP7_Reset.
3.5.7. SP7_Wreg
Status_t SP7_Wreg ( ); u16_t u16_t Reg, Data
Variable Reg Data
Type u16_t u16_t
Description Address of register that needs to be written. New value for the register.
3.5.8. SP7_Rreg
Status_t SP7_Rreg ( ); u16_t pu16_t Reg, Data
Variable
Type
Description
Reg Data
u16_t pu16_t
Address of register that needs to be read. Returns value of the register.
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3.5.9. SP7_Wvar
Status_t SP7_Wvar ( u16_t u16_t pu16_t Adr, Wnr, Wdata
);
Variable Adr Wnr Wdata
Type u16_t u16_t pu16_t
Description Address of (processor) variable that needs to be written. Number of words that must be written. New value for the variable (array).
3.5.10.SP7_Rvar
Status_t SP7_Rvar ( u16_t u16_t pu16_t Adr, Rnr, Rdata
);
Variable Adr Rnr Rdata
Type u16_t u16_t pu16_t
Description Address of (processor) variable that needs to be read. Number of words that must be read. Returns value of the variable (array).
3.6. Interrupts and Events The DRX 8872C has an IRQN output which can generate an interrupt to the host to trigger an event. Two types of interrupts are reported back to the host: "Command Completion" interrupt, and "Algorithm Event" interrupt. The API uses the "Command Completion" interrupt internally. The "Algorithm Event" interrupt is of special interest to the application.
3.6.1. SP7_ReadIrq
Status_t SP7_ReadIrq ( void );
Reads the interrupt status register, such that new interrupts may occur.
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On any occasion, the event register may be read to see if the DRX 8872C algorithm generated an event. If an event occurs, an interrupt is also generated. Thus if the interrupt line is used, it makes sense to only read the event register on an interrupt.
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3.6.2. SP7_PollEvent
Status_t SP7_PollEvent ( pu16_t OccurredEvents );
Reads the event register and sets bits in OccurredEvents according to the events that occurred since the last read.
Variable OccurredEvents
Type pu16_t
Description The following event bits may be set: SP7_EV_ERR Algorithm restarted (lock lost). SP7_EV_SIG Algorithm detected a DVB-T signal, lock will follow soon. SP7_EV_LCK Algorithm acquired a lock on the DVB-T signal and is demodulating now. SP7_EV_VBER A new Pre-Viterbi BER measurement is ready to be read. SP7_EV_RBER A new Post-Viterbi BER measurement (or packet error count) is ready to be read. SP7_EV_SN A new SN and MER measurement is ready to be read. SP7_EV_TPS A new TPS frame is ready to be read.
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4. Specifications 4.1. Outline Dimensions
Fig. 4-1: PTQFP80-1: Plastic Thin Quad Flat Package, 80 leads, 12 x 12 x 1.0 mm3, exposed die pad Ordering code: PL
Weight approximately 1.0 g
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4.2. Pin Connections and Short Descriptions
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Pin No.
Pin Name
Type
Connection
(If not used)
Short Description
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
VDDL VSS VSS ASEL VSS AGC VSSA VREF INM INP VSSA VDDA VRM VDDA VSSA VRH VRL VSSA VSSA VDDH SCL SDA VSS TCLK TDI TMS TDO
P GND GND I GND O GND P I I GND P P P GND P P GND GND P O I/O GND I I I O 10 k pull-up to VDDH 10 k pull-up to VDDH 10 k pull-up to VDDH
Digital core supply 2.5 volt Digital ground Digital ground Serial interface address select Digital ground Automatic gain output Analog ground Bias circuitry reference voltage decoupling pin Symmetrical IF or Base band input Symmetrical IF or Base band input Analog ground Analog supply 2.5V External middle rail reference Analog supply 2.5V Analog ground High reference Voltage Low reference Voltage Analog ground Analog ground Digital IO supply 3.3V Clock line for serial protocol Data line for serial protocol Digital ground JTAG test clock JTAG test data in JTAG test mode select JTAG test data out
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Pin No.
Pin Name
Type
Connection
(If not used)
Short Description
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58
VDDL VSS VDDH VSS VSS VSS VSS IRQN VDDL VSS SCL2 MERR MSTRT VDDL VDDH MVAL MCLK MD_7 VSS MD_6 MD_5 MD_4 VDDH VSS MD_3 MD_2 MD_1 MD_0 OFDM_LCK VSS VDDH
P GND P GND GND GND GND O P GND O O O P P O O O GND O O O P GND O O O O O GND P
Core supply 2.5V Digital ground Digital IO supply 3.3V Digital ground Digital ground Digital ground Digital ground Interrupt to host (active low) Digital core supply 2.5V Digital ground Secondary serial interface clock MPEG packet error flag Frame start flag Digital core supply 2.5V Digital IO supply 3.3V MPEG2 data valid signal MPEG2 clock MPEG2 data output Digital ground MPEG2 data output MPEG2 data output MPEG2 data output Digital IO supply 3.3V Digital ground MPEG2 data output MPEG2 data output MPEG2 data output MPEG2 data output/ MPEG serial data output Lock signal indicating valid OFDM signal Digital ground Digital IO supply 3.3V
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DATA SHEET
Pin No.
Pin Name
Type
Connection
(If not used)
Short Description
59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
FEC_LCK NC VDDL I2C_EN VSS VSS VSS VSS VSS VSS VDDH VSS XO NC XI VSS XPD VDDL VSS IREFSEL RST VSS
O LV P O GND GND GND GND GND GND P GND O
Lock signal indicating FEC lock Should be left open Digital core supply 2.5V Secondary serial interface enable line Digital ground Digital ground Digital ground Digital ground Digital ground Digital ground Digital IO supply 3.3V Digital ground Crystal oscillator output Internally not connected
I GND I P GND I I GND
Crystal oscillator input Digital ground Power down mode low = oscillator active Digital core supply 2.5V Digital ground Internal voltage reference select high = enable Reset signal (active low) Digital ground
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4.3. Pin Configurations
VSS MD_3 MD_2 MD_1 MD_0 OFDM_LCK VSS VDDH FEC_LCK NC
VDDH MD_4 MD_5 MD_6 VSS MD_7 MCLK MVAL VDDH VDDL
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VDDL I2C_EN VSS VSS VSS VSS VSS VSS VDDH VSS XO NC XI VSS XPD VDDL VSS IREFSEL RST VSS 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 MSTRT MERR SCL2 VSS VDDL IRQN VSS VSS VSS VSS VDDH VSS VDDL TDO TMS TDI TCLK VSS SDA SCL
DRX 8872C
31 30 29 28 27 26 25 24 23 22 21
VDDL VSS VSS ASEL VSS AGC VSSA VREF INM INP
VDDH VSSA VSSA VRL VRH VSSA VDDA VRM VDDA VSSA
Fig. 4-1: 80-pin PTQFP package
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4.4. Electrical Characteristics Abbreviations tbd = to be defined vacant = not applicable positive current values mean current flowing into the chip
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4.4.1. Absolute Maximum Ratings Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these conditions is not implied. Exposure to absolute maximum rating conditions for extended periods will affect device reliability. This device contains circuitry to protect the inputs and outputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than absolute maximum-rated voltages to this high-impedance circuit. All voltages listed are referenced to ground (list voltages = 0 V) except where noted. All GND pins must be connected to a low-resistive ground plane close to the IC. Table 4-1: Absolute Maximum Ratings Symbol Parameter Pin Name Min. TA TS PMAX VDDA VDDL VDDH VSUP VI analgoue VI digital Ambient Operating Temperature Storage Temperature Maximum Power Dissipation Analog supply Digital core supply Digital IO supply Voltage differences within supply domains (VDDA - VDDL) Analog Input Voltage Digital Input Voltage - - - VDDA VDDL VDDH - INM; INP; AGC; VRH; VRL ASEL; SDA; SCL; TDI; TMS; IRQN; XI, XPD, IREFSEL, RST 0 -40 - -0.3 -0.3 -0.3 -0.2 -0.3 -0.3 Limit Values Max. 701) 125 1.1 3.0 3.0 3.6 0.2 VDDA + 0.3 VDDH + 0.3 C C W V V V V V V Unit
1)
A thermally-optimized board layout is recommended; refer to the application note "Surface Mount Assembly of Exposed-Pad QFP packages".
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4.4.2. Recommended Operating Conditions Functional operation of the device beyond those indicated in the "Recommended Operating Conditions/Characteristics" is not implied and may result in unpredictable behavior, reduce reliability and lifetime of the device. All voltages listed are referenced to ground (list voltages = 0 V) except where noted. All GND pins must be connected to a low-resistive ground plane close to the IC. Do not insert the device into a live socket. Instead, apply power by switching on the external power supply. For power up/down sequences, see the instructions in section xxx of this document.
4.4.2.1. General Recommended Operating Conditions Symbol Parameter Pin Name Min. TA PMAX VDDA1 VDDL VDDH
1)
Limit Values Typ. Max. 701) - 2.5 2.5 3.3 1.1 2.7 2.7 3.6
Unit
Ambient Operating Temperature Maximum Power Dissipation Analog Supply Digital Core Supply Digital IO Supply
- - VDDA VDDL VDDH
0 - 2.3 2.3 3.0
C W V V V
A thermally-optimized board layout is recommended; refer to the application note "Surface Mount Assembly of Exposed-Pad QFP packages"
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4.4.3. Characteristics 4.4.3.1. DC Electrical Characteristics
Symbol VDDLL VDDAA VDDHH IDDL IDDA IDDH Parameter Digital Core Supply Analog Supply Digital IO Supply Digital Core Supply Current Analog Supply Current Digital Io Supply Current Pin Name VDDL VDDA VDDH VDDL VDDA VDDH Min. 2.3 2.3 3.0 Typ. 2.5 2.5 3.3 380 15 32 Max. 2.7 2.7 3.6 420 25 40 Unit V V V mA mA mA
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Test Conditions
- - -
4.4.3.2. Temperature Ratings
Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions
TJ TA TS TC
Junction Temperature Ambient Temperature Range Storage Temperature Range Case Temperature Range
- - - -
- 0 -40 -
- - - -
125 70 125 110
C C C C
4.4.3.3. ADC Parameters
Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions
VDDA Panalog (INM-INP) VRH VRL Rin Cin VCM
ADC Power Supply Analog Power Consumption Input Voltage Swing High Voltage Reference Low Voltage Reference Input Impedance Input Capacitance Common Mode
VDDA
2.3 -
2.5 50 1.2 1.6 0.85 200 2.5 1.2
2.7 70 - 1.7 - - - 1.35
V mW V V V pF V
INM, INP VRH VRL INM, INP INM, INP VRM
0.5 - 0.7 - - 1.0
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5. Appendix A - API Data Types For ease of porting the library across different operating systems and platforms, basic data types have been defined for 8-bit, 16-bit and 32-bit signed and unsigned integers. These data type definitions are valid for most 32-bit platforms. When porting the API to a 16-bit or 8-bit platform, you may need to redefine a few of these data types. Additionally, chip-specific data types are defined. All data types are defined in the file "SP7_Type.h"
5.1. Basic Data Types
(p)u8_t (p)s8_t (p)u16_t (p)s16_t (p)u32_t (p)s32_t (p)Bool_t
(pointer to) unsigned 8-bit integer value: 0...255 (pointer to) signed 8-bit integer value: -128...127 (pointer to) unsigned 16-bit integer value: 0...65,535 (pointer to) signed 16-bit integer value: -32,768...32,767 (pointer to) unsigned 32-bit integer value: 0...4,294,967,295 (pointer to) signed 32-bit integer value: -2,147,483,648...2,147,483,647 (pointer to) Boolean value: TRUE, FALSE
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5.2. Chip-specific Data Types
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(p)AGC_t (p)Bandwidth_t (p)Cls_t
(pointer to) AGC control data-type value: AGC_OFF, AGC_FAST, AGC_SLOW, AGC_INV (pointer to) bandwidth data type value: AUTO, BANDWIDTH_8MHZ, BANDWIDTH_7MHZ, BANDWIDTH_6MHZ (pointer to) channel classification data-type value: AUTO, CLS_GAUSS, CLS_HEAVYGAUSS, CLS_COCHANNEL, CLS_STATIC, CLS_MOVING, CLS_ZERODB (pointer to) constellation data-type value: AUTO, CONST_QPSK, CONST_QAM16, CONST_QAM64 (pointer to) guard data-type value: AUTO, GUARD_32, GUARD_16, GUARD_8, GUARD_4 (pointer to) hierarcy data-type value: AUTO, HIER_NONHIER, HIER_ALPHA_1, HIER_ALPHA_2, HIER_ALPHA_4 (pointer to) LCK pin usage data-type value: LCK_UIO_0, LCK_UIO_1, LCK_INDICATOR, LCK_SAW_8, LCK_SAW_7 (pointer to) mirrored signal data-type value: AUTO, NORMAL, MIRROR (pointer to) mode data-type value: AUTO, MODE_2K, MODE_8K (pointer to) priority data-type value: PRIOR_HIGH, PRIOR_LOW (pointer to) code rate data-type value: AUTO, RATE_1_2, RATE_2_3, RATE_3_4, RATE_5_6, RATE_7_8 (pointer to) NIM function call result status value: STS_OK, STS_BUSY, STS_INVALID_ARG, STS_ERROR (pointer to) TPS frame number data-type value: TPS_FRAME_1, TPS_FRAME_2, TPS_FRAME_3, TPS_FRAME_4
(p)Const_t (p)Guard_t (p)Hier_t (p)LCK_t (p)Mirror_t (p)Mode_t (p)Prior_t (p)Rate_t (p)Status_t (p)TpsFrame_t
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6.2. Other platforms The API assumes that the following two functions are made available to read and write registers inside the DRX 8872C:
6. Appendix B - API Required Platform Functions The API interfaces with the DRX 8872C via a serial protocol. The implementation of the serial protocol is platform dependent. If your platform is a PC running Microsoft Windows 98, 2000, NT, or XP you can use serial interface functions as supplied that make use of the Micronas proprietary serial driver that implements serial access via a parallel port. Refer to section 6.1. For other platforms, you will have to write your own serial access functionality. Refer to Section 6.2.
Status_t SP7_I2C_Write( u16_t NrOfWbytes, pu8_t Wdata ) Status_t SP7_I2C_Read ( u16_t NrOfWBytes, pu8_t Wdata, u16_t NrOfRbytes, pu8_t Rdata )
The SP7_I2C_Write and SP7_I2C_Read functions must be implemented using the available serial functionality of the specific platform. The functions must be created in the file "SP7_I2c.c"'. Below, the requirements for these functions are described in detail. After these serial functions have been implemented, use the supplied file "i2ctest.c" to verify the implementation.
6.1. PC Platforms Running Windows 98, NT, 2000, and XP If you want to use the Micronas serial driver for serial access via a parallel port, do the following: 1. Install the Signal Spyder application (as supplied on the CD). Refer to Signal Spyder manual for instructions. In file "SP7_Conf.h", make sure that the following definition is enabled:
GHILQH 63B,&B63$6(
By default, this line is commented out. 2. Compile the API and the supplied file "i2ctest.c" and link them into an executable "i2ctest.exe". 3. Make sure that the file "I2CECP.DLL" (as provided in the Signal Spyder distribution) is in the search path. 4. Test the serial access by running "i2ctest.exe".
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6.2.1. SP7_I2C_Write Writing data to the DRX8872C involves the following steps: 1. Generate I2C start condition. 2. Write the bytes pointed to by :GDWD. Wdata will include the device address (0xE0 or 0xE2 for the DRX 8872C and 0xC0 for tuner part). The number of bytes that must be written is 1U2I:%\WHV. 3. Generate I2C stop condition Or graphically:
DATA SHEET
Fig. 6-1: I2C_Write timing (in this case NrOfWbytes=5).
6.2.2. SP7_I2C_Read Reading data from the DRX8872C involves the following steps: 1. Generate I2C start condition. 2. Write the bytes pointed to by :GDWD. The number of bytes that must be written is 1U2I:%\WHV. This is used to setup the device address and the internal address of the register that is going to be programmed. Before the actual read operation starts, the device address needs to be setup again. Therefore the last byte of the :GDWD array needs to be preceded by a start operation as indicated in the picture below. 3. Read 1U2I5%\WHV consecutive data-bytes (minimum of 2 bytes) into the memory location pointed to by 5GDWD. 4. Generate I2C stop condition. Or graphically:
Fig. 6-2: I2C_Read timing (in this case NrOfWbytes=4, NrOfRbytes=2).
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6.2.3. I2ctest.c The API distribution includes the source file "i2ctest.c". The program "I2Ctest" can be used to test the functionality of your "SP7_I2c.c" implementation. Simply compile and link these two programs for your platform and then run the code. The program will return 0 (zero) if the test was successful, otherwise -1 if any error occurred. Additionally, if you define VERBOSE during compilation, the program will also show results using "printf" calls. In this file, the I2C address is set at 0xE0. Depending on your DRX8872C configuration, you may need to change this I2C address to 0xE2.
/****************************************************************************** * FILENAME: i2ctest.c * * DESCRIPTION: * Test the customer provided SP7_I2C_Read and SP7_I2C_Write functions * * This program does the following: * * - Switch off system controller * - Write test pattern in SC_INFO0 register * - Write different test pattern in SC_INFO1 register * - Read from SC_INFO0 register * - Check if read-back value from SC_INFO0 equals written value * * By default, it uses I2C address 0xE0. To use 0xE2 redefine I2C_ADDR in i2ctest.c. * * By default, it uses stdout to print the test results. * This can be switched off by removing the line: * #define VERBOSE * * This program only uses the SP7_I2C_Read and SP7_I2C_Write functions in the file SP7_I2C.c. * * USAGE: * Link with SP7_I2C.c to separate executable * Define VERBOSE to output test results to stdout * * NOTES: * $(c) 2003 Micronas GmbH. All rights reserved. * * This software and related documentation (the 'Software') are intellectual * property owned by Micronas and are copyright of Micronas, unless specifically * noted otherwise. * * Any use of the Software is permitted only pursuant to the terms of the * license agreement, if any, which accompanies, is included with or applicable * to the Software ('License Agreement') or upon express written consent of * Micronas. Any copying, reproduction or redistribution of the Software in * whole or in part by any means not in accordance with the License Agreement * or as agreed in writing by Micronas is expressly prohibited. * * THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE * LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE * IS DELIVERED 'AS IS' AND MICRONAS HEREBY DISCLAIMS ALL WARRANTIES AND * CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES * AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT * ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL * PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY * TO USE THE SOFTWARE. * * IN NO EVENT SHALL MICRONAS BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, * PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, * DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS * INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE * INABILITY TO USE THE SOFTWARE, EVEN IF MICRONAS HAS BEEN ADVISED OF THE * POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM * MICRONAS' NEGLIGENCE. $ * ******************************************************************************/ #include "SP7.h" #include "SP7_Regs.h"
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/* Change this I2C address to 0xE2 if ASEL pin of demodulator chip is high */ #define I2C_ADDR 0xE0 /* Remove next line if printf's must be suppressed */ #define VERBOSE #ifdef VERBOSE #include #endif /****************************************************************************** * Write a value to a register *****************************************************************************/ Status_t WriteReg (u16_t Reg, u16_t Data) { u8_t Wdata[5]; Status_t rc; #ifdef VERBOSE printf("Writing: I2C_addr: 0x%04x, Reg: 0x%04x <== 0x%04x ", I2C_ADDR, #endif Wdata[0] Wdata[1] Wdata[2] Wdata[3] Wdata[4] = = = = = (u8_t) I2C_ADDR; (u8_t)((Reg >> 8) (u8_t)((Reg >> 0) (u8_t)((Data >> 8) (u8_t)((Data >> 0)
DATA SHEET
Reg, Data);
& & & &
0xff); 0xff); 0xff); 0xff);
rc = SP7_I2C_Write(5, Wdata); if (rc == STS_OK) { #ifdef VERBOSE printf("OK\n"); #endif } else { #ifdef VERBOSE printf("FAILED\n"); #endif } return rc; } /****************************************************************************** * Read from a register *****************************************************************************/ Status_t ReadReg (u16_t Reg, pu16_t Data) { u8_t Wdata[4]; u8_t Rdata[2]; Status_t rc; #ifdef VERBOSE printf("Reading: I2C_addr: 0x%04x, Reg: 0x%04x ", I2C_ADDR, #endif Wdata[0] = (u8_t)(I2C_ADDR); Wdata[1] = (u8_t)((Reg >> 8) & 0xff); Wdata[2] = (u8_t)((Reg >> 0) & 0xff); /* I2C repeated start in between by Wdata[3] = (u8_t)(I2C_ADDR | 0x01); */
Reg);
rc = SP7_I2C_Read(4, Wdata, 2, Rdata); *Data = (u16_t)((Rdata[0] << 8) | Rdata[1]); #ifdef VERBOSE printf("==> 0x%04x ", *Data); if (rc == STS_OK) { printf("OK\n"); } else { printf("FAILED\n"); } #endif return rc; }
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/****************************************************************************** * Main test program *****************************************************************************/ int main(void) { u16_t value; int rc = 0; /* initialize I2C functionality */ SP7_I2C_Init(); if (WriteReg(SP7_SC_MV_MODE, 0) != STS_OK) { rc = -1; } /* write something in SP7_SC_INFO0 */ if (WriteReg(SP7_SC_INFO0, 0x0aaa) != STS_OK) { rc = -1; } /* write something else in SP7_SC_INFO1 */ if (WriteReg(SP7_SC_INFO1, 0x0555) != STS_OK) { rc = -1; } /* read SP7_SC_INFO0 */ if (ReadReg(SP7_SC_INFO0, &value) != STS_OK) { rc = -1; } if (value != 0x0aaa) { rc = -1; #ifdef VERBOSE printf("Read back check FAILED\n"); #endif } else { #ifdef VERBOSE printf("Read back check PASSED\n"); #endif } #ifdef VERBOSE if (rc == -1) { printf("\nI2C test FAILED\n"); } else { printf("\nI2C test PASSED\n"); } #endif /* Terminate I2C functionality SP7_I2C_Term(); return rc; } */
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7. Data Sheet History 1. Data Sheet: "DRX 8872C COFDM Demodulator/ FEC", May 28, 2003, 6251-618-1DS. First release of the data sheet. 2. Data Sheet: "DRX 8872C COFDM Demodulator/ FEC", Feb. 18, 2004, 6251-618-2DS. Second release of the data sheet.
DATA SHEET
Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-618-2DS
All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH.
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