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Features
* DC to DC Step Down 1.2 A, 0.9 V (Dynamically Adjustable to 0.87 V/1.1 V/1.2 V) * DC to DC step Down 1.2 A, 1.2 V (Dynamically Adjustable to 1.0 V/1.1 V/1.3 V) or 1.75 V
(Dynamically Adjustable 1.65 V/1.70 V/1.80 V)
* DC to DC Step Down 1.2 A, 1.8V (Dynamically Adjustable to 1.70 V/1.75 V/1.85 V) or
2.5 V (Dynamically Adjustable 2.3 V/2.4 V/2.6 V)
* DC to DC Step Up/Down 520 mA, 3.3V (Dynamically Adjustable to 3.0V/3.1V/3.4V) * Dual Battery Chargers: Li+ Precharge, Fast Charge, Top-up Charge, 4.1 V (or
Adjustable), Processor Tuned Algorithms - USB Trickle Charge: Precharge Flat Battery from USB Pre-enumeration, then Autowake of Processor at 3.8 V Battery Level - Battery Charge Select: 25 mA to 500 mA - Real-time Charge Inhibit: Allows Charge Suspend (e.g. During TX Slots) Supply Monitor of Four Power Sources: Thermistors, Temperature, DC/DC Rails, all Supplied with Out-of-regulation Threshold Detection SIM Interface: SIM / USIM, 1.8V / 3.0V Standards, Integrated TX and RX Data FIFO SPI Control Interface: Up to 13 MHz; Tuned for SA1110/PXA250/PXA255 1.2 MHz SPI, 128 8-bit Registers Power on Reset: for SA1110/PXA250/PXA255 Architectures plus Additional Sequenced System Level Resets Voltage and Temperature Supervision Calibrated Voltage Reference 8-bit ADC with 5-input multiplexer Integrated Oscillator, Start-up and Self-protection Circuitry Off Power: 60 A with External "Button Select" for Restart Applications Include: PDAs, PCMCIA Cards, SMART Phones, Pocket PCs, 3G Applications, Intel(R) XScaleTM Powered Applications
* * * * * * * * * *
Power Management AT73C203 Power Management IC for Datacom Platforms Preliminary
Description
The AT73C203 device provides an integrated solution to portable and handheld applications built around microprocessors requiring "smart" power management functions, such as PDAs, Palmtop computers, point-of-sales terminals, 3G modems, etc. Its compact package outline and small size of external components make the AT73C203 suitable for PCMCIA card power management as well. The AT73C203 integrates a power switch controller that, when connected to an external power switch, may be used for for automatically selecting one of four possible power sources: * * * * Internal battery External battery Plugtop power supply unit 5 V (PSU) PC Host USB supply
The power switch output (VDD-PSU line) is connected directly to external auxiliary components such as a radio or any other "current hungry" module. The AT73C203 is also equipped with four digital rails from VDD-PSU to supply a baseband chip, a reset generator for the baseband chip, and a SPI interface to control the AT73C203 via an internal register set. The USIM interface allows the application processor to communicate with and control a USIM card. Charge control enables the application processor to charge the battery from the PSU or USB. A state machine can also determine whether to charge the internal battery through USB at start-up. Additionally, hardware monitoring gives information to the application processor when a voltage drop occurs (programmed via internal registers).
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Functional Diagram
Figure 1. AT73C203 Functional Diagram
Stand Alone LDO Regulator
Power Switch
DC-DC Converter Buck 0.9 V (0.87 V to 1.2 V)/1.2 A
Digital Control
Internal 900 kHZ Oscillator Very Low Temperature Shift DC-DC Converter Buck 1.2 V (1 V to 1.8 V)/1.2 A
Serial Interface Clock Distributor
8-bit ADC Power Management State Machine
DC-DC Converter Buck 1.8 V (1.7 V to 2.6 V)/1.2 A
Measurement Bridge ISO 7816 UART DC-DC Converter Boost - LDO 3.3V (3 V to 5.4 V)/520 mA
Temperature Sensor
SIM Level Shifter Battery Charger Internal Voltage Reference
SIM LDO 1.8 V/2.8 V/10 A
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Pin Description
Table 1. AT73C203 Pin Description
Signal Name AVSS SELDC175 SELDC25 nEN_RAIL3 nEN_RAIL4 nASIC_RESET nBOARD_RESET BOARD_RESET nPROC_RESET nPROC_RESET_OUT nASIC_RESET_REQUEST POWER_EN SYST_CLK nUSIM_INT nINT BUTTON_OUT CHG_INHIBIT TEST1 TEST2 IDBITS3 IDBITS2 IDBITS1 IDBITS0 SDO SDI SCLK nSEN GNDDIG VOUT3 VBOOST DH3 GNDDC3 DL3 VDDPSU3 Pin Type A-I D-I D-I D-I/O D-I/O D-O D-O D-O D-O D-I D-I D-I D-I D-O D-O D-O D-I D-I/O D-I/O D-I/O D-I/O D-I/O D-I/O D-I/O D-I D-I D-I A-I A-I A-I A-O A-I A-O A-I Pack Pin A1 B2 B1 A3 A2 C3 C1 C2 D4 D3 D1 D2 A4 E1 E2 E3 F1 F2 F3 G1 F4 G2 H1 G3 H2 J1 E5 K1 K2 J2 K3 H3 J3 G4 Level AVSS gnddig - vsauv gnddig - vsauv gnddig - vsauv gnddig - vsauv gnddig - vout3 gnddig - vout3 gnddig - vout3 gnddig - vout3 gnddig - vout3 gnddig - vout3 gnddig - vout3 gnddig - vout3 gnddig - vout3 gnddig - vout3 gnddig - vout3 gnddig - vout3 gnddig - vsauv gnddig - vsauv gnddig - vout3 gnddig - vout3 gnddig - vout3 gnddig - vout3 gnddig - vout3 gnddig - vout3 gnddig - vout3 gnddig - vout3 GND gnddc3 - vout3 gnddc3 - vddpsu gnddc3 - vddpsu GND gnddc3 - vddpsu gnddc3 - vddpsu avss - vswin avss - vswin avss - vswin avss - vswin avss - vout3 avss - vout3 avss - vout3 avss - vout3 avss - vout3 avss - vout3 avss - vout3 avss - vout3 avss - vout3 avss - vout3 avss - vout3 avss - vout3 avss - vsauv avss - vsauv avss - vout3 avss - vout3 avss - vout3 avss - vout3 avss - vout3 avss - vout3 avss - vout3 avss - vout3 avss - gnddig avss - vboost PCboost avss - vboost avss - gnddc3 avss - PCmax avss - PCmax ESD Protection Comments ESD Ground Digital control Digital control Digital control Digital control RESET RESET RESET RESET RESET RESET Digital control Digital control Digital control Digital control Digital control Digital control TEST TEST Digital control Digital control Digital control Digital control SPI SPI SPI SPI Digital ground DCDC rail3 DCDC rail3 DCDC rail3 DCDC rail3 DCDC rail3 DCDC rail3
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Table 1. AT73C203 Pin Description (Continued)
Signal Name DCSENSE3 VOUT2 DCSENSE2 DH2 VDDPSU2 GNDDC2 DL2 VOUT1 DCSENSE1 DH1 VDDPSU1 GNDDC1 DL1 VOUT4 DCSENSE4 DH4 VDDPSU4 GNDDC4 DL4 SIM_CLK SIM_RESET SIM_IO SIM_VCC GND_CH BAT2_CH BAT1_CH BAT2_CH_ON BAT1_CH_ON BATSENSEM BATSENSEP USB_CH_EN USB_CH GABAT1 GABAT2 GAPSU VDDPSU Pin Type A-I A-I A-I A-O A-I A-I A-O A-I A-I A-O A-I A-I A-O A-I A-I A-O A-I A-I A-O D-O D-O D-I/O A-O A-I A-I A-I A-O A-O A-I A-I A-O A-I D-O D-O D-O A-I Pack Pin H4 K4 H5 K5 G5 J4 J5 K6 H6 K7 G6 J6 J7 J10 K9 K8 K10 J9 J8 H10 H9 G7 G8 E6 F7 F10 F9 F8 E10 E9 E8 D10 E7 D9 C10 G10 Level gnddc3 - vddpsu gnddc2 - vout2 gnddc2 - vddpsu gnddc2 - vddpsu gnddc2 - vddpsu GND gnddc2 - vddpsu gnddc1 - vout1 gnddc1 - vddpsu gnddc1 - vddpsu gnddc1 - vddpsu GND gnddc1 - vddpsu gnddc4 - vout4 gnddc4 - vddpsu gnddc4 - vddpsu gnddc4 - vddpsu GND gnddc4 - vddpsu gnddig - vsim gnddig - vsim gnddig - vsim gnddig - vsim GND gndch - maxsupply gndch - maxsupply gndch - maxsupply gndch - maxsupply gndch - maxsupply gndch - maxsupply gndch - maxsupply gndch - maxsupply gnda1 - maxsupply gnda1 - maxsupply gnda1 - maxsupply gnda1 - vddpsu ESD Protection avss - PCmax avss - PCmax avss - PCmax avss - PCmax avss - PCmax avss - gnddc2 avss - PCmax avss - PCmax avss - PCmax avss - PCmax avss - PCmax avss - gnddc1 avss - PCmax avss - PCmax avss - PCmax avss - PCmax avss - PCmax avss - gnddc4 avss - PCmax avss - PCmax avss - PCmax avss - PCmax avss - PCmax avss - gndch avss - PCmax avss - PCmax avss - PCmax avss - PCmax avss - PCmax avss - PCmax avss - PCmax avss - PCmax avss - PCmax avss - PCmax avss - PCmax avss - PCmax Comments DCDC rail3 DCDC rail2 DCDC rail2 DCDC rail2 DCDC rail2 DCDC rail2 DCDC rail2 DCDC rail1 DCDC rail1 DCDC rail1 DCDC rail1 DCDC rail1 DCDC rail1 DCDC rail4 DCDC rail4 DCDC rail4 DCDC rail4 DCDC rail4 DCDC rail4 SIM SIM SIM SIM regulator Charger Charger Charger Charger Charger Charger Charger Charger Charger Power switch Power switch Power switch Power switch
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Table 1. AT73C203 Pin Description (Continued)
Signal Name BAT1_PIO BAT2_PIO PSU_PIO USB_PIO MAXSUPPLY GND_PIO VREFFUSE VBIAS CREF VMES PORTEST THERM1 THERM2 GNDA VSAUV VSW VSWIN SCAN_TEST_MD SCAN_ENABLE nSHUTDOWN PCMCIA SIM_PRES BUTTON_IN NC NC NC NC NC NC NC Pin Type A-I A-I A-I A-I A-O A-I A-I A-O A-O A-O D-O A-O A-O A-I A-O A-I A-I D-I/O D-I/O D-I D-I D-I D-I Pack Pin D8 C9 B10 D6 A10 B9 A9 C8 A8 B8 D7 C7 A7 B7 C6 A6 B6 C4 A5 B5 C5 G9 D5 B4 E4 H8 H7 F5 B3 F6 Level gnda1 - bat1 gnda1 - bat2 gnda1 - psu gnda1 - usb gnda1 - maxsupply GND avss - 5.5v gnda - vsauv gnda - vsauv gnda - vsauv gnda - vsauv gnda - vsauv gnda - vsauv GND gnda - vsauv gnda - vswin gnda - vswin gnddig - vsauv gnddig - vsauv gnddig - vsauv gnddig - vsauv gnddig - vsauv gnddig - vsauv ESD Protection avss - PCmax avss - PCmax avss - PCmax avss - PCmax PCmax avss - gnda1 avss-vswin avss - vswin avss - vswin avss - vswin avss - vswin avss - vswin avss - vswin avss - gnda avss - vswin avss - vswin PCvswin avss - vswin avss - vswin avss - vswin avss - vswin avss - vswin avss - vswin Comments Power switch Power switch Power switch Power switch Power switch Power switch FUSES Reference generator Reference generator Measurement bridge Power on reset Current generator Current generator Internal regulator Internal regulator Internal regulator Internal regulator TEST TEST Digital control Digital control Digital control Digital control Not Connected Not Connected Not Connected Not Connected Not Connected Not Connected Not Connected
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Application Schematic
Figure 2. AT73C203 Application Schematic
BAT1 BAT2 Charger
GABAT1 GABAT2 GAPSU VSAUV Stand Alone LDO Regulator Power Switch
VDDPSU4 DC-DC Converter Buck 0.9 V (0.87 V to 1.2 V)/1.2 A DCSENSE4 DL4 DH4 VOUT4
Digital Control Internal 900 kHz Oscillator Very Low Temperature Drift DC-DC Converter Buck 1.2 V (1 V to 1.8 V)/1.2 A Serial Interface Clock Distributor VDDPSU1 DCSENSE1 DL1 DH1 VOUT1
VDDPSU2 VMES 8-bit ADC Power Management State Machine DC-DC Converter Buck 1.8 V (1.7 V to 2.6 V)/1.2 A DCSENSE2 DL2 DH2 VOUT2
Measurement Bridge ISO 7816 UART
VDDPSU3 DCSENSE3 DL3
USB USB_CH USB_CH_EN
Temperature Sensor
DC-DC Converter Boost - LDO 3.3V (3 V to 5.4 V)/520 mA VBOOST DH3 VOUT3
SIM Level Shifter BATSENSEP Battery Charger Internal Voltage Reference
SIM LDO 1.8 V/2.8 V/10 A
BATSENSEM
BAT1_CH_ON
BAT1_CH
BAT2_CH_ON
BAT2_CH
CREF
BAT1
BAT2
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SIM-VCC
AT73C203
Architecture Overview
Figure 3. AT73C203 Architecture Overview
Powerswitch Bat 1 Bat 2 Li+ 800 mAh PSU Li+ 1600 mAh VDD-PSU Radio
Plug Top AC/DC USB PC Host USB Core and Digital Digital Supply Rails Charger Controller Powerswitch Controller
Monitoring
Digital I/O
Companion Chip or Chipset, eg: VOUT3 Application Processor, VOUT4 Baseband SOC VOUT1 VOUT2
SPI
SIM
System Level Description
Several power sources may be used to power the AT73C203 circuitry including an internal or external battery, external PSU or USB. The internal battery is always physically present in the unit, but any or all of the other sources may be connected or disconnected at any time. The AT73C203 enables one application to be powered up from the correct source of up to four possible power sources under hardware control. When powered, the external processor can monitor the input power sources and initiate battery charging as required via the SPI. The application processor is also able to enable/disable the circuit power rails and configure a low power sleep state. An input-multiplexed 8-bit ADC is available that allows the application processor to monitor the presence of and measure the voltage of the power sources, batteries and rails. An associated threshold and comparator circuit may be used to indicate to the processor that an out-of limit event has occurred. The battery charging circuitry is designed to allow charging from the PSU input and to allow current-limited 'supplement' charging from the USB input. In both cases, the chargers operate under processor control and monitoring with hardware safety lockout. When the PSU is present, a power path is selected (e.g. from a DC jack) through the power switching circuitry to the external components (e.g. radio and companion chips or chipset, baseband chip etc.) This power path enables the application processor to boot up. A parallel path exists from the PSU input (e.g. jack) through current limiting devices to two battery chargers. The current switches only block reverse current when disabled so care must be taken when controlling them.
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When a USB input is powered, a single power path exists through the current limiting devices to the two battery chargers. The hardware defaults to a current limit of 100 mA but the application processor may set 500 mA after negotiation with the PC. This power should always be used to charge the batteries in the absence of the PSU power source. SIM/USIM interface hardware is provided, allowing the application processor to communicate and control a SIM/USIM card according to the required analog and digital specifications. Most of the blocks are switched on or off by the digital control block (not all the control lines are drawn on the block diagram). Only the supply monitor, digital control, power on reset, 10 kHz internal oscillator and internal regulator are always on. All these blocks are designed to have very low power consumption, capable of achieving three months standby time for the application.
Functional Integration
Supply Monitor
The AT73C203 integrates the following functions: The supply monitor block enables the AT73C203 to correctly switch the four main supplies (two batteries, PSU and USB). All the outputs are sent to the digital control. The internal regulator is a low drop out regulator generating VSAUV at 2.5 V with a maximum load of 5 mA. Its input is VSW. The internal power-on reset is supplied by VSAUV and resets the AT73C203 digital circuitry at 2 V. The 10 kHz low power oscillator is the clock source for the AT73C203 digital circuitry. VSAUV supplies it. The digital block controls each block and drives the SPI interface and the different interrupts (external and internal). The controls, inputs and outputs are level shifted when necessary and protected to avoid current flowing between the blocks (not represented in the block diagram). A state machine controls the AT73C203 circuitry according the supplies and inputs states. A table of registers is accessible via SPI to command or read status of the AT73C203. The reference generator provides the AT73C203 with a precise bandgap voltage (VREF) and current bias (IREF) used by all analog blocks (DC/DC, ADC, charger) except the core blocks. It is turned off under digital control when necessary and is VSAUV supplied. The 900 kHz oscillator provides the clock to all DC/DC converters. The clock distributor provides phased clocks to the DC/DC converters to avoid switching at the same time. The frequency of the oscillator is trimmed during production to optimize the DC/DC efficiency. The DC to DC step Down 1.2A, 0.9 V (dynamically adjustable to 0.87 V/0.9 V/1.1 V/ 1.2 V) is a programmable buck DC/DC converter dedicated to advanced sub-micron processors and SoC ASIC logic cores requiring dynamic power management at low voltages and high currents. The default voltage is 0.9 V for which the device is optimized.
Internal Regulator
Power-on Reset
10 kHz Internal Oscillator
Digital Control
Reference Generator
900 kHz Oscillator and Clock Distribution
DC to DC Step Down 1.2 A, 0.9 V
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The external components needed include a current sensing resistor, a dual PMOSNMOS, an inductor and an output capacitor. The application processor can change the output voltage via registers accessible by SPI. When the cell is off, the output is in high impedance state. If not used, this section can be permanently deactivated. DC to DC Step Down 1.2 A, 1.2V OR 1.75 V The DC to DC step Down 1.2 A, 1.2 V (dynamically adjustable to 1.0 V/1.1 V/1.2 V/ 1.3 V) is a programmable buck synchronous DC/DC converter dedicated to the application processor core and/or a "companion" ASIC SoC Processor Core. The default voltage is 1.2 V. An external pin can select 1.75 V output voltage with tuning: 1.80 V, 1.70 V or 1.65 V. The entire cell is optimized for 1.2 V. The application processor can change the output voltage as described above via registers accessible by SPI. The external components needed include a current sensing resistor, a dual PMOSNMOS, one inductor and one output capacitor. When the cell is off, the output is pulled to ground. If not used, this section can be permanently deactivated DC to DC Step Down 1.2 A, 1.8 V OR 2.5 V The DC to DC step Down 1.2 A, 1.8 V (dynamically adjustable to 1.70 V/1.75 V/1.80 V/1.85 V) is a programmable buck synchronous DC/DC converter dedicated to the supply of recent and future Flash and SDRAM memories and their associated buses on the application processor I/O section as well as additional memory extension modules such as CF cards, MMCards, Memory Stick, etc. The default voltage is 1.8 V. An external pin can select 2.5 V output voltage with tuning: 2.6 V, 2.4 V and 2.3 V. The entire cell is optimized for 1.8 V. The application processor can change the output voltage as described above via registers accessible by SPI. The external components needed include a current sensing resistor, a dual PMOSNMOS, an inductor and an output capacitor. A low quiescent current mode is implemented when a very low standby current is needed with a parallel voltage regulator. When the cell is off, the output is in high impedance state. DC to DC Step Up/ Down 520 mA, 3.3 V The DC to DC step Up/Down 520 mA, 3.3 V (dynamically adjustable to 3.0 V/3.1 V/ 3.4 V) is a boost DC/DC 3.6 V converter followed by a linear drop out regulator. It is intended to supply 3.3 V I/Os needed in the application (Audio Codec, LCD, Memories). The external components needed include a current sensing resistor, an NMOS, a Schottky diode, an inductor and an output capacitor. The default value of the LDO is 3.3 V but three other values can be programmed: 3.1 V, 3.2 V and 3.4 V. The entire cell is optimized for 3.3 V. The application processor can change the output voltage as described above via registers accessible by SPI. When the cell is off, the output is pulled to ground. Power Switch Controller The power switch controller drives an external PMOS switch to multiplex VDD-PSU from the internal or external battery or USB. The purpose of this cell is to guarantee a sufficient supply for VDD-PSU and to limit voltage drops even during switchover. In-rush current and current flow between the inputs must be avoided. When this cell is off, VDD-PSU is left in high impedance.
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Current Generators
Two accurate current generators allow the measurement of the resistance of two external battery thermistors. The outputs VTHE1 and VTHE2 go to the measurement bridge. The current generators are supplied by VSAUV and controlled by the digital control for use during battery charging. The temperature sensor voltage output depends linearly on temperature. It is supplied by V SAUV and driven by the digital control. The temperature seen by the sensor is directly related to the chip activity and the power internally dissipated. To get a good indication of the ambient temperature, the software must take into account this offset. The measurement bridge provides adapted voltages of the internal and external batteries, DC/DC converter outputs, USB, VDD-PSU, VTHE1 and VTHE2 to the multiplexed input of the serial analog to digital converter. An 8-bit analog to digital converter is integrated into the AT73C203 to give information about voltage and temperature to the application processor via the SPI interface. The battery chargers both have stand-alone constant current (CC) precharge and microprocessor-controlled CC fast charge as well as top-off mode end-of-charge algorithm. The digital block controls this cell. All current and voltage settings are programmable via registers. The charger controller is divided into two similar parts, one for the internal battery and one for the external battery. Each charger multiplexes the source (USB or PSU) and limits the programmable current charge (via sense resistor). An external PMOS and a Schottky diode are needed for each charger. The application processor must check that the temperature allows charging via the current generator, measurement bridge and ADC.
Temperature Sensor
Measurement Bridge/ Multiplexer
Analog to Digital Converter
Li-Ion/Battery Chargers
USIM Voltage Regulator
A regulator is provided to power up the USIM card. It is supplied directly from VDD_PSU. One of two different voltages can be selected: * * 2.8 V (50 mA) 1.8 V (30 mA)
By default, the regulator is in power-down mode. The pins connected to the USIM (SIM_CLK, SIM_IO, SIM_PWR) must have driver specification according to ETS TS 102 221. USIM Digital Section Reset Generation The main part of the USIM digital section is an ISO7816 UART compatible interface. A reset is generated via the internal state machine. The timer for this internal reset generator is 150 ms (typical). The application processor can set the AT73C203 to off mode via the POWER_EN pin. The "internal" reset is active at low level. Another way to generate a reset is to program it through the monitoring function (ADC with measurement bridge and data registers). The "monitoring" reset is active at low level. A logical AND of the "internal" and the "monitoring" reset drives the reset of the external application processor (NPROC_RESET pin). Other pins are used to generate separated resets for external "companion" chips such as baseband chips.
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NSHUTDOWN forces the AT73C203 internal digital block to the reset state. This turns all the supplies off and then restarts the internal state machine.
External Recommended Components
Table 2. External Recommended Components
Schematic Reference C1, C3, C5, C8, C16, C17, C18, C19 C2, C4, C9 C6, C7 C10, C11, C13, C22 C12 C14, C15 C20 C21 D2, D3 D4, D5, D1 L1, L4 L2, L3 R1, R2, R4 R3 R5 R6 T1, T2, T3 T4 T5 T6 T7, T9, T10 T8 T11 Component Reference 22 F ceramic 2 x 22 F tantalum low ESR 22 F tantalum low ESR 100 nF XR5 10% 2.2 F X5R 10% 330 nF X5R 10% 10 nF X5R 10% 100 nF 100 pF X5R 10% Bat54C MBRA120LT3 (ON Semiconductor(R)) 4.7H SMT3106-471M (Gowanda(R)) 10 H SMT3106-102M (Gowanda) 100 m 2% 250mW 100 m 2% 250mW 220 k 1% 200 m 2% 50mW Si4965DY Si5513DC Si5513DC Si1400DL Si8401DL Si5513DC Si1405DL
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Absolute Maximum Ratings
Operating Ambient Temperature........................-40C to +85C Storage Temperature......................................-55C to + 150C BAT1_PIO, BAT2_PIO, PSU_PIO, USB_PIO, USB_CH, BAT1_CH, BAT2_CH, VSW_IN to ground Pins.....................................................-0.3V to +6.5V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Table 3. Recommended Operating Conditions
Parameter Operating Ambient Temperature Storage Temperature Signal to Ground Pins BAT1_PIO, BAT2_PIO, PSU_PIO, USB_PIO, USB_CH, BAT1_CH, BAT2_CH, VSW_IN Conditions Min -40 -55 -0.3 Max +85 +150 +5.5 Unit C C V
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System Overview
Startup and Off Mode
Most of the blocks are switched on or off by the digital block. Only the supply monitor, digital control, power-on reset, internal 10kHz oscillator and internal regulator are always on. Figure 4. Start-up Overview
POR2 Digital Control POR1
Internal Oscillator 10 kHz
Supply Monitor
Power-on Reset 2V
Rint
Internal Regulator 2.5 V 5 mA
BAT1_SM BAT2_SM PSU_SM USB_SM BAT1 BAT2 PSU USB D3 D2
VSW_IN
VSW
VSAUV
C12
C13
The system has two modes: Off and Active. Off Mode: All the cells are off except the supply monitor, digital control, power-on reset, internal 10 kHz oscillator and internal regulator. These blocks are designed to consume very little power in order to achieve an off time of three months from a 600 mAh fully charged battery. Active Mode: The power switch and all the DC/DC controllers are on. All the other cells are controlled by software (via internal registers).
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Startup Description
VSW_IN is an analog OR of BAT1, BAT2, USB and PSU implemented using four external Schottky diodes. Schottky diodes are used to minimize the power source to the AT73C203 voltage drop in order to maximize battery life. See Figure 4 on page 13. When at least one of these supplies are present, VSW_IN tracks the highest voltage of the four inputs. An internal resistor (Rint) between VSW and VSW_IN limits the current flowing through the diodes and C12. VSW is the input of the internal regulator, which delivers the supply for the digital, oscillators, power-on reset, measurement bridge, reference generator, AD converter, temperature sensor, current generator and supply monitor blocks. Only a small current is supplied from VSW_IN which minimizes the voltage drop across the Schottky diodes.
Power-on-reset Protection
Figure 5 below and Figure 6 on page 15 illustrate the start-up sequence of the AT73C203 under the following conditions. * * * * * One supply is present (PSU), the others are connected to ground or not present. POR1 supervises VSW. It goes to low level after the start-up time of the internal regulator. POR2 supervises VSAUV. It goes to low after VSAUV reaches the correct value for the digital core to run. Both VSW and VSAUV must be stable for the digital block to operate correctly. The reset for the digital core is the logical OR of POR1 and POR2.
Figure 5. PSU Rising Sequence
PSU
VSW tSTARTUPREG VSAUV
(1)
POR1
POR2
Note:
1. tSTARTUPREG = Startup time of the internal regulator.
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Figure 6. PSU Drop Sequence
PSU
VSW tSHUTDOWNREG VSAUV
(1)
POR1
POR2
Note:
1. tSHUTDOWNREG = Shutdown time of the internal regulator.
State Machine Description
State machines for the start-up and off modes are described in the following pages. The state machine is completely synchronous to the internal 10 kHz oscillator and all the signals connected to the analog blocks are level shifted as necessary and protected to allow a reliable level. USB_FST is a digital flag. By default USB_FST is set at 0. If the digital core begins to precharge battery 1 from USB at startup, USB_FST is set to 1 by the internal digital block. The application processor can reset it to 0 via the SPI if needed by setting the USB_FCR flag. This flag acts to avoid digital oscillation when the charge through USB is the start condition. It is also used to inform the application processor that the AT73C203 has charged the internal battery from USB with a minimal amount of charge. The digital core can also put the AT73C203 via USB_SCR register into a mode where the digital core is off and battery1 is charged (25 mA) through USB until 4,1 V. In this mode (see Figure 10 on page 19) and when battery1 is precharged by USB (see Figure 8 on page 17), a CTN thermistor must be connected to therm1. The CTN thermistor used must be equivalent to the thermistor 103JT-025 from SEMITEC(R). * * * Temperature to allow precharging through USB: 0C to 60C. Safety timer for the USB stand alone mode: 1 hour Safety timer for the USB Sleep mode: 24 hours
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Figure 7. Startup State Machine (1of 3)
INIT After power-on reset Flag_USB = 0
Startup State Machine (1)
First counter running (Wait stabilization of the internal clock)
GUARD_TIME
2 1
Wait 1 ms
3
PSU unplugged USB plugged in FLAG_USB = 0 Button not pressed USB not present
GUARD_TIME_END
1
PSU present
2
Button not pressed PSU not present (VBAT1 or VBAT2) present and not flat Button pressed
1
USB_DEBOUNCE
PSU not present
1
10 ms timer for debouncing running
CHARGER_DEBOUNCE
3 3 2
CHARGER_DEBOUNCE
Wait button pressed during 10 ms
3
START End of debouncing timer (10 ms)
End of debouncing timer (10 ms)
Wait PSU present during 10 ms
BGP-OSC_START
1
Wait bandgap and OSC 500 k start (5 ms)
2
End of bandgap and DC/DC timer
POW_SW_ON
POW_SW_START
1
Wait power switch start (5 ms)
2
End of power switch timer
DCDC_3V3_ON
DCDC_3V3_START
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Figure 8. Startup State Machine (2 of 3)
GUARD_TIME_END PSU unplugged USB plugged in FLAG_USB = 0 Button not pressed USB not present
1
Startup State Machine (2)
USB_DEBOUNCE
2
Wait USB present during 10 ms
3
START_USB
Main bandgap on Current generator on ADC on
BGP_ADC_START
2
Wait bandgap start 5 ms
1 Charger Debounce
End of bandgap timer
PSU present
TEMPERATRUE_TEST
2
Temperature not correct
3 1
3
TEMPERATURE_NOK
1 2
Wait temperature ok
Temperature correct PSU present
Temperature correct
4
USB unplugged Charger on: battery 150 mA Charger timer launched CHARGER_DEBOUNCE PSU present BAT1 > 3.8 V and timer still running BAT1 < 3.8 V
4 2 2
PSU present
1
CHARGER_ON
GUARD_TIME_END 4
USB unplugged
GUARD_TIME_END
End of charger timer and BAT1 > 3.8V BATTERY_ERROR Charger off
USB_FST = 1 BAT1_CHECK
3 1
BAT1 > 3.8 V during 10 ms
Wait BAT1 > 3.8 V during 10 ms
USB deconnected or PSU connected
START
GUARD_TIME_END
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Figure 9. Startup State Machine (3 of 3)
DC/DC_3V3_START
Startup State Machine (3)
Rail3_Start
1
Wait DC/DC converter start (5 ms)
2 End of 3.3 V DC/DC startup and PWR_EN = 1
Rail1_ON
Rail1 on Reset pin active
Rail1_START
1
Wait DC/DC converter start (5 ms)
2 End of DC/DC startup
Rail2_ON
Rail2 on Reset pin active
Rail2_START
1
Wait DC/DC converter start (5 ms)
2 End of DC/DC startup
Rail4_ON
Rail4 on Reset pin active
Rail4_START
1 2 End of DC/DC startup
Wait DC/DC converter start (5 ms)
Reset timer launched Reset pin active
RESET_TIMER
1 2 End of reset timer
Wait end of reset timer
END_OF_RESET Reset pin disactivated
=> under software control
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Figure 10. USB Sleep State Machine
USB Sleep State Machine
END_OF_RESET STATE
Active after "END_OF_ RESET" state
USB_SCR = 1
Rail4_OFF1
Rail4 off Reset active
Rail2_OFF1
Rail2 off Reset active
Rail1_OFF1
Rail1 off Reset active
Rail3_OFF1
Rail3 off Reset active
Charger Debounce
PSU present
2
3
TEMPERATRUE_TEST2 Temperature not correct
3
TEMPERATURE_NOK2
1 1
4
Wait temperature ok
2
PSU present
Temperature correct Temperature correct
USB unplugged Charger on: battery 150 mA Charger timer launched CHARGER_DEBOUNCE PSU present
1 2
PSU present
CHARGER_ON2
GUARD_TIME_END 4
USB unplugged
GUARD_TIME_END
BAT1 > 4.1 V and timer still running
End of charger timer and BAT1 > 4.1 V BATTERY_ERROR2
BAT1_CHECK2 USB disconnected or PSU connected
GUARD_TIME_END
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Figure 11. Stop Off State Machine
Stop Off State Machine
PWREN_DEBOUNCE
1 Active after "END_OF_ RESET" state
Wait PWREN = 0 during 10 ms
2
Rail4_OFF1
Rail4 off Reset active
Rail2_OFF1
Rail2 off Reset active
Rail1_OFF1
Rail1 off Reset active
1
Rail3_OFF1
Rail3 off Reset active
Wait button released
1
1
BUTTON_RELEASE
All cells (except the core cell) are off
Wait button released during 200 ms
2
Button released during 200 ms
CASE_ANALYSIS
1 2
PSU present
PSU not present
Button pressed BUTTON_DEBOUNCE
OFF_MODE_PSU
PSU not present
OFF_MODE_NO_PSU
GUARD_TIME_END
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Reset Generation
A reset is generated via the internal state machine as described in Figure 7 on page 16, Figure 8 on page 17, Figure 9 on page 18 and Figure 11 on page 20. The timer for the internal reset generator is 150 ms (typical). The application processor can set the AT73C203 to off mode via the POWER_EN pin (Figure 11 on page 20). This "internal" reset is active at low level. Another way to generate a reset is to program it through the monitoring function. The "monitoring" reset is active at low level. An logical AND of the "internal" reset and the "monitoring" reset drives the reset of the external microprocessor. It is connected to the NPROC_RESET pin and directly drives the external microprocessor. Additional pins are used to generate separated resets for the baseband chips (see Figure 12 below). NSHUTDOWN forces the AT73C203 internal digital block to the reset state. This turns all the supplies off and then restarts the internal state machine. Power-on reset resets the internal state machine. nPROC_RESET resets all other digital parts, with the exception of the USIM interface which is reset via the nBOARD_RES pin. Figure 12. Reset Generation Architecture
Internal Reset Generator
Internal Reset
POWER_EN
NPROC_RESET
NPROC_RESET_OUT Monitoring Reset Generator Monitoring Reset BOARD_RES
NBOARD_RES
NASIC_RESET NASIC_RESET_REQUEST NSHUTDOWN
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Electrical Characteristics
Power Switch
The power switch control block drives external dual PMOS devices to multiplex VDDPSU from battery 1 (BAT1), battery 2 (BAT2) and an AC/DC Power supply unit (PSUIN). The purpose of this cell is to guarantee a sufficient supply for VDDPSU and to limit drops even during switchover. Inrush current from source to VDDPSU must be avoided. Back powering from a selected power source to all other power sources must be avoided. Figure 13. Power Switch Controller
C16 T1 C17 T2 C18 T3
C19 PSU BAT1 BAT2 BAT1_PIO BAT2_PIO GABAT1 D3 D2 Power Switch Controller PSU_PIO GABAT2 GAPSU VDDPSU
C20
MAXSUPPLY
Rint(1)
USB_PIO USB Vsw_in
Vsw
C12
Note:
1. Rint is internal to the AT73C203.
Automatic Selection
When the power switch digital control block is off, VDDPSU is set to the high impedance state. The supply of this cell comes from an analog OR done with four external Schottky diodes connected to BAT_1PIO, BAT2_PIO, PSU_PIO and USB_IN.
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The system should respect the "Universal Serial Bus Specification", especially section 7.2.4.1, which specifies that the maximum equivalent load seen by the USB is 10 F in parallel with 44 ohms. When the cell is on, the power switch must automatically select the correct power source. PSU is a non current-limited 5 V supply output. BAT2 is a Lithium Ion battery and can be removed. BAT1 is a Lithium Ion battery and is always soldered to the PCB. A selection priority rule is used: PSU > BAT2 > BAT1 When the PSU is plugged in, it is selected by default. If the PSU is not plugged in, BAT2 is used if it is present and has enough voltage. If PSU is not plugged in, and BAT2 is unplugged or below the flat threshold, BAT1 is used if BAT1's voltage is high enough. For a critical situation on any of the power sources, the automatic switching shall ensure that VDDPSU stays within specifications. This means that the automatic supply selection FETs must be switched as quickly as possible, ideally with a maximum switchover of 1 s (max: 5 s) and guarantee that the already enabled FETs are switched off before the newly selected FETs are switched on. The faster the switching, the smaller the capacitance required to hold up VDDPSU (target: 100 F max). To handle all cases, fast analog comparators on each input with appropriate hysteresis (in voltage and in time) must be used within the AT73C203. To meet the 5 s requirement, the comparator must be fast enough to detect when a source is disconnected (or a low voltage threshold is reached) but slow enough when detecting that a new source is plugged in (depending on contact bounce during the insertion/removal of a power source). The slow delay is done with the 10 kHz internal oscillator. At start-up, the cell is off and is turned on by the internal digital block. With PWS_CR register (bits accessible via SPI), the application processor can force an input source to be selected. This may be used for testing the AT73C203 or by the application processor to force use of one of the batteries. Using PWS_SR register, the application processor can read which supply is currently selected by the AT73C203. If one input is not used (PSU, BAT1 or BAT2), it can be grounded. The corresponding unused output (GAPSU, GABAT1 or GABAT2) can be left unconnected in this case.
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Power Switch Controller Electrical Specifications
Table 4. Power Switch Controller Electrical Specifications
Symbol Top Psupio BAT2PIO BAT1PIO IPSU ICC IOFF tSW VDDPSUMIN tSTARTUP tPRECHAREGE tDEBOUN_PSU tDEBOUN_BAT2 Psupio_r1 Psupio_f1 Psupio_hy1 Psupio_r2 Psupio_f2 Psupio_hy2 Bat2pio_r Bat2pio_f Bat2pio_hy Bat1pio_r Bat1pio_f Bat1pio_hy Parameter Operating temperature Charger supply voltage Battery 2 supply voltage Battery 1 supply voltage Current load on VDDPSU Current consumption Off current Switching time between two sources Minimum voltage on VDDPSU Time to start Time to precharge the VDDPSU capacitor Time for debouncing the PSU presence Time for debouncing the bat2 presence Voltage to consider PSU plugged in Voltage to consider PSU removed PSU hysteresis Voltage to consider PSU plugged in Voltage to consider PSU removed PSU hysteresis Voltage to consider BAT2 available Rising, VBG = 1.23 V, Pcmcia = 0 Falling, VBG = 1.23 V, Pcmcia = 0 Input hysteresis, Pcmcia = 0 Rising, VBG = 1.23 V, Pcmcia = 1 Falling, VBG = 1.23 V, Pcmcia = 1 Input hysteresis, Pcmcia = 1 Rising, VBG = 1.23 V 3.43 2.96 470 3.05 2.80 250 3.20 2.95 250 3.20 2.95 250 onpio = 0 and precharg = 1, external load on VDDPSU = 100 A onpio = 1, input selected = 3.1 V 2.85 50 100 100 100 100 onpio = 1, psupio = 5.5 V, BAT2PIO = 4.35 V and BAT1PIO = 4.35 V. onpio = 0 and precharg = 0 1 Condition Min -20 5 3.6 3.6 Typ Max +85 5.5 4.35 4.35 2 500 30 5 Unit C V V V A uA A s V s ms ms ms V V mV V V mV V V mV V V mV
Voltage to consider BAT2 removed or flat Falling, VBG = 1.23 V BAT2 hysteresis Voltage to consider bat1 available Voltage to consider bat1 removed or flat BAT1 hysteresis Input hysteresis Rising, VBG = 1.23 V Falling, VBG = 1.23 V Input hysteresis
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Serial Peripheral Interface (SPI)
Figure 14. SPI Architecture
SPI_CORE SDI SDI
The SPI interface between the system and the AT73C203 is detailed below.
SDI_SELECT R/W
A6
A0
D7
D0
8 NSEN NSEN Write Control 7
REG_in ADDR WRITE Register Bank
8 Reset
REG_OUT
Read Control SCLK SCLK
WRITE_DATA_BUFFER
SDO_SELECT SDO_EN 3
D7
D0
SDO
SDO
Protocol
The SPI is a 4-wire bidirectional asynchronous serial link providing 128 x 8 register access by the microprocessor. The SPI operates in slave mode only. The SPI protocol is as follows.
Figure 15. SPI Protocol
NSEN
SCLK
SDI
rw
a6
a5
a4
a3
a2
a1
a0
d7
d6
d5
d4
d3
d2
d1
d0
SDO
d7
d6
d5
d4
d3
d2
d1
d0
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On SDI, the first bit is read/write. "0" indicates a write operation while "1" denotes a read operation. The seven following bits are used for the register address and the eight that follow are the write data. For both address and data, the most significant bit is the first one. In case of a read operation, SDO first provides the contents of the read register, MSB. The transfer is enabled by the NSEN signal active low. When the SPI is not operating, SDO output is set to high impedance to allow sharing of the CPU serial interface with other devices. The interface is reset at every rising edge of NSEN in order to return to an idle state, even if the transfer does not succeed. The SPI is synchronized with the serial clock SCLK. Falling edge latches SDI input and rising edge shifts SDO output bits. Timing for SPI Interface SPI interface timings are as follows.
Figure 16. SPI Interface Timing Diagram
NSEN tSSEN tWL SCLK tWH tSSDI SDI tHSDI tC tHSEN
tDSDO SDO
tHSDO
Table 5. SPI Timing Parameters
Timing Parameter tC tWL tWH tSSEN tHSEN tSSDI tHSDI tDSDO tHSDO Note: 1. tSYSCLK = system clock period. Description SCLK min period SCLK min pulse width low SCLK min pulse width high Setup time SEN falling to SCLK rising Hold time SCLK falling to SEN rising Setup time SDI valid to SCLK falling Hold time SCLK falling to SDI not valid Delay time SCLK rising to SDO valid Hold time SCLK rising to SDO not valid
(1)
Min tSYSCLK/2 50 ns 50 ns 50 ns tSYSCLK 20 ns 20 ns 0 ns
Max
20 ns -
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The frequency of SYS_CLK must be at least two times superior to that of SCLK. After the end of reset (nPROC_RESET = 1), SYS_CLK must run at least during 500 s before the first SPI access. The minimum time for the USIM is one system clock period (tSYSCLK). As the clock domain is 900 kHz, to monitor function registers, two consecutive accesses at the same register must be superior to the 900 kHz period. Otherwise, only the second access will be taken into account. The same approach is used for the charger registers but with 10 kHz.
RAIL1 DC/DC Converter 1.20 V, 1.2 A
Rail1 is a programmable buck DC/DC converter dedicated to the application processor core supply. The default voltage is 1.20 V. Three other values can be programmed: 1.3 V, 1.1 V and 1.5 V. An external pin can select 1.75 V (SELDC175) output voltage with tuning: 1.80V, 1.70V and 1.65V. The entire cell is optimized for 1.20V. When the cell is off, the output is pulled to ground. The application processor can change the output voltage, as stated above, via registers accessible by the SPI. Figure 17. Rail1 Schematic
VDDPSU1 Seldc175 R1 Dcsense1 DH1 C1
DC/DC Converter 1.2 V, 1.2A
L1
DL1 Trim dc1[1:0] T4 VOUT1
On dc1
Clk_dc1 C2
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Table 6. Rail1 External Components
Schematic Reference C1 C2 L1 R1 T4 Reference 22 F Ceramic capacitor 2 x 22 F tantalum capacitors low ESR 4.7 H: SMT3106-471M `(Gowanda) 100 m 2% 250 mW Si5513DC
Rail1 can operate up to a load of 1.5 A if the R1 resistor is replaced by 80 m 2%. Rail 1 can also operate at VIN = 2.85 V. Table 7. Rail1 Electrical Specifications
Rail1 Electrical Specifications
Symbol VIN
Parameter Operating Supply Voltage Temperature Range
Condition (1.2V Selected)
Min 2.97 -20
Typ
Max 5.5 85
Unit V C V
VOUT IOUT
Output Voltage Output Current Ripple Voltage
0 < ILOAD < 1200 mA, 3 V < VIN < 5.5 V
1.2 1200 40
mA mV % % mV mV mV mV
Eff36 Eff50
Efficiency Efficiency Static line regulation Static load regulation Transient line regulation Transient load regulation
VIN = 3.6 V, ILOAD = 600 mA VIN = 5V, ILOAD = 600 mA tR = tF = 5 s, VIN from 3 V to 5.5 V ILOAD = 1200 mA tR = tF = 5 s, VIN = 3V and VIN =5.5 V ILOAD from 0 to 1200 mA tR = tF = 5 s, VIN from 3V to 5.5 V ILOAD = 1200 mA tR = tF = 5 s, VIN = 3 V and VIN = 5.5 V ILOAD from 0 to 1200 mA VIN = 5.5 V ILOAD = 400 mA ILOAD = 1200 mA Full load, 0.85 V to 1.3 V condition 3V < VIN < 5.5 V 1.2 0.01 0.01
83 85 25 10 35 80 1 10 15 70
ICC tR tR1200 tSETTLE ISC
Powerdown Current Rise Time Rise Time Settling time for programmed voltage switching Limitation current
A ms ms s A
Rail2 DC/DC Converter 1.8V, 1.2 A
Rail2 is a programmable buck DC/DC converter dedicated to digital supply. The default voltage is 1.8 V. Three other values can be programmed: 1.85 V, 1.75 V and 1.70 V. An external pin can select 2.5 V output voltage (SELDC25) tuning: 2.6 V, 2.4 V and 2.3 V. The entire cell is optimized for 1.8 V When the cell is off, the output is in high impedance state. The application processor can change the output voltage, as stated above, via registers accessible by the SPI.
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Figure 18. Rail2 Schematic
VDDPSU2 Seldc25 R2 Dcsense2 DH2 C3
DC/DC Converter 1.8V, 1.2A
L2
DL2 Trim dc2[1:0] T5 VOUT2
On dc2
Clk_dc2 C4
Table 8. Rail2 Preliminary External Components
Schematic Reference C3 C4 L2 R2 T5 Reference 22 F Ceramic capacitor 2 x 22 F tantalum capacitors low ESR 10 H: SMT3106-102M (Gowanda) 100 m 2% 250 mW Si5513DC
Rail2 Electrical Specifications
Symbol VIN Parameter Operating Supply Voltage Temperature Range VOUT IOUT Output Voltage Output Current Ripple Voltage Eff36 Eff50 Efficiency Efficiency
Rail 2 can also operate at VIN = 2.85 V.
Table 9. Rail2 Electrical Specifications
Condition (1.2 V Selected) Min 2.97 -20 0 < ILOAD < 1200 mA, 3 V < VIN < 5.5 V 1.8 1200 ILOAD = 1.2 A, VIN = 3.6 V VIN = 3.6 V, ILOAD = 600 mA VIN = 5V, ILOAD = 600 mA 200 85 87 Typ Max 5.5 85 Unit V C V mA mV % %
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Table 9. Rail2 Electrical Specifications (Continued)
Symbol Parameter Static line regulation Static load regulation Transient line regulation Transient load regulation ICC tR tSETTLE ISC Powerdown Current Rise Time Settling time for programmed voltage switching Limitation current Condition (1.2 V Selected) tR = tF = 5 s, VIN from 3 V to 5.5 V, ILOAD = 1200 mA tR = tF = 5 s, VIN = 3V and VIN = 5.5 V, ILOAD from 0 to 1200 mA tR = tF = 5 s, VIN from 3V to 5.5 V, ILOAD = 1200 mA tR = tF = 5 s, VIN = 3 V and VIN = 5.5 V, ILOAD from 0 to 1200 mA VIN = 5.5 V ILOAD = 1200 mA Full load, 0.85 V to 1.3 V condition 3V < VIN < 5.5 V 1.2 50 2 Min Typ 25 10 35 80 1 1000 Max Unit mV mV mV mV A ms s A
Rail3 DC/DC Converter 3.3V, 520 mA
Rail3 is a programmable buck DC/DC converter followed by a linear drop out regulator. The default value of the LDO is 3.3 V. Three other values can be programmed: 3.1 V, 3.2 V and 3.4 V. The entire cell is optimized for 3.3 V. When the cell is off, the output is pulled to ground. The application processor can change the output voltage, as stated above, via registers accessible by the SPI. Figure 19. Rail3 Schematic
VDDPSU3 C5 L3 DL3 Dcsense3 Trim dc3[1:0] DC/DC Converter 3.3V, 520 mA R3 C6 On dc2 Clk_dc2 LDO 3.3 V VBOOST DH3 VOUT3 T6 D1
T7
C7
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Table 10. Rail3 Preliminary External Components
Schematic Reference C5, C6, C7 D1 L3 R3 T6 T7 Reference 22 F ceramic capacitor 22 F tantalum capacitor low ESR Schottky diode: MBRA120LT3 (ON Semiconductor) 10 H: SMT3106-102M (Gowanda) 100 m 2% 250 mW Si1400DL Si8401DL
Rail3 Electrical Specifications
Symbol VIN Parameter Operating Supply Voltage Temperature Range VOUT IOUT Output Voltage Output Current Ripple Voltage Eff36 Eff50 Efficiency Efficiency Static line regulation Static load regulation Transient line regulation Transient load regulation ICC tR tSETTLE ISC Powerdown Current Rise Time
Rail 3 can also operate at VIN = 2.85 V.
Table 11. Rail3 Electrical Specifications
Condition (3.3 V Selected) Min 2.97 -20 0 < ILOAD < 520 mA, 3 V < VIN < 5.5 V Typ Max 5.5 85 520 1200 70 VIN = 3.6 V, ILOAD = 430 mA VIN = 5V, ILOAD = 430 mA tR = tF = 5 s, VIN from 3 V to 5.5 V, ILOAD = 430 mA tR = tF = 5 s, VIN = 3 V and VIN = 5.5 V, ILOAD from 52 to 468 mA tR = tF = 5 s, VIN from 3V to 5.5 V, ILOAD = 300 mA tR = tF = 5 s, VIN = 3 V and VIN = 5.5 V, ILOAD from 0 to 300 mA VIN = 5.5 V ILOAD = 400 mA Full load, 3.1 V to 3.4 V condition 3V < VIN < 5.5 V 520 0.01 500 850 73 65 30 20 80 70 1 100 Unit V C V mA mV % % mV mV mV mV A ms s mA
Settling time for programmed voltage switching Limitation current
Rail 4 DC/DC Converter 0.9 V, 1.2A
Rail4 is a programmable buck DC/DC converter dedicated to the supply of advanced core processing units. The default voltage is 0.9 V. Three other values can be programmed: 1.2 V, 0.87 V and 1.1 V. The entire cell is optimized for 0.9 V. When the cell is off, the output is in high impedance state. The application processor can change the output voltage, as stated above, via registers accessible by the SPI.
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Figure 20. Rail4 schematic
VDDPSU4
R4 Dcsense4 DH4 C8
DC/DC Converter 0.9V, 1.2A
L4
DL4 Trim dc4[1:0] T8 VOUT4
On dc4
Clk_dc4 C9
Table 12. Rail4 Preliminary External Components
Schematic Reference C8, C9 L4 R4 T8 Reference 22 F ceramic capacitor 2 x 22 F tantalum capacitor low ESR 4.7 H: SMT3106-47M (Gowanda) 100 m 2% 250 mW Si5513DC
Rail4 Electrical Specifications
Symbol VIN Parameter Operating Supply Voltage Temperature Range VOUT IOUT Output Voltage Output Current Ripple Voltage Eff36 Eff50 Efficiency Efficiency
Rail 4 can also operate at VIN = 2.85 V.
Table 13. Rail4 Electrical Specifications
Condition (0.9 V Selected) Min 2.97 -20 0 < ILOAD < 1200 mA, 3 V < VIN < 5.5 V 0.9 1200 ILOAD = 1.2 A, VIN = 3.6 V VIN = 3.6 V, ILOAD = 600 mA VIN = 5V, ILOAD = 600 mA 35 78 80 Typ Max 5.5 85 Unit V C V mA mV % %
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Table 13. Rail4 Electrical Specifications (Continued)
Symbol Parameter Static line regulation Static load regulation Transient line regulation Transient load regulation ICC tR tsettle ISC Powerdown Current Rise Time Settling time for programmed voltage switching Limitation current Condition (0.9 V Selected) tR = tF = 5 s, VIN from 3 V to 5.5 V, ILOAD = 1200 mA tR = tF = 5 s, VIN = 3 V and VIN = 5.5 V, ILOAD from 120 to 1200 mA tR = tF = 5 s, VIN from 3V to 5.5 V, ILOAD = 1200 mA tR = tF = 5 s, VIN = 3 V and VIN = 5.5 V, ILOAD from 120 to 1200 mA VIN = 5.5 V ILOAD = 1200 mA Full load, 0.84 V to 0.93 V condition 3V < VIN < 5.5 V 1200 50 2 Min Typ 20 10 35 85 1 3000 Max Unit mV mV mV mV A s s mA
900 kHz Oscillator and Clock Distribution
The 900 kHz oscillator provides the clock to all DC/DC converters. The clock distributor provides phased clocks to the DC/DC converters to avoid them switching at the same time. Figure 21. 900 kHz Oscillator Distribution
900 kHz Oscillator
Rail1 Oscillator
Rail2 Oscillator
Rail3 Oscillator
Rail4 Oscillator
Monitoring Voltage and Temperature Function
The AT73C203 integrates voltage monitoring and temperature monitoring functionality, thus enabling the application processor to know when an under-voltage or over-temperature error condition occurs. The application processor can control this situation by changing the thresholds and programming an interrupt or a reset in the event and error condition occurs. All the controls are performed via registers accessed via the SPI.
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Figure 22. Voltage and Temperature Monitoring Architecture
VOUT1 Interuption Reset
Current Register Measure Registers
VOUT2 Under Limit Registers Over Limit Registers VOUT3 Mask Registers IT or Reset Registers Status Registers
VOUT4
VBAT1 VBAT2 USB VDDPSU VOUT1 VOUT2 VOUT3 VOUT4 VTE1 VTE2 VTS Multiplexer and Attenuators 8 Bits ADC
Voltage Reference
Temperature Sensor
THERM1 T
THERM2 T
VMES
Analog to Digital Converter and Multiplexer
An internal 8-bit analog to digital converter is used to measure the different voltages. The analog to digital converter has eleven internal inputs listed as follows: * * * * * VBAT1 (internal battery) VBAT2 (external battery) USB (USB supply) VDDPSU (output of the power switch) VOUT1 (output of Rail1)
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AT73C203
* * * * * * VOUT2 (output of Rail2) VOUT3 (output of Rail3) VOUT4 (output of Rail4) VTE1 (voltage on thermistor 1) VTE2 (voltage on thermistor 2) VTS (output of the internal temperature sensor)
An external capacitor (C21) on VMES pin enables filtering of the ADC input and provides immunity to high frequency noise. These inputs are multiplexed into the analog to digital converter. This has a resolution of eight bits. The basic input range is 0.6 V to 2.25 V (typical) but the inputs have built-in attenuators to allow measurements without external components. Take note that no attenuator is present for VOUT1, VOUT4, VTE1, VTE2 and VTS.
Monitoring Voltage and Temperature Electrical Characteristics
Symbol RATBAT1 RATBAT2 RATUSB RVDDPSU ROUT2 ROUT3 Parameter Ratio VBAT1 Ratio VBAT2 Ratio USB
All bridge resistance values are given with 30% of global variations and mismatch values of less than 1%. All ratios will be confirmed during the design process.
Table 14. Monitoring Bridge (Attenuators) Electrical Specifications
Condition 0V / 5.5 V 0V / 5.5 V 0V / 5.5 V 0V / 2.5 V 0V / 3.4 V 0V / 5.5 V Min Typ 2.5 2.5 2.5 2.5 2.0 2.0 Max
Ratio VDDPSU Ratio VOUT2 Ratio VOUT3
Typical sensor characteristic law: V ( T ) = 1.31 - 3.6 x 10 Table 15. Temperature Sensor Electrical Specifications
Symbol VCC ICC DJ T T/ V/ V/ VTNOM Parameter Supply Voltage Supply current Temperature sense dynamic Absolute error Differential error Voltage dynamic range Sensor voltage sensitivity Sensor output voltage @27C = 27C = 55C 10% - 90%, = [45C, 55C] 10% - 90%, = [0C, 80C] VCC = 2.5 V Condition
-3
x ( T - 27 )
Min 2.4
Typ 2.5
Max 2.6 100
Units V A C C
0
80 10 5% 1
V mV/C V
1 1.23
20 1.33
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Figure 23. Typical Sensor Characteristics
Digital Core Function
By default, the digital core function is disabled. To enable it, the MON_ON bit in register MON_CR must be set to 1. A transition from 0 to 1 of MON_ON resets all the internal registers. When the digital core function is on, the internal digital core automatically starts the monitoring sequence. It cycles sequentially through the measurement of the analog inputs. Eight measurements are taken, then the digital core computes the average of these eight values to reduce noise before moving to the next input. Average values from these inputs are stored in value registers. These can be read out through the SPI bus. Measurements are updated every 2 ms (approximate). Table 16. Value Registers
MON_VBAT1_MEAS MON_VBAT2_MEAS MON_USB_MEAS MON_VDDPSU_MEAS MON_VOUT1_MEAS MON_VOUT2_MEAS MON_VOUT3_MEAS MON_VOUT4_MEAS MON_VTE1_MEAS MON_VTE2_MEAS MON_VTS_MEAS
To assure better accuracy, a calibration should be made during the printed circuit board test by injecting an accurate voltage into the analog inputs and checking the voltage read by the ADC. By comparing the voltage read by the ADC to the theoretical value stored in an external flash memory, the software can remove the internal offset.
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An automatic comparison is launched when the monitoring function is enabled. The digital core compares the measurement with programmed limits stored in the limit registers. Table 17. Limit Registers
MON_VBAT1_UNDL MON_VBAT2_UNDL MON_USB_UNDL MON_VDDPSU_UNDL MON_VOUT1_UNDL MON_VOUT2_UNDL MON_VOUT3_UNDL MON_VOUT4_UNDL MON_VTE1_UNDL MON_VTE2_UNDL MON_VTS_UNDL MON_VBAT1_OVL MON_VBAT2_OVL MON_USB_OVL MON_VDDPSU_OVL MON_VOUT1_OVL MON_VOUT2_OVL MON_VOUT3_OVL MON_VOUT4_OVL MON_VTE1_OVL MON_VTE2_OVL MON_VTS_OVL
The results of out-of-limit comparisons are stored in the status registers, which can be read over the SPI to flag an out-of-limit condition. Table 18. Status Registers
MON_SR1 MON_SR2
When an out-of-limit comparison occurs, an interrupt or a reset can be programmed via mask and interrupt/reset registers. Table 19. Mask and Interrupt /Reset Registers MON_MR1 MON_MR2 Thermistor Measurement MON_IR1 MON_IR2
Two external NTC thermistors are used to measure the temperature of the battery. The resistance of the NTC is proportional to the temperature. To measure the resistance and determine the temperature two 6-bit current DACs are integrated into the AT73C203. The software can program the current flowing through thermistors 1 and 2 via MON_VTE1_CURR and MON_VTE2_CURR registers and can then read back the voltage through MON_VTE1_MEAS and MON_VTE2_MEAS registers. The temperature can then be estimated by the microprocessor.
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Current DAC Electrical Specifications
The 6-bit DAC parameters are shown in Table 20 below.
Table 20. Current DAC Electrical Specifications
Symbol VTEXCURR<0> VTEXCURR<1> VTEXCURR<2> VTEXCURR<3> VTEXCURR<4> VTEXCURR<5> Lincurr Parameter VTEXCURR<0> VTEXCURR<1> VTEXCURR<2> VTEXCURR<3> VTEXCURR<4> VTEXCURR<5> Linearity IOUT = f(Rl) Rl: resistive load to ground VOUT = 0 to 2.35 V Condition Min 6 12 24 48 96 192 Typ 7.5 15 30 60 120 240 Max 9 18 36 72 144 288 2 Units A A A A A A %
Comparator Electrical Specifications
In parallel to the DAC, a comparator for each digital core supply rail (VOUT1, VOUT2, VOUT3 and VOUT4) is used as a real time supply rail brownout detector for a drop. The value of the comparator is not programmable but the threshold moves according to the voltage chosen. (Refer to the DC/DC converter specifications specific to each supply rail.)
Table 21. Comparator Electrical Specifications
Symbol VTEXCURR<0> VTEXCURR<1> VTEXCURR<2> VTEXCURR<3> Parameter VTEXCURR<0> VTEXCURR<1> VTEXCURR<2> VTEXCURR<3> Condition Min 6 12 24 48 Typ 7.5 15 30 60 Max 9 18 36 72 Units A A A A
USIM Interface
A Low Drop Out (LDO) voltage regulator provides an accurate power supply to the SIM card. Two nominal values can be programmed: 1.8 V or 2.8 V. It is supplied by VDDPSU. When the cell is off, the output is pulled to ground. The application processor can change the output voltage, as stated above, via registers accessible by the SPI. Figure 24. USIM Regulator
SIM Regulator 1.8 V 30 mA/2.8 V 50 mA
SIM_VCC C13
External components: 2.2 FX5R 10% output capacitor 38
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USIM 1.8 V Regulator Electrical Specifications
The USIM 1.8 V regulator complies with ETS TS 102 221, sections 5 and 6.
Table 22. USIM 1.8 V Regulator Electrical Specifications
Symbol VDDSIM Parameter Operating Supply Voltage Temperature Range VSIM IOUT VDROP Output Voltage Output Current Min Supply for SIM_VCC > 1.75 V ILOAD = 50 mA Transient Line Regulation Transient Load Regulation ICC ICC tR ISC VN Quiescent Current Powerdown Current Rise Time Limitation Current Output Noise tR = tF = 5 s, VDDSIM from 3V to 5.5 V, ILOAD = 30 mA tR = tF = 5 s, VIN = 2.97 V, ILOAD from 3 to 27 mA VDDSIM = 5.5V VDDSIM = 5.5V ILOAD = 30 mA 10% - 90% VOUT 3V < VDDSIM < 5.5 V BW: 10 Hz to 100 kHz Including bandgap noise 30 1 1.90 40 40 50 1 500 0 < ILOAD < 30 mA, 3 V < VDDSIM < 5.5 V Condition Min 2.97 -20 1.75 1.80 Typ Max 5.5 85 1.85 30 Units V C V mA V mV mV A A s mA mVrms
USIM 2.8 V Regulator Electrical Specifications
The USIM 2.8 V regulator complies with ETS TS 102 221, sections 5 and 6.
Table 23. USIM 2.8 V Regulator Electrical Specifications
Symbol VDDSIM Parameter Operating Supply Voltage Temperature Range VSIM IOUT VDROP Output Voltage Output Current Min Supply for SIM_VCC > 1.75 V ILOAD = 50 mA Transient Line Regulation Transient Load Regulation ICC ICC tR ISC VN Quiescent Current Powerdown Current Rise Time Limitation Current Output Noise tR = tF = 5 s, VDDSIM from 3V to 5.5 V, ILOAD = 30 mA tR = tF = 5 s, VIN = 2.97 V, ILOAD from 3 to 27 mA VDDSIM = 5.5V VDDSIM = 5.5V ILOAD = 30 mA 10% - 90% VOUT 3V < VDDSIM < 5.5 V BW: 10 Hz to 100 kHz Including bandgap noise 50 1 2.85 30 30 50 1 500 0 < ILOAD < 30 mA, 3 V < VDDSIM < 5.5 V Condition Min 2.97 -20 2.77 2.8 Typ Max 5.5 85 2.83 30 Units V C V mA V mV mV A A s mA mVrms
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2742A-PMGMT-09/03
Charger Control
The AT73C203 is able to control the charging of two Lithium Ion batteries from either a PSU or USB supply. Charging can occur in two different modes as follows: * * Stand-alone mode. The AT73C203 preconditions the battery independently of the application processor (the application processor is not powered up). Controlled mode. The application processor controls the charging phases via registers accessed via the SPI.
Figure 25. Charger Control Schematic
USB USB_CH T11 PSU D5 D4 BATsensep R6 BATsensem BAT1_Ch_on T10 C15 Charger Control BAT1_Ch Digital Control USB_Ch_en
Battery1
BAT2_Ch_on T9 C14
BAT2_Ch
Battery2
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Table 24. Charger Preliminary Components
Schematic Reference BAT1 BAT2 C14, C15 D4, D5 R6 T7 T11 Reference Li-ion battery 4.2 V-3.0 V. Permanently connected to module Li-ion battery 4.2 V-3.0 V. Optional battery 10 nFX56 10% ceramic capacitor MBRA120LT3 (ON Semiconductor) 200 m +/- 2% 50 mW Si8401DL Si1405DL
Charge Principles
Stand-alone Mode The stand-alone mode occurs only when the USB is plugged in and there is no battery 2 (or it is flat) and battery 1 is flat and the PSU unplugged. (See"State Machine Description" on page 15 and Figure 28 on page 44).The AT73C203 can then choose to precharge battery 1 if the temperature range is within limits. The stand-alone mode is terminated if the charge timer expires or if the voltage of battery 1 goes above 3.8 V. The digital core (via the USB_SCR register) can put the AT73C203 into a mode in which the digital core is off and battery 1 is charged (25 mA) through the USB until 4.1 V. Figure 26. Stand-alone Mode
Voltage Stand-alone Mode
3.8 V
Time Current T < Timer for Stand-alone Mode
25 mA
Time
Controlled Mode
After the digital reset phase, the application processor can launch a charge phase. By default the charge phase is stopped when the application processor wakes up.
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The charge control includes three charging phases (preconditioning, fast charge and pulsed charge) during which the application processor must check via the monitoring function that the operating temperature is within allowable limits for battery charging. Figure 27. Controlled Mode
Voltage Preconditioning Phase Fast Charge Phase Pulsed Charge Phase
Preconditioning Voltage
Time Current T < Timer for Preconditioning T < Timer for Fast Charge T < Timer for Pulsed Phase
Fast Charge Current
25 mA
Time
Preconditioning Phase
Battery 1 and Battery 2 can be preconditioned to a predetermined voltage from either the PSU or USB source. Precondition current is set to 25 mA. To enable the precondition phase, the application processor must use the charger control register. To program the preconditioning voltage threshold, the application processor must use an interrupt, which can be programmed for battery 1 and battery 2 with the over limit registers included in the monitoring function. A safety timer (CHA_STR_CR) can be launched during this phase. If the safety timer expires, an interrupt is launched and the pre-conditioning phase is automatically stopped. If the pre-conditioning voltage threshold has been reached, the application processor should put the charger into the fast charge phase.
Fast Charge Phase
To enable the fast charge phase, the application processor must use the charger control register. The battery is charged at a constant current that can be adjusted (CHA_CURR in the CHA_MR in register). Note that battery 1 and battery 2 can not be in the fast charge phase at the same time. The fast charge is automatically stopped when the battery voltage reaches the regulation voltage. The regulation voltage can be trimmed. By default, the voltage is 4.2 V. When this voltage is reached an interrupt is sent to warn the microprocessor.
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A safety timer (CHA_STR_CR) can be launched during this phase. Pulsed Charge Phase To enable the pulsed charge phase, the application processor must use the charger control register. Note that battery 1 and battery 2 can not be in pulsed charge phase at the same time. The charger control uses a hysteretic algorithm with minimum on-times and minimum off-times of the external PMOS. These minimum on-times and off-times can be programmed via registers CHA_TMINON and CHA_TMINOFF. The battery voltage is sampled every 0.3 millisecond (typical). If the battery voltage is less than the battery regulation voltage, the external PMOS FET either turns on or, if already on, remains on. If the battery voltage is greater than, or equal to, the regulation voltage threshold, the FET either turns off or, if already off, remains off until the next sample. At the beginning of the pulsed charge phase, the current stays on for many consecutive cycles between single off periods. As the battery continues to charge, the percentage of time spent in the "current-on" mode decreases. At the end of the pulsed phase, the current stays off for many cycles between single "on" pulses. This phase is automatically stopped when the duty ratio of "on" cycles to "off" cycles falls below a threshold which must be programmed trough register CHA_TR. Additionally, an interrupt is sent to warn the microprocessor. For safety, a timer (CHA_STR_CR) can be launched during this phase. If this timer expires, an interrupt is launched and the pulsed charge phase is automatically stopped. The "Start-up State Machine Pulsed Charge Phase" shown in Figure 28 on page 44 presents a summary of the pulsed charge phase. Refer also to the "State Machine Description" on page 15 for more information on the pulsed charge phase. The parameters (CHA_TMINON, CHA_TMINOFF and CHA_TR) can be trimmed in order to be adapted to the battery. To properly choose the parameters, a test must been done with the real battery. At the end of top-off mode, it is preferable to use a small current (100 mA). A good default value seems to be 200 ms for CHA_TMINON and CHA_TMINOFF and a duty cycle threshold of 1/64.
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Figure 28. Start-up State Machine Pulsed Charge Phase
Pulse Charge Phase Selected
Wait for the end of minimum on-time timer PMOS on PMOS_ON Charger minimum on-time timer launched 1 Battery voltage > regulation voltage and minimum on-time timer has expired Battery voltage > regulation voltage and minimum on-time timer has expired 2 End of pulsed charge phase 3 Duty Cycle PMOS_ON/PMOS_OFF < CHA_DUTY 1 Wait for the end of minimum off-time timer 2 Duty Cycle PMOS_ON/PMOS_OFF < CHA_DUTY 3
END_CHARGE
PMOS off PMOS_OFF Charger minimum off-time timer launched
Watchdog
For safety, during any phase of the controlled mode a watchdog is launched automatically. The application processor must rearm the watchdog via the charger control register, CHA_CR, at least every 13 s. If during 13 s (typical time), the watchdog has not been rearmed, the charge is stopped.
Charger Control Electrical Specifications
Table 25. Charger Control Electrical Specifications
Symbol PSU USB IPRECOND ICH Parameter Charger Voltage USB Voltage Preconditioning Current Charge Current USB or PSU CHA_CURR = 11 CHA_CURR = 10 CHA_CURR = 01 CHA_CURR = 00 VREGTH Regulation Voltage Threshold CHA_VOLT_TRIM =000 CHA_VOLT_TRIM =001 Condition Min 4.90 4.62 Typ 5.0 5.0 25 500 300 200 100 4.20 4.170 Max 5.10 5.25 Units V V mA mA mA mA mA V V
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Table 25. Charger Control Electrical Specifications (Continued)
Symbol Parameter Condition CHA_VOLT_TRIM = 010 CHA_VOLT_TRIM = 011 CHA_VOLT_TRIM = 100 CHA_VOLT_TRIM = 101 CHA_VOLT_TRIM = 110 CHA_VOLT_TRIM = 111 Hystbat1 Input hysteresis Timer for stand alone mode Threshold voltage for stand alone mode tACCURACY ICC Timing accuracy Current consumption Min Typ 4.130 4.10 4.23 4.26 4.30 4.07 2 1 3.8 25 1 Max Units V V V V V V mV h V % mA
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2742A-PMGMT-09/03
Package Outline (Top View)
Figure 29. 10 x 10 balls, 0.8mm Pitch BGA Package on 9 x 9mm Body Size for AT73C203
1 A
AVSS
2
nEN_RAIL4
3
nEN_RAIL3
4
SYST_CLK
5
SCAN_ENABLE
6
VSW
7
THERM2
8
CREF
9
VREFFUSE
10
MAXSUPPLY
B
SELDC25
SELDC175
NC
NC
nSHUTDOWN
VSWIN
GNDA
VMES
GND_PIO
PSU_PIO
C
nBOARD_RESET
BOARD_RE SET
nASIC_RESET
SCAN_TEST_MD
PCMCIA
VSAUV
THERM1
VBIAS
BAT2_PIO
GAPSU
D
nASIC_RESET _REQUEST
POWER_EN
nPROC_RES ET_OUT
nPROC_RESET
BUTTON_IN
USB_PIO
PORTEST
BAT1_PIO
GABAT2
USB_CH
E
nUSIM_INT
nINT
BUTTON_OUT
NC
nSEN
GND_CH
GABAT1
USB_CH_EN
BATSENSEP
BATSENSEM
F CHG_INHIBIT
TEST1
TEST2
IDBITS2
NC
NC
BAT2_CH
BAT1_CH_ON
BAT2_CH_ON
BAT1_CH
G
IDBITS3
IDBITS1
SDO
VDDPSU3
VDDPSU2
VDDPSU1
SIM_IO
SIM_VCC
SIM_PRES
VDDPSU
H
IDBITS0
SDI
GNDDC3
DCSENSE3
DCSENSE2
DCSENSE1
NC
NC
SIM_RESET
SIM_CLK
J
SCLK
VBOOST
DL3
GNDDC2
DL2
GNDDC1
DL1
DL4
GNDDC4
VOUT4
K
GNDDIG
VOUT3
DH3
VOUT2
DH2
VOUT1
DH1
DH4
DCSENSE4
VDDPSU4
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Package Specification
Figure 30. AT73C203 Package Specification
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2742A-PMGMT-09/03
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2742A-PMGMT-09/03

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