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| CXK77V1840GB -8/10/12 262,144-Word by 18-bit High Speed CMOS Synchronous Static RAM Description The CXK77V1840GB is a high speed CMOS synchronous static RAM with common I/O pins, organized as 262,144-words by 18-bits. This synchronous SRAM integrates input registers, high speed SRAM and output registers onto a single monolithic IC. All input signals except OE are latched at the positive edge of an external clock (CLK). The RAM data from the previous cycle is presented at the positive edge of the subsequent clock cycle. Write operation is initiated by the positive edge of CLK and is internally self-timed. This feature eliminates complex off-chip write pulse generation and provides increased flexibility for incoming signals. Asynchronous OE adds the flexibility of data bus control. 125 MHz operation is obtained from a single 3.3 V power supply. Preliminary 119 pin BGA (Plastic) Features * Fast cycle time: (Cycle) (Frequency) CXK77V1840GB-8 8 ns 125 MHz CXK77V1840GB-10 10 ns 100 MHz CXK77V1840GB-12 12 ns 83.3 MHz * Fast clock to data valid CXK77V1840GB-8 4 ns CXK77V1840GB-10 5.5 ns CXK77V1840GB-12 7.5 ns * High speed, low power consumption * Single +3.3 V power supply: 3.3 V +10 % -5 % * Inputs and outputs are LVTTL/LVCMOS compatible * Byte Select capability * Asynchronous OE * Common data input and output * All inputs (except OE) and outputs are registered on a single clock edge * Self-timed write cycle * Package CXK77V1840GB 7 x 17 Plastic Ball Grid Array with 50 mil pitch Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. --1-- PE96748-TE CXK77V1840GB Block Diagram CLK A0 CE WE UB LB ******* Register A17 Register CK Decoder CK ******* Self-Timed Write Logic 256k x 18 RAM OE CK Register Sense Amp CK Register DQ 0 to DQ 8 DQ 9 to DQ 17 --2-- Register CK CXK77V1840GB Pin Configuration (Top View) CXK77V1840GB 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQ8 NC VDDQ NC DQ5 VDDQ NC DQ3 VDDQ DQ1 NC NC NC VDDQ 2 A0 NC A1 NC DQ7 NC DQ6 NC VDD DQ4 NC DQ2 NC DQ0 A16 A17 NC 3 A2 A3 A4 VSS VSS VSS LB VSS NC VSS VSS VSS VSS VSS NC A15 NC 4 NC NC VDD NC CE OE NC NC VDD CLK NC WE A13 A14 VDD NC NC 5 A5 A6 A7 VSS VSS VSS VSS VSS NC VSS UB VSS VSS VSS NC A12 NC 6 A8 NC A9 DQ9 NC DQ11 NC DQ13 VDD NC DQ15 NC DQ16 NC A10 A11 NC 7 VDDQ NC NC NC DQ10 VDDQ DQ12 NC VDDQ DQ14 NC VDDQ NC DQ17 NC NC VDDQ Pin Description Symbol A0 to A17 DQ0 to DQ8 DQ9 to DQ17 VDD VDDQ VSS Description Address input Lower Byte Data input/output Upper Byte Data input/output +3.3 V power supply +3.3 V output power supply Ground Symbol CLK LB UB CE WE OE Description Clock input Lower Byte enable input Upper Byte enable input Chip Enable input Write Enable input Output Enable input For proper operation, VDD VDDQ at all times including power up. --3-- CXK77V1840GB Absolute Maximum Ratings Item Supply voltage Input voltage Output voltage Allowable power dissipation Operating temperature Storage temperature Soldering temperature time Symbol VDD VIN VO PD Topr Tstg Tsolder Rating -0.5 to +4.6 -0.5 to VCC +0.5 (4.6 V max.) -0.5 to VCC +0.5 (4.6 V max.) 1.7 0 to 70 -55 to 150 235 * 10 (Ta=25 C, GND=0 V) Unit V V V W C C C * sec Truth Table CE (tn) H L L L L L L L L WE (tn) X H H H H H L L L UB (tn) X X H L H L L H L LB (tn) X X H L L H L L H OE X H X L L L X X X Mode Deselect Read, output Hi-z Read bits 0-17 Read bits 0-8 Read bits 9-17 Write bits 0-17 Write bits 0-8 Write bits 9-17 DQ0-17 (tn) Don't care Don't care Don't care Don't care Don't care Din (tn) Din (tn) Din (tn) DQ0-17 (tn +1) Hi-Z Hi-Z DOUT (tn) DOUT (tn) DOUT (tn) Hi-Z Hi-Z Hi-Z VDD Current ISB ICC ICC ICC ICC ICC ICC ICC DC Recommended Operating Conditions Item Supply voltage Output supply voltage Input high voltage Input low voltage Symbol VDD VDDQ1 VIH VIL Min 3.135 3.135 2.0 -0.32 Typ 3.3 3.3 -- -- (Ta=25 C, GND=0 V) Max 3.6 3.6 VDD +0.32 0.8 Unit V V V V 1 VDDQ must be VDD at all times including power up 2 VIL=-1.5 V Min. and VIH=VDD +1.5 V for pulse width less than 5 ns. --4-- CXK77V1840GB Electrical Characteristics * DC and Operating characteristics Item Input leakage current Output leakage current Operating power supply current Symbol ILI ILO (VDD=3.3 V +10 % -5 %, GND=0 V, Ta=0 to 70 C Test Conditions VIN=GND to VDD VO=GND to VDD OE=VIH Cycle=min. -8 Duty=100 % -10 Iout=0 mA -12 CE VIH -8 Cycle=min. -10 Duty=100 % -12 Iout=0 mA IOH=-2.0 mA IOL=2.0 mA Min -1 -1 -- -- -- -- -- -- 2.4 -- Typ1 -- -- -- -- -- -- -- -- -- -- Max 1 1 3302 2702 2502 2602 2002 2002 -- 0.4 V V mA Unit A A ICC mA Standby Current ISB Output high voltage Output low voltage VOH VOL 1 VDD=3.3 V, Ta=25 C 2 For Address increment pattern only * I/O capacitance Item Input capacitance Output capacitance Clock input capacitance Symbol CIN COUT CCLK Test conditions VIN=0 V VOUT=0 V VIN=0 V Min -- -- -- (Ta=25 C, f=1 MHz) Max 7 10 8 Unit pF pF pF Note) These parameters are sampled and are not 100 % tested. --5-- CXK77V1840GB * AC ELECTRICAL CHARACTERISTICS Item Clock period Clock pulse high Clock pulse low Setup time Hold time Clock to output Clock to output high impedance Clock to output low impedance OE to output OE to output high impedance OE to output low impedance Symbol tCP tCH tCL tS tH tCQ tHZ2 tLZ2 tOE tOHZ2 tOLZ2 -8 Min 8 2.5 2.5 1.5 0.5 1 -- 1 1 -- 0.5 Max -- -- -- -- -- 4 3.5 -- 3.5 3.5 -- Min 10 3.5 3.5 2.5 0.5 1 -- 1 1 -- 0.5 -10 Max -- -- -- -- -- 5.5 5 -- 5 4.5 -- Min 12 4.5 4.5 3 0.5 1 -- 1 1 -- 0.5 -12 Max -- -- -- -- -- 7.5 6 -- 5 5.5 -- Unit ns ns ns ns ns ns ns ns ns ns ns 1. All parameters are specified over the range 0-70 C 2. These parameters are measured at 200 mV from steady voltage with output load (2). 3. They are sampled and are not 100 % tested. AC characteristics * AC test conditions (VDD=3.3 V +10 % -5 %, Ta=0 to 70 C) Item Input pulse high level Input pulse low level Input rise time Input fall time Input reference level Output reference level Output load conditions Conditions VIH=2.4 V VIL=0.4 V 1 V/ns 1 V/ns 1.4 V 1.4 V Fig. 1 I/O Output Load (1) Output Load (2)2 3.3V 50 I/O 50 5pF1 1.4V 1178 868 [1] Including scope and jig capacitance. [2] For tLZ, tHZ, tOLZ, tOHZ. --6-- CXK77V1840GB Timing Waveform * Read Cycle CLK tS n tH tCP tCH tCL A0-A17 n+1 n+2 WE tS tH CE/UB/LB OE (VIL) tCQ DQ0-DQ17 Qn-2 Qn-1 tLZ Qn --7-- CXK77V1840GB * Write Cycle CLK tS n tH n+1 n+2 A0-A17 CE/UB/LB WE OE DQ0-DQ17 Dn Dn+1 Dn+2 --8-- CXK77V1840GB * Read/Write Cycle (CE/UB/LB control) CLK A0-A17 N N+1 N+2 N+3 N+4 CE/UB/LB WE tS tH OE (VIL) tCQ DQ0-DQ17 QN-1 tHZ tS tH DN+2 tCQ QN+3 * Read/Write Cycle (OE control) CLK A0-A17 N N+1 N+2 N+3 N+4 CE/UB/LB (VIL) WE OE tOHZ DQ0-DQ17 QN-1 tS tH DN+2 tOE tCQ QN+3 --9-- CXK77V1840GB Package Outline Unit : mm 119 TERMINAL BGA (PLASTIC) 2.1 B X S 0.84 14.0 13.0 A 0.6 3.19 U T R P N M L K J H G F E D C B A 7.62 1.27 0.35 S 22.0 1.27 3- C1 .0 X4 0.20 C1 .5 0.6 12 3 45 6 7 0.75 0.15 0.4 0.2 S S AB 0.15 S DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE BGA-119P-02 BGA119-P-1422-1.27 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN COPPER-CLAD LAMINATE SOLDER 1.1g --10-- 20.32 21.0 47 1. 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