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CXD2436Q
Timing Generator for LCD Panels
Description The CXD2436Q is a timing signal generator for the VGA LCD panel LCX012 driver. This chip has a built-in serial interface circuit which allows the mode to be switched with respect to various VGA signals through direct control from an external microcomputer, etc. Features * Generates the LCX012 drive pulse. * Supports three-panel projectors. * Built-in serial interface circuit * Supports various VGA signals. (non-interlaced mode) * * * * * Built-in 2-line pair drive circuits Supports NTSC and PAL systems. Supports up/down and/or right/left inversion. Supports line inversion and field inversion. Generates timing signal of external sample-andhold circuit. 100 pin QFP (Plastic)
Absolute Maximum Ratings (Ta=25 C) * Supply voltage VDD VSS-0.5 to +7.0 * Input voltage VI VSS-0.5 to VDD+0.5 * Output voltage VO VSS-0.5 to VDD+0.5 * Operating temperature Topr -20 to +75 * Storage temperature Tstg -55 to +150 Recommended Operating Conditions * Supply voltage VDD +4.5 to +5.5 * Supply voltage VCC -20 to +75
V V V C C
Applications LCD projectors, etc. Structure Silicon gate CMOS IC
V C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
--1--
E95810-TE
CXD2436Q
Block Diagram
3
28 53 78
4
15
29
40
42
45
46
47
48
49
51
52
54
65
79
90
22
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VSS
VSS
VSS
NC
32
PWM
EXT-CKI CKI
30
31
PEO
34
DIRECT CLEAR MASTER CLOCK
8 XCLR 9 PLNT
10 18
CKO
33
36
VGAV SLSY SLCKI RPD FPD TC
HPOL 6 VPOL 7 PLL PHASE COMPARATOR CSYNC 5 HD2IN VD2IN
16 17
35 38
H-SYNC DETECTOR H-SKEW DETECTOR
39
HD1IN 1 VD1IN 2 TST1 TST2 TST3 TST4 TST5 TST6 TST7 TST8 TST9 TST10 VCK VST1 VDO SLDWN SLMNB
14 20 21 23 24 25 26 27 37 50 92 93 72 11 19
PLL COUNTER
68 69 73 74
HDN XHDN HDO XHDO SCK SI CS PO0 PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11
41
V-SYNC SEPARATOR V-RESET PULSE GENERATOR SERIAL INTERFACE V-RESET PULSE GENERATOR
43 44
55 56 57 58 59 60 61
V-POSITION COUNTER
H-POSITION COUNTER
62 63 64 66
V-TIMING PULSE DWN PRG XCLP1 XCLP2 HST HCK1 HCK2 CLR ENB INT PCG SH1 SH2 SH3 SH4 SH5 SH6 SH7
71 75 76 77 84 85 86 87 88 89 91 94 95 96 97 98 99 100
H-TIMING PULSE GENERATOR
67
GENERATOR & PULSE ELIMINATOR
12 82 83
SLRGT RGT XRGT
FIELD & LINE CONTROLLER
AUX-VD COUNTER
80 81 70 13
FRP XFRP FLD SLFR
--2--
CXD2436Q
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Symbol HD1IN VD1IN VDD VSS CSYNC HPOL VPOL XCLR PLNT VGAV SLDWN SLRGT SLFR TST1 VSS HD2IN VD2IN SLSY SLMNB TST2 TST3 N.C. TST4 TST5 TST6 TST7 TST8 VDD VSS EXT-CKI PEO PWM CKO CKI RPD SLCKI TST9 FPD I/O I I -- -- I I I I I I I I I I -- I I I I I I -- -- -- -- -- -- -- -- I I/O I I/O I O I I O Description Hsync input (VGA) Vsync input (VGA) Power supply GND Composite sync input (NTSC/PAL) HD, CSYNC polarity identification input (High: positive polarity, Low: negative polarity) VD, CSYNC polarity identification input (High: positive polarity, Low: negative polarity) External clear (all clear when Low) PAL/NTSC switching (High: NTSC, Low: PAL) VGA (NTSC/PAL) switching (High: VGA, Low: NTSC/PAL) Up/down inversion discrimination signal input (High: Down, Low: Up) Right/left inversion discrimination signal input (High: Normal, Low: Reverse) 1H/1F inversion switching (High: 1H, Low: 1F) Test pin (Not connected or High.) GND HD2 input (for NTSC/PAL separate-sync) VD2 input (for NTSC/PAL separate-sync) SYNC input switching (High: CSYNC, Low: HD2IN and VD2IN) Switches mode (High: Nothing, Low: 400 480 line conversion) Test pin (Not connected or High.) Test pin (Connect to GND.) N.C. Test pin (Not connected or High.) Test pin (Not connected or High.) Test pin (Not connected or High.) Test pin (Not connected.) Test pin (Connect to GND.) Power supply GND External clock input Loop filter integrator output Loop filter integrator input Oscillation cell output (NTSC/PAL) Oscillation cell input (NTSC/PAL) Phase comparator output (NTSC/PAL) Clock input selection (High: CKI, Low: EXT-CKI) (NTSC/PAL mode only) Test pin (Not connected or High.) Phase comparator output (NTSC/PAL) Input pin for open status -- -- -- -- -- H H H H H H H H H -- -- -- H H H H -- -- -- -- -- -- -- -- -- -- -- -- -- -- H H --
--3--
CXD2436Q
Pin No. 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82
Symbol TC VSS SCK VSS SI CS VSS VSS VSS VSS VSS TST10 VSS VSS VDD VSS PO0 PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 VSS PO10 PO11 HDN XHDN FLD DWM VDO HDO XHDO PRG XCLP1 XCLP2 VDD VSS FRP XFRP RGT
I/O I/O -- I -- I I -- -- -- -- -- I -- -- -- -- O O O O O O O O O O -- O O O O O O O O O O O O -- -- O O O
Description FPD pin pulse width adjustment GND Serial interface clock input GND Serial interface data input Serial interface chip select GND GND GND GND GND Test pin (Not connected or High.) GND GND Power supply GND Serial I/O data output Serial I/O data output Serial I/O data output Serial I/O data output Serial I/O data output Serial I/O data output Serial I/O data output Serial I/O data output Serial I/O data output Serial I/O data output GND Serial I/O data output Serial I/O data output Phase comparator output (positive polarity) Phase comparator output (negative polarity) Field discrimination signal output Up/down inversion discrimination signal output VD pulse output (positive polarity) HD pulse output (positive polarity) HD pulse output (negative polarity) Precharge signal pulse (positive polarity) Pedestal clamp pulse 1 Pedestal clamp pulse 2 Power supply GND AC drive inversion timing output AC drive inversion timing output Right/left inversion discrimination signal output
Input pin for open status -- -- H -- L H -- -- -- -- -- H -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--4--
CXD2436Q
Pin No. 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Symbol XRGT HST HCK1 HCK2 CLR ENB INT VSS PCG VCK VST1 SH1 SH2 SH3 SH4 SH5 SH6 SH7
I/O O O O O O O O O O O O O O O O O O O
Description Right/left inversion discrimination signal output H start pulse output (positive polarity) H clock pulse 1 output H clock pulse 2 output CLR pin output ENB pin output INT pin output GND PCG pin output (positive polarity) V clock pulse output V start pulse output Sample-and-hold pulse 1 (positive polarity) Sample-and-hold pulse 2 (positive polarity) Sample-and-hold pulse 3 (positive polarity) Sample-and-hold pulse 4 (positive polarity) Sample-and-hold pulse 5 (positive polarity) Sample-and-hold pulse 6 (positive polarity) Sample-and-hold pulse 7 (positive polarity)
Input pin for open status -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Electrical Characteristics 1. DC characteristics Item Symbol Supply voltage VDD VIH1 Input voltage 1 VIL1 VIH2 Input voltage 2 VIL2 VT+ -VT+ VOH Output voltage 1 VOL VOH Output voltage 2 VOL VOH Output voltage 3 VOL VOH Output voltage 4 VOL Input leak IIL current IIH Output leak ILZ current Current IDD consumption
Conditions
CMOS input cell CMOS Schmitt trigger input cell IOH=-2 mA IOL=4 mA IOH=-4 mA IOL=8 mA IOH=-6 mA IOL=12 mA IOH=-3 mA IOL=3 mA Pull-up resistor connected Pull-down resistor connected High impedance status fclk=31 MHz VDD=5.0 V
Min. 4.5 0.7 VDD 0.8 VDD
Typ. 5.0
0.6 VDD-0.8 VDD-0.8
(Temperature = 25 C, VSS = 0 V) Max. Unit Applicable pins 5.5 V Input pins other than V 0.3 VDD those noted below HDnIN, VDnIN, CSYNC, 0.2 VDD V CKI, PWM, TC, PEO, CKO, SI, SCK, CS Output pins other than V 0.4 those noted below 0.4 V V V A VCK HCKn, SHn, HST CKO, PEO 1 SI
VDD-0.8 0.4 VDD/2 VDD/2
-40 -100 -240
40
-40
100
240 40
A RPD, FPD mA At no load
55
1 Input pins with pull-up resistors HPOL, VPOL, XCLR, PLNT, VGAV, SLDWN, SLRGT, SLFR, TST1, SLSY, TST2, TST3, SLCKI, TST9, SCK, CS --5--
CXD2436Q
2. AC characteristics Item Clock input cycle Cross-point time difference Output rise delay Output fall delay Output rise delay Output fall delay HCK1, SH1 delay time difference HCK2, SH1 delay time difference HCK1 duty HCK2 duty Applicable pins EXT-CKI, CKI HCK1, 2 HCKn, SHn HCKn, SHn Other than HCKn and SHn Other than HCKn and SHn HCK1, SH1 HCK2, SH1 HCK1 HCK2 Symbol t tpr tpf tpr tpf dt1 dt2 tH/tH+tL tH/tH+tL Conditions CL=30 pF CL=30 pF CL=30 pF CL=30 pF CL=30 pF CL=30 pF CL=30 pF CL=30 pF CL=30 pF
(VDD=5.0 V0.5 V, VSS=0 V) Min. 25 -10 Typ. Max. 10 20 20 30 30 10 10 48 48 50 50 52 52 Unit ns ns ns ns ns ns ns ns % %
VDD EXT-CKI/CKI 0V VDD
90% Output tpr
0V
VDD Output 10% tpf 0V
VDD HCK1 50% 50% 0V
VDD HCK2 50% 50% 0V t t
--6--
CXD2436Q
EXT-CKI /CKI
HCK1 HCK2
50% t2 tH
50%
50%
t1
tL
SH1
50%
50%
dt1
dt2
(SLRGT=H, SHP0/SHP1/SHP2/SHP3=L)
3. Serial interface block AC characteristics
SCK
50%
tw1 tw1
50%
50%
50%
SI (DATA)
50%
ts1
th1
50%
CS
50%
ts0
50%
th0
th1
(VDD=5.0 V0.5 V, VSS=0 V, Topr=-20 to +75 C Symbol ts1 th1 tw1 ts0 th0 th1 Item SI setup time with respect to rise of SCK SI hold time with respect to rise of SCK SCK pulse width CS setup time with respect to rise of SCK CS hold time with respect to rise of SCK SCK high-level hold time with respect to rise of CS Min. 200 ns 200 ns 200 ns 200 ns 200 ns 200 ns Max.
2tw1 2tw1
--7--
CXD2436Q
LCD Panel Structure The structure of LCD panels (LCX012AL) driven by this IC is shown below. The dot arrangement is a square arrangement, and the shaded region within the diagram is not displayed.
Gate SW1
Gate SW2
Gate SW109
Sig6
Sig2
Sig3
Sig4
Sig6
Sig3
Sig1
Sig4
Sig1
Sig3
Sig2
Sig5
Sig1
VSR1 VSR2 VSR3 VSR4 VSR5 VSR6
Sig4
Sig5
Sig2
Sig5
Sig6
Photo-shielding area
Display area
484
VSR 483 VSR 484 VSR 485 VSR 486 VSR 487 VSR 488 5 644 654 5
1
* The effective pixels are horizontal: 644 pixels and vertical: 484 pixels. * The horizontal pixel start position is from Sig6 of the first-stage scanner. (Sig1 to Sig5 of the first-stage scanner are the photo-shielding area and are not displayed.) * The vertical pixel start position is from the third-stage scanner. * These relationships are the same even during up/down and/or right/left inversion. (The entire area within the panel is inverted.)
--8--
1
486
CXD2436Q
Description of Operation * Sync input pins The CXD2436Q has three types of sync input pins. Pin No. 1 2 5 16 17 Symbol HD1IN VD1IN CSYNC HD2IN VD2IN SLSY setting -- H L Application SYNC input pins for VGA CSYNC input pin for NTSC/PAL Separate SYNC input pins for NTSC/PAL
* Clock input pins The CXD2436Q has two clock input pin systems to support two types of PLL circuits. 1) When using EXT-CKI (using an external PLL IC) The 1/N frequency divider output is output from the HDN and XHDN pins for the external PLL IC. The used pins are shown in the following table. (SLCKI = Low)
Pin No. 30 68 69
Symbol EXT-CKI HDN XHDN
Application Clock input Phase comparison output (positive polarity) Phase comparison output (negative polarity)
HSYNC
HDN OUTPUT 400 clk
2) When using CKI This system uses the built-in phase comparator and an externally attached VCO circuit (see the Application Circuit). This system is used during AV mode (NTSC/PAL). The used pins are shown in the following table. (Effective when SLCKI is set to High.) Pin No. 31 32 33 34 35 38 39 Symbol PEO PWM CKO CKI RPD FPD TC
HSYNC
Application Loop filter integrator output Loop filter integrator input Clock output (oscillation cell output) Clock input (oscillation cell input) Phase comparator output Phase comparator output FPD pin pulse width adjustment
RPD
An outline of the output waveforms during PLL lock is shown in the figure to the left.
FPD
--9--
CXD2436Q
* Connections supporting up/down and/or right/left inversion The CXD2436Q is designed for use with three-panel projectors, and has a system configuration which permits both normal and reverse scan. The RGT and XRGT output to the panel are switched according to the SLRGT input, and the DWN output is switched according to the SLDWN input in the same manner.
LCX012 RGT DWN SLRGT 12 82 83 SLDWN 11 71 DWN DWN LCX012 RGT Example of supporting a three-panel system DWN Reverse scanning panel RGT XRGT Normal scanning panel
LCX012 RGT
Normal scanning panel
* AC driving of LCD panels for no signal The following measures have been adopted to allow AC driving of LCD panels even when there is no signal. * Horizontal direction pulse: The PLL is set to free running status. Therefore, the frequency of the horizontal direction pulse is dependent on the PLL free running frequency. * Vertical direction pulse: The number of lines is counted by an internal counter and VST and FRP are output at a specified cycle. * VST cycle for no signal * Free running detection timing NTSC PAL VGA 269H 321H 526H NTSC PAL VGA 291H 339H 873H
Free running operates at the following cycles. (No signal is judged if there is no VSYNC input for longer than the following periods.) * Description of the MODE selector switch * VGA/AV (NTSC/PAL) switching is performed with two pins. VGAV H H L L PLNT H L H L MODE VGA VGA NTSC PAL
* The HD1IN, HD2IN, VD1IN, VD2IN and CSYNC input polarities are supported by two pins. HPOL H H L L VPOL H L H L HD1IN HD2IN Positive polarity Positive polarity Negative polarity Negative polarity VD1IN VD2IN Positive polarity Negative polarity Positive polarity Negative polarity CSYNC Positive polarity -- -- Negative polarity
--10--
CXD2436Q
* XCLR (External clear) Reset should be performed during startup in order to initialize the serial interface. Performing external clear sets all serial interface modes to Low. * Serial interface specifications The CXD2436Q can set and switch the driving mode with the serial interface. Set the corresponding timing data for each VGA signal according to the format in the diagram below. Be sure to make the initial mode settings. (See the AC characteristics for detailed timing specifications.)
CS
SCK
SI
D0
D1
D2
D3
D4
D5
D6
D7
Fig. 1. Timing chart for the serial interface input block Note) D0 to D7 internal transfer is completed by the CS signal switching from a Low to High pulse. Therefore, the data should be transferred in 1-byte units with the CS signal reset each time. * Description of mode switching settings using the serial interface The CXD2436Q can set the following six modes. (1) Frequency division ratio setting for the 1/N frequency divider of the master clock PLL circuit block. (2) H screen center adjustment. The center changes by one dot with LSB. (3) V screen center adjustment. The center changes by one line with LSB. (4) Sample-and-hold circuit phase adjustment. The phase changes by a half-dot with LSB. (See the Description of Sample-and-Hold Timing for details.) (5) Clamp pulse timing adjustment (4-way) (6) Data output (Serial data is held and output.) Upper 4-bit address value D7 to D4 0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH Lower 4-bit data D3 PHP3 PHP7 -- HP3 -- VP3 -- SHP3 -- PO3 PO7 PO11 D2 PHP2 PHP6 PHP10 HP2 HP6 VP2 VP6 SHP2 -- PO2 PO6 PO10 D1 PHP1 PHP5 PHP9 HP1 HP5 VP1 VP5 SHP1 CLPP1 PO1 PO5 PO9 D0 PHP0 PHP4 PHP8 HP0 HP4 VP0 VP4 SHP0 CLPP0 PO0 PO4 PO8 --11-- Functions
PLL 1/N frequency divisions H screen center adjustment V screen center adjustment S/H timing Clamp timing Data output PHP0, HP0, VP0, SHP0, CLPP0
CXD2436Q
* PLL 1/N frequency division ratio setting For the frequency division ratio setting during VGA mode, set the value of the number of dots for the horizontal period -1 in PHP0-10. (Example) When the horizontal period is set to 800 dots PHP setting value = 800-1 799 (01100011111 LSB) PHP 10 0 9 1 8 1 7 0 6 0 5 0 4 1 3 1 2 1 1 1 0 1
Set the value of the number of dots fixed to 816 during NTSC/PAL. PHP setting value = 816-1 815 (01100101111 LSB) PHP 10 0 9 1 8 1 7 0 6 0 5 1 4 0 3 1 2 1 1 1 0 1
* Horizontal position setting The horizontal display start position setting can be changed one dot at a time by the HP0 to 6 setting.
HSYNC
Thp
644dots Image display period
The maximum and minimum Thp values which can be set are shown in the following table. HP Minimum value Maximum value 6 1 0 5 1 0 4 1 0 3 1 0 2 1 0 1 1 0 0 1 0 VGA 110 dots 237 dots NTSC 5.8 s 15.7 s PAL 5.8 s 15.8 s
* Vertical position setting The vertical display start position setting can be changed one dot at a time by the VP0 to 6 setting.
VSYNC
HSYNC
Tvp
484 line Image display period
The maximum and minimum Tvp values which can be set are shown in the following table. VP Minimum value Maximum value 6 1 0 5 1 0 4 1 0 3 1 0 2 1 0 1 1 0 0 1 0 VGA 5H 133 H NTSC 14 H 141 H PAL 14 H 141 H
(This table shows the ODD field values for NTSC and PAL.)
--12--
CXD2436Q
* CLP pulse position setting The XCLP pulse position can be changed to four different positions. Each of these positions is shown below. The XCLP pulse is linked with the horizontal position setting, and is indicated with the HP (1000000 LSB) setting.
HSYNC Wclp1 XCLP1 tclp1 XCLP2 tclp2 The centers of the XCLP1 and XCLP2 pulses match.
Wclp2
* VGA mode CLPP1 CLPP0 0 0 0 1 1 0 1 1 * NTSC mode CLPP1 CLPP0 tclp1 Wclp1 0 0 4.83 s 1.17 s 0 1 5.30 s 1.17 s 1 0 5.76 s 1.17 s 1 1 6.23 s 1.17 s * PAL mode CLPP1 CLPP0 tclp1 Wclp1 0 0 4.87 s 1.18 s 0 1 5.33 s 1.18 s 1 0 5.80 s 1.18 s 1 1 6.27 s 1.18 s tclp2 4.39 s 4.86 s 5.33 s 5.80 s Wclp2 2.20 s 2.20 s 2.20 s 2.20 s tclp2 4.36 s 4.83 s 5.30 s 5.76 s Wclp2 2.18 s 2.18 s 2.18 s 2.18 s tclp1 74 dot 81 dot 88 dot 95 dot Wclp1 40 dot 40 dot 40 dot 40 dot tclp2 61 dot 68 dot 75 dot 82 dot Wclp2 67 dot 67 dot 67 dot 67 dot
--13--
CXD2436Q
* Switching the SH pulse timing The phase relationship between the sample-and-hold pulses and HCK can be switched in 12 different ways with SHP0, SHP1, SHP2 and SHP3. (This timing generator has a 0.5 DOT OFFSET function in order to ensure the phase margin.) In addition, the timing differs according to the scanning direction (right/left scan).
Right scanning pulse (RGT = H)
HCK
SH1
SH2
SH3
SH4 SH5
SH6
SH7 SHP0=L SHP1=L SHP2=L SHP3=L SHP0=H SHP1=L SHP2=L SHP3=L SHP0=L SHP1=H SHP2=L SHP3=L SHP0=H SHP1=H SHP2=L SHP3=L
HCK
SH1
SH2
SH3
SH4 SH5
SH6
SH7 SHP0=L SHP1=L SHP2=H SHP3=L SHP0=H SHP1=L SHP2=H SHP3=L SHP0=L SHP1=H SHP2=H SHP3=L SHP0=H SHP1=H SHP2=H SHP3=L
--14--
CXD2436Q
HCK
SH1
SH2
SH3
SH4 SH5
SH6
SH7 SHP0=L SHP1=L SHP2=L SHP3=H SHP0=H SHP1=L SHP2=L SHP3=H SHP0H=L SHP1=H SHP2=L SHP3=H SHP0=H SHP1=H SHP2=L SHP3=H
Left scanning pulse (RGT = L)
HCK
SH1
SH2
SH3
SH4 SH5
SH6
SH7 SHP0=L SHP1=L SHP2=L SHP3=L SHP0=H SHP1=L SHP2=L SHP3=L SHP0=L SHP1=H SHP2=L SHP3=L SHP0=H SHP1=H SHP2=L SHP3=L
--15--
CXD2436Q
HCK
SH1
SH2
SH3
SH4 SH5
SH6
SH7
SHP0=L SHP1=L SHP2=H SHP3=L
SHP0=H SHP1=L SHP2=H SHP3=L
SHP0=L SHP1=H SHP2=H SHP3=L
SHP0=H SHP1=H SHP2=H SHP3=L
HCK
SH1
SH2
SH3
SH4 SH5
SH6
SH7 SHP0=L SHP1=L SHP2=L SHP3=H SHP0=H SHP1=L SHP2=L SHP3=H SHP0=L SHP1=H SHP2=L SHP3=H SHP0=H SHP1=H SHP2=L SHP3=H
--16--
Horizontal Direction Timing Chart (IBM-VGA 640 x 480) SLRGT: H (Normal scan) HP: 1100001 LSB CLPP: 10 LSB SHP: 0000 LSB
20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 189
770
780
790
0
10
MCK CSYNC /HD1IN (BLK) 100fh 40fh 67fh 42fh 55fh
HDO
XCLP1
XCLP2
HST
HCK1
HCK2
SH1
--17--
76fh 15fh 76fh 34fh 40fh 36fh 30fh 1fh 24fh
SH2
SH3
SH4
SH5
SH6
SH7
CLR
ENB
VCK
PRG
PCG
FRP
VST1
CXD2436Q
INT
Horizontal Direction Timing Chart (IBM-VGA 640 x 480) SLRGT: L (Reverse scan) HP: 1100001 LSB CLPP: 10 LSB SHP: 0000 LSB
20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 189
770
780
790
0
10
MCK
CSYNC /HD1IN (BLK) 100fh 40fh 55fh 67fh 42fh
HDO
XCLP1
XCLP2
HST
HCK1
HCK2
SH1
--18--
76fh 15fh 76fh 34fh 40fh 36fh 30fh 1fh 24fh
SH2
SH3
SH4
SH5
SH6
SH7
CLR
ENB
VCK
PRG
PCG
FRP
VST1
CXD2436Q
INT
Vertical Direction Timing Chart (IBM-VGA 640 x 480) SLDWN: H (Down scan) VP: 1100100 LSB
VD1IN
HD1IN
HDO 1 10 20 30 40 46
460
470
480
(BLK)
VST1
VCK
--19--
FRP
(1H inversed)
HST
INT
ENB
CLR
FRP
(1F inversed)
VDO
VRST
CXD2436Q
(Internal reset)
Vertical Direction Timing Chart (IBM-VGA 640 x 480) SLDWN: L (Up scan) VP: 1100100 LSB
VD1IN
HD1IN
HDO 1 10 20 30 40 46
462
470
480
(BLK)
VST1
VCK
--20--
FRP
(1H inversed)
HST
INT
ENB
CLR
FRP
(1F inversed)
VDO
VRST
CXD2436Q
(Internal reset)
Horizontal Direction Timing Chart (NTSC) RGT: H (Normal scan) HP: 1000000 LSB CLPP: 10 LSB SHP: 0000 LSB MCK: 12.84 MHz (77.89 ns) Loop Counter: 816 fh
40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 10 20 30
776
786
796
806
0
MCK
CSYNC /HD2IN 1.17 s (15fh) 1.01 s (13fh) 0.55 s (7fh) 2.18 s (28fh) 4.98 s (64fh)
(BLK) 4.75 s (61fh)
HDO
1.32 s (17fh)
XCLP1
XCLP2
HST
HCK1
HCK2
SH1
--21--
0.55s (7fh) 3.04 s (39fh) 3.51 s (45fh) 1.48 s (19fh) 2.03 s (26fh)
SH2
SH3
SH4
SH5
SH6
SH7 0.47 s (6fh)
CLR
ENB
VCK
1.48 s (19fh)
PRG
PCG
1.01 s (13fh) 1.01 s (13fh) 0.78 s (10fh)
FRP
VST1
CXD2436Q
INT
Horizontal Direction Timing Chart (NTSC) RGT: L (Reverse scan) HP: 1000000 LSB CLPP: 10 LSB SHP: 0000 LSB MCK: 12.84 MHz (77.89 ns) Loop Counter: 816 fh
40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 10 20 30
776
786
796
806
0
MCK
CSYNC /HD2IN 4.98 s (64fh)
(BLK) 4.75s (61fh) 1.01s (7fh) 0.55s (7fh) 2.18s (28fh) 1.17s (15fh)
HDO
1.32s (17fh)
XCLP1
XCLP2
HST
HCK1
HCK2
SH1
--22--
3.04s (39fh) 3.51s (45fh) 0.55s (7fh) 1.48s (19fh) 2.03s (26fh)
SH2
SH3
SH4
SH5
SH6
SH7 0.47s (6fh)
CLR
ENB
VCK
1.48s (19fh)
PRG
PCG
1.01s (13fh) 1.01s (13fh) 0.78s (10fh)
FRP
VST1
CXD2436Q
INT
Vertical Direction Timing Chart (NTSC, odd field) SLDWN: H (Down scan) VP: 1111010 LSB
HD2IN
VD2IN
CSYNC 240 243 1 10 20 30 40 50 60
214
220
230
(BLK)
VST1
VCK
FRP
--23--
(1H inversed)
HST
INT
ENB
CLR
FRP
(1F inversed)
FLD
VDO
VRST
CXD2436Q
(Internal reset)
Vertical Direction Timing Chart (NTSC, even field) SLDWN: H (Down scan) VP: 1111010 LSB
HD2IN
VD2IN
CSYNC 240 243 1 10 20 30 40 50 60
213
220
230
(BLK)
VST1
VCK
FRP
--24--
(1H inversed)
HST
INT
ENB
CLR
FRP
(1F inversed)
FLD
VDO
VRST
CXD2436Q
(Internal reset)
Vertical Direction Timing Chart (NTSC, odd field) SLDWN: L (Up scan) VP: 1111010 LSB
HD2IN
VD2IN
CSYNC 240 243 1 10 20 30 40 50 60
214
220
230
(BLK)
VST1
VCK
FRP
--25--
(1H inversed)
HST
INT
ENB
CLR
FRP
(1F inversed)
FLD
VDO
VRST
CXD2436Q
(Internal reset)
Vertical Direction Timing Chart (NTSC, even field) SLDWN: L (Up scan) VP: 1111010 LSB
HD2IN
VD2IN
CSYNC 240 243 1 10 20 30 40 50 60
214
220
230
(BLK)
VST1
VCK
FRP
--26--
(1H inversed)
HST
INT
ENB
CLR
FRP
(1F inversed)
FLD
VDO
VRST
CXD2436Q
(Internal reset)
Horizontal Direction Timing Chart (PAL) SLRGT: H (Normal scan) HP: 1000000 LSB CLPP: 10 LSB SHP: 0000 LSB MCK: 12.75 MHz (78.43 ns) Loop Counter: 816 fh
40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 10 20 30
776 MCK CSYNC /HD2IN 5.73 s (73fh)
786
796
806
0
(BLK) 4.78 s (61fh) 1.02 s (13fh) 0.55 s (7fh) 2.20 s (28fh) 1.18 s (15fh)
HDO
1.49 s (19fh)
XCLP1
XCLP2
HST
HCK1
HCK2
SH1
--27--
3.06 s (39fh) 3.53 s (45fh) 0.55 s (7fh) 1.49 s (19fh) VCK inversion timing for the decimation cycle
SH2
SH3
SH4
SH5
SH6
SH7 0.47 s (6fh)
CLR
ENB
VCK
1.49 s (19fh) 2.04 s (26fh) 1.02 s (13fh) 1.02 s (13fh) 0.78 s (10fh)
PRG
PCG
FRP
VST1
CXD2436Q
INT
Horizontal Direction Timing Chart (PAL) SLRGT: L (Reverse scan) HP: 1000000 LSB CLPP: 10 LSB SHP: 0000 LSB MCK: 12.75 MHz (78.43 ns) Loop Counter: 816fh
40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 10 20 30
776 MCK SYNC /HD2IN 5.73 s (73fh)
786
796
806
0
(BLK) 4.78 s (61fh) 1.02 s (13fh) 0.55 s (7fh) 2.20 s (28fh) 1.18 s (15fh)
HDO
1.49 s (19fh)
XCLP1
XCLP2
HST
HCK1
HCK2
SH1
--28--
0.55 s (7fh) 3.06 s (39fh) 3.53 s (45fh) 1.49 s (19fh) VCK inversion timing for the decimation cycle
SH2
SH3
SH4
SH5
SH6
SH7 0.47 s (6fh)
CLR
ENB
VCK
2.04 s (19fh) 1.49s (26fh) 1.02s (13fh) 1.02s (13fh) 0.78s (10fh)
PRG
PCG
FRP
VST1
CXD2436Q
INT
Vertical Direction Timing Chart (PAL, odd field) SLDWN: H (Down scan) VP: 1110010 LSB
HD2IN
VD2IN
CSYNC 280 10 20 30 288 1 40 50 55
258260
270
(BLK)
VST1
VCK
FRP
--29--
(1H inversed)
HST
INT
ENB
CLR
FRP
(1F inversed)
FLD
VDO
VRST
CXD2436Q
(Internal reset)
Vertical Direction Timing Chart (PAL, even field) SLDWN: H (Down scan) VP: 1110010 LSB
HD2IN
VD2IN
CSYNC 288 1 10 20 30 40 50 55
259
270
280
(BLK)
VST1
VCK
FRP
--30--
(1H inversed)
HST
INT
ENB
CLR
FRP
(1F inversed)
FLD
VDO
VRST
CXD2436Q
(Internal reset)
Vertical Direction Timing Chart (PAL, odd field) SLDWN: L (Up scan) VP: 1110010 LSB
HD2IN
VD2IN
CSYNC 280 288 1 10 20 30 40 50
258
270
(BLK)
VST1
VCK
FRP
--31--
(1H inversed)
HST
INT
ENB
CLR
FRP
(1F inversed)
FLD
VDO
VRST
CXD2436Q
(Internal reset)
Vertical Direction Timing Chart (PAL, even field) SLDWN: L (Up scan) VP: 1110010 LSB
HD2IN
VD2IN
CSYNC 280 1 10 20 30 40 50 55
259
270
280
(BLK)
VST1
VCK
FRP
--32--
(1H inversed)
HST
INT
ENB
CLR
FRP
(1F inversed)
FLD
VDO
VRST
CXD2436Q
(Internal reset)
Application Circuit
+5V 47/16V 0.1 +5V
+5V
47/16V 80 74 GND TST10 50 VSS 49 VSS 48 100p VSS 47 VSS 46 +5V VSS 45 3-line serial input CS SI SCK 1M CS 44 SI 43 VSS 42 SCK 41 GND 47/16V 50k 79 78 77 76 75 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
0.1
GND
PO5
FLD
PO9
PO8
PO7
PO6
VSS
PO0
VSS
VSS VSS
FRP
VSS
VDD
PRG
VDO
PO4
PO3
PO2
PO1
HDO
DWN
HDN
82 RGT
XCLP2
XCLP1
XHDO
XHDN
PO11
PO10
VDD
81 XFRP
0.01
83 XRGT
84 HST
85 HCK1
to the panel
CXD2436QA
TC 39 FP D 38 1M TST 9 37 SL CKI 36 RP D 35 CKI 34 5.1k VSS 40 CKO 33 PWM 32 PEO 31 0.1
86 HCK2
87 CLR
88 ENB
89 INT
90 VSS
91 PCG
92 VCK
93 VST1
94 SH1
95 SH2
GND
96 SH3
97 SH4
6.8
98 SH5
99 SH6
to the RGB driver
HD1IN
SLSY
PLNT
XCLR
VPOL
HD2IN
VD2IN
VSS
TST7
TST4
TST1
TST6
TST8
VSS
HPOL
SLRGT
CSYNC
SLFR
VDD
SLDWN
TST2
TST3
NC
VD1IN
VGAV
SLMNB
TST5
VDD
VSS
EXT-CKI
--33--
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 PLL IC FB IN IN +5V POSI NT POSI VGA DOWN NOR 1H NEGA HPOL VPOL NEGA PAL PLNT AV VGAV UP SLDWN REV SLRGT 1F SLFR
100 SH7
1000p
+5V
28
29
30 1k 10k +5V 3.3 /25V 47 /16V 0.1 33k
33k 56p +12A 1T363 50k 3300p 0.01 3.3/ 35V 10k 33k 0.01
0.1
47/16V
GND
HD1 IN
VD1 IN GND CLK 1. PLL IC * Fall lock type * VCO variable range: 20 to 35MHz GND
CSYNC
HD2 IN
VD2 IN
+5V
10k
1
GND
CSYNC
CKI
HVD SLSY
EXT-CKI SLCKI
GND
CXD2436Q
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party and other right due to same.
CXD2436Q
Package Outline
Unit : mm
100PIN QFP (PLASTIC)
+ 0.1 0.15 - 0.05
23.9 0.4 + 0.4 20.0 - 0.1
+ 0.4 14.0 - 0.01 17.9 0.4
15.8 0.4
A
0.65 0.12 M
+ 0.35 2.75 - 0.15
0.15
0 to 15 DETAIL A
0.8 0.2
(16.3)
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-100P-L01 QFP100-P-1420-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 1.4g
--34--

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